1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 /* Register contains RO bits */ 51 #define F_RO (1 << 0) 52 /* Register contains graphics address */ 53 #define F_GMADR (1 << 1) 54 /* Mode mask registers with high 16 bits as the mask bits */ 55 #define F_MODE_MASK (1 << 2) 56 /* This reg can be accessed by GPU commands */ 57 #define F_CMD_ACCESS (1 << 3) 58 /* This reg has been accessed by a VM */ 59 #define F_ACCESSED (1 << 4) 60 /* This reg has been accessed through GPU commands */ 61 #define F_CMD_ACCESSED (1 << 5) 62 /* This reg could be accessed by unaligned address */ 63 #define F_UNALIGN (1 << 6) 64 65 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 66 { 67 if (IS_BROADWELL(gvt->dev_priv)) 68 return D_BDW; 69 else if (IS_SKYLAKE(gvt->dev_priv)) 70 return D_SKL; 71 72 return 0; 73 } 74 75 bool intel_gvt_match_device(struct intel_gvt *gvt, 76 unsigned long device) 77 { 78 return intel_gvt_get_device_type(gvt) & device; 79 } 80 81 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 82 void *p_data, unsigned int bytes) 83 { 84 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 85 } 86 87 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 88 void *p_data, unsigned int bytes) 89 { 90 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 91 } 92 93 static int new_mmio_info(struct intel_gvt *gvt, 94 u32 offset, u32 flags, u32 size, 95 u32 addr_mask, u32 ro_mask, u32 device, 96 void *read, void *write) 97 { 98 struct intel_gvt_mmio_info *info, *p; 99 u32 start, end, i; 100 101 if (!intel_gvt_match_device(gvt, device)) 102 return 0; 103 104 if (WARN_ON(!IS_ALIGNED(offset, 4))) 105 return -EINVAL; 106 107 start = offset; 108 end = offset + size; 109 110 for (i = start; i < end; i += 4) { 111 info = kzalloc(sizeof(*info), GFP_KERNEL); 112 if (!info) 113 return -ENOMEM; 114 115 info->offset = i; 116 p = intel_gvt_find_mmio_info(gvt, info->offset); 117 if (p) 118 gvt_err("dup mmio definition offset %x\n", 119 info->offset); 120 info->size = size; 121 info->length = (i + 4) < end ? 4 : (end - i); 122 info->addr_mask = addr_mask; 123 info->device = device; 124 info->read = read ? read : intel_vgpu_default_mmio_read; 125 info->write = write ? write : intel_vgpu_default_mmio_write; 126 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 127 INIT_HLIST_NODE(&info->node); 128 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 129 } 130 return 0; 131 } 132 133 static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) 134 { 135 int i; 136 137 reg &= ~GENMASK(11, 0); 138 for (i = 0; i < I915_NUM_ENGINES; i++) { 139 if (gvt->dev_priv->engine[i]->mmio_base == reg) 140 return i; 141 } 142 return -1; 143 } 144 145 #define offset_to_fence_num(offset) \ 146 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 147 148 #define fence_num_to_offset(num) \ 149 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 150 151 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 152 unsigned int fence_num, void *p_data, unsigned int bytes) 153 { 154 if (fence_num >= vgpu_fence_sz(vgpu)) { 155 gvt_err("vgpu%d: found oob fence register access\n", 156 vgpu->id); 157 gvt_err("vgpu%d: total fence num %d access fence num %d\n", 158 vgpu->id, vgpu_fence_sz(vgpu), fence_num); 159 memset(p_data, 0, bytes); 160 } 161 return 0; 162 } 163 164 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 165 void *p_data, unsigned int bytes) 166 { 167 int ret; 168 169 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 170 p_data, bytes); 171 if (ret) 172 return ret; 173 read_vreg(vgpu, off, p_data, bytes); 174 return 0; 175 } 176 177 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 178 void *p_data, unsigned int bytes) 179 { 180 unsigned int fence_num = offset_to_fence_num(off); 181 int ret; 182 183 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 184 if (ret) 185 return ret; 186 write_vreg(vgpu, off, p_data, bytes); 187 188 intel_vgpu_write_fence(vgpu, fence_num, 189 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 190 return 0; 191 } 192 193 #define CALC_MODE_MASK_REG(old, new) \ 194 (((new) & GENMASK(31, 16)) \ 195 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 196 | ((new) & ((new) >> 16)))) 197 198 static int mul_force_wake_write(struct intel_vgpu *vgpu, 199 unsigned int offset, void *p_data, unsigned int bytes) 200 { 201 u32 old, new; 202 uint32_t ack_reg_offset; 203 204 old = vgpu_vreg(vgpu, offset); 205 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 206 207 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) { 208 switch (offset) { 209 case FORCEWAKE_RENDER_GEN9_REG: 210 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 211 break; 212 case FORCEWAKE_BLITTER_GEN9_REG: 213 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 214 break; 215 case FORCEWAKE_MEDIA_GEN9_REG: 216 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 217 break; 218 default: 219 /*should not hit here*/ 220 gvt_err("invalid forcewake offset 0x%x\n", offset); 221 return 1; 222 } 223 } else { 224 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 225 } 226 227 vgpu_vreg(vgpu, offset) = new; 228 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 229 return 0; 230 } 231 232 static int handle_device_reset(struct intel_vgpu *vgpu, unsigned int offset, 233 void *p_data, unsigned int bytes, unsigned long bitmap) 234 { 235 struct intel_gvt_workload_scheduler *scheduler = 236 &vgpu->gvt->scheduler; 237 238 vgpu->resetting = true; 239 240 intel_vgpu_stop_schedule(vgpu); 241 if (scheduler->current_vgpu == vgpu) { 242 mutex_unlock(&vgpu->gvt->lock); 243 intel_gvt_wait_vgpu_idle(vgpu); 244 mutex_lock(&vgpu->gvt->lock); 245 } 246 247 intel_vgpu_reset_execlist(vgpu, bitmap); 248 249 vgpu->resetting = false; 250 251 return 0; 252 } 253 254 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 255 void *p_data, unsigned int bytes) 256 { 257 u32 data; 258 u64 bitmap = 0; 259 260 data = vgpu_vreg(vgpu, offset); 261 262 if (data & GEN6_GRDOM_FULL) { 263 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 264 bitmap = 0xff; 265 } 266 if (data & GEN6_GRDOM_RENDER) { 267 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 268 bitmap |= (1 << RCS); 269 } 270 if (data & GEN6_GRDOM_MEDIA) { 271 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 272 bitmap |= (1 << VCS); 273 } 274 if (data & GEN6_GRDOM_BLT) { 275 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 276 bitmap |= (1 << BCS); 277 } 278 if (data & GEN6_GRDOM_VECS) { 279 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 280 bitmap |= (1 << VECS); 281 } 282 if (data & GEN8_GRDOM_MEDIA2) { 283 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 284 if (HAS_BSD2(vgpu->gvt->dev_priv)) 285 bitmap |= (1 << VCS2); 286 } 287 return handle_device_reset(vgpu, offset, p_data, bytes, bitmap); 288 } 289 290 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 291 void *p_data, unsigned int bytes) 292 { 293 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 294 } 295 296 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 297 void *p_data, unsigned int bytes) 298 { 299 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 300 } 301 302 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 303 unsigned int offset, void *p_data, unsigned int bytes) 304 { 305 write_vreg(vgpu, offset, p_data, bytes); 306 307 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 308 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; 309 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 310 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 311 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 312 313 } else 314 vgpu_vreg(vgpu, PCH_PP_STATUS) &= 315 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 316 | PP_CYCLE_DELAY_ACTIVE); 317 return 0; 318 } 319 320 static int transconf_mmio_write(struct intel_vgpu *vgpu, 321 unsigned int offset, void *p_data, unsigned int bytes) 322 { 323 write_vreg(vgpu, offset, p_data, bytes); 324 325 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 326 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 327 else 328 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 329 return 0; 330 } 331 332 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 333 void *p_data, unsigned int bytes) 334 { 335 write_vreg(vgpu, offset, p_data, bytes); 336 337 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 338 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 339 else 340 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 341 342 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 343 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 344 else 345 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 346 347 return 0; 348 } 349 350 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 351 void *p_data, unsigned int bytes) 352 { 353 *(u32 *)p_data = (1 << 17); 354 return 0; 355 } 356 357 static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset, 358 void *p_data, unsigned int bytes) 359 { 360 *(u32 *)p_data = 3; 361 return 0; 362 } 363 364 static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset, 365 void *p_data, unsigned int bytes) 366 { 367 *(u32 *)p_data = (0x2f << 16); 368 return 0; 369 } 370 371 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 372 void *p_data, unsigned int bytes) 373 { 374 u32 data; 375 376 write_vreg(vgpu, offset, p_data, bytes); 377 data = vgpu_vreg(vgpu, offset); 378 379 if (data & PIPECONF_ENABLE) 380 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 381 else 382 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 383 intel_gvt_check_vblank_emulation(vgpu->gvt); 384 return 0; 385 } 386 387 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 388 void *p_data, unsigned int bytes) 389 { 390 write_vreg(vgpu, offset, p_data, bytes); 391 392 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 393 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 394 } else { 395 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 396 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 397 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) 398 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 399 } 400 return 0; 401 } 402 403 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 404 unsigned int offset, void *p_data, unsigned int bytes) 405 { 406 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 407 return 0; 408 } 409 410 #define FDI_LINK_TRAIN_PATTERN1 0 411 #define FDI_LINK_TRAIN_PATTERN2 1 412 413 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 414 { 415 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); 416 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 417 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); 418 419 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 420 (rx_ctl & FDI_RX_ENABLE) && 421 (rx_ctl & FDI_AUTO_TRAINING) && 422 (tx_ctl & DP_TP_CTL_ENABLE) && 423 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 424 return 1; 425 else 426 return 0; 427 } 428 429 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 430 enum pipe pipe, unsigned int train_pattern) 431 { 432 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 433 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 434 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 435 unsigned int fdi_iir_check_bits; 436 437 fdi_rx_imr = FDI_RX_IMR(pipe); 438 fdi_tx_ctl = FDI_TX_CTL(pipe); 439 fdi_rx_ctl = FDI_RX_CTL(pipe); 440 441 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 442 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 443 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 444 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 445 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 446 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 447 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 448 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 449 } else { 450 gvt_err("Invalid train pattern %d\n", train_pattern); 451 return -EINVAL; 452 } 453 454 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 455 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 456 457 /* If imr bit has been masked */ 458 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 459 return 0; 460 461 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 462 == fdi_tx_check_bits) 463 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 464 == fdi_rx_check_bits)) 465 return 1; 466 else 467 return 0; 468 } 469 470 #define INVALID_INDEX (~0U) 471 472 static unsigned int calc_index(unsigned int offset, unsigned int start, 473 unsigned int next, unsigned int end, i915_reg_t i915_end) 474 { 475 unsigned int range = next - start; 476 477 if (!end) 478 end = i915_mmio_reg_offset(i915_end); 479 if (offset < start || offset > end) 480 return INVALID_INDEX; 481 offset -= start; 482 return offset / range; 483 } 484 485 #define FDI_RX_CTL_TO_PIPE(offset) \ 486 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 487 488 #define FDI_TX_CTL_TO_PIPE(offset) \ 489 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 490 491 #define FDI_RX_IMR_TO_PIPE(offset) \ 492 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 493 494 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 495 unsigned int offset, void *p_data, unsigned int bytes) 496 { 497 i915_reg_t fdi_rx_iir; 498 unsigned int index; 499 int ret; 500 501 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 502 index = FDI_RX_CTL_TO_PIPE(offset); 503 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 504 index = FDI_TX_CTL_TO_PIPE(offset); 505 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 506 index = FDI_RX_IMR_TO_PIPE(offset); 507 else { 508 gvt_err("Unsupport registers %x\n", offset); 509 return -EINVAL; 510 } 511 512 write_vreg(vgpu, offset, p_data, bytes); 513 514 fdi_rx_iir = FDI_RX_IIR(index); 515 516 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 517 if (ret < 0) 518 return ret; 519 if (ret) 520 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 521 522 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 523 if (ret < 0) 524 return ret; 525 if (ret) 526 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 527 528 if (offset == _FDI_RXA_CTL) 529 if (fdi_auto_training_started(vgpu)) 530 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= 531 DP_TP_STATUS_AUTOTRAIN_DONE; 532 return 0; 533 } 534 535 #define DP_TP_CTL_TO_PORT(offset) \ 536 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 537 538 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 539 void *p_data, unsigned int bytes) 540 { 541 i915_reg_t status_reg; 542 unsigned int index; 543 u32 data; 544 545 write_vreg(vgpu, offset, p_data, bytes); 546 547 index = DP_TP_CTL_TO_PORT(offset); 548 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 549 if (data == 0x2) { 550 status_reg = DP_TP_STATUS(index); 551 vgpu_vreg(vgpu, status_reg) |= (1 << 25); 552 } 553 return 0; 554 } 555 556 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 557 unsigned int offset, void *p_data, unsigned int bytes) 558 { 559 u32 reg_val; 560 u32 sticky_mask; 561 562 reg_val = *((u32 *)p_data); 563 sticky_mask = GENMASK(27, 26) | (1 << 24); 564 565 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 566 (vgpu_vreg(vgpu, offset) & sticky_mask); 567 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 568 return 0; 569 } 570 571 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 572 unsigned int offset, void *p_data, unsigned int bytes) 573 { 574 u32 data; 575 576 write_vreg(vgpu, offset, p_data, bytes); 577 data = vgpu_vreg(vgpu, offset); 578 579 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 580 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 581 return 0; 582 } 583 584 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 585 unsigned int offset, void *p_data, unsigned int bytes) 586 { 587 u32 data; 588 589 write_vreg(vgpu, offset, p_data, bytes); 590 data = vgpu_vreg(vgpu, offset); 591 592 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 593 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 594 else 595 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 596 return 0; 597 } 598 599 #define DSPSURF_TO_PIPE(offset) \ 600 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 601 602 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 603 void *p_data, unsigned int bytes) 604 { 605 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 606 unsigned int index = DSPSURF_TO_PIPE(offset); 607 i915_reg_t surflive_reg = DSPSURFLIVE(index); 608 int flip_event[] = { 609 [PIPE_A] = PRIMARY_A_FLIP_DONE, 610 [PIPE_B] = PRIMARY_B_FLIP_DONE, 611 [PIPE_C] = PRIMARY_C_FLIP_DONE, 612 }; 613 614 write_vreg(vgpu, offset, p_data, bytes); 615 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 616 617 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 618 return 0; 619 } 620 621 #define SPRSURF_TO_PIPE(offset) \ 622 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 623 624 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 625 void *p_data, unsigned int bytes) 626 { 627 unsigned int index = SPRSURF_TO_PIPE(offset); 628 i915_reg_t surflive_reg = SPRSURFLIVE(index); 629 int flip_event[] = { 630 [PIPE_A] = SPRITE_A_FLIP_DONE, 631 [PIPE_B] = SPRITE_B_FLIP_DONE, 632 [PIPE_C] = SPRITE_C_FLIP_DONE, 633 }; 634 635 write_vreg(vgpu, offset, p_data, bytes); 636 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 637 638 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 639 return 0; 640 } 641 642 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 643 unsigned int reg) 644 { 645 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 646 enum intel_gvt_event_type event; 647 648 if (reg == _DPA_AUX_CH_CTL) 649 event = AUX_CHANNEL_A; 650 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 651 event = AUX_CHANNEL_B; 652 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 653 event = AUX_CHANNEL_C; 654 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 655 event = AUX_CHANNEL_D; 656 else { 657 WARN_ON(true); 658 return -EINVAL; 659 } 660 661 intel_vgpu_trigger_virtual_event(vgpu, event); 662 return 0; 663 } 664 665 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 666 unsigned int reg, int len, bool data_valid) 667 { 668 /* mark transaction done */ 669 value |= DP_AUX_CH_CTL_DONE; 670 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 671 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 672 673 if (data_valid) 674 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 675 else 676 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 677 678 /* message size */ 679 value &= ~(0xf << 20); 680 value |= (len << 20); 681 vgpu_vreg(vgpu, reg) = value; 682 683 if (value & DP_AUX_CH_CTL_INTERRUPT) 684 return trigger_aux_channel_interrupt(vgpu, reg); 685 return 0; 686 } 687 688 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 689 uint8_t t) 690 { 691 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 692 /* training pattern 1 for CR */ 693 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 694 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 695 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 696 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 697 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 698 DPCD_TRAINING_PATTERN_2) { 699 /* training pattern 2 for EQ */ 700 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 701 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 702 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 703 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 704 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 705 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 706 /* set INTERLANE_ALIGN_DONE */ 707 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 708 DPCD_INTERLANE_ALIGN_DONE; 709 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 710 DPCD_LINK_TRAINING_DISABLED) { 711 /* finish link training */ 712 /* set sink status as synchronized */ 713 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 714 } 715 } 716 717 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 718 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 719 720 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 721 722 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 723 724 #define dpy_is_valid_port(port) \ 725 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 726 727 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 728 unsigned int offset, void *p_data, unsigned int bytes) 729 { 730 struct intel_vgpu_display *display = &vgpu->display; 731 int msg, addr, ctrl, op, len; 732 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 733 struct intel_vgpu_dpcd_data *dpcd = NULL; 734 struct intel_vgpu_port *port = NULL; 735 u32 data; 736 737 if (!dpy_is_valid_port(port_index)) { 738 gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id); 739 return 0; 740 } 741 742 write_vreg(vgpu, offset, p_data, bytes); 743 data = vgpu_vreg(vgpu, offset); 744 745 if (IS_SKYLAKE(vgpu->gvt->dev_priv) && 746 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 747 /* SKL DPB/C/D aux ctl register changed */ 748 return 0; 749 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 750 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 751 /* write to the data registers */ 752 return 0; 753 } 754 755 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 756 /* just want to clear the sticky bits */ 757 vgpu_vreg(vgpu, offset) = 0; 758 return 0; 759 } 760 761 port = &display->ports[port_index]; 762 dpcd = port->dpcd; 763 764 /* read out message from DATA1 register */ 765 msg = vgpu_vreg(vgpu, offset + 4); 766 addr = (msg >> 8) & 0xffff; 767 ctrl = (msg >> 24) & 0xff; 768 len = msg & 0xff; 769 op = ctrl >> 4; 770 771 if (op == GVT_AUX_NATIVE_WRITE) { 772 int t; 773 uint8_t buf[16]; 774 775 if ((addr + len + 1) >= DPCD_SIZE) { 776 /* 777 * Write request exceeds what we supported, 778 * DCPD spec: When a Source Device is writing a DPCD 779 * address not supported by the Sink Device, the Sink 780 * Device shall reply with AUX NACK and “M” equal to 781 * zero. 782 */ 783 784 /* NAK the write */ 785 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 786 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 787 return 0; 788 } 789 790 /* 791 * Write request format: (command + address) occupies 792 * 3 bytes, followed by (len + 1) bytes of data. 793 */ 794 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 795 return -EINVAL; 796 797 /* unpack data from vreg to buf */ 798 for (t = 0; t < 4; t++) { 799 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 800 801 buf[t * 4] = (r >> 24) & 0xff; 802 buf[t * 4 + 1] = (r >> 16) & 0xff; 803 buf[t * 4 + 2] = (r >> 8) & 0xff; 804 buf[t * 4 + 3] = r & 0xff; 805 } 806 807 /* write to virtual DPCD */ 808 if (dpcd && dpcd->data_valid) { 809 for (t = 0; t <= len; t++) { 810 int p = addr + t; 811 812 dpcd->data[p] = buf[t]; 813 /* check for link training */ 814 if (p == DPCD_TRAINING_PATTERN_SET) 815 dp_aux_ch_ctl_link_training(dpcd, 816 buf[t]); 817 } 818 } 819 820 /* ACK the write */ 821 vgpu_vreg(vgpu, offset + 4) = 0; 822 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 823 dpcd && dpcd->data_valid); 824 return 0; 825 } 826 827 if (op == GVT_AUX_NATIVE_READ) { 828 int idx, i, ret = 0; 829 830 if ((addr + len + 1) >= DPCD_SIZE) { 831 /* 832 * read request exceeds what we supported 833 * DPCD spec: A Sink Device receiving a Native AUX CH 834 * read request for an unsupported DPCD address must 835 * reply with an AUX ACK and read data set equal to 836 * zero instead of replying with AUX NACK. 837 */ 838 839 /* ACK the READ*/ 840 vgpu_vreg(vgpu, offset + 4) = 0; 841 vgpu_vreg(vgpu, offset + 8) = 0; 842 vgpu_vreg(vgpu, offset + 12) = 0; 843 vgpu_vreg(vgpu, offset + 16) = 0; 844 vgpu_vreg(vgpu, offset + 20) = 0; 845 846 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 847 true); 848 return 0; 849 } 850 851 for (idx = 1; idx <= 5; idx++) { 852 /* clear the data registers */ 853 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 854 } 855 856 /* 857 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 858 */ 859 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 860 return -EINVAL; 861 862 /* read from virtual DPCD to vreg */ 863 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 864 if (dpcd && dpcd->data_valid) { 865 for (i = 1; i <= (len + 1); i++) { 866 int t; 867 868 t = dpcd->data[addr + i - 1]; 869 t <<= (24 - 8 * (i % 4)); 870 ret |= t; 871 872 if ((i % 4 == 3) || (i == (len + 1))) { 873 vgpu_vreg(vgpu, offset + 874 (i / 4 + 1) * 4) = ret; 875 ret = 0; 876 } 877 } 878 } 879 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 880 dpcd && dpcd->data_valid); 881 return 0; 882 } 883 884 /* i2c transaction starts */ 885 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 886 887 if (data & DP_AUX_CH_CTL_INTERRUPT) 888 trigger_aux_channel_interrupt(vgpu, offset); 889 return 0; 890 } 891 892 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 893 void *p_data, unsigned int bytes) 894 { 895 bool vga_disable; 896 897 write_vreg(vgpu, offset, p_data, bytes); 898 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 899 900 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 901 vga_disable ? "Disable" : "Enable"); 902 return 0; 903 } 904 905 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 906 unsigned int sbi_offset) 907 { 908 struct intel_vgpu_display *display = &vgpu->display; 909 int num = display->sbi.number; 910 int i; 911 912 for (i = 0; i < num; ++i) 913 if (display->sbi.registers[i].offset == sbi_offset) 914 break; 915 916 if (i == num) 917 return 0; 918 919 return display->sbi.registers[i].value; 920 } 921 922 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 923 unsigned int offset, u32 value) 924 { 925 struct intel_vgpu_display *display = &vgpu->display; 926 int num = display->sbi.number; 927 int i; 928 929 for (i = 0; i < num; ++i) { 930 if (display->sbi.registers[i].offset == offset) 931 break; 932 } 933 934 if (i == num) { 935 if (num == SBI_REG_MAX) { 936 gvt_err("vgpu%d: SBI caching meets maximum limits\n", 937 vgpu->id); 938 return; 939 } 940 display->sbi.number++; 941 } 942 943 display->sbi.registers[i].offset = offset; 944 display->sbi.registers[i].value = value; 945 } 946 947 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 948 void *p_data, unsigned int bytes) 949 { 950 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 951 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 952 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 953 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 954 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 955 sbi_offset); 956 } 957 read_vreg(vgpu, offset, p_data, bytes); 958 return 0; 959 } 960 961 static bool sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 962 void *p_data, unsigned int bytes) 963 { 964 u32 data; 965 966 write_vreg(vgpu, offset, p_data, bytes); 967 data = vgpu_vreg(vgpu, offset); 968 969 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 970 data |= SBI_READY; 971 972 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 973 data |= SBI_RESPONSE_SUCCESS; 974 975 vgpu_vreg(vgpu, offset) = data; 976 977 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 978 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 979 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 980 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 981 982 write_virtual_sbi_register(vgpu, sbi_offset, 983 vgpu_vreg(vgpu, SBI_DATA)); 984 } 985 return 0; 986 } 987 988 #define _vgtif_reg(x) \ 989 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 990 991 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 992 void *p_data, unsigned int bytes) 993 { 994 bool invalid_read = false; 995 996 read_vreg(vgpu, offset, p_data, bytes); 997 998 switch (offset) { 999 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1000 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1001 invalid_read = true; 1002 break; 1003 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1004 _vgtif_reg(avail_rs.fence_num): 1005 if (offset + bytes > 1006 _vgtif_reg(avail_rs.fence_num) + 4) 1007 invalid_read = true; 1008 break; 1009 case 0x78010: /* vgt_caps */ 1010 case 0x7881c: 1011 break; 1012 default: 1013 invalid_read = true; 1014 break; 1015 } 1016 if (invalid_read) 1017 gvt_err("invalid pvinfo read: [%x:%x] = %x\n", 1018 offset, bytes, *(u32 *)p_data); 1019 return 0; 1020 } 1021 1022 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1023 { 1024 int ret = 0; 1025 1026 switch (notification) { 1027 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1028 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); 1029 break; 1030 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1031 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); 1032 break; 1033 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1034 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); 1035 break; 1036 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1037 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); 1038 break; 1039 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1040 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1041 case 1: /* Remove this in guest driver. */ 1042 break; 1043 default: 1044 gvt_err("Invalid PV notification %d\n", notification); 1045 } 1046 return ret; 1047 } 1048 1049 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1050 { 1051 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1052 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1053 char *env[3] = {NULL, NULL, NULL}; 1054 char vmid_str[20]; 1055 char display_ready_str[20]; 1056 1057 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready); 1058 env[0] = display_ready_str; 1059 1060 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1061 env[1] = vmid_str; 1062 1063 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1064 } 1065 1066 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1067 void *p_data, unsigned int bytes) 1068 { 1069 u32 data; 1070 int ret; 1071 1072 write_vreg(vgpu, offset, p_data, bytes); 1073 data = vgpu_vreg(vgpu, offset); 1074 1075 switch (offset) { 1076 case _vgtif_reg(display_ready): 1077 send_display_ready_uevent(vgpu, data ? 1 : 0); 1078 break; 1079 case _vgtif_reg(g2v_notify): 1080 ret = handle_g2v_notification(vgpu, data); 1081 break; 1082 /* add xhot and yhot to handled list to avoid error log */ 1083 case 0x78830: 1084 case 0x78834: 1085 case _vgtif_reg(pdp[0].lo): 1086 case _vgtif_reg(pdp[0].hi): 1087 case _vgtif_reg(pdp[1].lo): 1088 case _vgtif_reg(pdp[1].hi): 1089 case _vgtif_reg(pdp[2].lo): 1090 case _vgtif_reg(pdp[2].hi): 1091 case _vgtif_reg(pdp[3].lo): 1092 case _vgtif_reg(pdp[3].hi): 1093 case _vgtif_reg(execlist_context_descriptor_lo): 1094 case _vgtif_reg(execlist_context_descriptor_hi): 1095 break; 1096 default: 1097 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n", 1098 offset, bytes, data); 1099 break; 1100 } 1101 return 0; 1102 } 1103 1104 static int pf_write(struct intel_vgpu *vgpu, 1105 unsigned int offset, void *p_data, unsigned int bytes) 1106 { 1107 u32 val = *(u32 *)p_data; 1108 1109 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1110 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1111 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1112 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1113 vgpu->id); 1114 return 0; 1115 } 1116 1117 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1118 } 1119 1120 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1121 unsigned int offset, void *p_data, unsigned int bytes) 1122 { 1123 write_vreg(vgpu, offset, p_data, bytes); 1124 1125 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) 1126 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; 1127 else 1128 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; 1129 return 0; 1130 } 1131 1132 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1133 unsigned int offset, void *p_data, unsigned int bytes) 1134 { 1135 write_vreg(vgpu, offset, p_data, bytes); 1136 1137 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1138 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1139 return 0; 1140 } 1141 1142 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1143 void *p_data, unsigned int bytes) 1144 { 1145 u32 mode = *(u32 *)p_data; 1146 1147 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1148 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n", 1149 vgpu->id); 1150 return 0; 1151 } 1152 1153 return 0; 1154 } 1155 1156 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1157 void *p_data, unsigned int bytes) 1158 { 1159 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1160 u32 trtte = *(u32 *)p_data; 1161 1162 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1163 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1164 vgpu->id); 1165 return -EINVAL; 1166 } 1167 write_vreg(vgpu, offset, p_data, bytes); 1168 /* TRTTE is not per-context */ 1169 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1170 1171 return 0; 1172 } 1173 1174 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1175 void *p_data, unsigned int bytes) 1176 { 1177 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1178 u32 val = *(u32 *)p_data; 1179 1180 if (val & 1) { 1181 /* unblock hw logic */ 1182 I915_WRITE(_MMIO(offset), val); 1183 } 1184 write_vreg(vgpu, offset, p_data, bytes); 1185 return 0; 1186 } 1187 1188 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1189 void *p_data, unsigned int bytes) 1190 { 1191 u32 v = 0; 1192 1193 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1194 v |= (1 << 0); 1195 1196 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1197 v |= (1 << 8); 1198 1199 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1200 v |= (1 << 16); 1201 1202 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1203 v |= (1 << 24); 1204 1205 vgpu_vreg(vgpu, offset) = v; 1206 1207 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1208 } 1209 1210 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1211 void *p_data, unsigned int bytes) 1212 { 1213 u32 value = *(u32 *)p_data; 1214 u32 cmd = value & 0xff; 1215 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); 1216 1217 switch (cmd) { 1218 case 0x6: 1219 /** 1220 * "Read memory latency" command on gen9. 1221 * Below memory latency values are read 1222 * from skylake platform. 1223 */ 1224 if (!*data0) 1225 *data0 = 0x1e1a1100; 1226 else 1227 *data0 = 0x61514b3d; 1228 break; 1229 case 0x5: 1230 *data0 |= 0x1; 1231 break; 1232 } 1233 1234 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1235 vgpu->id, value, *data0); 1236 1237 value &= ~(1 << 31); 1238 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1239 } 1240 1241 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1242 unsigned int offset, void *p_data, unsigned int bytes) 1243 { 1244 u32 v = *(u32 *)p_data; 1245 1246 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1247 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1248 v |= (v >> 1); 1249 1250 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1251 } 1252 1253 static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1254 void *p_data, unsigned int bytes) 1255 { 1256 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1257 i915_reg_t reg = {.reg = offset}; 1258 1259 switch (offset) { 1260 case 0x4ddc: 1261 vgpu_vreg(vgpu, offset) = 0x8000003c; 1262 break; 1263 case 0x42080: 1264 vgpu_vreg(vgpu, offset) = 0x8000; 1265 break; 1266 default: 1267 return -EINVAL; 1268 } 1269 1270 /** 1271 * TODO: need detect stepping info after gvt contain such information 1272 * 0x4ddc enabled after C0, 0x42080 enabled after E0. 1273 */ 1274 I915_WRITE(reg, vgpu_vreg(vgpu, offset)); 1275 return 0; 1276 } 1277 1278 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1279 void *p_data, unsigned int bytes) 1280 { 1281 u32 v = *(u32 *)p_data; 1282 1283 /* other bits are MBZ. */ 1284 v &= (1 << 31) | (1 << 30); 1285 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1286 1287 vgpu_vreg(vgpu, offset) = v; 1288 1289 return 0; 1290 } 1291 1292 static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu, 1293 unsigned int offset, void *p_data, unsigned int bytes) 1294 { 1295 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1296 1297 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1298 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1299 } 1300 1301 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1302 void *p_data, unsigned int bytes) 1303 { 1304 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1305 struct intel_vgpu_execlist *execlist; 1306 u32 data = *(u32 *)p_data; 1307 int ret; 1308 1309 if (WARN_ON(ring_id < 0)) 1310 return -EINVAL; 1311 1312 execlist = &vgpu->execlist[ring_id]; 1313 1314 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data; 1315 if (execlist->elsp_dwords.index == 3) 1316 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1317 1318 ++execlist->elsp_dwords.index; 1319 execlist->elsp_dwords.index &= 0x3; 1320 return 0; 1321 } 1322 1323 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1324 void *p_data, unsigned int bytes) 1325 { 1326 u32 data = *(u32 *)p_data; 1327 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1328 bool enable_execlist; 1329 1330 write_vreg(vgpu, offset, p_data, bytes); 1331 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1332 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1333 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1334 1335 gvt_dbg_core("EXECLIST %s on ring %d\n", 1336 (enable_execlist ? "enabling" : "disabling"), 1337 ring_id); 1338 1339 if (enable_execlist) 1340 intel_vgpu_start_schedule(vgpu); 1341 } 1342 return 0; 1343 } 1344 1345 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1346 unsigned int offset, void *p_data, unsigned int bytes) 1347 { 1348 int rc = 0; 1349 unsigned int id = 0; 1350 1351 switch (offset) { 1352 case 0x4260: 1353 id = RCS; 1354 break; 1355 case 0x4264: 1356 id = VCS; 1357 break; 1358 case 0x4268: 1359 id = VCS2; 1360 break; 1361 case 0x426c: 1362 id = BCS; 1363 break; 1364 case 0x4270: 1365 id = VECS; 1366 break; 1367 default: 1368 rc = -EINVAL; 1369 break; 1370 } 1371 set_bit(id, (void *)vgpu->tlb_handle_pending); 1372 1373 return rc; 1374 } 1375 1376 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1377 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 1378 f, s, am, rm, d, r, w); \ 1379 if (ret) \ 1380 return ret; \ 1381 } while (0) 1382 1383 #define MMIO_D(reg, d) \ 1384 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1385 1386 #define MMIO_DH(reg, d, r, w) \ 1387 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1388 1389 #define MMIO_DFH(reg, d, f, r, w) \ 1390 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1391 1392 #define MMIO_GM(reg, d, r, w) \ 1393 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1394 1395 #define MMIO_RO(reg, d, f, rm, r, w) \ 1396 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1397 1398 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1399 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1400 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1401 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1402 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1403 } while (0) 1404 1405 #define MMIO_RING_D(prefix, d) \ 1406 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1407 1408 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1409 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1410 1411 #define MMIO_RING_GM(prefix, d, r, w) \ 1412 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1413 1414 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1415 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1416 1417 static int init_generic_mmio_info(struct intel_gvt *gvt) 1418 { 1419 struct drm_i915_private *dev_priv = gvt->dev_priv; 1420 int ret; 1421 1422 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1423 1424 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1425 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1426 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1427 MMIO_D(SDEISR, D_ALL); 1428 1429 MMIO_RING_D(RING_HWSTAM, D_ALL); 1430 1431 MMIO_GM(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1432 MMIO_GM(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1433 MMIO_GM(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1434 MMIO_GM(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1435 1436 #define RING_REG(base) (base + 0x28) 1437 MMIO_RING_D(RING_REG, D_ALL); 1438 #undef RING_REG 1439 1440 #define RING_REG(base) (base + 0x134) 1441 MMIO_RING_D(RING_REG, D_ALL); 1442 #undef RING_REG 1443 1444 MMIO_GM(0x2148, D_ALL, NULL, NULL); 1445 MMIO_GM(CCID, D_ALL, NULL, NULL); 1446 MMIO_GM(0x12198, D_ALL, NULL, NULL); 1447 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1448 1449 MMIO_RING_D(RING_TAIL, D_ALL); 1450 MMIO_RING_D(RING_HEAD, D_ALL); 1451 MMIO_RING_D(RING_CTL, D_ALL); 1452 MMIO_RING_D(RING_ACTHD, D_ALL); 1453 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 1454 1455 /* RING MODE */ 1456 #define RING_REG(base) (base + 0x29c) 1457 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK, NULL, ring_mode_mmio_write); 1458 #undef RING_REG 1459 1460 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1461 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL); 1462 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1463 ring_timestamp_mmio_read, NULL); 1464 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1465 ring_timestamp_mmio_read, NULL); 1466 1467 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1468 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL); 1469 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK, NULL, NULL); 1470 1471 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL); 1472 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL); 1473 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK, NULL, NULL); 1474 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK, NULL, NULL); 1475 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK, NULL, NULL); 1476 MMIO_D(GAM_ECOCHK, D_ALL); 1477 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK, NULL, NULL); 1478 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK, NULL, NULL); 1479 MMIO_D(0x9030, D_ALL); 1480 MMIO_D(0x20a0, D_ALL); 1481 MMIO_D(0x2420, D_ALL); 1482 MMIO_D(0x2430, D_ALL); 1483 MMIO_D(0x2434, D_ALL); 1484 MMIO_D(0x2438, D_ALL); 1485 MMIO_D(0x243c, D_ALL); 1486 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK, NULL, NULL); 1487 MMIO_DFH(0xe184, D_ALL, F_MODE_MASK, NULL, NULL); 1488 MMIO_DFH(0xe100, D_ALL, F_MODE_MASK, NULL, NULL); 1489 1490 /* display */ 1491 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1492 MMIO_D(0x602a0, D_ALL); 1493 1494 MMIO_D(0x65050, D_ALL); 1495 MMIO_D(0x650b4, D_ALL); 1496 1497 MMIO_D(0xc4040, D_ALL); 1498 MMIO_D(DERRMR, D_ALL); 1499 1500 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1501 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1502 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1503 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1504 1505 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1506 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1507 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1508 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1509 1510 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1511 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1512 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1513 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1514 1515 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1516 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1517 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1518 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1519 1520 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1521 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1522 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1523 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1524 1525 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1526 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1527 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1528 1529 MMIO_D(CURPOS(PIPE_A), D_ALL); 1530 MMIO_D(CURPOS(PIPE_B), D_ALL); 1531 MMIO_D(CURPOS(PIPE_C), D_ALL); 1532 1533 MMIO_D(CURBASE(PIPE_A), D_ALL); 1534 MMIO_D(CURBASE(PIPE_B), D_ALL); 1535 MMIO_D(CURBASE(PIPE_C), D_ALL); 1536 1537 MMIO_D(0x700ac, D_ALL); 1538 MMIO_D(0x710ac, D_ALL); 1539 MMIO_D(0x720ac, D_ALL); 1540 1541 MMIO_D(0x70090, D_ALL); 1542 MMIO_D(0x70094, D_ALL); 1543 MMIO_D(0x70098, D_ALL); 1544 MMIO_D(0x7009c, D_ALL); 1545 1546 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1547 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1548 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1549 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1550 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1551 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1552 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1553 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1554 1555 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1556 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1557 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1558 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1559 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1560 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1561 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1562 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1563 1564 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1565 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1566 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1567 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1568 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1569 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1570 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1571 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1572 1573 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1574 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1575 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1576 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1577 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1578 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1579 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1580 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1581 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1582 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1583 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1584 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1585 1586 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1587 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1588 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1589 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1590 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1591 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1592 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1593 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1594 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1595 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1596 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1597 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1598 1599 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1600 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1601 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1602 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1603 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1604 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1605 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1606 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1607 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1608 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1609 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1610 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1611 1612 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1613 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1614 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1615 1616 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1617 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1618 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1619 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1620 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1621 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1622 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1623 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1624 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1625 1626 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1627 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1628 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1629 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1630 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1631 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1632 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1633 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1634 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1635 1636 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1637 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1638 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1639 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1640 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1641 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1642 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1643 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1644 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1645 1646 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1647 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1648 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1649 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1650 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1651 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1652 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1653 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1654 1655 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1656 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1657 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1658 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1659 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1660 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1661 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1662 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1663 1664 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1665 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1666 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1667 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1668 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1669 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1670 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1671 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1672 1673 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1674 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1675 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1676 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1677 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1678 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1679 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1680 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1681 1682 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1683 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1684 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1685 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1686 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1687 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1688 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1689 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1690 1691 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1692 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1693 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1694 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1695 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1696 1697 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1698 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1699 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1700 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1701 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1702 1703 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1704 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1705 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1706 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1707 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1708 1709 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1710 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1711 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1712 MMIO_D(WM1_LP_ILK, D_ALL); 1713 MMIO_D(WM2_LP_ILK, D_ALL); 1714 MMIO_D(WM3_LP_ILK, D_ALL); 1715 MMIO_D(WM1S_LP_ILK, D_ALL); 1716 MMIO_D(WM2S_LP_IVB, D_ALL); 1717 MMIO_D(WM3S_LP_IVB, D_ALL); 1718 1719 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1720 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1721 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1722 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1723 1724 MMIO_D(0x48268, D_ALL); 1725 1726 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1727 gmbus_mmio_write); 1728 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1729 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1730 1731 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1732 dp_aux_ch_ctl_mmio_write); 1733 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1734 dp_aux_ch_ctl_mmio_write); 1735 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1736 dp_aux_ch_ctl_mmio_write); 1737 1738 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write); 1739 1740 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); 1741 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); 1742 1743 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1744 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1745 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1746 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1747 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1748 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1749 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1750 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1751 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1752 1753 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 1754 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 1755 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 1756 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 1757 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 1758 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 1759 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 1760 1761 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 1762 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 1763 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 1764 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 1765 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 1766 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 1767 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 1768 1769 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 1770 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 1771 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 1772 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 1773 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 1774 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 1775 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 1776 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 1777 1778 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 1779 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 1780 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 1781 1782 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 1783 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 1784 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 1785 1786 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 1787 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 1788 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 1789 1790 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 1791 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 1792 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 1793 1794 MMIO_D(_FDI_RXA_MISC, D_ALL); 1795 MMIO_D(_FDI_RXB_MISC, D_ALL); 1796 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 1797 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 1798 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 1799 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 1800 1801 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 1802 MMIO_D(PCH_PP_DIVISOR, D_ALL); 1803 MMIO_D(PCH_PP_STATUS, D_ALL); 1804 MMIO_D(PCH_LVDS, D_ALL); 1805 MMIO_D(_PCH_DPLL_A, D_ALL); 1806 MMIO_D(_PCH_DPLL_B, D_ALL); 1807 MMIO_D(_PCH_FPA0, D_ALL); 1808 MMIO_D(_PCH_FPA1, D_ALL); 1809 MMIO_D(_PCH_FPB0, D_ALL); 1810 MMIO_D(_PCH_FPB1, D_ALL); 1811 MMIO_D(PCH_DREF_CONTROL, D_ALL); 1812 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 1813 MMIO_D(PCH_DPLL_SEL, D_ALL); 1814 1815 MMIO_D(0x61208, D_ALL); 1816 MMIO_D(0x6120c, D_ALL); 1817 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 1818 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 1819 1820 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); 1821 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); 1822 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); 1823 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); 1824 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL); 1825 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL); 1826 1827 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 1828 PORTA_HOTPLUG_STATUS_MASK 1829 | PORTB_HOTPLUG_STATUS_MASK 1830 | PORTC_HOTPLUG_STATUS_MASK 1831 | PORTD_HOTPLUG_STATUS_MASK, 1832 NULL, NULL); 1833 1834 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 1835 MMIO_D(FUSE_STRAP, D_ALL); 1836 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 1837 1838 MMIO_D(DISP_ARB_CTL, D_ALL); 1839 MMIO_D(DISP_ARB_CTL2, D_ALL); 1840 1841 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 1842 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 1843 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 1844 1845 MMIO_D(SOUTH_CHICKEN1, D_ALL); 1846 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 1847 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 1848 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 1849 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 1850 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 1851 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 1852 1853 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 1854 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 1855 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 1856 MMIO_D(ILK_DPFC_STATUS, D_ALL); 1857 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 1858 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 1859 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 1860 1861 MMIO_D(IPS_CTL, D_ALL); 1862 1863 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 1864 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 1865 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 1866 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 1867 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 1868 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 1869 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 1870 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 1871 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 1872 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 1873 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 1874 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 1875 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 1876 1877 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 1878 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 1879 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 1880 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 1881 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 1882 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 1883 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 1884 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 1885 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 1886 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 1887 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 1888 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 1889 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 1890 1891 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 1892 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 1893 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 1894 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 1895 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 1896 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 1897 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 1898 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 1899 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 1900 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 1901 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 1902 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 1903 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 1904 1905 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 1906 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 1907 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1908 1909 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 1910 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 1911 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1912 1913 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 1914 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 1915 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1916 1917 MMIO_D(0x60110, D_ALL); 1918 MMIO_D(0x61110, D_ALL); 1919 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1920 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1921 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1922 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1923 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1924 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1925 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1926 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1927 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1928 1929 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 1930 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 1931 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 1932 MMIO_D(SPLL_CTL, D_ALL); 1933 MMIO_D(_WRPLL_CTL1, D_ALL); 1934 MMIO_D(_WRPLL_CTL2, D_ALL); 1935 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 1936 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 1937 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 1938 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 1939 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 1940 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 1941 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 1942 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 1943 1944 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 1945 MMIO_D(0x46508, D_ALL); 1946 1947 MMIO_D(0x49080, D_ALL); 1948 MMIO_D(0x49180, D_ALL); 1949 MMIO_D(0x49280, D_ALL); 1950 1951 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1952 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1953 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1954 1955 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 1956 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 1957 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 1958 1959 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 1960 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 1961 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 1962 1963 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 1964 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 1965 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 1966 1967 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 1968 MMIO_D(SBI_ADDR, D_ALL); 1969 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 1970 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 1971 MMIO_D(PIXCLK_GATE, D_ALL); 1972 1973 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, 1974 dp_aux_ch_ctl_mmio_write); 1975 1976 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1977 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1978 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1979 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1980 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1981 1982 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 1983 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 1984 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 1985 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 1986 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 1987 1988 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 1989 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 1990 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 1991 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 1992 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 1993 1994 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1995 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1996 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1997 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1998 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1999 2000 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2001 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2002 2003 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 2004 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 2005 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 2006 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 2007 2008 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 2009 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 2010 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 2011 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 2012 2013 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2014 MMIO_D(FORCEWAKE_ACK, D_ALL); 2015 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2016 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2017 MMIO_D(GTFIFODBG, D_ALL); 2018 MMIO_D(GTFIFOCTL, D_ALL); 2019 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2020 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL); 2021 MMIO_D(ECOBUS, D_ALL); 2022 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2023 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2024 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2025 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2026 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2027 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2028 MMIO_D(GEN6_RPSTAT1, D_ALL); 2029 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2030 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2031 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2032 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2033 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2034 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2035 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2036 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2037 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2038 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2039 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2040 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2041 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2042 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2043 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2044 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2045 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2046 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2047 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2048 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2049 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2050 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2051 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2052 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2053 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2054 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2055 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2056 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2057 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2058 2059 MMIO_D(RSTDBYCTL, D_ALL); 2060 2061 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2062 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2063 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write); 2064 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2065 2066 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL); 2067 2068 MMIO_D(TILECTL, D_ALL); 2069 2070 MMIO_D(GEN6_UCGCTL1, D_ALL); 2071 MMIO_D(GEN6_UCGCTL2, D_ALL); 2072 2073 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2074 2075 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_SKL); 2076 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2077 MMIO_D(0x13812c, D_ALL); 2078 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2079 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2080 MMIO_D(HSW_IDICR, D_ALL); 2081 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2082 2083 MMIO_D(0x3c, D_ALL); 2084 MMIO_D(0x860, D_ALL); 2085 MMIO_D(ECOSKPD, D_ALL); 2086 MMIO_D(0x121d0, D_ALL); 2087 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2088 MMIO_D(0x41d0, D_ALL); 2089 MMIO_D(GAC_ECO_BITS, D_ALL); 2090 MMIO_D(0x6200, D_ALL); 2091 MMIO_D(0x6204, D_ALL); 2092 MMIO_D(0x6208, D_ALL); 2093 MMIO_D(0x7118, D_ALL); 2094 MMIO_D(0x7180, D_ALL); 2095 MMIO_D(0x7408, D_ALL); 2096 MMIO_D(0x7c00, D_ALL); 2097 MMIO_D(GEN6_MBCTL, D_ALL); 2098 MMIO_D(0x911c, D_ALL); 2099 MMIO_D(0x9120, D_ALL); 2100 2101 MMIO_D(GAB_CTL, D_ALL); 2102 MMIO_D(0x48800, D_ALL); 2103 MMIO_D(0xce044, D_ALL); 2104 MMIO_D(0xe6500, D_ALL); 2105 MMIO_D(0xe6504, D_ALL); 2106 MMIO_D(0xe6600, D_ALL); 2107 MMIO_D(0xe6604, D_ALL); 2108 MMIO_D(0xe6700, D_ALL); 2109 MMIO_D(0xe6704, D_ALL); 2110 MMIO_D(0xe6800, D_ALL); 2111 MMIO_D(0xe6804, D_ALL); 2112 MMIO_D(PCH_GMBUS4, D_ALL); 2113 MMIO_D(PCH_GMBUS5, D_ALL); 2114 2115 MMIO_D(0x902c, D_ALL); 2116 MMIO_D(0xec008, D_ALL); 2117 MMIO_D(0xec00c, D_ALL); 2118 MMIO_D(0xec008 + 0x18, D_ALL); 2119 MMIO_D(0xec00c + 0x18, D_ALL); 2120 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 2121 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 2122 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 2123 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 2124 MMIO_D(0xec408, D_ALL); 2125 MMIO_D(0xec40c, D_ALL); 2126 MMIO_D(0xec408 + 0x18, D_ALL); 2127 MMIO_D(0xec40c + 0x18, D_ALL); 2128 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 2129 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 2130 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 2131 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 2132 MMIO_D(0xfc810, D_ALL); 2133 MMIO_D(0xfc81c, D_ALL); 2134 MMIO_D(0xfc828, D_ALL); 2135 MMIO_D(0xfc834, D_ALL); 2136 MMIO_D(0xfcc00, D_ALL); 2137 MMIO_D(0xfcc0c, D_ALL); 2138 MMIO_D(0xfcc18, D_ALL); 2139 MMIO_D(0xfcc24, D_ALL); 2140 MMIO_D(0xfd000, D_ALL); 2141 MMIO_D(0xfd00c, D_ALL); 2142 MMIO_D(0xfd018, D_ALL); 2143 MMIO_D(0xfd024, D_ALL); 2144 MMIO_D(0xfd034, D_ALL); 2145 2146 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2147 MMIO_D(0x2054, D_ALL); 2148 MMIO_D(0x12054, D_ALL); 2149 MMIO_D(0x22054, D_ALL); 2150 MMIO_D(0x1a054, D_ALL); 2151 2152 MMIO_D(0x44070, D_ALL); 2153 2154 MMIO_D(0x215c, D_HSW_PLUS); 2155 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2156 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2157 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2158 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2159 2160 MMIO_F(0x2290, 8, 0, 0, 0, D_HSW_PLUS, NULL, NULL); 2161 MMIO_D(OACONTROL, D_HSW); 2162 MMIO_D(0x2b00, D_BDW_PLUS); 2163 MMIO_D(0x2360, D_BDW_PLUS); 2164 MMIO_F(0x5200, 32, 0, 0, 0, D_ALL, NULL, NULL); 2165 MMIO_F(0x5240, 32, 0, 0, 0, D_ALL, NULL, NULL); 2166 MMIO_F(0x5280, 16, 0, 0, 0, D_ALL, NULL, NULL); 2167 2168 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2169 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2170 MMIO_D(BCS_SWCTRL, D_ALL); 2171 2172 MMIO_F(HS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2173 MMIO_F(DS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2174 MMIO_F(IA_VERTICES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2175 MMIO_F(IA_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2176 MMIO_F(VS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2177 MMIO_F(GS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2178 MMIO_F(GS_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2179 MMIO_F(CL_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2180 MMIO_F(CL_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2181 MMIO_F(PS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2182 MMIO_F(PS_DEPTH_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2183 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2184 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2185 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2186 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2187 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2188 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2189 2190 return 0; 2191 } 2192 2193 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2194 { 2195 struct drm_i915_private *dev_priv = gvt->dev_priv; 2196 int ret; 2197 2198 MMIO_DH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, 2199 intel_vgpu_reg_imr_handler); 2200 2201 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2202 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2203 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2204 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2205 2206 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2207 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2208 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2209 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2210 2211 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2212 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2213 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2214 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2215 2216 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2217 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2218 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2219 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2220 2221 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2222 intel_vgpu_reg_imr_handler); 2223 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2224 intel_vgpu_reg_ier_handler); 2225 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2226 intel_vgpu_reg_iir_handler); 2227 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2228 2229 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2230 intel_vgpu_reg_imr_handler); 2231 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2232 intel_vgpu_reg_ier_handler); 2233 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2234 intel_vgpu_reg_iir_handler); 2235 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2236 2237 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2238 intel_vgpu_reg_imr_handler); 2239 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2240 intel_vgpu_reg_ier_handler); 2241 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2242 intel_vgpu_reg_iir_handler); 2243 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2244 2245 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2246 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2247 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2248 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2249 2250 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2251 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2252 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2253 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2254 2255 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2256 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2257 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2258 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2259 2260 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2261 intel_vgpu_reg_master_irq_handler); 2262 2263 MMIO_D(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2264 MMIO_D(0x1c134, D_BDW_PLUS); 2265 2266 MMIO_D(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2267 MMIO_D(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2268 MMIO_GM(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2269 MMIO_D(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2270 MMIO_D(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2271 MMIO_D(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2272 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK, NULL, ring_mode_mmio_write); 2273 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2274 NULL, NULL); 2275 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2276 NULL, NULL); 2277 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2278 ring_timestamp_mmio_read, NULL); 2279 2280 MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS); 2281 2282 #define RING_REG(base) (base + 0x230) 2283 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2284 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write); 2285 #undef RING_REG 2286 2287 #define RING_REG(base) (base + 0x234) 2288 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2289 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, ~0LL, D_BDW_PLUS, NULL, NULL); 2290 #undef RING_REG 2291 2292 #define RING_REG(base) (base + 0x244) 2293 MMIO_RING_D(RING_REG, D_BDW_PLUS); 2294 MMIO_D(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2295 #undef RING_REG 2296 2297 #define RING_REG(base) (base + 0x370) 2298 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2299 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS, 2300 NULL, NULL); 2301 #undef RING_REG 2302 2303 #define RING_REG(base) (base + 0x3a0) 2304 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2305 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2306 #undef RING_REG 2307 2308 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2309 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2310 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2311 MMIO_D(0x1c1d0, D_BDW_PLUS); 2312 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2313 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2314 MMIO_D(0x1c054, D_BDW_PLUS); 2315 2316 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2317 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2318 2319 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2320 2321 #define RING_REG(base) (base + 0x270) 2322 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2323 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2324 #undef RING_REG 2325 2326 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); 2327 MMIO_GM(0x1c080, D_BDW_PLUS, NULL, NULL); 2328 2329 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2330 2331 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW); 2332 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW); 2333 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW); 2334 2335 MMIO_D(WM_MISC, D_BDW); 2336 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 2337 2338 MMIO_D(0x66c00, D_BDW_PLUS); 2339 MMIO_D(0x66c04, D_BDW_PLUS); 2340 2341 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2342 2343 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2344 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2345 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2346 2347 MMIO_D(0xfdc, D_BDW); 2348 MMIO_D(GEN8_ROW_CHICKEN, D_BDW_PLUS); 2349 MMIO_D(GEN7_ROW_CHICKEN2, D_BDW_PLUS); 2350 MMIO_D(GEN8_UCGCTL6, D_BDW_PLUS); 2351 2352 MMIO_D(0xb1f0, D_BDW); 2353 MMIO_D(0xb1c0, D_BDW); 2354 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2355 MMIO_D(0xb100, D_BDW); 2356 MMIO_D(0xb10c, D_BDW); 2357 MMIO_D(0xb110, D_BDW); 2358 2359 MMIO_DH(0x24d0, D_BDW_PLUS, NULL, NULL); 2360 MMIO_DH(0x24d4, D_BDW_PLUS, NULL, NULL); 2361 MMIO_DH(0x24d8, D_BDW_PLUS, NULL, NULL); 2362 MMIO_DH(0x24dc, D_BDW_PLUS, NULL, NULL); 2363 2364 MMIO_D(0x83a4, D_BDW); 2365 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2366 2367 MMIO_D(0x8430, D_BDW); 2368 2369 MMIO_D(0x110000, D_BDW_PLUS); 2370 2371 MMIO_D(0x48400, D_BDW_PLUS); 2372 2373 MMIO_D(0x6e570, D_BDW_PLUS); 2374 MMIO_D(0x65f10, D_BDW_PLUS); 2375 2376 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2377 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2378 MMIO_DFH(0xe180, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2379 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2380 2381 MMIO_D(0x2248, D_BDW); 2382 2383 return 0; 2384 } 2385 2386 static int init_skl_mmio_info(struct intel_gvt *gvt) 2387 { 2388 struct drm_i915_private *dev_priv = gvt->dev_priv; 2389 int ret; 2390 2391 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2392 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2393 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2394 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2395 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2396 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2397 2398 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2399 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2400 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2401 2402 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL); 2403 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write); 2404 2405 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, mailbox_write); 2406 MMIO_D(0xa210, D_SKL_PLUS); 2407 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2408 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2409 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write); 2410 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write); 2411 MMIO_D(0x45504, D_SKL); 2412 MMIO_D(0x45520, D_SKL); 2413 MMIO_D(0x46000, D_SKL); 2414 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write); 2415 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write); 2416 MMIO_D(0x6C040, D_SKL); 2417 MMIO_D(0x6C048, D_SKL); 2418 MMIO_D(0x6C050, D_SKL); 2419 MMIO_D(0x6C044, D_SKL); 2420 MMIO_D(0x6C04C, D_SKL); 2421 MMIO_D(0x6C054, D_SKL); 2422 MMIO_D(0x6c058, D_SKL); 2423 MMIO_D(0x6c05c, D_SKL); 2424 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL); 2425 2426 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write); 2427 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write); 2428 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write); 2429 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write); 2430 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write); 2431 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write); 2432 2433 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write); 2434 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write); 2435 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write); 2436 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write); 2437 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write); 2438 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write); 2439 2440 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write); 2441 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write); 2442 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write); 2443 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write); 2444 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write); 2445 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write); 2446 2447 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2448 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2449 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2450 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2451 2452 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2453 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2454 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2455 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2456 2457 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2458 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2459 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2460 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2461 2462 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL); 2463 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL); 2464 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL); 2465 2466 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2467 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2468 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2469 2470 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2471 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2472 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2473 2474 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2475 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2476 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2477 2478 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2479 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2480 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2481 2482 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL); 2483 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL); 2484 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL); 2485 2486 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL); 2487 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL); 2488 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL); 2489 2490 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL); 2491 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL); 2492 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL); 2493 2494 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL); 2495 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL); 2496 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL); 2497 2498 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2499 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2500 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2501 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2502 2503 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2504 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2505 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2506 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2507 2508 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2509 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2510 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2511 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2512 2513 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL); 2514 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL); 2515 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL); 2516 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL); 2517 2518 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL); 2519 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL); 2520 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL); 2521 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL); 2522 2523 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL); 2524 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL); 2525 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL); 2526 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL); 2527 2528 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL); 2529 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL); 2530 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL); 2531 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL); 2532 2533 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL); 2534 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL); 2535 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL); 2536 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL); 2537 2538 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL); 2539 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL); 2540 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL); 2541 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL); 2542 2543 MMIO_D(0x70380, D_SKL); 2544 MMIO_D(0x71380, D_SKL); 2545 MMIO_D(0x72380, D_SKL); 2546 MMIO_D(0x7039c, D_SKL); 2547 2548 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL); 2549 MMIO_D(0x8f074, D_SKL); 2550 MMIO_D(0x8f004, D_SKL); 2551 MMIO_D(0x8f034, D_SKL); 2552 2553 MMIO_D(0xb11c, D_SKL); 2554 2555 MMIO_D(0x51000, D_SKL); 2556 MMIO_D(0x6c00c, D_SKL); 2557 2558 MMIO_F(0xc800, 0x7f8, 0, 0, 0, D_SKL, NULL, NULL); 2559 MMIO_F(0xb020, 0x80, 0, 0, 0, D_SKL, NULL, NULL); 2560 2561 MMIO_D(0xd08, D_SKL); 2562 MMIO_D(0x20e0, D_SKL); 2563 MMIO_D(0x20ec, D_SKL); 2564 2565 /* TRTT */ 2566 MMIO_D(0x4de0, D_SKL); 2567 MMIO_D(0x4de4, D_SKL); 2568 MMIO_D(0x4de8, D_SKL); 2569 MMIO_D(0x4dec, D_SKL); 2570 MMIO_D(0x4df0, D_SKL); 2571 MMIO_DH(0x4df4, D_SKL, NULL, gen9_trtte_write); 2572 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write); 2573 2574 MMIO_D(0x45008, D_SKL); 2575 2576 MMIO_D(0x46430, D_SKL); 2577 2578 MMIO_D(0x46520, D_SKL); 2579 2580 MMIO_D(0xc403c, D_SKL); 2581 MMIO_D(0xb004, D_SKL); 2582 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2583 2584 MMIO_D(0x65900, D_SKL); 2585 MMIO_D(0x1082c0, D_SKL); 2586 MMIO_D(0x4068, D_SKL); 2587 MMIO_D(0x67054, D_SKL); 2588 MMIO_D(0x6e560, D_SKL); 2589 MMIO_D(0x6e554, D_SKL); 2590 MMIO_D(0x2b20, D_SKL); 2591 MMIO_D(0x65f00, D_SKL); 2592 MMIO_D(0x65f08, D_SKL); 2593 MMIO_D(0x320f0, D_SKL); 2594 2595 MMIO_D(_REG_VCS2_EXCC, D_SKL); 2596 MMIO_D(0x70034, D_SKL); 2597 MMIO_D(0x71034, D_SKL); 2598 MMIO_D(0x72034, D_SKL); 2599 2600 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL); 2601 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL); 2602 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL); 2603 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL); 2604 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL); 2605 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL); 2606 2607 MMIO_D(0x44500, D_SKL); 2608 return 0; 2609 } 2610 2611 /** 2612 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset 2613 * @gvt: GVT device 2614 * @offset: register offset 2615 * 2616 * This function is used to find the MMIO information entry from hash table 2617 * 2618 * Returns: 2619 * pointer to MMIO information entry, NULL if not exists 2620 */ 2621 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 2622 unsigned int offset) 2623 { 2624 struct intel_gvt_mmio_info *e; 2625 2626 WARN_ON(!IS_ALIGNED(offset, 4)); 2627 2628 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 2629 if (e->offset == offset) 2630 return e; 2631 } 2632 return NULL; 2633 } 2634 2635 /** 2636 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2637 * @gvt: GVT device 2638 * 2639 * This function is called at the driver unloading stage, to clean up the MMIO 2640 * information table of GVT device 2641 * 2642 */ 2643 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2644 { 2645 struct hlist_node *tmp; 2646 struct intel_gvt_mmio_info *e; 2647 int i; 2648 2649 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2650 kfree(e); 2651 2652 vfree(gvt->mmio.mmio_attribute); 2653 gvt->mmio.mmio_attribute = NULL; 2654 } 2655 2656 /** 2657 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2658 * @gvt: GVT device 2659 * 2660 * This function is called at the initialization stage, to setup the MMIO 2661 * information table for GVT device 2662 * 2663 * Returns: 2664 * zero on success, negative if failed. 2665 */ 2666 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2667 { 2668 struct intel_gvt_device_info *info = &gvt->device_info; 2669 struct drm_i915_private *dev_priv = gvt->dev_priv; 2670 int ret; 2671 2672 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size); 2673 if (!gvt->mmio.mmio_attribute) 2674 return -ENOMEM; 2675 2676 ret = init_generic_mmio_info(gvt); 2677 if (ret) 2678 goto err; 2679 2680 if (IS_BROADWELL(dev_priv)) { 2681 ret = init_broadwell_mmio_info(gvt); 2682 if (ret) 2683 goto err; 2684 } else if (IS_SKYLAKE(dev_priv)) { 2685 ret = init_broadwell_mmio_info(gvt); 2686 if (ret) 2687 goto err; 2688 ret = init_skl_mmio_info(gvt); 2689 if (ret) 2690 goto err; 2691 } 2692 return 0; 2693 err: 2694 intel_gvt_clean_mmio_info(gvt); 2695 return ret; 2696 } 2697 2698 /** 2699 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 2700 * @gvt: a GVT device 2701 * @offset: register offset 2702 * 2703 */ 2704 void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset) 2705 { 2706 gvt->mmio.mmio_attribute[offset >> 2] |= 2707 F_ACCESSED; 2708 } 2709 2710 /** 2711 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 2712 * @gvt: a GVT device 2713 * @offset: register offset 2714 * 2715 */ 2716 bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt, 2717 unsigned int offset) 2718 { 2719 return gvt->mmio.mmio_attribute[offset >> 2] & 2720 F_CMD_ACCESS; 2721 } 2722 2723 /** 2724 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 2725 * @gvt: a GVT device 2726 * @offset: register offset 2727 * 2728 */ 2729 bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, 2730 unsigned int offset) 2731 { 2732 return gvt->mmio.mmio_attribute[offset >> 2] & 2733 F_UNALIGN; 2734 } 2735 2736 /** 2737 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 2738 * @gvt: a GVT device 2739 * @offset: register offset 2740 * 2741 */ 2742 void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt, 2743 unsigned int offset) 2744 { 2745 gvt->mmio.mmio_attribute[offset >> 2] |= 2746 F_CMD_ACCESSED; 2747 } 2748 2749 /** 2750 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 2751 * @gvt: a GVT device 2752 * @offset: register offset 2753 * 2754 * Returns: 2755 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 2756 * 2757 */ 2758 bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset) 2759 { 2760 return gvt->mmio.mmio_attribute[offset >> 2] & 2761 F_MODE_MASK; 2762 } 2763 2764 /** 2765 * intel_vgpu_default_mmio_read - default MMIO read handler 2766 * @vgpu: a vGPU 2767 * @offset: access offset 2768 * @p_data: data return buffer 2769 * @bytes: access data length 2770 * 2771 * Returns: 2772 * Zero on success, negative error code if failed. 2773 */ 2774 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 2775 void *p_data, unsigned int bytes) 2776 { 2777 read_vreg(vgpu, offset, p_data, bytes); 2778 return 0; 2779 } 2780 2781 /** 2782 * intel_t_default_mmio_write - default MMIO write handler 2783 * @vgpu: a vGPU 2784 * @offset: access offset 2785 * @p_data: write data buffer 2786 * @bytes: access data length 2787 * 2788 * Returns: 2789 * Zero on success, negative error code if failed. 2790 */ 2791 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2792 void *p_data, unsigned int bytes) 2793 { 2794 write_vreg(vgpu, offset, p_data, bytes); 2795 return 0; 2796 } 2797