1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 41 /* XXX FIXME i915 has changed PP_XXX definition */ 42 #define PCH_PP_STATUS _MMIO(0xc7200) 43 #define PCH_PP_CONTROL _MMIO(0xc7204) 44 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 45 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 46 #define PCH_PP_DIVISOR _MMIO(0xc7210) 47 48 /* Register contains RO bits */ 49 #define F_RO (1 << 0) 50 /* Register contains graphics address */ 51 #define F_GMADR (1 << 1) 52 /* Mode mask registers with high 16 bits as the mask bits */ 53 #define F_MODE_MASK (1 << 2) 54 /* This reg can be accessed by GPU commands */ 55 #define F_CMD_ACCESS (1 << 3) 56 /* This reg has been accessed by a VM */ 57 #define F_ACCESSED (1 << 4) 58 /* This reg has been accessed through GPU commands */ 59 #define F_CMD_ACCESSED (1 << 5) 60 /* This reg could be accessed by unaligned address */ 61 #define F_UNALIGN (1 << 6) 62 63 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 64 { 65 if (IS_BROADWELL(gvt->dev_priv)) 66 return D_BDW; 67 else if (IS_SKYLAKE(gvt->dev_priv)) 68 return D_SKL; 69 70 return 0; 71 } 72 73 bool intel_gvt_match_device(struct intel_gvt *gvt, 74 unsigned long device) 75 { 76 return intel_gvt_get_device_type(gvt) & device; 77 } 78 79 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 80 void *p_data, unsigned int bytes) 81 { 82 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 83 } 84 85 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 86 void *p_data, unsigned int bytes) 87 { 88 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 89 } 90 91 static int new_mmio_info(struct intel_gvt *gvt, 92 u32 offset, u32 flags, u32 size, 93 u32 addr_mask, u32 ro_mask, u32 device, 94 void *read, void *write) 95 { 96 struct intel_gvt_mmio_info *info, *p; 97 u32 start, end, i; 98 99 if (!intel_gvt_match_device(gvt, device)) 100 return 0; 101 102 if (WARN_ON(!IS_ALIGNED(offset, 4))) 103 return -EINVAL; 104 105 start = offset; 106 end = offset + size; 107 108 for (i = start; i < end; i += 4) { 109 info = kzalloc(sizeof(*info), GFP_KERNEL); 110 if (!info) 111 return -ENOMEM; 112 113 info->offset = i; 114 p = intel_gvt_find_mmio_info(gvt, info->offset); 115 if (p) 116 gvt_err("dup mmio definition offset %x\n", 117 info->offset); 118 info->size = size; 119 info->length = (i + 4) < end ? 4 : (end - i); 120 info->addr_mask = addr_mask; 121 info->device = device; 122 info->read = read ? read : intel_vgpu_default_mmio_read; 123 info->write = write ? write : intel_vgpu_default_mmio_write; 124 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 125 INIT_HLIST_NODE(&info->node); 126 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 127 } 128 return 0; 129 } 130 131 static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) 132 { 133 int i; 134 135 reg &= ~GENMASK(11, 0); 136 for (i = 0; i < I915_NUM_ENGINES; i++) { 137 if (gvt->dev_priv->engine[i].mmio_base == reg) 138 return i; 139 } 140 return -1; 141 } 142 143 #define offset_to_fence_num(offset) \ 144 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 145 146 #define fence_num_to_offset(num) \ 147 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 148 149 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 150 unsigned int fence_num, void *p_data, unsigned int bytes) 151 { 152 if (fence_num >= vgpu_fence_sz(vgpu)) { 153 gvt_err("vgpu%d: found oob fence register access\n", 154 vgpu->id); 155 gvt_err("vgpu%d: total fence num %d access fence num %d\n", 156 vgpu->id, vgpu_fence_sz(vgpu), fence_num); 157 memset(p_data, 0, bytes); 158 } 159 return 0; 160 } 161 162 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 163 void *p_data, unsigned int bytes) 164 { 165 int ret; 166 167 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 168 p_data, bytes); 169 if (ret) 170 return ret; 171 read_vreg(vgpu, off, p_data, bytes); 172 return 0; 173 } 174 175 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 176 void *p_data, unsigned int bytes) 177 { 178 unsigned int fence_num = offset_to_fence_num(off); 179 int ret; 180 181 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 182 if (ret) 183 return ret; 184 write_vreg(vgpu, off, p_data, bytes); 185 186 intel_vgpu_write_fence(vgpu, fence_num, 187 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 188 return 0; 189 } 190 191 #define CALC_MODE_MASK_REG(old, new) \ 192 (((new) & GENMASK(31, 16)) \ 193 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 194 | ((new) & ((new) >> 16)))) 195 196 static int mul_force_wake_write(struct intel_vgpu *vgpu, 197 unsigned int offset, void *p_data, unsigned int bytes) 198 { 199 u32 old, new; 200 uint32_t ack_reg_offset; 201 202 old = vgpu_vreg(vgpu, offset); 203 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 204 205 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) { 206 switch (offset) { 207 case FORCEWAKE_RENDER_GEN9_REG: 208 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 209 break; 210 case FORCEWAKE_BLITTER_GEN9_REG: 211 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 212 break; 213 case FORCEWAKE_MEDIA_GEN9_REG: 214 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 215 break; 216 default: 217 /*should not hit here*/ 218 gvt_err("invalid forcewake offset 0x%x\n", offset); 219 return 1; 220 } 221 } else { 222 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 223 } 224 225 vgpu_vreg(vgpu, offset) = new; 226 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 227 return 0; 228 } 229 230 static int handle_device_reset(struct intel_vgpu *vgpu, unsigned int offset, 231 void *p_data, unsigned int bytes, unsigned long bitmap) 232 { 233 struct intel_gvt_workload_scheduler *scheduler = 234 &vgpu->gvt->scheduler; 235 236 vgpu->resetting = true; 237 238 if (scheduler->current_vgpu == vgpu) { 239 mutex_unlock(&vgpu->gvt->lock); 240 intel_gvt_wait_vgpu_idle(vgpu); 241 mutex_lock(&vgpu->gvt->lock); 242 } 243 244 intel_vgpu_reset_execlist(vgpu, bitmap); 245 246 vgpu->resetting = false; 247 248 return 0; 249 } 250 251 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 252 void *p_data, unsigned int bytes) 253 { 254 u32 data; 255 u64 bitmap = 0; 256 257 data = vgpu_vreg(vgpu, offset); 258 259 if (data & GEN6_GRDOM_FULL) { 260 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 261 bitmap = 0xff; 262 } 263 if (data & GEN6_GRDOM_RENDER) { 264 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 265 bitmap |= (1 << RCS); 266 } 267 if (data & GEN6_GRDOM_MEDIA) { 268 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 269 bitmap |= (1 << VCS); 270 } 271 if (data & GEN6_GRDOM_BLT) { 272 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 273 bitmap |= (1 << BCS); 274 } 275 if (data & GEN6_GRDOM_VECS) { 276 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 277 bitmap |= (1 << VECS); 278 } 279 if (data & GEN8_GRDOM_MEDIA2) { 280 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 281 if (HAS_BSD2(vgpu->gvt->dev_priv)) 282 bitmap |= (1 << VCS2); 283 } 284 return handle_device_reset(vgpu, offset, p_data, bytes, bitmap); 285 } 286 287 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 288 void *p_data, unsigned int bytes) 289 { 290 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 291 } 292 293 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 294 void *p_data, unsigned int bytes) 295 { 296 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 297 } 298 299 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 300 unsigned int offset, void *p_data, unsigned int bytes) 301 { 302 write_vreg(vgpu, offset, p_data, bytes); 303 304 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 305 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; 306 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 307 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 308 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 309 310 } else 311 vgpu_vreg(vgpu, PCH_PP_STATUS) &= 312 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 313 | PP_CYCLE_DELAY_ACTIVE); 314 return 0; 315 } 316 317 static int transconf_mmio_write(struct intel_vgpu *vgpu, 318 unsigned int offset, void *p_data, unsigned int bytes) 319 { 320 write_vreg(vgpu, offset, p_data, bytes); 321 322 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 323 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 324 else 325 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 326 return 0; 327 } 328 329 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 330 void *p_data, unsigned int bytes) 331 { 332 write_vreg(vgpu, offset, p_data, bytes); 333 334 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 335 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 336 else 337 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 338 339 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 340 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 341 else 342 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 343 344 return 0; 345 } 346 347 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 348 void *p_data, unsigned int bytes) 349 { 350 *(u32 *)p_data = (1 << 17); 351 return 0; 352 } 353 354 static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset, 355 void *p_data, unsigned int bytes) 356 { 357 *(u32 *)p_data = 3; 358 return 0; 359 } 360 361 static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset, 362 void *p_data, unsigned int bytes) 363 { 364 *(u32 *)p_data = (0x2f << 16); 365 return 0; 366 } 367 368 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 369 void *p_data, unsigned int bytes) 370 { 371 u32 data; 372 373 write_vreg(vgpu, offset, p_data, bytes); 374 data = vgpu_vreg(vgpu, offset); 375 376 if (data & PIPECONF_ENABLE) 377 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 378 else 379 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 380 intel_gvt_check_vblank_emulation(vgpu->gvt); 381 return 0; 382 } 383 384 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 385 void *p_data, unsigned int bytes) 386 { 387 write_vreg(vgpu, offset, p_data, bytes); 388 389 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 390 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 391 } else { 392 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 393 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 394 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) 395 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 396 } 397 return 0; 398 } 399 400 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 401 unsigned int offset, void *p_data, unsigned int bytes) 402 { 403 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 404 return 0; 405 } 406 407 #define FDI_LINK_TRAIN_PATTERN1 0 408 #define FDI_LINK_TRAIN_PATTERN2 1 409 410 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 411 { 412 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); 413 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 414 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); 415 416 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 417 (rx_ctl & FDI_RX_ENABLE) && 418 (rx_ctl & FDI_AUTO_TRAINING) && 419 (tx_ctl & DP_TP_CTL_ENABLE) && 420 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 421 return 1; 422 else 423 return 0; 424 } 425 426 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 427 enum pipe pipe, unsigned int train_pattern) 428 { 429 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 430 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 431 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 432 unsigned int fdi_iir_check_bits; 433 434 fdi_rx_imr = FDI_RX_IMR(pipe); 435 fdi_tx_ctl = FDI_TX_CTL(pipe); 436 fdi_rx_ctl = FDI_RX_CTL(pipe); 437 438 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 439 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 440 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 441 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 442 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 443 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 444 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 445 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 446 } else { 447 gvt_err("Invalid train pattern %d\n", train_pattern); 448 return -EINVAL; 449 } 450 451 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 452 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 453 454 /* If imr bit has been masked */ 455 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 456 return 0; 457 458 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 459 == fdi_tx_check_bits) 460 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 461 == fdi_rx_check_bits)) 462 return 1; 463 else 464 return 0; 465 } 466 467 #define INVALID_INDEX (~0U) 468 469 static unsigned int calc_index(unsigned int offset, unsigned int start, 470 unsigned int next, unsigned int end, i915_reg_t i915_end) 471 { 472 unsigned int range = next - start; 473 474 if (!end) 475 end = i915_mmio_reg_offset(i915_end); 476 if (offset < start || offset > end) 477 return INVALID_INDEX; 478 offset -= start; 479 return offset / range; 480 } 481 482 #define FDI_RX_CTL_TO_PIPE(offset) \ 483 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 484 485 #define FDI_TX_CTL_TO_PIPE(offset) \ 486 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 487 488 #define FDI_RX_IMR_TO_PIPE(offset) \ 489 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 490 491 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 492 unsigned int offset, void *p_data, unsigned int bytes) 493 { 494 i915_reg_t fdi_rx_iir; 495 unsigned int index; 496 int ret; 497 498 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 499 index = FDI_RX_CTL_TO_PIPE(offset); 500 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 501 index = FDI_TX_CTL_TO_PIPE(offset); 502 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 503 index = FDI_RX_IMR_TO_PIPE(offset); 504 else { 505 gvt_err("Unsupport registers %x\n", offset); 506 return -EINVAL; 507 } 508 509 write_vreg(vgpu, offset, p_data, bytes); 510 511 fdi_rx_iir = FDI_RX_IIR(index); 512 513 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 514 if (ret < 0) 515 return ret; 516 if (ret) 517 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 518 519 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 520 if (ret < 0) 521 return ret; 522 if (ret) 523 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 524 525 if (offset == _FDI_RXA_CTL) 526 if (fdi_auto_training_started(vgpu)) 527 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= 528 DP_TP_STATUS_AUTOTRAIN_DONE; 529 return 0; 530 } 531 532 #define DP_TP_CTL_TO_PORT(offset) \ 533 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 534 535 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 536 void *p_data, unsigned int bytes) 537 { 538 i915_reg_t status_reg; 539 unsigned int index; 540 u32 data; 541 542 write_vreg(vgpu, offset, p_data, bytes); 543 544 index = DP_TP_CTL_TO_PORT(offset); 545 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 546 if (data == 0x2) { 547 status_reg = DP_TP_STATUS(index); 548 vgpu_vreg(vgpu, status_reg) |= (1 << 25); 549 } 550 return 0; 551 } 552 553 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 554 unsigned int offset, void *p_data, unsigned int bytes) 555 { 556 u32 reg_val; 557 u32 sticky_mask; 558 559 reg_val = *((u32 *)p_data); 560 sticky_mask = GENMASK(27, 26) | (1 << 24); 561 562 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 563 (vgpu_vreg(vgpu, offset) & sticky_mask); 564 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 565 return 0; 566 } 567 568 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 569 unsigned int offset, void *p_data, unsigned int bytes) 570 { 571 u32 data; 572 573 write_vreg(vgpu, offset, p_data, bytes); 574 data = vgpu_vreg(vgpu, offset); 575 576 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 577 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 578 return 0; 579 } 580 581 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 582 unsigned int offset, void *p_data, unsigned int bytes) 583 { 584 u32 data; 585 586 write_vreg(vgpu, offset, p_data, bytes); 587 data = vgpu_vreg(vgpu, offset); 588 589 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 590 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 591 else 592 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 593 return 0; 594 } 595 596 #define DSPSURF_TO_PIPE(offset) \ 597 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 598 599 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 600 void *p_data, unsigned int bytes) 601 { 602 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 603 unsigned int index = DSPSURF_TO_PIPE(offset); 604 i915_reg_t surflive_reg = DSPSURFLIVE(index); 605 int flip_event[] = { 606 [PIPE_A] = PRIMARY_A_FLIP_DONE, 607 [PIPE_B] = PRIMARY_B_FLIP_DONE, 608 [PIPE_C] = PRIMARY_C_FLIP_DONE, 609 }; 610 611 write_vreg(vgpu, offset, p_data, bytes); 612 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 613 614 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 615 return 0; 616 } 617 618 #define SPRSURF_TO_PIPE(offset) \ 619 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 620 621 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 622 void *p_data, unsigned int bytes) 623 { 624 unsigned int index = SPRSURF_TO_PIPE(offset); 625 i915_reg_t surflive_reg = SPRSURFLIVE(index); 626 int flip_event[] = { 627 [PIPE_A] = SPRITE_A_FLIP_DONE, 628 [PIPE_B] = SPRITE_B_FLIP_DONE, 629 [PIPE_C] = SPRITE_C_FLIP_DONE, 630 }; 631 632 write_vreg(vgpu, offset, p_data, bytes); 633 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 634 635 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 636 return 0; 637 } 638 639 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 640 unsigned int reg) 641 { 642 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 643 enum intel_gvt_event_type event; 644 645 if (reg == _DPA_AUX_CH_CTL) 646 event = AUX_CHANNEL_A; 647 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 648 event = AUX_CHANNEL_B; 649 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 650 event = AUX_CHANNEL_C; 651 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 652 event = AUX_CHANNEL_D; 653 else { 654 WARN_ON(true); 655 return -EINVAL; 656 } 657 658 intel_vgpu_trigger_virtual_event(vgpu, event); 659 return 0; 660 } 661 662 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 663 unsigned int reg, int len, bool data_valid) 664 { 665 /* mark transaction done */ 666 value |= DP_AUX_CH_CTL_DONE; 667 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 668 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 669 670 if (data_valid) 671 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 672 else 673 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 674 675 /* message size */ 676 value &= ~(0xf << 20); 677 value |= (len << 20); 678 vgpu_vreg(vgpu, reg) = value; 679 680 if (value & DP_AUX_CH_CTL_INTERRUPT) 681 return trigger_aux_channel_interrupt(vgpu, reg); 682 return 0; 683 } 684 685 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 686 uint8_t t) 687 { 688 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 689 /* training pattern 1 for CR */ 690 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 691 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 692 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 693 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 694 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 695 DPCD_TRAINING_PATTERN_2) { 696 /* training pattern 2 for EQ */ 697 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 698 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 699 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 700 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 701 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 702 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 703 /* set INTERLANE_ALIGN_DONE */ 704 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 705 DPCD_INTERLANE_ALIGN_DONE; 706 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 707 DPCD_LINK_TRAINING_DISABLED) { 708 /* finish link training */ 709 /* set sink status as synchronized */ 710 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 711 } 712 } 713 714 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 715 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 716 717 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 718 719 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 720 721 #define dpy_is_valid_port(port) \ 722 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 723 724 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 725 unsigned int offset, void *p_data, unsigned int bytes) 726 { 727 struct intel_vgpu_display *display = &vgpu->display; 728 int msg, addr, ctrl, op, len; 729 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 730 struct intel_vgpu_dpcd_data *dpcd = NULL; 731 struct intel_vgpu_port *port = NULL; 732 u32 data; 733 734 if (!dpy_is_valid_port(port_index)) { 735 gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id); 736 return 0; 737 } 738 739 write_vreg(vgpu, offset, p_data, bytes); 740 data = vgpu_vreg(vgpu, offset); 741 742 if (IS_SKYLAKE(vgpu->gvt->dev_priv) && 743 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 744 /* SKL DPB/C/D aux ctl register changed */ 745 return 0; 746 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 747 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 748 /* write to the data registers */ 749 return 0; 750 } 751 752 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 753 /* just want to clear the sticky bits */ 754 vgpu_vreg(vgpu, offset) = 0; 755 return 0; 756 } 757 758 port = &display->ports[port_index]; 759 dpcd = port->dpcd; 760 761 /* read out message from DATA1 register */ 762 msg = vgpu_vreg(vgpu, offset + 4); 763 addr = (msg >> 8) & 0xffff; 764 ctrl = (msg >> 24) & 0xff; 765 len = msg & 0xff; 766 op = ctrl >> 4; 767 768 if (op == GVT_AUX_NATIVE_WRITE) { 769 int t; 770 uint8_t buf[16]; 771 772 if ((addr + len + 1) >= DPCD_SIZE) { 773 /* 774 * Write request exceeds what we supported, 775 * DCPD spec: When a Source Device is writing a DPCD 776 * address not supported by the Sink Device, the Sink 777 * Device shall reply with AUX NACK and “M” equal to 778 * zero. 779 */ 780 781 /* NAK the write */ 782 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 783 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 784 return 0; 785 } 786 787 /* 788 * Write request format: (command + address) occupies 789 * 3 bytes, followed by (len + 1) bytes of data. 790 */ 791 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 792 return -EINVAL; 793 794 /* unpack data from vreg to buf */ 795 for (t = 0; t < 4; t++) { 796 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 797 798 buf[t * 4] = (r >> 24) & 0xff; 799 buf[t * 4 + 1] = (r >> 16) & 0xff; 800 buf[t * 4 + 2] = (r >> 8) & 0xff; 801 buf[t * 4 + 3] = r & 0xff; 802 } 803 804 /* write to virtual DPCD */ 805 if (dpcd && dpcd->data_valid) { 806 for (t = 0; t <= len; t++) { 807 int p = addr + t; 808 809 dpcd->data[p] = buf[t]; 810 /* check for link training */ 811 if (p == DPCD_TRAINING_PATTERN_SET) 812 dp_aux_ch_ctl_link_training(dpcd, 813 buf[t]); 814 } 815 } 816 817 /* ACK the write */ 818 vgpu_vreg(vgpu, offset + 4) = 0; 819 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 820 dpcd && dpcd->data_valid); 821 return 0; 822 } 823 824 if (op == GVT_AUX_NATIVE_READ) { 825 int idx, i, ret = 0; 826 827 if ((addr + len + 1) >= DPCD_SIZE) { 828 /* 829 * read request exceeds what we supported 830 * DPCD spec: A Sink Device receiving a Native AUX CH 831 * read request for an unsupported DPCD address must 832 * reply with an AUX ACK and read data set equal to 833 * zero instead of replying with AUX NACK. 834 */ 835 836 /* ACK the READ*/ 837 vgpu_vreg(vgpu, offset + 4) = 0; 838 vgpu_vreg(vgpu, offset + 8) = 0; 839 vgpu_vreg(vgpu, offset + 12) = 0; 840 vgpu_vreg(vgpu, offset + 16) = 0; 841 vgpu_vreg(vgpu, offset + 20) = 0; 842 843 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 844 true); 845 return 0; 846 } 847 848 for (idx = 1; idx <= 5; idx++) { 849 /* clear the data registers */ 850 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 851 } 852 853 /* 854 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 855 */ 856 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 857 return -EINVAL; 858 859 /* read from virtual DPCD to vreg */ 860 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 861 if (dpcd && dpcd->data_valid) { 862 for (i = 1; i <= (len + 1); i++) { 863 int t; 864 865 t = dpcd->data[addr + i - 1]; 866 t <<= (24 - 8 * (i % 4)); 867 ret |= t; 868 869 if ((i % 4 == 3) || (i == (len + 1))) { 870 vgpu_vreg(vgpu, offset + 871 (i / 4 + 1) * 4) = ret; 872 ret = 0; 873 } 874 } 875 } 876 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 877 dpcd && dpcd->data_valid); 878 return 0; 879 } 880 881 /* i2c transaction starts */ 882 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 883 884 if (data & DP_AUX_CH_CTL_INTERRUPT) 885 trigger_aux_channel_interrupt(vgpu, offset); 886 return 0; 887 } 888 889 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 890 void *p_data, unsigned int bytes) 891 { 892 bool vga_disable; 893 894 write_vreg(vgpu, offset, p_data, bytes); 895 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 896 897 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 898 vga_disable ? "Disable" : "Enable"); 899 return 0; 900 } 901 902 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 903 unsigned int sbi_offset) 904 { 905 struct intel_vgpu_display *display = &vgpu->display; 906 int num = display->sbi.number; 907 int i; 908 909 for (i = 0; i < num; ++i) 910 if (display->sbi.registers[i].offset == sbi_offset) 911 break; 912 913 if (i == num) 914 return 0; 915 916 return display->sbi.registers[i].value; 917 } 918 919 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 920 unsigned int offset, u32 value) 921 { 922 struct intel_vgpu_display *display = &vgpu->display; 923 int num = display->sbi.number; 924 int i; 925 926 for (i = 0; i < num; ++i) { 927 if (display->sbi.registers[i].offset == offset) 928 break; 929 } 930 931 if (i == num) { 932 if (num == SBI_REG_MAX) { 933 gvt_err("vgpu%d: SBI caching meets maximum limits\n", 934 vgpu->id); 935 return; 936 } 937 display->sbi.number++; 938 } 939 940 display->sbi.registers[i].offset = offset; 941 display->sbi.registers[i].value = value; 942 } 943 944 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 945 void *p_data, unsigned int bytes) 946 { 947 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 948 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 949 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 950 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 951 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 952 sbi_offset); 953 } 954 read_vreg(vgpu, offset, p_data, bytes); 955 return 0; 956 } 957 958 static bool sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 959 void *p_data, unsigned int bytes) 960 { 961 u32 data; 962 963 write_vreg(vgpu, offset, p_data, bytes); 964 data = vgpu_vreg(vgpu, offset); 965 966 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 967 data |= SBI_READY; 968 969 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 970 data |= SBI_RESPONSE_SUCCESS; 971 972 vgpu_vreg(vgpu, offset) = data; 973 974 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 975 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 976 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 977 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 978 979 write_virtual_sbi_register(vgpu, sbi_offset, 980 vgpu_vreg(vgpu, SBI_DATA)); 981 } 982 return 0; 983 } 984 985 #define _vgtif_reg(x) \ 986 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 987 988 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 989 void *p_data, unsigned int bytes) 990 { 991 bool invalid_read = false; 992 993 read_vreg(vgpu, offset, p_data, bytes); 994 995 switch (offset) { 996 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 997 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 998 invalid_read = true; 999 break; 1000 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1001 _vgtif_reg(avail_rs.fence_num): 1002 if (offset + bytes > 1003 _vgtif_reg(avail_rs.fence_num) + 4) 1004 invalid_read = true; 1005 break; 1006 case 0x78010: /* vgt_caps */ 1007 case 0x7881c: 1008 break; 1009 default: 1010 invalid_read = true; 1011 break; 1012 } 1013 if (invalid_read) 1014 gvt_err("invalid pvinfo read: [%x:%x] = %x\n", 1015 offset, bytes, *(u32 *)p_data); 1016 return 0; 1017 } 1018 1019 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1020 { 1021 int ret = 0; 1022 1023 switch (notification) { 1024 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1025 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); 1026 break; 1027 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1028 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); 1029 break; 1030 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1031 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); 1032 break; 1033 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1034 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); 1035 break; 1036 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1037 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1038 case 1: /* Remove this in guest driver. */ 1039 break; 1040 default: 1041 gvt_err("Invalid PV notification %d\n", notification); 1042 } 1043 return ret; 1044 } 1045 1046 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1047 { 1048 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1049 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1050 char *env[3] = {NULL, NULL, NULL}; 1051 char vmid_str[20]; 1052 char display_ready_str[20]; 1053 1054 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready); 1055 env[0] = display_ready_str; 1056 1057 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1058 env[1] = vmid_str; 1059 1060 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1061 } 1062 1063 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1064 void *p_data, unsigned int bytes) 1065 { 1066 u32 data; 1067 int ret; 1068 1069 write_vreg(vgpu, offset, p_data, bytes); 1070 data = vgpu_vreg(vgpu, offset); 1071 1072 switch (offset) { 1073 case _vgtif_reg(display_ready): 1074 send_display_ready_uevent(vgpu, data ? 1 : 0); 1075 break; 1076 case _vgtif_reg(g2v_notify): 1077 ret = handle_g2v_notification(vgpu, data); 1078 break; 1079 /* add xhot and yhot to handled list to avoid error log */ 1080 case 0x78830: 1081 case 0x78834: 1082 case _vgtif_reg(pdp[0].lo): 1083 case _vgtif_reg(pdp[0].hi): 1084 case _vgtif_reg(pdp[1].lo): 1085 case _vgtif_reg(pdp[1].hi): 1086 case _vgtif_reg(pdp[2].lo): 1087 case _vgtif_reg(pdp[2].hi): 1088 case _vgtif_reg(pdp[3].lo): 1089 case _vgtif_reg(pdp[3].hi): 1090 case _vgtif_reg(execlist_context_descriptor_lo): 1091 case _vgtif_reg(execlist_context_descriptor_hi): 1092 break; 1093 default: 1094 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n", 1095 offset, bytes, data); 1096 break; 1097 } 1098 return 0; 1099 } 1100 1101 static int pf_write(struct intel_vgpu *vgpu, 1102 unsigned int offset, void *p_data, unsigned int bytes) 1103 { 1104 u32 val = *(u32 *)p_data; 1105 1106 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1107 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1108 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1109 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1110 vgpu->id); 1111 return 0; 1112 } 1113 1114 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1115 } 1116 1117 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1118 unsigned int offset, void *p_data, unsigned int bytes) 1119 { 1120 write_vreg(vgpu, offset, p_data, bytes); 1121 1122 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) 1123 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; 1124 else 1125 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; 1126 return 0; 1127 } 1128 1129 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1130 unsigned int offset, void *p_data, unsigned int bytes) 1131 { 1132 write_vreg(vgpu, offset, p_data, bytes); 1133 1134 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1135 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1136 return 0; 1137 } 1138 1139 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1140 void *p_data, unsigned int bytes) 1141 { 1142 u32 mode = *(u32 *)p_data; 1143 1144 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1145 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n", 1146 vgpu->id); 1147 return 0; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1154 void *p_data, unsigned int bytes) 1155 { 1156 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1157 u32 trtte = *(u32 *)p_data; 1158 1159 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1160 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1161 vgpu->id); 1162 return -EINVAL; 1163 } 1164 write_vreg(vgpu, offset, p_data, bytes); 1165 /* TRTTE is not per-context */ 1166 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1167 1168 return 0; 1169 } 1170 1171 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1172 void *p_data, unsigned int bytes) 1173 { 1174 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1175 u32 val = *(u32 *)p_data; 1176 1177 if (val & 1) { 1178 /* unblock hw logic */ 1179 I915_WRITE(_MMIO(offset), val); 1180 } 1181 write_vreg(vgpu, offset, p_data, bytes); 1182 return 0; 1183 } 1184 1185 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1186 void *p_data, unsigned int bytes) 1187 { 1188 u32 v = 0; 1189 1190 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1191 v |= (1 << 0); 1192 1193 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1194 v |= (1 << 8); 1195 1196 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1197 v |= (1 << 16); 1198 1199 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1200 v |= (1 << 24); 1201 1202 vgpu_vreg(vgpu, offset) = v; 1203 1204 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1205 } 1206 1207 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1208 void *p_data, unsigned int bytes) 1209 { 1210 u32 value = *(u32 *)p_data; 1211 u32 cmd = value & 0xff; 1212 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); 1213 1214 switch (cmd) { 1215 case 0x6: 1216 /** 1217 * "Read memory latency" command on gen9. 1218 * Below memory latency values are read 1219 * from skylake platform. 1220 */ 1221 if (!*data0) 1222 *data0 = 0x1e1a1100; 1223 else 1224 *data0 = 0x61514b3d; 1225 break; 1226 case 0x5: 1227 *data0 |= 0x1; 1228 break; 1229 } 1230 1231 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1232 vgpu->id, value, *data0); 1233 1234 value &= ~(1 << 31); 1235 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1236 } 1237 1238 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1239 unsigned int offset, void *p_data, unsigned int bytes) 1240 { 1241 u32 v = *(u32 *)p_data; 1242 1243 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1244 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1245 v |= (v >> 1); 1246 1247 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1248 } 1249 1250 static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1251 void *p_data, unsigned int bytes) 1252 { 1253 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1254 i915_reg_t reg = {.reg = offset}; 1255 1256 switch (offset) { 1257 case 0x4ddc: 1258 vgpu_vreg(vgpu, offset) = 0x8000003c; 1259 break; 1260 case 0x42080: 1261 vgpu_vreg(vgpu, offset) = 0x8000; 1262 break; 1263 default: 1264 return -EINVAL; 1265 } 1266 1267 /** 1268 * TODO: need detect stepping info after gvt contain such information 1269 * 0x4ddc enabled after C0, 0x42080 enabled after E0. 1270 */ 1271 I915_WRITE(reg, vgpu_vreg(vgpu, offset)); 1272 return 0; 1273 } 1274 1275 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1276 void *p_data, unsigned int bytes) 1277 { 1278 u32 v = *(u32 *)p_data; 1279 1280 /* other bits are MBZ. */ 1281 v &= (1 << 31) | (1 << 30); 1282 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1283 1284 vgpu_vreg(vgpu, offset) = v; 1285 1286 return 0; 1287 } 1288 1289 static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu, 1290 unsigned int offset, void *p_data, unsigned int bytes) 1291 { 1292 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1293 1294 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1295 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1296 } 1297 1298 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1299 void *p_data, unsigned int bytes) 1300 { 1301 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1302 struct intel_vgpu_execlist *execlist; 1303 u32 data = *(u32 *)p_data; 1304 int ret; 1305 1306 if (WARN_ON(ring_id < 0)) 1307 return -EINVAL; 1308 1309 execlist = &vgpu->execlist[ring_id]; 1310 1311 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data; 1312 if (execlist->elsp_dwords.index == 3) 1313 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1314 1315 ++execlist->elsp_dwords.index; 1316 execlist->elsp_dwords.index &= 0x3; 1317 return 0; 1318 } 1319 1320 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1321 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 1322 f, s, am, rm, d, r, w); \ 1323 if (ret) \ 1324 return ret; \ 1325 } while (0) 1326 1327 #define MMIO_D(reg, d) \ 1328 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1329 1330 #define MMIO_DH(reg, d, r, w) \ 1331 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1332 1333 #define MMIO_DFH(reg, d, f, r, w) \ 1334 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1335 1336 #define MMIO_GM(reg, d, r, w) \ 1337 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1338 1339 #define MMIO_RO(reg, d, f, rm, r, w) \ 1340 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1341 1342 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1343 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1344 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1345 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1346 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1347 } while (0) 1348 1349 #define MMIO_RING_D(prefix, d) \ 1350 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1351 1352 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1353 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1354 1355 #define MMIO_RING_GM(prefix, d, r, w) \ 1356 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1357 1358 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1359 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1360 1361 static int init_generic_mmio_info(struct intel_gvt *gvt) 1362 { 1363 struct drm_i915_private *dev_priv = gvt->dev_priv; 1364 int ret; 1365 1366 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1367 1368 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1369 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1370 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1371 MMIO_D(SDEISR, D_ALL); 1372 1373 MMIO_RING_D(RING_HWSTAM, D_ALL); 1374 1375 MMIO_GM(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1376 MMIO_GM(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1377 MMIO_GM(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1378 MMIO_GM(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1379 1380 #define RING_REG(base) (base + 0x28) 1381 MMIO_RING_D(RING_REG, D_ALL); 1382 #undef RING_REG 1383 1384 #define RING_REG(base) (base + 0x134) 1385 MMIO_RING_D(RING_REG, D_ALL); 1386 #undef RING_REG 1387 1388 MMIO_GM(0x2148, D_ALL, NULL, NULL); 1389 MMIO_GM(CCID, D_ALL, NULL, NULL); 1390 MMIO_GM(0x12198, D_ALL, NULL, NULL); 1391 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1392 1393 MMIO_RING_D(RING_TAIL, D_ALL); 1394 MMIO_RING_D(RING_HEAD, D_ALL); 1395 MMIO_RING_D(RING_CTL, D_ALL); 1396 MMIO_RING_D(RING_ACTHD, D_ALL); 1397 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 1398 1399 /* RING MODE */ 1400 #define RING_REG(base) (base + 0x29c) 1401 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK, NULL, NULL); 1402 #undef RING_REG 1403 1404 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1405 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL); 1406 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1407 ring_timestamp_mmio_read, NULL); 1408 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1409 ring_timestamp_mmio_read, NULL); 1410 1411 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1412 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL); 1413 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK, NULL, NULL); 1414 1415 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL); 1416 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL); 1417 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK, NULL, NULL); 1418 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK, NULL, NULL); 1419 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK, NULL, NULL); 1420 MMIO_D(GAM_ECOCHK, D_ALL); 1421 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK, NULL, NULL); 1422 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK, NULL, NULL); 1423 MMIO_D(0x9030, D_ALL); 1424 MMIO_D(0x20a0, D_ALL); 1425 MMIO_D(0x2420, D_ALL); 1426 MMIO_D(0x2430, D_ALL); 1427 MMIO_D(0x2434, D_ALL); 1428 MMIO_D(0x2438, D_ALL); 1429 MMIO_D(0x243c, D_ALL); 1430 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK, NULL, NULL); 1431 MMIO_DFH(0xe184, D_ALL, F_MODE_MASK, NULL, NULL); 1432 MMIO_DFH(0xe100, D_ALL, F_MODE_MASK, NULL, NULL); 1433 1434 /* display */ 1435 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1436 MMIO_D(0x602a0, D_ALL); 1437 1438 MMIO_D(0x65050, D_ALL); 1439 MMIO_D(0x650b4, D_ALL); 1440 1441 MMIO_D(0xc4040, D_ALL); 1442 MMIO_D(DERRMR, D_ALL); 1443 1444 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1445 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1446 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1447 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1448 1449 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1450 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1451 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1452 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1453 1454 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1455 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1456 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1457 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1458 1459 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1460 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1461 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1462 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1463 1464 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1465 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1466 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1467 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1468 1469 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1470 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1471 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1472 1473 MMIO_D(CURPOS(PIPE_A), D_ALL); 1474 MMIO_D(CURPOS(PIPE_B), D_ALL); 1475 MMIO_D(CURPOS(PIPE_C), D_ALL); 1476 1477 MMIO_D(CURBASE(PIPE_A), D_ALL); 1478 MMIO_D(CURBASE(PIPE_B), D_ALL); 1479 MMIO_D(CURBASE(PIPE_C), D_ALL); 1480 1481 MMIO_D(0x700ac, D_ALL); 1482 MMIO_D(0x710ac, D_ALL); 1483 MMIO_D(0x720ac, D_ALL); 1484 1485 MMIO_D(0x70090, D_ALL); 1486 MMIO_D(0x70094, D_ALL); 1487 MMIO_D(0x70098, D_ALL); 1488 MMIO_D(0x7009c, D_ALL); 1489 1490 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1491 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1492 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1493 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1494 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1495 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1496 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1497 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1498 1499 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1500 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1501 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1502 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1503 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1504 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1505 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1506 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1507 1508 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1509 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1510 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1511 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1512 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1513 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1514 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1515 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1516 1517 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1518 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1519 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1520 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1521 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1522 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1523 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1524 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1525 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1526 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1527 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1528 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1529 1530 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1531 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1532 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1533 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1534 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1535 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1536 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1537 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1538 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1539 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1540 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1541 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1542 1543 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1544 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1545 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1546 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1547 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1548 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1549 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1550 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1551 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1552 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1553 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1554 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1555 1556 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1557 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1558 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1559 1560 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1561 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1562 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1563 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1564 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1565 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1566 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1567 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1568 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1569 1570 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1571 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1572 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1573 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1574 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1575 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1576 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1577 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1578 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1579 1580 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1581 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1582 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1583 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1584 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1585 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1586 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1587 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1588 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1589 1590 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1591 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1592 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1593 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1594 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1595 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1596 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1597 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1598 1599 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1600 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1601 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1602 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1603 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1604 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1605 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1606 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1607 1608 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1609 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1610 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1611 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1612 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1613 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1614 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1615 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1616 1617 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1618 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1619 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1620 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1621 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1622 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1623 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1624 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1625 1626 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1627 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1628 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1629 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1630 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1631 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1632 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1633 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1634 1635 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1636 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1637 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1638 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1639 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1640 1641 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1642 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1643 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1644 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1645 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1646 1647 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1648 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1649 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1650 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1651 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1652 1653 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1654 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1655 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1656 MMIO_D(WM1_LP_ILK, D_ALL); 1657 MMIO_D(WM2_LP_ILK, D_ALL); 1658 MMIO_D(WM3_LP_ILK, D_ALL); 1659 MMIO_D(WM1S_LP_ILK, D_ALL); 1660 MMIO_D(WM2S_LP_IVB, D_ALL); 1661 MMIO_D(WM3S_LP_IVB, D_ALL); 1662 1663 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1664 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1665 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1666 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1667 1668 MMIO_D(0x48268, D_ALL); 1669 1670 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1671 gmbus_mmio_write); 1672 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1673 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1674 1675 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1676 dp_aux_ch_ctl_mmio_write); 1677 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1678 dp_aux_ch_ctl_mmio_write); 1679 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1680 dp_aux_ch_ctl_mmio_write); 1681 1682 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write); 1683 1684 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); 1685 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); 1686 1687 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1688 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1689 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1690 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1691 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1692 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1693 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1694 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1695 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1696 1697 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 1698 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 1699 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 1700 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 1701 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 1702 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 1703 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 1704 1705 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 1706 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 1707 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 1708 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 1709 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 1710 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 1711 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 1712 1713 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 1714 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 1715 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 1716 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 1717 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 1718 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 1719 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 1720 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 1721 1722 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 1723 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 1724 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 1725 1726 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 1727 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 1728 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 1729 1730 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 1731 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 1732 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 1733 1734 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 1735 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 1736 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 1737 1738 MMIO_D(_FDI_RXA_MISC, D_ALL); 1739 MMIO_D(_FDI_RXB_MISC, D_ALL); 1740 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 1741 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 1742 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 1743 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 1744 1745 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 1746 MMIO_D(PCH_PP_DIVISOR, D_ALL); 1747 MMIO_D(PCH_PP_STATUS, D_ALL); 1748 MMIO_D(PCH_LVDS, D_ALL); 1749 MMIO_D(_PCH_DPLL_A, D_ALL); 1750 MMIO_D(_PCH_DPLL_B, D_ALL); 1751 MMIO_D(_PCH_FPA0, D_ALL); 1752 MMIO_D(_PCH_FPA1, D_ALL); 1753 MMIO_D(_PCH_FPB0, D_ALL); 1754 MMIO_D(_PCH_FPB1, D_ALL); 1755 MMIO_D(PCH_DREF_CONTROL, D_ALL); 1756 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 1757 MMIO_D(PCH_DPLL_SEL, D_ALL); 1758 1759 MMIO_D(0x61208, D_ALL); 1760 MMIO_D(0x6120c, D_ALL); 1761 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 1762 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 1763 1764 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); 1765 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); 1766 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); 1767 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); 1768 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL); 1769 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL); 1770 1771 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 1772 PORTA_HOTPLUG_STATUS_MASK 1773 | PORTB_HOTPLUG_STATUS_MASK 1774 | PORTC_HOTPLUG_STATUS_MASK 1775 | PORTD_HOTPLUG_STATUS_MASK, 1776 NULL, NULL); 1777 1778 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 1779 MMIO_D(FUSE_STRAP, D_ALL); 1780 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 1781 1782 MMIO_D(DISP_ARB_CTL, D_ALL); 1783 MMIO_D(DISP_ARB_CTL2, D_ALL); 1784 1785 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 1786 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 1787 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 1788 1789 MMIO_D(SOUTH_CHICKEN1, D_ALL); 1790 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 1791 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 1792 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 1793 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 1794 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 1795 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 1796 1797 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 1798 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 1799 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 1800 MMIO_D(ILK_DPFC_STATUS, D_ALL); 1801 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 1802 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 1803 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 1804 1805 MMIO_D(IPS_CTL, D_ALL); 1806 1807 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 1808 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 1809 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 1810 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 1811 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 1812 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 1813 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 1814 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 1815 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 1816 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 1817 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 1818 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 1819 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 1820 1821 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 1822 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 1823 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 1824 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 1825 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 1826 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 1827 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 1828 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 1829 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 1830 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 1831 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 1832 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 1833 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 1834 1835 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 1836 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 1837 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 1838 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 1839 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 1840 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 1841 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 1842 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 1843 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 1844 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 1845 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 1846 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 1847 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 1848 1849 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 1850 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 1851 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1852 1853 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 1854 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 1855 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1856 1857 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 1858 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 1859 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1860 1861 MMIO_D(0x60110, D_ALL); 1862 MMIO_D(0x61110, D_ALL); 1863 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1864 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1865 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1866 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1867 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1868 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1869 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1870 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1871 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1872 1873 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 1874 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 1875 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 1876 MMIO_D(SPLL_CTL, D_ALL); 1877 MMIO_D(_WRPLL_CTL1, D_ALL); 1878 MMIO_D(_WRPLL_CTL2, D_ALL); 1879 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 1880 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 1881 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 1882 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 1883 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 1884 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 1885 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 1886 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 1887 1888 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 1889 MMIO_D(0x46508, D_ALL); 1890 1891 MMIO_D(0x49080, D_ALL); 1892 MMIO_D(0x49180, D_ALL); 1893 MMIO_D(0x49280, D_ALL); 1894 1895 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1896 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1897 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1898 1899 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 1900 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 1901 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 1902 1903 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 1904 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 1905 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 1906 1907 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 1908 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 1909 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 1910 1911 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 1912 MMIO_D(SBI_ADDR, D_ALL); 1913 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 1914 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 1915 MMIO_D(PIXCLK_GATE, D_ALL); 1916 1917 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, 1918 dp_aux_ch_ctl_mmio_write); 1919 1920 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1921 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1922 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1923 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1924 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1925 1926 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 1927 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 1928 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 1929 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 1930 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 1931 1932 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 1933 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 1934 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 1935 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 1936 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 1937 1938 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1939 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1940 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1941 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1942 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1943 1944 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 1945 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 1946 1947 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 1948 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 1949 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 1950 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 1951 1952 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 1953 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 1954 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 1955 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 1956 1957 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 1958 MMIO_D(FORCEWAKE_ACK, D_ALL); 1959 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 1960 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 1961 MMIO_D(GTFIFODBG, D_ALL); 1962 MMIO_D(GTFIFOCTL, D_ALL); 1963 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 1964 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL); 1965 MMIO_D(ECOBUS, D_ALL); 1966 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 1967 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 1968 MMIO_D(GEN6_RPNSWREQ, D_ALL); 1969 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 1970 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 1971 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 1972 MMIO_D(GEN6_RPSTAT1, D_ALL); 1973 MMIO_D(GEN6_RP_CONTROL, D_ALL); 1974 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 1975 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 1976 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 1977 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 1978 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 1979 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 1980 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 1981 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 1982 MMIO_D(GEN6_RP_UP_EI, D_ALL); 1983 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 1984 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 1985 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 1986 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 1987 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 1988 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 1989 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 1990 MMIO_D(GEN6_RC_SLEEP, D_ALL); 1991 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 1992 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 1993 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 1994 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 1995 MMIO_D(GEN6_PMINTRMSK, D_ALL); 1996 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1997 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1998 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1999 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2000 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2001 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2002 2003 MMIO_D(RSTDBYCTL, D_ALL); 2004 2005 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2006 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2007 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write); 2008 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2009 2010 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL); 2011 2012 MMIO_D(TILECTL, D_ALL); 2013 2014 MMIO_D(GEN6_UCGCTL1, D_ALL); 2015 MMIO_D(GEN6_UCGCTL2, D_ALL); 2016 2017 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2018 2019 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_SKL); 2020 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2021 MMIO_D(0x13812c, D_ALL); 2022 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2023 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2024 MMIO_D(HSW_IDICR, D_ALL); 2025 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2026 2027 MMIO_D(0x3c, D_ALL); 2028 MMIO_D(0x860, D_ALL); 2029 MMIO_D(ECOSKPD, D_ALL); 2030 MMIO_D(0x121d0, D_ALL); 2031 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2032 MMIO_D(0x41d0, D_ALL); 2033 MMIO_D(GAC_ECO_BITS, D_ALL); 2034 MMIO_D(0x6200, D_ALL); 2035 MMIO_D(0x6204, D_ALL); 2036 MMIO_D(0x6208, D_ALL); 2037 MMIO_D(0x7118, D_ALL); 2038 MMIO_D(0x7180, D_ALL); 2039 MMIO_D(0x7408, D_ALL); 2040 MMIO_D(0x7c00, D_ALL); 2041 MMIO_D(GEN6_MBCTL, D_ALL); 2042 MMIO_D(0x911c, D_ALL); 2043 MMIO_D(0x9120, D_ALL); 2044 2045 MMIO_D(GAB_CTL, D_ALL); 2046 MMIO_D(0x48800, D_ALL); 2047 MMIO_D(0xce044, D_ALL); 2048 MMIO_D(0xe6500, D_ALL); 2049 MMIO_D(0xe6504, D_ALL); 2050 MMIO_D(0xe6600, D_ALL); 2051 MMIO_D(0xe6604, D_ALL); 2052 MMIO_D(0xe6700, D_ALL); 2053 MMIO_D(0xe6704, D_ALL); 2054 MMIO_D(0xe6800, D_ALL); 2055 MMIO_D(0xe6804, D_ALL); 2056 MMIO_D(PCH_GMBUS4, D_ALL); 2057 MMIO_D(PCH_GMBUS5, D_ALL); 2058 2059 MMIO_D(0x902c, D_ALL); 2060 MMIO_D(0xec008, D_ALL); 2061 MMIO_D(0xec00c, D_ALL); 2062 MMIO_D(0xec008 + 0x18, D_ALL); 2063 MMIO_D(0xec00c + 0x18, D_ALL); 2064 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 2065 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 2066 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 2067 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 2068 MMIO_D(0xec408, D_ALL); 2069 MMIO_D(0xec40c, D_ALL); 2070 MMIO_D(0xec408 + 0x18, D_ALL); 2071 MMIO_D(0xec40c + 0x18, D_ALL); 2072 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 2073 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 2074 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 2075 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 2076 MMIO_D(0xfc810, D_ALL); 2077 MMIO_D(0xfc81c, D_ALL); 2078 MMIO_D(0xfc828, D_ALL); 2079 MMIO_D(0xfc834, D_ALL); 2080 MMIO_D(0xfcc00, D_ALL); 2081 MMIO_D(0xfcc0c, D_ALL); 2082 MMIO_D(0xfcc18, D_ALL); 2083 MMIO_D(0xfcc24, D_ALL); 2084 MMIO_D(0xfd000, D_ALL); 2085 MMIO_D(0xfd00c, D_ALL); 2086 MMIO_D(0xfd018, D_ALL); 2087 MMIO_D(0xfd024, D_ALL); 2088 MMIO_D(0xfd034, D_ALL); 2089 2090 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2091 MMIO_D(0x2054, D_ALL); 2092 MMIO_D(0x12054, D_ALL); 2093 MMIO_D(0x22054, D_ALL); 2094 MMIO_D(0x1a054, D_ALL); 2095 2096 MMIO_D(0x44070, D_ALL); 2097 2098 MMIO_D(0x215c, D_HSW_PLUS); 2099 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2100 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2101 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2102 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2103 2104 MMIO_F(0x2290, 8, 0, 0, 0, D_HSW_PLUS, NULL, NULL); 2105 MMIO_D(OACONTROL, D_HSW); 2106 MMIO_D(0x2b00, D_BDW_PLUS); 2107 MMIO_D(0x2360, D_BDW_PLUS); 2108 MMIO_F(0x5200, 32, 0, 0, 0, D_ALL, NULL, NULL); 2109 MMIO_F(0x5240, 32, 0, 0, 0, D_ALL, NULL, NULL); 2110 MMIO_F(0x5280, 16, 0, 0, 0, D_ALL, NULL, NULL); 2111 2112 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2113 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2114 MMIO_D(BCS_SWCTRL, D_ALL); 2115 2116 MMIO_F(HS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2117 MMIO_F(DS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2118 MMIO_F(IA_VERTICES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2119 MMIO_F(IA_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2120 MMIO_F(VS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2121 MMIO_F(GS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2122 MMIO_F(GS_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2123 MMIO_F(CL_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2124 MMIO_F(CL_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2125 MMIO_F(PS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2126 MMIO_F(PS_DEPTH_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2127 MMIO_DH(0x4260, D_BDW_PLUS, NULL, NULL); 2128 MMIO_DH(0x4264, D_BDW_PLUS, NULL, NULL); 2129 MMIO_DH(0x4268, D_BDW_PLUS, NULL, NULL); 2130 MMIO_DH(0x426c, D_BDW_PLUS, NULL, NULL); 2131 MMIO_DH(0x4270, D_BDW_PLUS, NULL, NULL); 2132 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2133 2134 return 0; 2135 } 2136 2137 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2138 { 2139 struct drm_i915_private *dev_priv = gvt->dev_priv; 2140 int ret; 2141 2142 MMIO_DH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, 2143 intel_vgpu_reg_imr_handler); 2144 2145 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2146 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2147 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2148 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2149 2150 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2151 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2152 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2153 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2154 2155 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2156 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2157 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2158 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2159 2160 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2161 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2162 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2163 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2164 2165 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2166 intel_vgpu_reg_imr_handler); 2167 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2168 intel_vgpu_reg_ier_handler); 2169 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2170 intel_vgpu_reg_iir_handler); 2171 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2172 2173 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2174 intel_vgpu_reg_imr_handler); 2175 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2176 intel_vgpu_reg_ier_handler); 2177 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2178 intel_vgpu_reg_iir_handler); 2179 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2180 2181 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2182 intel_vgpu_reg_imr_handler); 2183 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2184 intel_vgpu_reg_ier_handler); 2185 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2186 intel_vgpu_reg_iir_handler); 2187 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2188 2189 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2190 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2191 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2192 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2193 2194 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2195 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2196 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2197 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2198 2199 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2200 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2201 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2202 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2203 2204 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2205 intel_vgpu_reg_master_irq_handler); 2206 2207 MMIO_D(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2208 MMIO_D(0x1c134, D_BDW_PLUS); 2209 2210 MMIO_D(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2211 MMIO_D(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2212 MMIO_GM(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2213 MMIO_D(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2214 MMIO_D(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2215 MMIO_D(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2216 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2217 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2218 NULL, NULL); 2219 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2220 NULL, NULL); 2221 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2222 ring_timestamp_mmio_read, NULL); 2223 2224 MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS); 2225 2226 #define RING_REG(base) (base + 0x230) 2227 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2228 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write); 2229 #undef RING_REG 2230 2231 #define RING_REG(base) (base + 0x234) 2232 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2233 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, ~0LL, D_BDW_PLUS, NULL, NULL); 2234 #undef RING_REG 2235 2236 #define RING_REG(base) (base + 0x244) 2237 MMIO_RING_D(RING_REG, D_BDW_PLUS); 2238 MMIO_D(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2239 #undef RING_REG 2240 2241 #define RING_REG(base) (base + 0x370) 2242 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2243 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS, 2244 NULL, NULL); 2245 #undef RING_REG 2246 2247 #define RING_REG(base) (base + 0x3a0) 2248 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2249 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2250 #undef RING_REG 2251 2252 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2253 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2254 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2255 MMIO_D(0x1c1d0, D_BDW_PLUS); 2256 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2257 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2258 MMIO_D(0x1c054, D_BDW_PLUS); 2259 2260 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2261 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2262 2263 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2264 2265 #define RING_REG(base) (base + 0x270) 2266 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2267 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2268 #undef RING_REG 2269 2270 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); 2271 MMIO_GM(0x1c080, D_BDW_PLUS, NULL, NULL); 2272 2273 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2274 2275 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW); 2276 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW); 2277 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW); 2278 2279 MMIO_D(WM_MISC, D_BDW); 2280 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 2281 2282 MMIO_D(0x66c00, D_BDW_PLUS); 2283 MMIO_D(0x66c04, D_BDW_PLUS); 2284 2285 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2286 2287 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2288 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2289 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2290 2291 MMIO_D(0xfdc, D_BDW); 2292 MMIO_D(GEN8_ROW_CHICKEN, D_BDW_PLUS); 2293 MMIO_D(GEN7_ROW_CHICKEN2, D_BDW_PLUS); 2294 MMIO_D(GEN8_UCGCTL6, D_BDW_PLUS); 2295 2296 MMIO_D(0xb1f0, D_BDW); 2297 MMIO_D(0xb1c0, D_BDW); 2298 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2299 MMIO_D(0xb100, D_BDW); 2300 MMIO_D(0xb10c, D_BDW); 2301 MMIO_D(0xb110, D_BDW); 2302 2303 MMIO_DH(0x24d0, D_BDW_PLUS, NULL, NULL); 2304 MMIO_DH(0x24d4, D_BDW_PLUS, NULL, NULL); 2305 MMIO_DH(0x24d8, D_BDW_PLUS, NULL, NULL); 2306 MMIO_DH(0x24dc, D_BDW_PLUS, NULL, NULL); 2307 2308 MMIO_D(0x83a4, D_BDW); 2309 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2310 2311 MMIO_D(0x8430, D_BDW); 2312 2313 MMIO_D(0x110000, D_BDW_PLUS); 2314 2315 MMIO_D(0x48400, D_BDW_PLUS); 2316 2317 MMIO_D(0x6e570, D_BDW_PLUS); 2318 MMIO_D(0x65f10, D_BDW_PLUS); 2319 2320 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2321 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2322 MMIO_DFH(0xe180, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2323 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2324 2325 MMIO_D(0x2248, D_BDW); 2326 2327 return 0; 2328 } 2329 2330 static int init_skl_mmio_info(struct intel_gvt *gvt) 2331 { 2332 struct drm_i915_private *dev_priv = gvt->dev_priv; 2333 int ret; 2334 2335 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2336 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2337 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2338 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2339 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2340 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2341 2342 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2343 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2344 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2345 2346 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL); 2347 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write); 2348 2349 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, mailbox_write); 2350 MMIO_D(0xa210, D_SKL_PLUS); 2351 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2352 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2353 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write); 2354 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write); 2355 MMIO_D(0x45504, D_SKL); 2356 MMIO_D(0x45520, D_SKL); 2357 MMIO_D(0x46000, D_SKL); 2358 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write); 2359 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write); 2360 MMIO_D(0x6C040, D_SKL); 2361 MMIO_D(0x6C048, D_SKL); 2362 MMIO_D(0x6C050, D_SKL); 2363 MMIO_D(0x6C044, D_SKL); 2364 MMIO_D(0x6C04C, D_SKL); 2365 MMIO_D(0x6C054, D_SKL); 2366 MMIO_D(0x6c058, D_SKL); 2367 MMIO_D(0x6c05c, D_SKL); 2368 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL); 2369 2370 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write); 2371 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write); 2372 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write); 2373 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write); 2374 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write); 2375 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write); 2376 2377 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write); 2378 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write); 2379 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write); 2380 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write); 2381 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write); 2382 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write); 2383 2384 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write); 2385 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write); 2386 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write); 2387 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write); 2388 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write); 2389 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write); 2390 2391 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2392 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2393 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2394 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2395 2396 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2397 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2398 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2399 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2400 2401 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2402 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2403 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2404 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2405 2406 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL); 2407 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL); 2408 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL); 2409 2410 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2411 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2412 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2413 2414 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2415 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2416 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2417 2418 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2419 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2420 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2421 2422 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2423 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2424 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2425 2426 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL); 2427 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL); 2428 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL); 2429 2430 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL); 2431 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL); 2432 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL); 2433 2434 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL); 2435 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL); 2436 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL); 2437 2438 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL); 2439 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL); 2440 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL); 2441 2442 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2443 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2444 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2445 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2446 2447 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2448 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2449 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2450 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2451 2452 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2453 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2454 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2455 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2456 2457 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL); 2458 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL); 2459 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL); 2460 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL); 2461 2462 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL); 2463 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL); 2464 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL); 2465 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL); 2466 2467 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL); 2468 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL); 2469 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL); 2470 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL); 2471 2472 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL); 2473 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL); 2474 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL); 2475 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL); 2476 2477 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL); 2478 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL); 2479 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL); 2480 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL); 2481 2482 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL); 2483 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL); 2484 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL); 2485 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL); 2486 2487 MMIO_D(0x70380, D_SKL); 2488 MMIO_D(0x71380, D_SKL); 2489 MMIO_D(0x72380, D_SKL); 2490 MMIO_D(0x7039c, D_SKL); 2491 2492 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL); 2493 MMIO_D(0x8f074, D_SKL); 2494 MMIO_D(0x8f004, D_SKL); 2495 MMIO_D(0x8f034, D_SKL); 2496 2497 MMIO_D(0xb11c, D_SKL); 2498 2499 MMIO_D(0x51000, D_SKL); 2500 MMIO_D(0x6c00c, D_SKL); 2501 2502 MMIO_F(0xc800, 0x7f8, 0, 0, 0, D_SKL, NULL, NULL); 2503 MMIO_F(0xb020, 0x80, 0, 0, 0, D_SKL, NULL, NULL); 2504 2505 MMIO_D(0xd08, D_SKL); 2506 MMIO_D(0x20e0, D_SKL); 2507 MMIO_D(0x20ec, D_SKL); 2508 2509 /* TRTT */ 2510 MMIO_D(0x4de0, D_SKL); 2511 MMIO_D(0x4de4, D_SKL); 2512 MMIO_D(0x4de8, D_SKL); 2513 MMIO_D(0x4dec, D_SKL); 2514 MMIO_D(0x4df0, D_SKL); 2515 MMIO_DH(0x4df4, D_SKL, NULL, gen9_trtte_write); 2516 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write); 2517 2518 MMIO_D(0x45008, D_SKL); 2519 2520 MMIO_D(0x46430, D_SKL); 2521 2522 MMIO_D(0x46520, D_SKL); 2523 2524 MMIO_D(0xc403c, D_SKL); 2525 MMIO_D(0xb004, D_SKL); 2526 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2527 2528 MMIO_D(0x65900, D_SKL); 2529 MMIO_D(0x1082c0, D_SKL); 2530 MMIO_D(0x4068, D_SKL); 2531 MMIO_D(0x67054, D_SKL); 2532 MMIO_D(0x6e560, D_SKL); 2533 MMIO_D(0x6e554, D_SKL); 2534 MMIO_D(0x2b20, D_SKL); 2535 MMIO_D(0x65f00, D_SKL); 2536 MMIO_D(0x65f08, D_SKL); 2537 MMIO_D(0x320f0, D_SKL); 2538 2539 MMIO_D(_REG_VCS2_EXCC, D_SKL); 2540 MMIO_D(0x70034, D_SKL); 2541 MMIO_D(0x71034, D_SKL); 2542 MMIO_D(0x72034, D_SKL); 2543 2544 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL); 2545 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL); 2546 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL); 2547 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL); 2548 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL); 2549 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL); 2550 2551 MMIO_D(0x44500, D_SKL); 2552 return 0; 2553 } 2554 2555 /** 2556 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset 2557 * @gvt: GVT device 2558 * @offset: register offset 2559 * 2560 * This function is used to find the MMIO information entry from hash table 2561 * 2562 * Returns: 2563 * pointer to MMIO information entry, NULL if not exists 2564 */ 2565 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 2566 unsigned int offset) 2567 { 2568 struct intel_gvt_mmio_info *e; 2569 2570 WARN_ON(!IS_ALIGNED(offset, 4)); 2571 2572 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 2573 if (e->offset == offset) 2574 return e; 2575 } 2576 return NULL; 2577 } 2578 2579 /** 2580 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2581 * @gvt: GVT device 2582 * 2583 * This function is called at the driver unloading stage, to clean up the MMIO 2584 * information table of GVT device 2585 * 2586 */ 2587 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2588 { 2589 struct hlist_node *tmp; 2590 struct intel_gvt_mmio_info *e; 2591 int i; 2592 2593 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2594 kfree(e); 2595 2596 vfree(gvt->mmio.mmio_attribute); 2597 gvt->mmio.mmio_attribute = NULL; 2598 } 2599 2600 /** 2601 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2602 * @gvt: GVT device 2603 * 2604 * This function is called at the initialization stage, to setup the MMIO 2605 * information table for GVT device 2606 * 2607 * Returns: 2608 * zero on success, negative if failed. 2609 */ 2610 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2611 { 2612 struct intel_gvt_device_info *info = &gvt->device_info; 2613 struct drm_i915_private *dev_priv = gvt->dev_priv; 2614 int ret; 2615 2616 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size); 2617 if (!gvt->mmio.mmio_attribute) 2618 return -ENOMEM; 2619 2620 ret = init_generic_mmio_info(gvt); 2621 if (ret) 2622 goto err; 2623 2624 if (IS_BROADWELL(dev_priv)) { 2625 ret = init_broadwell_mmio_info(gvt); 2626 if (ret) 2627 goto err; 2628 } else if (IS_SKYLAKE(dev_priv)) { 2629 ret = init_broadwell_mmio_info(gvt); 2630 if (ret) 2631 goto err; 2632 ret = init_skl_mmio_info(gvt); 2633 if (ret) 2634 goto err; 2635 } 2636 return 0; 2637 err: 2638 intel_gvt_clean_mmio_info(gvt); 2639 return ret; 2640 } 2641 2642 /** 2643 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 2644 * @gvt: a GVT device 2645 * @offset: register offset 2646 * 2647 */ 2648 void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset) 2649 { 2650 gvt->mmio.mmio_attribute[offset >> 2] |= 2651 F_ACCESSED; 2652 } 2653 2654 /** 2655 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 2656 * @gvt: a GVT device 2657 * @offset: register offset 2658 * 2659 */ 2660 bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt, 2661 unsigned int offset) 2662 { 2663 return gvt->mmio.mmio_attribute[offset >> 2] & 2664 F_CMD_ACCESS; 2665 } 2666 2667 /** 2668 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 2669 * @gvt: a GVT device 2670 * @offset: register offset 2671 * 2672 */ 2673 bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, 2674 unsigned int offset) 2675 { 2676 return gvt->mmio.mmio_attribute[offset >> 2] & 2677 F_UNALIGN; 2678 } 2679 2680 /** 2681 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 2682 * @gvt: a GVT device 2683 * @offset: register offset 2684 * 2685 */ 2686 void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt, 2687 unsigned int offset) 2688 { 2689 gvt->mmio.mmio_attribute[offset >> 2] |= 2690 F_CMD_ACCESSED; 2691 } 2692 2693 /** 2694 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 2695 * @gvt: a GVT device 2696 * @offset: register offset 2697 * 2698 * Returns: 2699 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 2700 * 2701 */ 2702 bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset) 2703 { 2704 return gvt->mmio.mmio_attribute[offset >> 2] & 2705 F_MODE_MASK; 2706 } 2707 2708 /** 2709 * intel_vgpu_default_mmio_read - default MMIO read handler 2710 * @vgpu: a vGPU 2711 * @offset: access offset 2712 * @p_data: data return buffer 2713 * @bytes: access data length 2714 * 2715 * Returns: 2716 * Zero on success, negative error code if failed. 2717 */ 2718 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 2719 void *p_data, unsigned int bytes) 2720 { 2721 read_vreg(vgpu, offset, p_data, bytes); 2722 return 0; 2723 } 2724 2725 /** 2726 * intel_t_default_mmio_write - default MMIO write handler 2727 * @vgpu: a vGPU 2728 * @offset: access offset 2729 * @p_data: write data buffer 2730 * @bytes: access data length 2731 * 2732 * Returns: 2733 * Zero on success, negative error code if failed. 2734 */ 2735 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2736 void *p_data, unsigned int bytes) 2737 { 2738 write_vreg(vgpu, offset, p_data, bytes); 2739 return 0; 2740 } 2741