1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 41 /* XXX FIXME i915 has changed PP_XXX definition */ 42 #define PCH_PP_STATUS _MMIO(0xc7200) 43 #define PCH_PP_CONTROL _MMIO(0xc7204) 44 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 45 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 46 #define PCH_PP_DIVISOR _MMIO(0xc7210) 47 48 /* Register contains RO bits */ 49 #define F_RO (1 << 0) 50 /* Register contains graphics address */ 51 #define F_GMADR (1 << 1) 52 /* Mode mask registers with high 16 bits as the mask bits */ 53 #define F_MODE_MASK (1 << 2) 54 /* This reg can be accessed by GPU commands */ 55 #define F_CMD_ACCESS (1 << 3) 56 /* This reg has been accessed by a VM */ 57 #define F_ACCESSED (1 << 4) 58 /* This reg has been accessed through GPU commands */ 59 #define F_CMD_ACCESSED (1 << 5) 60 /* This reg could be accessed by unaligned address */ 61 #define F_UNALIGN (1 << 6) 62 63 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 64 { 65 if (IS_BROADWELL(gvt->dev_priv)) 66 return D_BDW; 67 else if (IS_SKYLAKE(gvt->dev_priv)) 68 return D_SKL; 69 70 return 0; 71 } 72 73 bool intel_gvt_match_device(struct intel_gvt *gvt, 74 unsigned long device) 75 { 76 return intel_gvt_get_device_type(gvt) & device; 77 } 78 79 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 80 void *p_data, unsigned int bytes) 81 { 82 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 83 } 84 85 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 86 void *p_data, unsigned int bytes) 87 { 88 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 89 } 90 91 static int new_mmio_info(struct intel_gvt *gvt, 92 u32 offset, u32 flags, u32 size, 93 u32 addr_mask, u32 ro_mask, u32 device, 94 void *read, void *write) 95 { 96 struct intel_gvt_mmio_info *info, *p; 97 u32 start, end, i; 98 99 if (!intel_gvt_match_device(gvt, device)) 100 return 0; 101 102 if (WARN_ON(!IS_ALIGNED(offset, 4))) 103 return -EINVAL; 104 105 start = offset; 106 end = offset + size; 107 108 for (i = start; i < end; i += 4) { 109 info = kzalloc(sizeof(*info), GFP_KERNEL); 110 if (!info) 111 return -ENOMEM; 112 113 info->offset = i; 114 p = intel_gvt_find_mmio_info(gvt, info->offset); 115 if (p) 116 gvt_err("dup mmio definition offset %x\n", 117 info->offset); 118 info->size = size; 119 info->length = (i + 4) < end ? 4 : (end - i); 120 info->addr_mask = addr_mask; 121 info->device = device; 122 info->read = read ? read : intel_vgpu_default_mmio_read; 123 info->write = write ? write : intel_vgpu_default_mmio_write; 124 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 125 INIT_HLIST_NODE(&info->node); 126 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 127 } 128 return 0; 129 } 130 131 #define offset_to_fence_num(offset) \ 132 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 133 134 #define fence_num_to_offset(num) \ 135 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 136 137 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 138 unsigned int fence_num, void *p_data, unsigned int bytes) 139 { 140 if (fence_num >= vgpu_fence_sz(vgpu)) { 141 gvt_err("vgpu%d: found oob fence register access\n", 142 vgpu->id); 143 gvt_err("vgpu%d: total fence num %d access fence num %d\n", 144 vgpu->id, vgpu_fence_sz(vgpu), fence_num); 145 memset(p_data, 0, bytes); 146 } 147 return 0; 148 } 149 150 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 151 void *p_data, unsigned int bytes) 152 { 153 int ret; 154 155 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 156 p_data, bytes); 157 if (ret) 158 return ret; 159 read_vreg(vgpu, off, p_data, bytes); 160 return 0; 161 } 162 163 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 164 void *p_data, unsigned int bytes) 165 { 166 unsigned int fence_num = offset_to_fence_num(off); 167 int ret; 168 169 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 170 if (ret) 171 return ret; 172 write_vreg(vgpu, off, p_data, bytes); 173 174 intel_vgpu_write_fence(vgpu, fence_num, 175 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 176 return 0; 177 } 178 179 #define CALC_MODE_MASK_REG(old, new) \ 180 (((new) & GENMASK(31, 16)) \ 181 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 182 | ((new) & ((new) >> 16)))) 183 184 static int mul_force_wake_write(struct intel_vgpu *vgpu, 185 unsigned int offset, void *p_data, unsigned int bytes) 186 { 187 u32 old, new; 188 uint32_t ack_reg_offset; 189 190 old = vgpu_vreg(vgpu, offset); 191 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 192 193 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) { 194 switch (offset) { 195 case FORCEWAKE_RENDER_GEN9_REG: 196 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 197 break; 198 case FORCEWAKE_BLITTER_GEN9_REG: 199 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 200 break; 201 case FORCEWAKE_MEDIA_GEN9_REG: 202 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 203 break; 204 default: 205 /*should not hit here*/ 206 gvt_err("invalid forcewake offset 0x%x\n", offset); 207 return 1; 208 } 209 } else { 210 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 211 } 212 213 vgpu_vreg(vgpu, offset) = new; 214 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 215 return 0; 216 } 217 218 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 219 void *p_data, unsigned int bytes) 220 { 221 u32 data; 222 u32 bitmap = 0; 223 224 data = vgpu_vreg(vgpu, offset); 225 226 if (data & GEN6_GRDOM_FULL) { 227 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 228 bitmap = 0xff; 229 } 230 if (data & GEN6_GRDOM_RENDER) { 231 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 232 bitmap |= (1 << RCS); 233 } 234 if (data & GEN6_GRDOM_MEDIA) { 235 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 236 bitmap |= (1 << VCS); 237 } 238 if (data & GEN6_GRDOM_BLT) { 239 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 240 bitmap |= (1 << BCS); 241 } 242 if (data & GEN6_GRDOM_VECS) { 243 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 244 bitmap |= (1 << VECS); 245 } 246 if (data & GEN8_GRDOM_MEDIA2) { 247 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 248 if (HAS_BSD2(vgpu->gvt->dev_priv)) 249 bitmap |= (1 << VCS2); 250 } 251 return 0; 252 } 253 254 #define _vgtif_reg(x) \ 255 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 256 257 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 258 void *p_data, unsigned int bytes) 259 { 260 bool invalid_read = false; 261 262 read_vreg(vgpu, offset, p_data, bytes); 263 264 switch (offset) { 265 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 266 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 267 invalid_read = true; 268 break; 269 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 270 _vgtif_reg(avail_rs.fence_num): 271 if (offset + bytes > 272 _vgtif_reg(avail_rs.fence_num) + 4) 273 invalid_read = true; 274 break; 275 case 0x78010: /* vgt_caps */ 276 case 0x7881c: 277 break; 278 default: 279 invalid_read = true; 280 break; 281 } 282 if (invalid_read) 283 gvt_err("invalid pvinfo read: [%x:%x] = %x\n", 284 offset, bytes, *(u32 *)p_data); 285 return 0; 286 } 287 288 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 289 { 290 int ret = 0; 291 292 switch (notification) { 293 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 294 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); 295 break; 296 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 297 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); 298 break; 299 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 300 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); 301 break; 302 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 303 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); 304 break; 305 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 306 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 307 case 1: /* Remove this in guest driver. */ 308 break; 309 default: 310 gvt_err("Invalid PV notification %d\n", notification); 311 } 312 return ret; 313 } 314 315 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 316 void *p_data, unsigned int bytes) 317 { 318 u32 data; 319 int ret; 320 321 write_vreg(vgpu, offset, p_data, bytes); 322 data = vgpu_vreg(vgpu, offset); 323 324 switch (offset) { 325 case _vgtif_reg(display_ready): 326 case _vgtif_reg(g2v_notify): 327 ret = handle_g2v_notification(vgpu, data); 328 break; 329 /* add xhot and yhot to handled list to avoid error log */ 330 case 0x78830: 331 case 0x78834: 332 case _vgtif_reg(pdp[0].lo): 333 case _vgtif_reg(pdp[0].hi): 334 case _vgtif_reg(pdp[1].lo): 335 case _vgtif_reg(pdp[1].hi): 336 case _vgtif_reg(pdp[2].lo): 337 case _vgtif_reg(pdp[2].hi): 338 case _vgtif_reg(pdp[3].lo): 339 case _vgtif_reg(pdp[3].hi): 340 case _vgtif_reg(execlist_context_descriptor_lo): 341 case _vgtif_reg(execlist_context_descriptor_hi): 342 break; 343 default: 344 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n", 345 offset, bytes, data); 346 break; 347 } 348 return 0; 349 } 350 351 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 352 unsigned int offset, void *p_data, unsigned int bytes) 353 { 354 write_vreg(vgpu, offset, p_data, bytes); 355 356 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 357 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 358 return 0; 359 } 360 361 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 362 void *p_data, unsigned int bytes) 363 { 364 u32 mode = *(u32 *)p_data; 365 366 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 367 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n", 368 vgpu->id); 369 return 0; 370 } 371 372 return 0; 373 } 374 375 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 376 void *p_data, unsigned int bytes) 377 { 378 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 379 u32 trtte = *(u32 *)p_data; 380 381 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 382 WARN(1, "VM(%d): Use physical address for TRTT!\n", 383 vgpu->id); 384 return -EINVAL; 385 } 386 write_vreg(vgpu, offset, p_data, bytes); 387 /* TRTTE is not per-context */ 388 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 389 390 return 0; 391 } 392 393 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 394 void *p_data, unsigned int bytes) 395 { 396 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 397 u32 val = *(u32 *)p_data; 398 399 if (val & 1) { 400 /* unblock hw logic */ 401 I915_WRITE(_MMIO(offset), val); 402 } 403 write_vreg(vgpu, offset, p_data, bytes); 404 return 0; 405 } 406 407 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 408 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 409 f, s, am, rm, d, r, w); \ 410 if (ret) \ 411 return ret; \ 412 } while (0) 413 414 #define MMIO_D(reg, d) \ 415 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 416 417 #define MMIO_DH(reg, d, r, w) \ 418 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 419 420 #define MMIO_DFH(reg, d, f, r, w) \ 421 MMIO_F(reg, 4, f, 0, 0, d, r, w) 422 423 #define MMIO_GM(reg, d, r, w) \ 424 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 425 426 #define MMIO_RO(reg, d, f, rm, r, w) \ 427 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 428 429 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 430 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 431 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 432 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 433 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 434 } while (0) 435 436 #define MMIO_RING_D(prefix, d) \ 437 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 438 439 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 440 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 441 442 #define MMIO_RING_GM(prefix, d, r, w) \ 443 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 444 445 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 446 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 447 448 static int init_generic_mmio_info(struct intel_gvt *gvt) 449 { 450 struct drm_i915_private *dev_priv = gvt->dev_priv; 451 int ret; 452 453 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 454 455 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 456 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 457 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 458 MMIO_D(SDEISR, D_ALL); 459 460 MMIO_RING_D(RING_HWSTAM, D_ALL); 461 462 MMIO_GM(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 463 MMIO_GM(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 464 MMIO_GM(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 465 MMIO_GM(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 466 467 #define RING_REG(base) (base + 0x28) 468 MMIO_RING_D(RING_REG, D_ALL); 469 #undef RING_REG 470 471 #define RING_REG(base) (base + 0x134) 472 MMIO_RING_D(RING_REG, D_ALL); 473 #undef RING_REG 474 475 MMIO_GM(0x2148, D_ALL, NULL, NULL); 476 MMIO_GM(CCID, D_ALL, NULL, NULL); 477 MMIO_GM(0x12198, D_ALL, NULL, NULL); 478 MMIO_D(GEN7_CXT_SIZE, D_ALL); 479 480 MMIO_RING_D(RING_TAIL, D_ALL); 481 MMIO_RING_D(RING_HEAD, D_ALL); 482 MMIO_RING_D(RING_CTL, D_ALL); 483 MMIO_RING_D(RING_ACTHD, D_ALL); 484 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 485 486 /* RING MODE */ 487 #define RING_REG(base) (base + 0x29c) 488 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK, NULL, NULL); 489 #undef RING_REG 490 491 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 492 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL); 493 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, NULL, NULL); 494 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, NULL, NULL); 495 496 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 497 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL); 498 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK, NULL, NULL); 499 500 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL); 501 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL); 502 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK, NULL, NULL); 503 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK, NULL, NULL); 504 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK, NULL, NULL); 505 MMIO_D(GAM_ECOCHK, D_ALL); 506 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK, NULL, NULL); 507 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK, NULL, NULL); 508 MMIO_D(0x9030, D_ALL); 509 MMIO_D(0x20a0, D_ALL); 510 MMIO_D(0x2420, D_ALL); 511 MMIO_D(0x2430, D_ALL); 512 MMIO_D(0x2434, D_ALL); 513 MMIO_D(0x2438, D_ALL); 514 MMIO_D(0x243c, D_ALL); 515 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK, NULL, NULL); 516 MMIO_DFH(0xe184, D_ALL, F_MODE_MASK, NULL, NULL); 517 MMIO_DFH(0xe100, D_ALL, F_MODE_MASK, NULL, NULL); 518 519 /* display */ 520 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 521 MMIO_D(0x602a0, D_ALL); 522 523 MMIO_D(0x65050, D_ALL); 524 MMIO_D(0x650b4, D_ALL); 525 526 MMIO_D(0xc4040, D_ALL); 527 MMIO_D(DERRMR, D_ALL); 528 529 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 530 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 531 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 532 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 533 534 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, NULL); 535 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, NULL); 536 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, NULL); 537 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, NULL); 538 539 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 540 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 541 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 542 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 543 544 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 545 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 546 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 547 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 548 549 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 550 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 551 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 552 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 553 554 MMIO_D(CURCNTR(PIPE_A), D_ALL); 555 MMIO_D(CURCNTR(PIPE_B), D_ALL); 556 MMIO_D(CURCNTR(PIPE_C), D_ALL); 557 558 MMIO_D(CURPOS(PIPE_A), D_ALL); 559 MMIO_D(CURPOS(PIPE_B), D_ALL); 560 MMIO_D(CURPOS(PIPE_C), D_ALL); 561 562 MMIO_D(CURBASE(PIPE_A), D_ALL); 563 MMIO_D(CURBASE(PIPE_B), D_ALL); 564 MMIO_D(CURBASE(PIPE_C), D_ALL); 565 566 MMIO_D(0x700ac, D_ALL); 567 MMIO_D(0x710ac, D_ALL); 568 MMIO_D(0x720ac, D_ALL); 569 570 MMIO_D(0x70090, D_ALL); 571 MMIO_D(0x70094, D_ALL); 572 MMIO_D(0x70098, D_ALL); 573 MMIO_D(0x7009c, D_ALL); 574 575 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 576 MMIO_D(DSPADDR(PIPE_A), D_ALL); 577 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 578 MMIO_D(DSPPOS(PIPE_A), D_ALL); 579 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 580 MMIO_D(DSPSURF(PIPE_A), D_ALL); 581 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 582 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 583 584 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 585 MMIO_D(DSPADDR(PIPE_B), D_ALL); 586 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 587 MMIO_D(DSPPOS(PIPE_B), D_ALL); 588 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 589 MMIO_D(DSPSURF(PIPE_B), D_ALL); 590 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 591 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 592 593 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 594 MMIO_D(DSPADDR(PIPE_C), D_ALL); 595 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 596 MMIO_D(DSPPOS(PIPE_C), D_ALL); 597 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 598 MMIO_D(DSPSURF(PIPE_C), D_ALL); 599 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 600 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 601 602 MMIO_D(SPRCTL(PIPE_A), D_ALL); 603 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 604 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 605 MMIO_D(SPRPOS(PIPE_A), D_ALL); 606 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 607 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 608 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 609 MMIO_D(SPRSURF(PIPE_A), D_ALL); 610 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 611 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 612 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 613 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 614 615 MMIO_D(SPRCTL(PIPE_B), D_ALL); 616 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 617 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 618 MMIO_D(SPRPOS(PIPE_B), D_ALL); 619 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 620 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 621 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 622 MMIO_D(SPRSURF(PIPE_B), D_ALL); 623 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 624 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 625 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 626 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 627 628 MMIO_D(SPRCTL(PIPE_C), D_ALL); 629 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 630 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 631 MMIO_D(SPRPOS(PIPE_C), D_ALL); 632 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 633 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 634 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 635 MMIO_D(SPRSURF(PIPE_C), D_ALL); 636 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 637 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 638 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 639 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 640 641 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 642 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 643 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 644 645 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 646 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 647 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 648 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 649 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 650 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 651 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 652 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 653 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 654 655 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 656 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 657 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 658 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 659 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 660 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 661 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 662 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 663 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 664 665 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 666 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 667 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 668 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 669 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 670 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 671 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 672 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 673 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 674 675 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 676 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 677 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 678 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 679 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 680 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 681 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 682 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 683 684 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 685 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 686 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 687 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 688 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 689 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 690 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 691 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 692 693 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 694 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 695 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 696 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 697 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 698 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 699 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 700 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 701 702 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 703 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 704 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 705 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 706 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 707 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 708 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 709 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 710 711 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 712 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 713 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 714 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 715 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 716 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 717 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 718 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 719 720 MMIO_D(PF_CTL(PIPE_A), D_ALL); 721 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 722 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 723 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 724 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 725 726 MMIO_D(PF_CTL(PIPE_B), D_ALL); 727 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 728 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 729 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 730 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 731 732 MMIO_D(PF_CTL(PIPE_C), D_ALL); 733 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 734 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 735 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 736 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 737 738 MMIO_D(WM0_PIPEA_ILK, D_ALL); 739 MMIO_D(WM0_PIPEB_ILK, D_ALL); 740 MMIO_D(WM0_PIPEC_IVB, D_ALL); 741 MMIO_D(WM1_LP_ILK, D_ALL); 742 MMIO_D(WM2_LP_ILK, D_ALL); 743 MMIO_D(WM3_LP_ILK, D_ALL); 744 MMIO_D(WM1S_LP_ILK, D_ALL); 745 MMIO_D(WM2S_LP_IVB, D_ALL); 746 MMIO_D(WM3S_LP_IVB, D_ALL); 747 748 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 749 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 750 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 751 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 752 753 MMIO_D(0x48268, D_ALL); 754 755 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, NULL, NULL); 756 MMIO_F(PCH_GPIOA, 6 * 4, 0, 0, 0, D_ALL, NULL, NULL); 757 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 758 759 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, NULL); 760 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, NULL); 761 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, NULL); 762 763 MMIO_RO(PCH_ADPA, D_ALL, 0, 764 ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, NULL); 765 766 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, NULL); 767 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, NULL); 768 769 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, NULL); 770 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, NULL); 771 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, NULL); 772 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, NULL); 773 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, NULL); 774 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, NULL); 775 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, NULL); 776 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, NULL); 777 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, NULL); 778 779 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 780 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 781 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 782 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 783 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 784 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 785 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 786 787 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 788 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 789 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 790 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 791 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 792 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 793 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 794 795 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 796 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 797 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 798 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 799 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 800 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 801 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 802 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 803 804 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 805 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 806 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 807 808 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 809 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 810 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 811 812 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 813 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 814 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 815 816 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 817 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 818 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 819 820 MMIO_D(_FDI_RXA_MISC, D_ALL); 821 MMIO_D(_FDI_RXB_MISC, D_ALL); 822 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 823 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 824 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 825 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 826 827 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, NULL); 828 MMIO_D(PCH_PP_DIVISOR, D_ALL); 829 MMIO_D(PCH_PP_STATUS, D_ALL); 830 MMIO_D(PCH_LVDS, D_ALL); 831 MMIO_D(_PCH_DPLL_A, D_ALL); 832 MMIO_D(_PCH_DPLL_B, D_ALL); 833 MMIO_D(_PCH_FPA0, D_ALL); 834 MMIO_D(_PCH_FPA1, D_ALL); 835 MMIO_D(_PCH_FPB0, D_ALL); 836 MMIO_D(_PCH_FPB1, D_ALL); 837 MMIO_D(PCH_DREF_CONTROL, D_ALL); 838 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 839 MMIO_D(PCH_DPLL_SEL, D_ALL); 840 841 MMIO_D(0x61208, D_ALL); 842 MMIO_D(0x6120c, D_ALL); 843 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 844 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 845 846 MMIO_DH(0xe651c, D_ALL, NULL, NULL); 847 MMIO_DH(0xe661c, D_ALL, NULL, NULL); 848 MMIO_DH(0xe671c, D_ALL, NULL, NULL); 849 MMIO_DH(0xe681c, D_ALL, NULL, NULL); 850 MMIO_DH(0xe6c04, D_ALL, NULL, NULL); 851 MMIO_DH(0xe6e1c, D_ALL, NULL, NULL); 852 853 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 854 PORTA_HOTPLUG_STATUS_MASK 855 | PORTB_HOTPLUG_STATUS_MASK 856 | PORTC_HOTPLUG_STATUS_MASK 857 | PORTD_HOTPLUG_STATUS_MASK, 858 NULL, NULL); 859 860 MMIO_DH(LCPLL_CTL, D_ALL, NULL, NULL); 861 MMIO_D(FUSE_STRAP, D_ALL); 862 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 863 864 MMIO_D(DISP_ARB_CTL, D_ALL); 865 MMIO_D(DISP_ARB_CTL2, D_ALL); 866 867 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 868 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 869 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 870 871 MMIO_D(SOUTH_CHICKEN1, D_ALL); 872 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, NULL); 873 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 874 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 875 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 876 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 877 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 878 879 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 880 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 881 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 882 MMIO_D(ILK_DPFC_STATUS, D_ALL); 883 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 884 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 885 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 886 887 MMIO_D(IPS_CTL, D_ALL); 888 889 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 890 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 891 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 892 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 893 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 894 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 895 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 896 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 897 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 898 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 899 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 900 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 901 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 902 903 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 904 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 905 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 906 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 907 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 908 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 909 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 910 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 911 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 912 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 913 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 914 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 915 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 916 917 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 918 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 919 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 920 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 921 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 922 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 923 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 924 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 925 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 926 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 927 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 928 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 929 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 930 931 MMIO_D(0x60110, D_ALL); 932 MMIO_D(0x61110, D_ALL); 933 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 934 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 935 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 936 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 937 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 938 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 939 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 940 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 941 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 942 943 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 944 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 945 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 946 MMIO_D(SPLL_CTL, D_ALL); 947 MMIO_D(_WRPLL_CTL1, D_ALL); 948 MMIO_D(_WRPLL_CTL2, D_ALL); 949 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 950 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 951 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 952 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 953 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 954 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 955 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 956 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 957 958 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 959 MMIO_D(0x46508, D_ALL); 960 961 MMIO_D(0x49080, D_ALL); 962 MMIO_D(0x49180, D_ALL); 963 MMIO_D(0x49280, D_ALL); 964 965 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 966 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 967 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 968 969 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 970 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 971 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 972 973 MMIO_D(0x4a400, D_ALL); 974 MMIO_D(0x4ac00, D_ALL); 975 MMIO_D(0x4b400, D_ALL); 976 977 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 978 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 979 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 980 981 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 982 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 983 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 984 985 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 986 MMIO_D(SBI_ADDR, D_ALL); 987 MMIO_DH(SBI_DATA, D_ALL, NULL, NULL); 988 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, NULL); 989 MMIO_D(PIXCLK_GATE, D_ALL); 990 991 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, NULL); 992 993 MMIO_RO(DDI_BUF_CTL(PORT_A), D_ALL, 0, 994 DDI_INIT_DISPLAY_DETECTED, NULL, NULL); 995 MMIO_RO(DDI_BUF_CTL(PORT_B), D_ALL, 0, 996 DDI_INIT_DISPLAY_DETECTED, NULL, NULL); 997 MMIO_RO(DDI_BUF_CTL(PORT_C), D_ALL, 0, 998 DDI_INIT_DISPLAY_DETECTED, NULL, NULL); 999 MMIO_RO(DDI_BUF_CTL(PORT_D), D_ALL, 0, 1000 DDI_INIT_DISPLAY_DETECTED, NULL, NULL); 1001 MMIO_RO(DDI_BUF_CTL(PORT_E), D_ALL, 0, 1002 DDI_INIT_DISPLAY_DETECTED, NULL, NULL); 1003 1004 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, NULL); 1005 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, NULL); 1006 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, NULL); 1007 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, NULL); 1008 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, NULL); 1009 1010 MMIO_RO(DP_TP_STATUS(PORT_A), D_ALL, 0, 1011 (1 << 27) | (1 << 26) | (1 << 24), NULL, NULL); 1012 MMIO_RO(DP_TP_STATUS(PORT_B), D_ALL, 0, 1013 (1 << 27) | (1 << 26) | (1 << 24), NULL, NULL); 1014 MMIO_RO(DP_TP_STATUS(PORT_C), D_ALL, 0, 1015 (1 << 27) | (1 << 26) | (1 << 24), NULL, NULL); 1016 MMIO_RO(DP_TP_STATUS(PORT_D), D_ALL, 0, 1017 (1 << 27) | (1 << 26) | (1 << 24), NULL, NULL); 1018 MMIO_RO(DP_TP_STATUS(PORT_E), D_ALL, 0, 1019 (1 << 27) | (1 << 26) | (1 << 24), NULL, NULL); 1020 1021 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1022 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1023 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1024 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1025 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1026 1027 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 1028 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 1029 1030 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 1031 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 1032 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 1033 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 1034 1035 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 1036 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 1037 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 1038 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 1039 1040 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 1041 MMIO_D(FORCEWAKE_ACK, D_ALL); 1042 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 1043 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 1044 MMIO_D(GTFIFODBG, D_ALL); 1045 MMIO_D(GTFIFOCTL, D_ALL); 1046 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 1047 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL); 1048 MMIO_D(ECOBUS, D_ALL); 1049 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 1050 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 1051 MMIO_D(GEN6_RPNSWREQ, D_ALL); 1052 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 1053 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 1054 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 1055 MMIO_D(GEN6_RPSTAT1, D_ALL); 1056 MMIO_D(GEN6_RP_CONTROL, D_ALL); 1057 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 1058 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 1059 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 1060 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 1061 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 1062 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 1063 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 1064 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 1065 MMIO_D(GEN6_RP_UP_EI, D_ALL); 1066 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 1067 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 1068 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 1069 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 1070 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 1071 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 1072 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 1073 MMIO_D(GEN6_RC_SLEEP, D_ALL); 1074 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 1075 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 1076 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 1077 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 1078 MMIO_D(GEN6_PMINTRMSK, D_ALL); 1079 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, NULL); 1080 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, NULL); 1081 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, NULL); 1082 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, NULL); 1083 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, NULL); 1084 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, NULL); 1085 1086 MMIO_D(RSTDBYCTL, D_ALL); 1087 1088 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 1089 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 1090 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write); 1091 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, NULL); 1092 1093 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL); 1094 1095 MMIO_D(TILECTL, D_ALL); 1096 1097 MMIO_D(GEN6_UCGCTL1, D_ALL); 1098 MMIO_D(GEN6_UCGCTL2, D_ALL); 1099 1100 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 1101 1102 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_SKL); 1103 MMIO_D(GEN6_PCODE_DATA, D_ALL); 1104 MMIO_D(0x13812c, D_ALL); 1105 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 1106 MMIO_D(HSW_EDRAM_CAP, D_ALL); 1107 MMIO_D(HSW_IDICR, D_ALL); 1108 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 1109 1110 MMIO_D(0x3c, D_ALL); 1111 MMIO_D(0x860, D_ALL); 1112 MMIO_D(ECOSKPD, D_ALL); 1113 MMIO_D(0x121d0, D_ALL); 1114 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 1115 MMIO_D(0x41d0, D_ALL); 1116 MMIO_D(GAC_ECO_BITS, D_ALL); 1117 MMIO_D(0x6200, D_ALL); 1118 MMIO_D(0x6204, D_ALL); 1119 MMIO_D(0x6208, D_ALL); 1120 MMIO_D(0x7118, D_ALL); 1121 MMIO_D(0x7180, D_ALL); 1122 MMIO_D(0x7408, D_ALL); 1123 MMIO_D(0x7c00, D_ALL); 1124 MMIO_D(GEN6_MBCTL, D_ALL); 1125 MMIO_D(0x911c, D_ALL); 1126 MMIO_D(0x9120, D_ALL); 1127 1128 MMIO_D(GAB_CTL, D_ALL); 1129 MMIO_D(0x48800, D_ALL); 1130 MMIO_D(0xce044, D_ALL); 1131 MMIO_D(0xe6500, D_ALL); 1132 MMIO_D(0xe6504, D_ALL); 1133 MMIO_D(0xe6600, D_ALL); 1134 MMIO_D(0xe6604, D_ALL); 1135 MMIO_D(0xe6700, D_ALL); 1136 MMIO_D(0xe6704, D_ALL); 1137 MMIO_D(0xe6800, D_ALL); 1138 MMIO_D(0xe6804, D_ALL); 1139 MMIO_D(PCH_GMBUS4, D_ALL); 1140 MMIO_D(PCH_GMBUS5, D_ALL); 1141 1142 MMIO_D(0x902c, D_ALL); 1143 MMIO_D(0xec008, D_ALL); 1144 MMIO_D(0xec00c, D_ALL); 1145 MMIO_D(0xec008 + 0x18, D_ALL); 1146 MMIO_D(0xec00c + 0x18, D_ALL); 1147 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 1148 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 1149 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 1150 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 1151 MMIO_D(0xec408, D_ALL); 1152 MMIO_D(0xec40c, D_ALL); 1153 MMIO_D(0xec408 + 0x18, D_ALL); 1154 MMIO_D(0xec40c + 0x18, D_ALL); 1155 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 1156 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 1157 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 1158 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 1159 MMIO_D(0xfc810, D_ALL); 1160 MMIO_D(0xfc81c, D_ALL); 1161 MMIO_D(0xfc828, D_ALL); 1162 MMIO_D(0xfc834, D_ALL); 1163 MMIO_D(0xfcc00, D_ALL); 1164 MMIO_D(0xfcc0c, D_ALL); 1165 MMIO_D(0xfcc18, D_ALL); 1166 MMIO_D(0xfcc24, D_ALL); 1167 MMIO_D(0xfd000, D_ALL); 1168 MMIO_D(0xfd00c, D_ALL); 1169 MMIO_D(0xfd018, D_ALL); 1170 MMIO_D(0xfd024, D_ALL); 1171 MMIO_D(0xfd034, D_ALL); 1172 1173 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 1174 MMIO_D(0x2054, D_ALL); 1175 MMIO_D(0x12054, D_ALL); 1176 MMIO_D(0x22054, D_ALL); 1177 MMIO_D(0x1a054, D_ALL); 1178 1179 MMIO_D(0x44070, D_ALL); 1180 1181 MMIO_D(0x215c, D_HSW_PLUS); 1182 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 1183 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 1184 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 1185 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 1186 1187 MMIO_F(0x2290, 8, 0, 0, 0, D_HSW_PLUS, NULL, NULL); 1188 MMIO_D(OACONTROL, D_HSW); 1189 MMIO_D(0x2b00, D_BDW_PLUS); 1190 MMIO_D(0x2360, D_BDW_PLUS); 1191 MMIO_F(0x5200, 32, 0, 0, 0, D_ALL, NULL, NULL); 1192 MMIO_F(0x5240, 32, 0, 0, 0, D_ALL, NULL, NULL); 1193 MMIO_F(0x5280, 16, 0, 0, 0, D_ALL, NULL, NULL); 1194 1195 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 1196 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 1197 MMIO_D(BCS_SWCTRL, D_ALL); 1198 1199 MMIO_F(HS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 1200 MMIO_F(DS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 1201 MMIO_F(IA_VERTICES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 1202 MMIO_F(IA_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 1203 MMIO_F(VS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 1204 MMIO_F(GS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 1205 MMIO_F(GS_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 1206 MMIO_F(CL_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 1207 MMIO_F(CL_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 1208 MMIO_F(PS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 1209 MMIO_F(PS_DEPTH_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 1210 MMIO_DH(0x4260, D_BDW_PLUS, NULL, NULL); 1211 MMIO_DH(0x4264, D_BDW_PLUS, NULL, NULL); 1212 MMIO_DH(0x4268, D_BDW_PLUS, NULL, NULL); 1213 MMIO_DH(0x426c, D_BDW_PLUS, NULL, NULL); 1214 MMIO_DH(0x4270, D_BDW_PLUS, NULL, NULL); 1215 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 1216 1217 return 0; 1218 } 1219 1220 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 1221 { 1222 struct drm_i915_private *dev_priv = gvt->dev_priv; 1223 int ret; 1224 1225 MMIO_DH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, 1226 intel_vgpu_reg_imr_handler); 1227 1228 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 1229 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 1230 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 1231 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 1232 1233 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 1234 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 1235 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 1236 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 1237 1238 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 1239 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 1240 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 1241 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 1242 1243 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 1244 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 1245 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 1246 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 1247 1248 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 1249 intel_vgpu_reg_imr_handler); 1250 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 1251 intel_vgpu_reg_ier_handler); 1252 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 1253 intel_vgpu_reg_iir_handler); 1254 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 1255 1256 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 1257 intel_vgpu_reg_imr_handler); 1258 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 1259 intel_vgpu_reg_ier_handler); 1260 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 1261 intel_vgpu_reg_iir_handler); 1262 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 1263 1264 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 1265 intel_vgpu_reg_imr_handler); 1266 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 1267 intel_vgpu_reg_ier_handler); 1268 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 1269 intel_vgpu_reg_iir_handler); 1270 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 1271 1272 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 1273 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 1274 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 1275 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 1276 1277 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 1278 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 1279 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 1280 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 1281 1282 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 1283 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 1284 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 1285 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 1286 1287 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 1288 intel_vgpu_reg_master_irq_handler); 1289 1290 MMIO_D(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 1291 MMIO_D(0x1c134, D_BDW_PLUS); 1292 1293 MMIO_D(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 1294 MMIO_D(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 1295 MMIO_GM(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 1296 MMIO_D(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 1297 MMIO_D(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 1298 MMIO_D(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 1299 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 1300 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 1301 NULL, NULL); 1302 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 1303 NULL, NULL); 1304 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 1305 NULL, NULL); 1306 1307 MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS); 1308 1309 #define RING_REG(base) (base + 0x230) 1310 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, NULL); 1311 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 1312 #undef RING_REG 1313 1314 #define RING_REG(base) (base + 0x234) 1315 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 1316 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, ~0LL, D_BDW_PLUS, NULL, NULL); 1317 #undef RING_REG 1318 1319 #define RING_REG(base) (base + 0x244) 1320 MMIO_RING_D(RING_REG, D_BDW_PLUS); 1321 MMIO_D(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 1322 #undef RING_REG 1323 1324 #define RING_REG(base) (base + 0x370) 1325 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 1326 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS, 1327 NULL, NULL); 1328 #undef RING_REG 1329 1330 #define RING_REG(base) (base + 0x3a0) 1331 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 1332 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 1333 #undef RING_REG 1334 1335 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 1336 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 1337 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 1338 MMIO_D(0x1c1d0, D_BDW_PLUS); 1339 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 1340 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 1341 MMIO_D(0x1c054, D_BDW_PLUS); 1342 1343 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 1344 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 1345 1346 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 1347 1348 #define RING_REG(base) (base + 0x270) 1349 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 1350 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 1351 #undef RING_REG 1352 1353 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); 1354 MMIO_GM(0x1c080, D_BDW_PLUS, NULL, NULL); 1355 1356 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 1357 1358 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW); 1359 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW); 1360 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW); 1361 1362 MMIO_D(WM_MISC, D_BDW); 1363 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 1364 1365 MMIO_D(0x66c00, D_BDW_PLUS); 1366 MMIO_D(0x66c04, D_BDW_PLUS); 1367 1368 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 1369 1370 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 1371 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 1372 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 1373 1374 MMIO_D(0xfdc, D_BDW); 1375 MMIO_D(GEN8_ROW_CHICKEN, D_BDW_PLUS); 1376 MMIO_D(GEN7_ROW_CHICKEN2, D_BDW_PLUS); 1377 MMIO_D(GEN8_UCGCTL6, D_BDW_PLUS); 1378 1379 MMIO_D(0xb1f0, D_BDW); 1380 MMIO_D(0xb1c0, D_BDW); 1381 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 1382 MMIO_D(0xb100, D_BDW); 1383 MMIO_D(0xb10c, D_BDW); 1384 MMIO_D(0xb110, D_BDW); 1385 1386 MMIO_DH(0x24d0, D_BDW_PLUS, NULL, NULL); 1387 MMIO_DH(0x24d4, D_BDW_PLUS, NULL, NULL); 1388 MMIO_DH(0x24d8, D_BDW_PLUS, NULL, NULL); 1389 MMIO_DH(0x24dc, D_BDW_PLUS, NULL, NULL); 1390 1391 MMIO_D(0x83a4, D_BDW); 1392 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 1393 1394 MMIO_D(0x8430, D_BDW); 1395 1396 MMIO_D(0x110000, D_BDW_PLUS); 1397 1398 MMIO_D(0x48400, D_BDW_PLUS); 1399 1400 MMIO_D(0x6e570, D_BDW_PLUS); 1401 MMIO_D(0x65f10, D_BDW_PLUS); 1402 1403 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 1404 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 1405 MMIO_DFH(0xe180, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 1406 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 1407 1408 MMIO_D(0x2248, D_BDW); 1409 1410 return 0; 1411 } 1412 1413 static int init_skl_mmio_info(struct intel_gvt *gvt) 1414 { 1415 struct drm_i915_private *dev_priv = gvt->dev_priv; 1416 int ret; 1417 1418 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 1419 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 1420 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 1421 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 1422 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 1423 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 1424 1425 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, NULL); 1426 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, NULL); 1427 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, NULL); 1428 1429 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL); 1430 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, NULL); 1431 1432 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, NULL); 1433 MMIO_D(0xa210, D_SKL_PLUS); 1434 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 1435 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 1436 MMIO_DH(0x4ddc, D_SKL, NULL, NULL); 1437 MMIO_DH(0x42080, D_SKL, NULL, NULL); 1438 MMIO_D(0x45504, D_SKL); 1439 MMIO_D(0x45520, D_SKL); 1440 MMIO_D(0x46000, D_SKL); 1441 MMIO_DH(0x46010, D_SKL, NULL, NULL); 1442 MMIO_DH(0x46014, D_SKL, NULL, NULL); 1443 MMIO_D(0x6C040, D_SKL); 1444 MMIO_D(0x6C048, D_SKL); 1445 MMIO_D(0x6C050, D_SKL); 1446 MMIO_D(0x6C044, D_SKL); 1447 MMIO_D(0x6C04C, D_SKL); 1448 MMIO_D(0x6C054, D_SKL); 1449 MMIO_D(0x6c058, D_SKL); 1450 MMIO_D(0x6c05c, D_SKL); 1451 MMIO_DH(0x6c060, D_SKL, NULL, NULL); 1452 1453 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, NULL); 1454 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, NULL); 1455 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, NULL); 1456 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, NULL); 1457 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, NULL); 1458 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, NULL); 1459 1460 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, NULL); 1461 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, NULL); 1462 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, NULL); 1463 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, NULL); 1464 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, NULL); 1465 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, NULL); 1466 1467 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, NULL); 1468 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, NULL); 1469 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, NULL); 1470 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, NULL); 1471 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, NULL); 1472 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, NULL); 1473 1474 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 1475 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 1476 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 1477 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 1478 1479 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 1480 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 1481 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 1482 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 1483 1484 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 1485 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 1486 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 1487 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 1488 1489 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL); 1490 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL); 1491 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL); 1492 1493 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 1494 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 1495 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 1496 1497 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 1498 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 1499 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 1500 1501 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 1502 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 1503 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 1504 1505 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 1506 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 1507 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 1508 1509 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL); 1510 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL); 1511 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL); 1512 1513 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL); 1514 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL); 1515 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL); 1516 1517 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL); 1518 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL); 1519 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL); 1520 1521 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL); 1522 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL); 1523 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL); 1524 1525 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 1526 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 1527 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 1528 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 1529 1530 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 1531 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 1532 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 1533 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 1534 1535 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 1536 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 1537 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 1538 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 1539 1540 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL); 1541 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL); 1542 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL); 1543 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL); 1544 1545 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL); 1546 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL); 1547 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL); 1548 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL); 1549 1550 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL); 1551 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL); 1552 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL); 1553 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL); 1554 1555 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL); 1556 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL); 1557 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL); 1558 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL); 1559 1560 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL); 1561 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL); 1562 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL); 1563 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL); 1564 1565 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL); 1566 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL); 1567 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL); 1568 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL); 1569 1570 MMIO_D(0x70380, D_SKL); 1571 MMIO_D(0x71380, D_SKL); 1572 MMIO_D(0x72380, D_SKL); 1573 MMIO_D(0x7039c, D_SKL); 1574 1575 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL); 1576 MMIO_D(0x8f074, D_SKL); 1577 MMIO_D(0x8f004, D_SKL); 1578 MMIO_D(0x8f034, D_SKL); 1579 1580 MMIO_D(0xb11c, D_SKL); 1581 1582 MMIO_D(0x51000, D_SKL); 1583 MMIO_D(0x6c00c, D_SKL); 1584 1585 MMIO_F(0xc800, 0x7f8, 0, 0, 0, D_SKL, NULL, NULL); 1586 MMIO_F(0xb020, 0x80, 0, 0, 0, D_SKL, NULL, NULL); 1587 1588 MMIO_D(0xd08, D_SKL); 1589 MMIO_D(0x20e0, D_SKL); 1590 MMIO_D(0x20ec, D_SKL); 1591 1592 /* TRTT */ 1593 MMIO_D(0x4de0, D_SKL); 1594 MMIO_D(0x4de4, D_SKL); 1595 MMIO_D(0x4de8, D_SKL); 1596 MMIO_D(0x4dec, D_SKL); 1597 MMIO_D(0x4df0, D_SKL); 1598 MMIO_DH(0x4df4, D_SKL, NULL, gen9_trtte_write); 1599 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write); 1600 1601 MMIO_D(0x45008, D_SKL); 1602 1603 MMIO_D(0x46430, D_SKL); 1604 1605 MMIO_D(0x46520, D_SKL); 1606 1607 MMIO_D(0xc403c, D_SKL); 1608 MMIO_D(0xb004, D_SKL); 1609 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 1610 1611 MMIO_D(0x65900, D_SKL); 1612 MMIO_D(0x1082c0, D_SKL); 1613 MMIO_D(0x4068, D_SKL); 1614 MMIO_D(0x67054, D_SKL); 1615 MMIO_D(0x6e560, D_SKL); 1616 MMIO_D(0x6e554, D_SKL); 1617 MMIO_D(0x2b20, D_SKL); 1618 MMIO_D(0x65f00, D_SKL); 1619 MMIO_D(0x65f08, D_SKL); 1620 MMIO_D(0x320f0, D_SKL); 1621 1622 MMIO_D(_REG_VCS2_EXCC, D_SKL); 1623 MMIO_D(0x70034, D_SKL); 1624 MMIO_D(0x71034, D_SKL); 1625 MMIO_D(0x72034, D_SKL); 1626 1627 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL); 1628 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL); 1629 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL); 1630 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL); 1631 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL); 1632 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL); 1633 1634 MMIO_D(0x44500, D_SKL); 1635 return 0; 1636 } 1637 /** 1638 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset 1639 * @gvt: GVT device 1640 * @offset: register offset 1641 * 1642 * This function is used to find the MMIO information entry from hash table 1643 * 1644 * Returns: 1645 * pointer to MMIO information entry, NULL if not exists 1646 */ 1647 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 1648 unsigned int offset) 1649 { 1650 struct intel_gvt_mmio_info *e; 1651 1652 WARN_ON(!IS_ALIGNED(offset, 4)); 1653 1654 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 1655 if (e->offset == offset) 1656 return e; 1657 } 1658 return NULL; 1659 } 1660 1661 /** 1662 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 1663 * @gvt: GVT device 1664 * 1665 * This function is called at the driver unloading stage, to clean up the MMIO 1666 * information table of GVT device 1667 * 1668 */ 1669 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 1670 { 1671 struct hlist_node *tmp; 1672 struct intel_gvt_mmio_info *e; 1673 int i; 1674 1675 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 1676 kfree(e); 1677 1678 vfree(gvt->mmio.mmio_attribute); 1679 gvt->mmio.mmio_attribute = NULL; 1680 } 1681 1682 /** 1683 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 1684 * @gvt: GVT device 1685 * 1686 * This function is called at the initialization stage, to setup the MMIO 1687 * information table for GVT device 1688 * 1689 * Returns: 1690 * zero on success, negative if failed. 1691 */ 1692 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 1693 { 1694 struct intel_gvt_device_info *info = &gvt->device_info; 1695 struct drm_i915_private *dev_priv = gvt->dev_priv; 1696 int ret; 1697 1698 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size); 1699 if (!gvt->mmio.mmio_attribute) 1700 return -ENOMEM; 1701 1702 ret = init_generic_mmio_info(gvt); 1703 if (ret) 1704 goto err; 1705 1706 if (IS_BROADWELL(dev_priv)) { 1707 ret = init_broadwell_mmio_info(gvt); 1708 if (ret) 1709 goto err; 1710 } else if (IS_SKYLAKE(dev_priv)) { 1711 ret = init_broadwell_mmio_info(gvt); 1712 if (ret) 1713 goto err; 1714 ret = init_skl_mmio_info(gvt); 1715 if (ret) 1716 goto err; 1717 } 1718 return 0; 1719 err: 1720 intel_gvt_clean_mmio_info(gvt); 1721 return ret; 1722 } 1723 1724 /** 1725 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 1726 * @gvt: a GVT device 1727 * @offset: register offset 1728 * 1729 */ 1730 void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset) 1731 { 1732 gvt->mmio.mmio_attribute[offset >> 2] |= 1733 F_ACCESSED; 1734 } 1735 1736 /** 1737 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 1738 * @gvt: a GVT device 1739 * @offset: register offset 1740 * 1741 */ 1742 bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt, 1743 unsigned int offset) 1744 { 1745 return gvt->mmio.mmio_attribute[offset >> 2] & 1746 F_CMD_ACCESS; 1747 } 1748 1749 /** 1750 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 1751 * @gvt: a GVT device 1752 * @offset: register offset 1753 * 1754 */ 1755 bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, 1756 unsigned int offset) 1757 { 1758 return gvt->mmio.mmio_attribute[offset >> 2] & 1759 F_UNALIGN; 1760 } 1761 1762 /** 1763 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 1764 * @gvt: a GVT device 1765 * @offset: register offset 1766 * 1767 */ 1768 void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt, 1769 unsigned int offset) 1770 { 1771 gvt->mmio.mmio_attribute[offset >> 2] |= 1772 F_CMD_ACCESSED; 1773 } 1774 1775 /** 1776 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 1777 * @gvt: a GVT device 1778 * @offset: register offset 1779 * 1780 * Returns: 1781 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 1782 * 1783 */ 1784 bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset) 1785 { 1786 return gvt->mmio.mmio_attribute[offset >> 2] & 1787 F_MODE_MASK; 1788 } 1789 1790 /** 1791 * intel_vgpu_default_mmio_read - default MMIO read handler 1792 * @vgpu: a vGPU 1793 * @offset: access offset 1794 * @p_data: data return buffer 1795 * @bytes: access data length 1796 * 1797 * Returns: 1798 * Zero on success, negative error code if failed. 1799 */ 1800 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1801 void *p_data, unsigned int bytes) 1802 { 1803 read_vreg(vgpu, offset, p_data, bytes); 1804 return 0; 1805 } 1806 1807 /** 1808 * intel_t_default_mmio_write - default MMIO write handler 1809 * @vgpu: a vGPU 1810 * @offset: access offset 1811 * @p_data: write data buffer 1812 * @bytes: access data length 1813 * 1814 * Returns: 1815 * Zero on success, negative error code if failed. 1816 */ 1817 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1818 void *p_data, unsigned int bytes) 1819 { 1820 write_vreg(vgpu, offset, p_data, bytes); 1821 return 0; 1822 } 1823