1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include <drm/display/drm_dp.h> 40 41 #include "i915_drv.h" 42 #include "i915_reg.h" 43 #include "gvt.h" 44 #include "i915_pvinfo.h" 45 #include "intel_mchbar_regs.h" 46 #include "display/bxt_dpio_phy_regs.h" 47 #include "display/i9xx_plane_regs.h" 48 #include "display/intel_crt_regs.h" 49 #include "display/intel_cursor_regs.h" 50 #include "display/intel_display_types.h" 51 #include "display/intel_dmc_regs.h" 52 #include "display/intel_dp_aux_regs.h" 53 #include "display/intel_dpio_phy.h" 54 #include "display/intel_fbc.h" 55 #include "display/intel_fdi_regs.h" 56 #include "display/intel_pps_regs.h" 57 #include "display/intel_psr_regs.h" 58 #include "display/intel_sprite_regs.h" 59 #include "display/skl_universal_plane_regs.h" 60 #include "display/skl_watermark_regs.h" 61 #include "display/vlv_dsi_pll_regs.h" 62 #include "gt/intel_gt_regs.h" 63 #include <linux/vmalloc.h> 64 65 /* XXX FIXME i915 has changed PP_XXX definition */ 66 #define PCH_PP_STATUS _MMIO(0xc7200) 67 #define PCH_PP_CONTROL _MMIO(0xc7204) 68 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 69 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 70 #define PCH_PP_DIVISOR _MMIO(0xc7210) 71 72 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 73 { 74 struct drm_i915_private *i915 = gvt->gt->i915; 75 76 if (IS_BROADWELL(i915)) 77 return D_BDW; 78 else if (IS_SKYLAKE(i915)) 79 return D_SKL; 80 else if (IS_KABYLAKE(i915)) 81 return D_KBL; 82 else if (IS_BROXTON(i915)) 83 return D_BXT; 84 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 85 return D_CFL; 86 87 return 0; 88 } 89 90 static bool intel_gvt_match_device(struct intel_gvt *gvt, 91 unsigned long device) 92 { 93 return intel_gvt_get_device_type(gvt) & device; 94 } 95 96 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 97 void *p_data, unsigned int bytes) 98 { 99 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 100 } 101 102 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 103 void *p_data, unsigned int bytes) 104 { 105 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 106 } 107 108 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 109 unsigned int offset) 110 { 111 struct intel_gvt_mmio_info *e; 112 113 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 114 if (e->offset == offset) 115 return e; 116 } 117 return NULL; 118 } 119 120 static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size, 121 u16 flags, u32 addr_mask, u32 ro_mask, u32 device, 122 gvt_mmio_func read, gvt_mmio_func write) 123 { 124 struct intel_gvt_mmio_info *p; 125 u32 start, end, i; 126 127 if (!intel_gvt_match_device(gvt, device)) 128 return 0; 129 130 if (WARN_ON(!IS_ALIGNED(offset, 4))) 131 return -EINVAL; 132 133 start = offset; 134 end = offset + size; 135 136 for (i = start; i < end; i += 4) { 137 p = intel_gvt_find_mmio_info(gvt, i); 138 if (!p) { 139 WARN(1, "assign a handler to a non-tracked mmio %x\n", 140 i); 141 return -ENODEV; 142 } 143 p->ro_mask = ro_mask; 144 gvt->mmio.mmio_attribute[i / 4] = flags; 145 if (read) 146 p->read = read; 147 if (write) 148 p->write = write; 149 } 150 return 0; 151 } 152 153 /** 154 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine 155 * @gvt: a GVT device 156 * @offset: register offset 157 * 158 * Returns: 159 * The engine containing the offset within its mmio page. 160 */ 161 const struct intel_engine_cs * 162 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset) 163 { 164 struct intel_engine_cs *engine; 165 enum intel_engine_id id; 166 167 offset &= ~GENMASK(11, 0); 168 for_each_engine(engine, gvt->gt, id) 169 if (engine->mmio_base == offset) 170 return engine; 171 172 return NULL; 173 } 174 175 #define offset_to_fence_num(offset) \ 176 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 177 178 #define fence_num_to_offset(num) \ 179 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 180 181 182 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 183 { 184 switch (reason) { 185 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 186 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 187 break; 188 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 189 pr_err("Graphics resource is not enough for the guest\n"); 190 break; 191 case GVT_FAILSAFE_GUEST_ERR: 192 pr_err("GVT Internal error for the guest\n"); 193 break; 194 default: 195 break; 196 } 197 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 198 vgpu->failsafe = true; 199 } 200 201 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 202 unsigned int fence_num, void *p_data, unsigned int bytes) 203 { 204 unsigned int max_fence = vgpu_fence_sz(vgpu); 205 206 if (fence_num >= max_fence) { 207 gvt_vgpu_err("access oob fence reg %d/%d\n", 208 fence_num, max_fence); 209 210 /* When guest access oob fence regs without access 211 * pv_info first, we treat guest not supporting GVT, 212 * and we will let vgpu enter failsafe mode. 213 */ 214 if (!vgpu->pv_notified) 215 enter_failsafe_mode(vgpu, 216 GVT_FAILSAFE_UNSUPPORTED_GUEST); 217 218 memset(p_data, 0, bytes); 219 return -EINVAL; 220 } 221 return 0; 222 } 223 224 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 225 unsigned int offset, void *p_data, unsigned int bytes) 226 { 227 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; 228 229 if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) { 230 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) 231 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); 232 else if (!ips) 233 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); 234 else { 235 /* All engines must be enabled together for vGPU, 236 * since we don't know which engine the ppgtt will 237 * bind to when shadowing. 238 */ 239 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", 240 ips); 241 return -EINVAL; 242 } 243 } 244 245 write_vreg(vgpu, offset, p_data, bytes); 246 return 0; 247 } 248 249 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 250 void *p_data, unsigned int bytes) 251 { 252 int ret; 253 254 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 255 p_data, bytes); 256 if (ret) 257 return ret; 258 read_vreg(vgpu, off, p_data, bytes); 259 return 0; 260 } 261 262 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 263 void *p_data, unsigned int bytes) 264 { 265 struct intel_gvt *gvt = vgpu->gvt; 266 unsigned int fence_num = offset_to_fence_num(off); 267 intel_wakeref_t wakeref; 268 int ret; 269 270 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 271 if (ret) 272 return ret; 273 write_vreg(vgpu, off, p_data, bytes); 274 275 wakeref = mmio_hw_access_pre(gvt->gt); 276 intel_vgpu_write_fence(vgpu, fence_num, 277 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 278 mmio_hw_access_post(gvt->gt, wakeref); 279 return 0; 280 } 281 282 #define CALC_MODE_MASK_REG(old, new) \ 283 (((new) & GENMASK(31, 16)) \ 284 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 285 | ((new) & ((new) >> 16)))) 286 287 static int mul_force_wake_write(struct intel_vgpu *vgpu, 288 unsigned int offset, void *p_data, unsigned int bytes) 289 { 290 u32 old, new; 291 u32 ack_reg_offset; 292 293 old = vgpu_vreg(vgpu, offset); 294 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 295 296 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) { 297 switch (offset) { 298 case FORCEWAKE_RENDER_GEN9_REG: 299 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 300 break; 301 case FORCEWAKE_GT_GEN9_REG: 302 ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG; 303 break; 304 case FORCEWAKE_MEDIA_GEN9_REG: 305 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 306 break; 307 default: 308 /*should not hit here*/ 309 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 310 return -EINVAL; 311 } 312 } else { 313 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 314 } 315 316 vgpu_vreg(vgpu, offset) = new; 317 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 318 return 0; 319 } 320 321 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 322 void *p_data, unsigned int bytes) 323 { 324 intel_engine_mask_t engine_mask = 0; 325 u32 data; 326 327 write_vreg(vgpu, offset, p_data, bytes); 328 data = vgpu_vreg(vgpu, offset); 329 330 if (data & GEN6_GRDOM_FULL) { 331 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 332 engine_mask = ALL_ENGINES; 333 } else { 334 if (data & GEN6_GRDOM_RENDER) { 335 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 336 engine_mask |= BIT(RCS0); 337 } 338 if (data & GEN6_GRDOM_MEDIA) { 339 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 340 engine_mask |= BIT(VCS0); 341 } 342 if (data & GEN6_GRDOM_BLT) { 343 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 344 engine_mask |= BIT(BCS0); 345 } 346 if (data & GEN6_GRDOM_VECS) { 347 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 348 engine_mask |= BIT(VECS0); 349 } 350 if (data & GEN8_GRDOM_MEDIA2) { 351 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 352 engine_mask |= BIT(VCS1); 353 } 354 if (data & GEN9_GRDOM_GUC) { 355 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); 356 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; 357 } 358 engine_mask &= vgpu->gvt->gt->info.engine_mask; 359 } 360 361 /* vgpu_lock already hold by emulate mmio r/w */ 362 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 363 364 /* sw will wait for the device to ack the reset request */ 365 vgpu_vreg(vgpu, offset) = 0; 366 367 return 0; 368 } 369 370 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 371 void *p_data, unsigned int bytes) 372 { 373 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 374 } 375 376 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 377 void *p_data, unsigned int bytes) 378 { 379 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 380 } 381 382 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 383 unsigned int offset, void *p_data, unsigned int bytes) 384 { 385 write_vreg(vgpu, offset, p_data, bytes); 386 387 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 388 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 389 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 390 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 391 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 392 393 } else 394 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 395 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 396 | PP_CYCLE_DELAY_ACTIVE); 397 return 0; 398 } 399 400 static int transconf_mmio_write(struct intel_vgpu *vgpu, 401 unsigned int offset, void *p_data, unsigned int bytes) 402 { 403 write_vreg(vgpu, offset, p_data, bytes); 404 405 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 406 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 407 else 408 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 409 return 0; 410 } 411 412 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 413 void *p_data, unsigned int bytes) 414 { 415 write_vreg(vgpu, offset, p_data, bytes); 416 417 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 418 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 419 else 420 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 421 422 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 423 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 424 else 425 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 426 427 return 0; 428 } 429 430 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 431 void *p_data, unsigned int bytes) 432 { 433 switch (offset) { 434 case 0xe651c: 435 case 0xe661c: 436 case 0xe671c: 437 case 0xe681c: 438 vgpu_vreg(vgpu, offset) = 1 << 17; 439 break; 440 case 0xe6c04: 441 vgpu_vreg(vgpu, offset) = 0x3; 442 break; 443 case 0xe6e1c: 444 vgpu_vreg(vgpu, offset) = 0x2f << 16; 445 break; 446 default: 447 return -EINVAL; 448 } 449 450 read_vreg(vgpu, offset, p_data, bytes); 451 return 0; 452 } 453 454 /* 455 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to 456 * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on 457 * setup_virtual_dp_monitor(). 458 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled 459 * DPLL. Later guest driver may setup a different DPLLx when setting mode. 460 * So the correct sequence to find DP stream clock is: 461 * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x. 462 * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate. 463 * Then Refresh rate then can be calculated based on follow equations: 464 * Pixel clock = h_total * v_total * refresh_rate 465 * stream clock = Pixel clock 466 * ls_clk = DP bitrate 467 * Link M/N = strm_clk / ls_clk 468 */ 469 470 static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 471 { 472 u32 dp_br = 0; 473 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); 474 475 switch (ddi_pll_sel) { 476 case PORT_CLK_SEL_LCPLL_2700: 477 dp_br = 270000 * 2; 478 break; 479 case PORT_CLK_SEL_LCPLL_1350: 480 dp_br = 135000 * 2; 481 break; 482 case PORT_CLK_SEL_LCPLL_810: 483 dp_br = 81000 * 2; 484 break; 485 case PORT_CLK_SEL_SPLL: 486 { 487 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { 488 case SPLL_FREQ_810MHz: 489 dp_br = 81000 * 2; 490 break; 491 case SPLL_FREQ_1350MHz: 492 dp_br = 135000 * 2; 493 break; 494 case SPLL_FREQ_2700MHz: 495 dp_br = 270000 * 2; 496 break; 497 default: 498 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n", 499 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); 500 break; 501 } 502 break; 503 } 504 case PORT_CLK_SEL_WRPLL1: 505 case PORT_CLK_SEL_WRPLL2: 506 { 507 u32 wrpll_ctl; 508 int refclk, n, p, r; 509 510 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1) 511 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); 512 else 513 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2)); 514 515 switch (wrpll_ctl & WRPLL_REF_MASK) { 516 case WRPLL_REF_PCH_SSC: 517 refclk = 135000; 518 break; 519 case WRPLL_REF_LCPLL: 520 refclk = 2700000; 521 break; 522 default: 523 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n", 524 vgpu->id, port_name(port), wrpll_ctl); 525 goto out; 526 } 527 528 r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK; 529 p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 530 n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 531 532 dp_br = (refclk * n / 10) / (p * r) * 2; 533 break; 534 } 535 default: 536 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", 537 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port))); 538 break; 539 } 540 541 out: 542 return dp_br; 543 } 544 545 static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 546 { 547 u32 dp_br = 0; 548 int refclk = 100000; 549 enum dpio_phy phy = DPIO_PHY0; 550 enum dpio_channel ch = DPIO_CH0; 551 struct dpll clock = {}; 552 u32 temp; 553 554 /* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */ 555 switch (port) { 556 case PORT_A: 557 phy = DPIO_PHY1; 558 ch = DPIO_CH0; 559 break; 560 case PORT_B: 561 phy = DPIO_PHY0; 562 ch = DPIO_CH0; 563 break; 564 case PORT_C: 565 phy = DPIO_PHY0; 566 ch = DPIO_CH1; 567 break; 568 default: 569 gvt_dbg_dpy("vgpu-%d no PHY for PORT_%c\n", vgpu->id, port_name(port)); 570 goto out; 571 } 572 573 temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)); 574 if (!(temp & PORT_PLL_ENABLE) || !(temp & PORT_PLL_LOCK)) { 575 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n", 576 vgpu->id, port_name(port), temp); 577 goto out; 578 } 579 580 clock.m1 = 2; 581 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, 582 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22; 583 if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE) 584 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, 585 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2))); 586 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, 587 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1))); 588 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, 589 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); 590 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, 591 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); 592 clock.m = clock.m1 * clock.m2; 593 clock.p = clock.p1 * clock.p2 * 5; 594 595 if (clock.n == 0 || clock.p == 0) { 596 gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port)); 597 goto out; 598 } 599 600 clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22); 601 clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p); 602 603 dp_br = clock.dot; 604 605 out: 606 return dp_br; 607 } 608 609 static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 610 { 611 u32 dp_br = 0; 612 enum intel_dpll_id dpll_id = DPLL_ID_SKL_DPLL0; 613 614 /* Find the enabled DPLL for the DDI/PORT */ 615 if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) && 616 (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) { 617 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) & 618 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 619 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 620 } else { 621 gvt_dbg_dpy("vgpu-%d DPLL for PORT_%c isn't turned on\n", 622 vgpu->id, port_name(port)); 623 return dp_br; 624 } 625 626 /* Find PLL output frequency from correct DPLL, and get bir rate */ 627 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) & 628 DPLL_CTRL1_LINK_RATE_MASK(dpll_id)) >> 629 DPLL_CTRL1_LINK_RATE_SHIFT(dpll_id)) { 630 case DPLL_CTRL1_LINK_RATE_810: 631 dp_br = 81000 * 2; 632 break; 633 case DPLL_CTRL1_LINK_RATE_1080: 634 dp_br = 108000 * 2; 635 break; 636 case DPLL_CTRL1_LINK_RATE_1350: 637 dp_br = 135000 * 2; 638 break; 639 case DPLL_CTRL1_LINK_RATE_1620: 640 dp_br = 162000 * 2; 641 break; 642 case DPLL_CTRL1_LINK_RATE_2160: 643 dp_br = 216000 * 2; 644 break; 645 case DPLL_CTRL1_LINK_RATE_2700: 646 dp_br = 270000 * 2; 647 break; 648 default: 649 dp_br = 0; 650 gvt_dbg_dpy("vgpu-%d PORT_%c fail to get DPLL-%d freq\n", 651 vgpu->id, port_name(port), dpll_id); 652 } 653 654 return dp_br; 655 } 656 657 static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) 658 { 659 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 660 struct intel_display *display = &dev_priv->display; 661 enum port port; 662 u32 dp_br, link_m, link_n, htotal, vtotal; 663 664 /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */ 665 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) & 666 TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 667 if (port != PORT_B && port != PORT_D) { 668 gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port)); 669 return; 670 } 671 672 /* Calculate DP bitrate from PLL */ 673 if (IS_BROADWELL(dev_priv)) 674 dp_br = bdw_vgpu_get_dp_bitrate(vgpu, port); 675 else if (IS_BROXTON(dev_priv)) 676 dp_br = bxt_vgpu_get_dp_bitrate(vgpu, port); 677 else 678 dp_br = skl_vgpu_get_dp_bitrate(vgpu, port); 679 680 /* Get DP link symbol clock M/N */ 681 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)); 682 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)); 683 684 /* Get H/V total from transcoder timing */ 685 htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); 686 vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); 687 688 if (dp_br && link_n && htotal && vtotal) { 689 u64 pixel_clk = 0; 690 u32 new_rate = 0; 691 u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k); 692 693 /* Calculate pixel clock by (ls_clk * M / N) */ 694 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); 695 pixel_clk *= MSEC_PER_SEC; 696 697 /* Calculate refresh rate by (pixel_clk / (h_total * v_total)) */ 698 new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1)); 699 700 if (*old_rate != new_rate) 701 *old_rate = new_rate; 702 703 gvt_dbg_dpy("vgpu-%d PIPE_%c refresh rate updated to %d\n", 704 vgpu->id, pipe_name(PIPE_A), new_rate); 705 } 706 } 707 708 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 709 void *p_data, unsigned int bytes) 710 { 711 u32 data; 712 713 write_vreg(vgpu, offset, p_data, bytes); 714 data = vgpu_vreg(vgpu, offset); 715 716 if (data & TRANSCONF_ENABLE) { 717 vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE; 718 vgpu_update_refresh_rate(vgpu); 719 vgpu_update_vblank_emulation(vgpu, true); 720 } else { 721 vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE; 722 vgpu_update_vblank_emulation(vgpu, false); 723 } 724 return 0; 725 } 726 727 /* sorted in ascending order */ 728 static i915_reg_t force_nonpriv_white_list[] = { 729 _MMIO(0xd80), 730 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 731 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 732 CL_PRIMITIVES_COUNT, //_MMIO(0x2340) 733 PS_INVOCATION_COUNT, //_MMIO(0x2348) 734 PS_DEPTH_COUNT, //_MMIO(0x2350) 735 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 736 _MMIO(0x2690), 737 _MMIO(0x2694), 738 _MMIO(0x2698), 739 _MMIO(0x2754), 740 _MMIO(0x28a0), 741 _MMIO(0x4de0), 742 _MMIO(0x4de4), 743 _MMIO(0x4dfc), 744 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 745 _MMIO(0x7014), 746 HDC_CHICKEN0,//_MMIO(0x7300) 747 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 748 _MMIO(0x7700), 749 _MMIO(0x7704), 750 _MMIO(0x7708), 751 _MMIO(0x770c), 752 _MMIO(0x83a8), 753 _MMIO(0xb110), 754 _MMIO(0xb118), 755 _MMIO(0xe100), 756 _MMIO(0xe18c), 757 _MMIO(0xe48c), 758 _MMIO(0xe5f4), 759 _MMIO(0x64844), 760 }; 761 762 /* a simple bsearch */ 763 static inline bool in_whitelist(u32 reg) 764 { 765 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 766 i915_reg_t *array = force_nonpriv_white_list; 767 768 while (left < right) { 769 int mid = (left + right)/2; 770 771 if (reg > array[mid].reg) 772 left = mid + 1; 773 else if (reg < array[mid].reg) 774 right = mid; 775 else 776 return true; 777 } 778 return false; 779 } 780 781 static int force_nonpriv_write(struct intel_vgpu *vgpu, 782 unsigned int offset, void *p_data, unsigned int bytes) 783 { 784 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2); 785 const struct intel_engine_cs *engine = 786 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 787 788 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) { 789 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 790 vgpu->id, offset, bytes); 791 return -EINVAL; 792 } 793 794 if (!in_whitelist(reg_nonpriv) && 795 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) { 796 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 797 vgpu->id, reg_nonpriv, offset); 798 } else 799 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 800 801 return 0; 802 } 803 804 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 805 void *p_data, unsigned int bytes) 806 { 807 write_vreg(vgpu, offset, p_data, bytes); 808 809 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 810 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 811 } else { 812 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 813 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 814 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 815 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 816 } 817 return 0; 818 } 819 820 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 821 unsigned int offset, void *p_data, unsigned int bytes) 822 { 823 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 824 return 0; 825 } 826 827 #define FDI_LINK_TRAIN_PATTERN1 0 828 #define FDI_LINK_TRAIN_PATTERN2 1 829 830 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 831 { 832 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 833 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 834 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 835 836 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 837 (rx_ctl & FDI_RX_ENABLE) && 838 (rx_ctl & FDI_AUTO_TRAINING) && 839 (tx_ctl & DP_TP_CTL_ENABLE) && 840 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 841 return 1; 842 else 843 return 0; 844 } 845 846 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 847 enum pipe pipe, unsigned int train_pattern) 848 { 849 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 850 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 851 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 852 unsigned int fdi_iir_check_bits; 853 854 fdi_rx_imr = FDI_RX_IMR(pipe); 855 fdi_tx_ctl = FDI_TX_CTL(pipe); 856 fdi_rx_ctl = FDI_RX_CTL(pipe); 857 858 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 859 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 860 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 861 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 862 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 863 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 864 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 865 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 866 } else { 867 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 868 return -EINVAL; 869 } 870 871 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 872 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 873 874 /* If imr bit has been masked */ 875 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 876 return 0; 877 878 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 879 == fdi_tx_check_bits) 880 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 881 == fdi_rx_check_bits)) 882 return 1; 883 else 884 return 0; 885 } 886 887 #define INVALID_INDEX (~0U) 888 889 static unsigned int calc_index(unsigned int offset, i915_reg_t _start, 890 i915_reg_t _next, i915_reg_t _end) 891 { 892 u32 start = i915_mmio_reg_offset(_start); 893 u32 next = i915_mmio_reg_offset(_next); 894 u32 end = i915_mmio_reg_offset(_end); 895 u32 stride = next - start; 896 897 if (offset < start || offset > end) 898 return INVALID_INDEX; 899 offset -= start; 900 return offset / stride; 901 } 902 903 #define FDI_RX_CTL_TO_PIPE(offset) \ 904 calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C)) 905 906 #define FDI_TX_CTL_TO_PIPE(offset) \ 907 calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C)) 908 909 #define FDI_RX_IMR_TO_PIPE(offset) \ 910 calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C)) 911 912 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 913 unsigned int offset, void *p_data, unsigned int bytes) 914 { 915 i915_reg_t fdi_rx_iir; 916 unsigned int index; 917 int ret; 918 919 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 920 index = FDI_RX_CTL_TO_PIPE(offset); 921 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 922 index = FDI_TX_CTL_TO_PIPE(offset); 923 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 924 index = FDI_RX_IMR_TO_PIPE(offset); 925 else { 926 gvt_vgpu_err("Unsupported registers %x\n", offset); 927 return -EINVAL; 928 } 929 930 write_vreg(vgpu, offset, p_data, bytes); 931 932 fdi_rx_iir = FDI_RX_IIR(index); 933 934 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 935 if (ret < 0) 936 return ret; 937 if (ret) 938 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 939 940 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 941 if (ret < 0) 942 return ret; 943 if (ret) 944 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 945 946 if (offset == _FDI_RXA_CTL) 947 if (fdi_auto_training_started(vgpu)) 948 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 949 DP_TP_STATUS_AUTOTRAIN_DONE; 950 return 0; 951 } 952 953 #define DP_TP_CTL_TO_PORT(offset) \ 954 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E)) 955 956 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 957 void *p_data, unsigned int bytes) 958 { 959 i915_reg_t status_reg; 960 unsigned int index; 961 u32 data; 962 963 write_vreg(vgpu, offset, p_data, bytes); 964 965 index = DP_TP_CTL_TO_PORT(offset); 966 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 967 if (data == 0x2) { 968 status_reg = DP_TP_STATUS(index); 969 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 970 } 971 return 0; 972 } 973 974 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 975 unsigned int offset, void *p_data, unsigned int bytes) 976 { 977 u32 reg_val; 978 u32 sticky_mask; 979 980 reg_val = *((u32 *)p_data); 981 sticky_mask = GENMASK(27, 26) | (1 << 24); 982 983 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 984 (vgpu_vreg(vgpu, offset) & sticky_mask); 985 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 986 return 0; 987 } 988 989 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 990 unsigned int offset, void *p_data, unsigned int bytes) 991 { 992 u32 data; 993 994 write_vreg(vgpu, offset, p_data, bytes); 995 data = vgpu_vreg(vgpu, offset); 996 997 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 998 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 999 return 0; 1000 } 1001 1002 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 1003 unsigned int offset, void *p_data, unsigned int bytes) 1004 { 1005 u32 data; 1006 1007 write_vreg(vgpu, offset, p_data, bytes); 1008 data = vgpu_vreg(vgpu, offset); 1009 1010 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 1011 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 1012 else 1013 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 1014 return 0; 1015 } 1016 1017 #define DSPSURF_TO_PIPE(display, offset) \ 1018 calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C)) 1019 1020 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1021 void *p_data, unsigned int bytes) 1022 { 1023 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1024 struct intel_display *display = &dev_priv->display; 1025 u32 pipe = DSPSURF_TO_PIPE(display, offset); 1026 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); 1027 1028 write_vreg(vgpu, offset, p_data, bytes); 1029 vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset); 1030 1031 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++; 1032 1033 if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP) 1034 intel_vgpu_trigger_virtual_event(vgpu, event); 1035 else 1036 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1037 1038 return 0; 1039 } 1040 1041 #define SPRSURF_TO_PIPE(offset) \ 1042 calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C)) 1043 1044 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1045 void *p_data, unsigned int bytes) 1046 { 1047 u32 pipe = SPRSURF_TO_PIPE(offset); 1048 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0); 1049 1050 write_vreg(vgpu, offset, p_data, bytes); 1051 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1052 1053 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) 1054 intel_vgpu_trigger_virtual_event(vgpu, event); 1055 else 1056 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1057 1058 return 0; 1059 } 1060 1061 static int reg50080_mmio_write(struct intel_vgpu *vgpu, 1062 unsigned int offset, void *p_data, 1063 unsigned int bytes) 1064 { 1065 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1066 struct intel_display *display = &dev_priv->display; 1067 enum pipe pipe = REG_50080_TO_PIPE(offset); 1068 enum plane_id plane = REG_50080_TO_PLANE(offset); 1069 int event = SKL_FLIP_EVENT(pipe, plane); 1070 1071 write_vreg(vgpu, offset, p_data, bytes); 1072 if (plane == PLANE_PRIMARY) { 1073 vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset); 1074 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++; 1075 } else { 1076 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1077 } 1078 1079 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) 1080 intel_vgpu_trigger_virtual_event(vgpu, event); 1081 else 1082 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1083 1084 return 0; 1085 } 1086 1087 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 1088 unsigned int reg) 1089 { 1090 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1091 enum intel_gvt_event_type event; 1092 1093 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) 1094 event = AUX_CHANNEL_A; 1095 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) || 1096 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) 1097 event = AUX_CHANNEL_B; 1098 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) || 1099 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) 1100 event = AUX_CHANNEL_C; 1101 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) || 1102 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) 1103 event = AUX_CHANNEL_D; 1104 else { 1105 drm_WARN_ON(&dev_priv->drm, true); 1106 return -EINVAL; 1107 } 1108 1109 intel_vgpu_trigger_virtual_event(vgpu, event); 1110 return 0; 1111 } 1112 1113 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 1114 unsigned int reg, int len, bool data_valid) 1115 { 1116 /* mark transaction done */ 1117 value |= DP_AUX_CH_CTL_DONE; 1118 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 1119 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 1120 1121 if (data_valid) 1122 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 1123 else 1124 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 1125 1126 /* message size */ 1127 value &= ~(0xf << 20); 1128 value |= (len << 20); 1129 vgpu_vreg(vgpu, reg) = value; 1130 1131 if (value & DP_AUX_CH_CTL_INTERRUPT) 1132 return trigger_aux_channel_interrupt(vgpu, reg); 1133 return 0; 1134 } 1135 1136 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 1137 u8 t) 1138 { 1139 if ((t & DP_TRAINING_PATTERN_MASK) == DP_TRAINING_PATTERN_1) { 1140 /* training pattern 1 for CR */ 1141 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 1142 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CR_DONE | 1143 DP_LANE_CR_DONE << 4; 1144 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 1145 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CR_DONE | 1146 DP_LANE_CR_DONE << 4; 1147 } else if ((t & DP_TRAINING_PATTERN_MASK) == 1148 DP_TRAINING_PATTERN_2) { 1149 /* training pattern 2 for EQ */ 1150 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 1151 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CHANNEL_EQ_DONE | 1152 DP_LANE_CHANNEL_EQ_DONE << 4; 1153 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_SYMBOL_LOCKED | 1154 DP_LANE_SYMBOL_LOCKED << 4; 1155 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 1156 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CHANNEL_EQ_DONE | 1157 DP_LANE_CHANNEL_EQ_DONE << 4; 1158 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_SYMBOL_LOCKED | 1159 DP_LANE_SYMBOL_LOCKED << 4; 1160 /* set INTERLANE_ALIGN_DONE */ 1161 dpcd->data[DP_LANE_ALIGN_STATUS_UPDATED] |= 1162 DP_INTERLANE_ALIGN_DONE; 1163 } else if ((t & DP_TRAINING_PATTERN_MASK) == 1164 DP_TRAINING_PATTERN_DISABLE) { 1165 /* finish link training */ 1166 /* set sink status as synchronized */ 1167 dpcd->data[DP_SINK_STATUS] = DP_RECEIVE_PORT_0_STATUS | 1168 DP_RECEIVE_PORT_1_STATUS; 1169 } 1170 } 1171 1172 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 1173 1174 #define dpy_is_valid_port(port) \ 1175 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 1176 1177 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 1178 unsigned int offset, void *p_data, unsigned int bytes) 1179 { 1180 struct intel_vgpu_display *display = &vgpu->display; 1181 int msg, addr, ctrl, op, len; 1182 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 1183 struct intel_vgpu_dpcd_data *dpcd = NULL; 1184 struct intel_vgpu_port *port = NULL; 1185 u32 data; 1186 1187 if (!dpy_is_valid_port(port_index)) { 1188 gvt_vgpu_err("Unsupported DP port access!\n"); 1189 return 0; 1190 } 1191 1192 write_vreg(vgpu, offset, p_data, bytes); 1193 data = vgpu_vreg(vgpu, offset); 1194 1195 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9 && 1196 offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) { 1197 /* SKL DPB/C/D aux ctl register changed */ 1198 return 0; 1199 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) && 1200 offset != i915_mmio_reg_offset(port_index ? 1201 PCH_DP_AUX_CH_CTL(port_index) : 1202 DP_AUX_CH_CTL(port_index))) { 1203 /* write to the data registers */ 1204 return 0; 1205 } 1206 1207 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 1208 /* just want to clear the sticky bits */ 1209 vgpu_vreg(vgpu, offset) = 0; 1210 return 0; 1211 } 1212 1213 port = &display->ports[port_index]; 1214 dpcd = port->dpcd; 1215 1216 /* read out message from DATA1 register */ 1217 msg = vgpu_vreg(vgpu, offset + 4); 1218 addr = (msg >> 8) & 0xffff; 1219 ctrl = (msg >> 24) & 0xff; 1220 len = msg & 0xff; 1221 op = ctrl >> 4; 1222 1223 if (op == DP_AUX_NATIVE_WRITE) { 1224 int t; 1225 u8 buf[16]; 1226 1227 if ((addr + len + 1) >= DPCD_SIZE) { 1228 /* 1229 * Write request exceeds what we supported, 1230 * DCPD spec: When a Source Device is writing a DPCD 1231 * address not supported by the Sink Device, the Sink 1232 * Device shall reply with AUX NACK and “M” equal to 1233 * zero. 1234 */ 1235 1236 /* NAK the write */ 1237 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 1238 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 1239 return 0; 1240 } 1241 1242 /* 1243 * Write request format: Headr (command + address + size) occupies 1244 * 4 bytes, followed by (len + 1) bytes of data. See details at 1245 * intel_dp_aux_transfer(). 1246 */ 1247 if ((len + 1 + 4) > AUX_BURST_SIZE) { 1248 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1249 return -EINVAL; 1250 } 1251 1252 /* unpack data from vreg to buf */ 1253 for (t = 0; t < 4; t++) { 1254 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 1255 1256 buf[t * 4] = (r >> 24) & 0xff; 1257 buf[t * 4 + 1] = (r >> 16) & 0xff; 1258 buf[t * 4 + 2] = (r >> 8) & 0xff; 1259 buf[t * 4 + 3] = r & 0xff; 1260 } 1261 1262 /* write to virtual DPCD */ 1263 if (dpcd && dpcd->data_valid) { 1264 for (t = 0; t <= len; t++) { 1265 int p = addr + t; 1266 1267 dpcd->data[p] = buf[t]; 1268 /* check for link training */ 1269 if (p == DP_TRAINING_PATTERN_SET) 1270 dp_aux_ch_ctl_link_training(dpcd, 1271 buf[t]); 1272 } 1273 } 1274 1275 /* ACK the write */ 1276 vgpu_vreg(vgpu, offset + 4) = 0; 1277 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 1278 dpcd && dpcd->data_valid); 1279 return 0; 1280 } 1281 1282 if (op == DP_AUX_NATIVE_READ) { 1283 int idx, i, ret = 0; 1284 1285 if ((addr + len + 1) >= DPCD_SIZE) { 1286 /* 1287 * read request exceeds what we supported 1288 * DPCD spec: A Sink Device receiving a Native AUX CH 1289 * read request for an unsupported DPCD address must 1290 * reply with an AUX ACK and read data set equal to 1291 * zero instead of replying with AUX NACK. 1292 */ 1293 1294 /* ACK the READ*/ 1295 vgpu_vreg(vgpu, offset + 4) = 0; 1296 vgpu_vreg(vgpu, offset + 8) = 0; 1297 vgpu_vreg(vgpu, offset + 12) = 0; 1298 vgpu_vreg(vgpu, offset + 16) = 0; 1299 vgpu_vreg(vgpu, offset + 20) = 0; 1300 1301 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1302 true); 1303 return 0; 1304 } 1305 1306 for (idx = 1; idx <= 5; idx++) { 1307 /* clear the data registers */ 1308 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 1309 } 1310 1311 /* 1312 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1313 */ 1314 if ((len + 2) > AUX_BURST_SIZE) { 1315 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1316 return -EINVAL; 1317 } 1318 1319 /* read from virtual DPCD to vreg */ 1320 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1321 if (dpcd && dpcd->data_valid) { 1322 for (i = 1; i <= (len + 1); i++) { 1323 int t; 1324 1325 t = dpcd->data[addr + i - 1]; 1326 t <<= (24 - 8 * (i % 4)); 1327 ret |= t; 1328 1329 if ((i % 4 == 3) || (i == (len + 1))) { 1330 vgpu_vreg(vgpu, offset + 1331 (i / 4 + 1) * 4) = ret; 1332 ret = 0; 1333 } 1334 } 1335 } 1336 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1337 dpcd && dpcd->data_valid); 1338 return 0; 1339 } 1340 1341 /* i2c transaction starts */ 1342 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1343 1344 if (data & DP_AUX_CH_CTL_INTERRUPT) 1345 trigger_aux_channel_interrupt(vgpu, offset); 1346 return 0; 1347 } 1348 1349 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1350 void *p_data, unsigned int bytes) 1351 { 1352 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1353 write_vreg(vgpu, offset, p_data, bytes); 1354 return 0; 1355 } 1356 1357 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1358 void *p_data, unsigned int bytes) 1359 { 1360 bool vga_disable; 1361 1362 write_vreg(vgpu, offset, p_data, bytes); 1363 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1364 1365 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1366 vga_disable ? "Disable" : "Enable"); 1367 return 0; 1368 } 1369 1370 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1371 unsigned int sbi_offset) 1372 { 1373 struct intel_vgpu_display *display = &vgpu->display; 1374 int num = display->sbi.number; 1375 int i; 1376 1377 for (i = 0; i < num; ++i) 1378 if (display->sbi.registers[i].offset == sbi_offset) 1379 break; 1380 1381 if (i == num) 1382 return 0; 1383 1384 return display->sbi.registers[i].value; 1385 } 1386 1387 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1388 unsigned int offset, u32 value) 1389 { 1390 struct intel_vgpu_display *display = &vgpu->display; 1391 int num = display->sbi.number; 1392 int i; 1393 1394 for (i = 0; i < num; ++i) { 1395 if (display->sbi.registers[i].offset == offset) 1396 break; 1397 } 1398 1399 if (i == num) { 1400 if (num == SBI_REG_MAX) { 1401 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1402 return; 1403 } 1404 display->sbi.number++; 1405 } 1406 1407 display->sbi.registers[i].offset = offset; 1408 display->sbi.registers[i].value = value; 1409 } 1410 1411 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1412 void *p_data, unsigned int bytes) 1413 { 1414 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1415 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1416 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1417 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1418 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1419 sbi_offset); 1420 } 1421 read_vreg(vgpu, offset, p_data, bytes); 1422 return 0; 1423 } 1424 1425 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1426 void *p_data, unsigned int bytes) 1427 { 1428 u32 data; 1429 1430 write_vreg(vgpu, offset, p_data, bytes); 1431 data = vgpu_vreg(vgpu, offset); 1432 1433 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1434 data |= SBI_READY; 1435 1436 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1437 data |= SBI_RESPONSE_SUCCESS; 1438 1439 vgpu_vreg(vgpu, offset) = data; 1440 1441 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1442 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1443 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1444 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1445 1446 write_virtual_sbi_register(vgpu, sbi_offset, 1447 vgpu_vreg_t(vgpu, SBI_DATA)); 1448 } 1449 return 0; 1450 } 1451 1452 #define _vgtif_reg(x) \ 1453 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1454 1455 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1456 void *p_data, unsigned int bytes) 1457 { 1458 bool invalid_read = false; 1459 1460 read_vreg(vgpu, offset, p_data, bytes); 1461 1462 switch (offset) { 1463 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1464 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1465 invalid_read = true; 1466 break; 1467 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1468 _vgtif_reg(avail_rs.fence_num): 1469 if (offset + bytes > 1470 _vgtif_reg(avail_rs.fence_num) + 4) 1471 invalid_read = true; 1472 break; 1473 case 0x78010: /* vgt_caps */ 1474 case 0x7881c: 1475 break; 1476 default: 1477 invalid_read = true; 1478 break; 1479 } 1480 if (invalid_read) 1481 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1482 offset, bytes, *(u32 *)p_data); 1483 vgpu->pv_notified = true; 1484 return 0; 1485 } 1486 1487 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1488 { 1489 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1490 struct intel_vgpu_mm *mm; 1491 u64 *pdps; 1492 1493 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1494 1495 switch (notification) { 1496 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1497 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1498 fallthrough; 1499 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1500 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1501 return PTR_ERR_OR_ZERO(mm); 1502 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1503 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1504 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1505 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1506 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1507 case 1: /* Remove this in guest driver. */ 1508 break; 1509 default: 1510 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1511 } 1512 return 0; 1513 } 1514 1515 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1516 { 1517 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj; 1518 char *env[3] = {NULL, NULL, NULL}; 1519 char vmid_str[20]; 1520 char display_ready_str[20]; 1521 1522 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1523 env[0] = display_ready_str; 1524 1525 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1526 env[1] = vmid_str; 1527 1528 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1529 } 1530 1531 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1532 void *p_data, unsigned int bytes) 1533 { 1534 u32 data = *(u32 *)p_data; 1535 bool invalid_write = false; 1536 1537 switch (offset) { 1538 case _vgtif_reg(display_ready): 1539 send_display_ready_uevent(vgpu, data ? 1 : 0); 1540 break; 1541 case _vgtif_reg(g2v_notify): 1542 handle_g2v_notification(vgpu, data); 1543 break; 1544 /* add xhot and yhot to handled list to avoid error log */ 1545 case _vgtif_reg(cursor_x_hot): 1546 case _vgtif_reg(cursor_y_hot): 1547 case _vgtif_reg(pdp[0].lo): 1548 case _vgtif_reg(pdp[0].hi): 1549 case _vgtif_reg(pdp[1].lo): 1550 case _vgtif_reg(pdp[1].hi): 1551 case _vgtif_reg(pdp[2].lo): 1552 case _vgtif_reg(pdp[2].hi): 1553 case _vgtif_reg(pdp[3].lo): 1554 case _vgtif_reg(pdp[3].hi): 1555 case _vgtif_reg(execlist_context_descriptor_lo): 1556 case _vgtif_reg(execlist_context_descriptor_hi): 1557 break; 1558 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1559 invalid_write = true; 1560 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1561 break; 1562 default: 1563 invalid_write = true; 1564 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1565 offset, bytes, data); 1566 break; 1567 } 1568 1569 if (!invalid_write) 1570 write_vreg(vgpu, offset, p_data, bytes); 1571 1572 return 0; 1573 } 1574 1575 static int pf_write(struct intel_vgpu *vgpu, 1576 unsigned int offset, void *p_data, unsigned int bytes) 1577 { 1578 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1579 u32 val = *(u32 *)p_data; 1580 1581 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1582 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1583 offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) { 1584 drm_WARN_ONCE(&i915->drm, true, 1585 "VM(%d): guest is trying to scaling a plane\n", 1586 vgpu->id); 1587 return 0; 1588 } 1589 1590 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1591 } 1592 1593 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1594 unsigned int offset, void *p_data, unsigned int bytes) 1595 { 1596 write_vreg(vgpu, offset, p_data, bytes); 1597 1598 if (vgpu_vreg(vgpu, offset) & 1599 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL)) 1600 vgpu_vreg(vgpu, offset) |= 1601 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1602 else 1603 vgpu_vreg(vgpu, offset) &= 1604 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1605 return 0; 1606 } 1607 1608 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1609 unsigned int offset, void *p_data, unsigned int bytes) 1610 { 1611 write_vreg(vgpu, offset, p_data, bytes); 1612 1613 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1614 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1615 else 1616 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1617 1618 return 0; 1619 } 1620 1621 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1622 unsigned int offset, void *p_data, unsigned int bytes) 1623 { 1624 write_vreg(vgpu, offset, p_data, bytes); 1625 1626 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1627 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1628 return 0; 1629 } 1630 1631 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1632 void *p_data, unsigned int bytes) 1633 { 1634 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1635 u32 mode; 1636 1637 write_vreg(vgpu, offset, p_data, bytes); 1638 mode = vgpu_vreg(vgpu, offset); 1639 1640 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1641 drm_WARN_ONCE(&i915->drm, 1, 1642 "VM(%d): iGVT-g doesn't support GuC\n", 1643 vgpu->id); 1644 return 0; 1645 } 1646 1647 return 0; 1648 } 1649 1650 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1651 void *p_data, unsigned int bytes) 1652 { 1653 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1654 u32 trtte = *(u32 *)p_data; 1655 1656 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1657 drm_WARN(&i915->drm, 1, 1658 "VM(%d): Use physical address for TRTT!\n", 1659 vgpu->id); 1660 return -EINVAL; 1661 } 1662 write_vreg(vgpu, offset, p_data, bytes); 1663 1664 return 0; 1665 } 1666 1667 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1668 void *p_data, unsigned int bytes) 1669 { 1670 write_vreg(vgpu, offset, p_data, bytes); 1671 return 0; 1672 } 1673 1674 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1675 void *p_data, unsigned int bytes) 1676 { 1677 u32 v = 0; 1678 1679 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1680 v |= (1 << 0); 1681 1682 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1683 v |= (1 << 8); 1684 1685 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1686 v |= (1 << 16); 1687 1688 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1689 v |= (1 << 24); 1690 1691 vgpu_vreg(vgpu, offset) = v; 1692 1693 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1694 } 1695 1696 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1697 void *p_data, unsigned int bytes) 1698 { 1699 u32 value = *(u32 *)p_data; 1700 u32 cmd = value & 0xff; 1701 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1702 1703 switch (cmd) { 1704 case GEN9_PCODE_READ_MEM_LATENCY: 1705 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1706 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1707 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1708 IS_COMETLAKE(vgpu->gvt->gt->i915)) { 1709 /** 1710 * "Read memory latency" command on gen9. 1711 * Below memory latency values are read 1712 * from skylake platform. 1713 */ 1714 if (!*data0) 1715 *data0 = 0x1e1a1100; 1716 else 1717 *data0 = 0x61514b3d; 1718 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) { 1719 /** 1720 * "Read memory latency" command on gen9. 1721 * Below memory latency values are read 1722 * from Broxton MRB. 1723 */ 1724 if (!*data0) 1725 *data0 = 0x16080707; 1726 else 1727 *data0 = 0x16161616; 1728 } 1729 break; 1730 case SKL_PCODE_CDCLK_CONTROL: 1731 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1732 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1733 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1734 IS_COMETLAKE(vgpu->gvt->gt->i915)) 1735 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1736 break; 1737 case GEN6_PCODE_READ_RC6VIDS: 1738 *data0 |= 0x1; 1739 break; 1740 } 1741 1742 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1743 vgpu->id, value, *data0); 1744 /** 1745 * PCODE_READY clear means ready for pcode read/write, 1746 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1747 * always emulate as pcode read/write success and ready for access 1748 * anytime, since we don't touch real physical registers here. 1749 */ 1750 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1751 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1752 } 1753 1754 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1755 void *p_data, unsigned int bytes) 1756 { 1757 u32 value = *(u32 *)p_data; 1758 const struct intel_engine_cs *engine = 1759 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1760 1761 if (value != 0 && 1762 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1763 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1764 offset, value); 1765 return -EINVAL; 1766 } 1767 1768 /* 1769 * Need to emulate all the HWSP register write to ensure host can 1770 * update the VM CSB status correctly. Here listed registers can 1771 * support BDW, SKL or other platforms with same HWSP registers. 1772 */ 1773 if (unlikely(!engine)) { 1774 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1775 offset); 1776 return -EINVAL; 1777 } 1778 vgpu->hws_pga[engine->id] = value; 1779 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1780 vgpu->id, value, offset); 1781 1782 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1783 } 1784 1785 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1786 unsigned int offset, void *p_data, unsigned int bytes) 1787 { 1788 u32 v = *(u32 *)p_data; 1789 1790 if (IS_BROXTON(vgpu->gvt->gt->i915)) 1791 v &= (1 << 31) | (1 << 29); 1792 else 1793 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1794 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1795 v |= (v >> 1); 1796 1797 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1798 } 1799 1800 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1801 void *p_data, unsigned int bytes) 1802 { 1803 u32 v = *(u32 *)p_data; 1804 1805 /* other bits are MBZ. */ 1806 v &= (1 << 31) | (1 << 30); 1807 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1808 1809 vgpu_vreg(vgpu, offset) = v; 1810 1811 return 0; 1812 } 1813 1814 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1815 unsigned int offset, void *p_data, unsigned int bytes) 1816 { 1817 u32 v = *(u32 *)p_data; 1818 1819 if (v & BXT_DE_PLL_PLL_ENABLE) 1820 v |= BXT_DE_PLL_LOCK; 1821 1822 vgpu_vreg(vgpu, offset) = v; 1823 1824 return 0; 1825 } 1826 1827 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1828 unsigned int offset, void *p_data, unsigned int bytes) 1829 { 1830 u32 v = *(u32 *)p_data; 1831 1832 if (v & PORT_PLL_ENABLE) 1833 v |= PORT_PLL_LOCK; 1834 1835 vgpu_vreg(vgpu, offset) = v; 1836 1837 return 0; 1838 } 1839 1840 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1841 unsigned int offset, void *p_data, unsigned int bytes) 1842 { 1843 u32 v = *(u32 *)p_data; 1844 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1845 1846 switch (offset) { 1847 case _PHY_CTL_FAMILY_EDP: 1848 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1849 break; 1850 case _PHY_CTL_FAMILY_DDI: 1851 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1852 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1853 break; 1854 } 1855 1856 vgpu_vreg(vgpu, offset) = v; 1857 1858 return 0; 1859 } 1860 1861 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1862 unsigned int offset, void *p_data, unsigned int bytes) 1863 { 1864 u32 v = vgpu_vreg(vgpu, offset); 1865 1866 v &= ~UNIQUE_TRANGE_EN_METHOD; 1867 1868 vgpu_vreg(vgpu, offset) = v; 1869 1870 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1871 } 1872 1873 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1874 unsigned int offset, void *p_data, unsigned int bytes) 1875 { 1876 u32 v = *(u32 *)p_data; 1877 1878 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1879 vgpu_vreg(vgpu, offset - 0x600) = v; 1880 vgpu_vreg(vgpu, offset - 0x800) = v; 1881 } else { 1882 vgpu_vreg(vgpu, offset - 0x400) = v; 1883 vgpu_vreg(vgpu, offset - 0x600) = v; 1884 } 1885 1886 vgpu_vreg(vgpu, offset) = v; 1887 1888 return 0; 1889 } 1890 1891 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1892 unsigned int offset, void *p_data, unsigned int bytes) 1893 { 1894 u32 v = *(u32 *)p_data; 1895 1896 if (v & BIT(0)) { 1897 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1898 ~PHY_RESERVED; 1899 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1900 PHY_POWER_GOOD; 1901 } 1902 1903 if (v & BIT(1)) { 1904 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1905 ~PHY_RESERVED; 1906 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1907 PHY_POWER_GOOD; 1908 } 1909 1910 1911 vgpu_vreg(vgpu, offset) = v; 1912 1913 return 0; 1914 } 1915 1916 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1917 unsigned int offset, void *p_data, unsigned int bytes) 1918 { 1919 vgpu_vreg(vgpu, offset) = 0; 1920 return 0; 1921 } 1922 1923 /* 1924 * FixMe: 1925 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did: 1926 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.) 1927 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing 1928 * these MI_BATCH_BUFFER. 1929 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT 1930 * PML4 PTE: PAT(0) PCD(1) PWT(1). 1931 * The performance is still expected to be low, will need further improvement. 1932 */ 1933 static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset, 1934 void *p_data, unsigned int bytes) 1935 { 1936 u64 pat = 1937 GEN8_PPAT(0, CHV_PPAT_SNOOP) | 1938 GEN8_PPAT(1, 0) | 1939 GEN8_PPAT(2, 0) | 1940 GEN8_PPAT(3, CHV_PPAT_SNOOP) | 1941 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 1942 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 1943 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 1944 GEN8_PPAT(7, CHV_PPAT_SNOOP); 1945 1946 vgpu_vreg(vgpu, offset) = lower_32_bits(pat); 1947 1948 return 0; 1949 } 1950 1951 static int guc_status_read(struct intel_vgpu *vgpu, 1952 unsigned int offset, void *p_data, 1953 unsigned int bytes) 1954 { 1955 /* keep MIA_IN_RESET before clearing */ 1956 read_vreg(vgpu, offset, p_data, bytes); 1957 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET; 1958 return 0; 1959 } 1960 1961 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1962 unsigned int offset, void *p_data, unsigned int bytes) 1963 { 1964 struct intel_gvt *gvt = vgpu->gvt; 1965 const struct intel_engine_cs *engine = 1966 intel_gvt_render_mmio_to_engine(gvt, offset); 1967 1968 /** 1969 * Read HW reg in following case 1970 * a. the offset isn't a ring mmio 1971 * b. the offset's ring is running on hw. 1972 * c. the offset is ring time stamp mmio 1973 */ 1974 1975 if (!engine || 1976 vgpu == gvt->scheduler.engine_owner[engine->id] || 1977 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) || 1978 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) { 1979 intel_wakeref_t wakeref; 1980 1981 wakeref = mmio_hw_access_pre(gvt->gt); 1982 vgpu_vreg(vgpu, offset) = 1983 intel_uncore_read(gvt->gt->uncore, _MMIO(offset)); 1984 mmio_hw_access_post(gvt->gt, wakeref); 1985 } 1986 1987 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1988 } 1989 1990 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1991 void *p_data, unsigned int bytes) 1992 { 1993 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1994 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1995 struct intel_vgpu_execlist *execlist; 1996 u32 data = *(u32 *)p_data; 1997 int ret = 0; 1998 1999 if (drm_WARN_ON(&i915->drm, !engine)) 2000 return -EINVAL; 2001 2002 /* 2003 * Due to d3_entered is used to indicate skipping PPGTT invalidation on 2004 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after 2005 * vGPU reset if in resuming. 2006 * In S0ix exit, the device power state also transite from D3 to D0 as 2007 * S3 resume, but no vGPU reset (triggered by QEMU device model). After 2008 * S0ix exit, all engines continue to work. However the d3_entered 2009 * remains set which will break next vGPU reset logic (miss the expected 2010 * PPGTT invalidation). 2011 * Engines can only work in D0. Thus the 1st elsp write gives GVT a 2012 * chance to clear d3_entered. 2013 */ 2014 if (vgpu->d3_entered) 2015 vgpu->d3_entered = false; 2016 2017 execlist = &vgpu->submission.execlist[engine->id]; 2018 2019 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 2020 if (execlist->elsp_dwords.index == 3) { 2021 ret = intel_vgpu_submit_execlist(vgpu, engine); 2022 if(ret) 2023 gvt_vgpu_err("fail submit workload on ring %s\n", 2024 engine->name); 2025 } 2026 2027 ++execlist->elsp_dwords.index; 2028 execlist->elsp_dwords.index &= 0x3; 2029 return ret; 2030 } 2031 2032 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2033 void *p_data, unsigned int bytes) 2034 { 2035 u32 data = *(u32 *)p_data; 2036 const struct intel_engine_cs *engine = 2037 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 2038 bool enable_execlist; 2039 int ret; 2040 2041 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); 2042 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2043 IS_COMETLAKE(vgpu->gvt->gt->i915)) 2044 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); 2045 write_vreg(vgpu, offset, p_data, bytes); 2046 2047 if (IS_MASKED_BITS_ENABLED(data, 1)) { 2048 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2049 return 0; 2050 } 2051 2052 if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2053 IS_COMETLAKE(vgpu->gvt->gt->i915)) && 2054 IS_MASKED_BITS_ENABLED(data, 2)) { 2055 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2056 return 0; 2057 } 2058 2059 /* when PPGTT mode enabled, we will check if guest has called 2060 * pvinfo, if not, we will treat this guest as non-gvtg-aware 2061 * guest, and stop emulating its cfg space, mmio, gtt, etc. 2062 */ 2063 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) || 2064 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) && 2065 !vgpu->pv_notified) { 2066 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2067 return 0; 2068 } 2069 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) || 2070 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) { 2071 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 2072 2073 gvt_dbg_core("EXECLIST %s on ring %s\n", 2074 (enable_execlist ? "enabling" : "disabling"), 2075 engine->name); 2076 2077 if (!enable_execlist) 2078 return 0; 2079 2080 ret = intel_vgpu_select_submission_ops(vgpu, 2081 engine->mask, 2082 INTEL_VGPU_EXECLIST_SUBMISSION); 2083 if (ret) 2084 return ret; 2085 2086 intel_vgpu_start_schedule(vgpu); 2087 } 2088 return 0; 2089 } 2090 2091 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 2092 unsigned int offset, void *p_data, unsigned int bytes) 2093 { 2094 unsigned int id = 0; 2095 2096 write_vreg(vgpu, offset, p_data, bytes); 2097 vgpu_vreg(vgpu, offset) = 0; 2098 2099 switch (offset) { 2100 case 0x4260: 2101 id = RCS0; 2102 break; 2103 case 0x4264: 2104 id = VCS0; 2105 break; 2106 case 0x4268: 2107 id = VCS1; 2108 break; 2109 case 0x426c: 2110 id = BCS0; 2111 break; 2112 case 0x4270: 2113 id = VECS0; 2114 break; 2115 default: 2116 return -EINVAL; 2117 } 2118 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 2119 2120 return 0; 2121 } 2122 2123 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 2124 unsigned int offset, void *p_data, unsigned int bytes) 2125 { 2126 u32 data; 2127 2128 write_vreg(vgpu, offset, p_data, bytes); 2129 data = vgpu_vreg(vgpu, offset); 2130 2131 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET)) 2132 data |= RESET_CTL_READY_TO_RESET; 2133 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 2134 data &= ~RESET_CTL_READY_TO_RESET; 2135 2136 vgpu_vreg(vgpu, offset) = data; 2137 return 0; 2138 } 2139 2140 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, 2141 unsigned int offset, void *p_data, 2142 unsigned int bytes) 2143 { 2144 u32 data = *(u32 *)p_data; 2145 2146 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); 2147 write_vreg(vgpu, offset, p_data, bytes); 2148 2149 if (IS_MASKED_BITS_ENABLED(data, 0x10) || 2150 IS_MASKED_BITS_ENABLED(data, 0x8)) 2151 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2152 2153 return 0; 2154 } 2155 2156 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 2157 ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 2158 s, f, am, rm, d, r, w); \ 2159 if (ret) \ 2160 return ret; \ 2161 } while (0) 2162 2163 #define MMIO_DH(reg, d, r, w) \ 2164 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 2165 2166 #define MMIO_DFH(reg, d, f, r, w) \ 2167 MMIO_F(reg, 4, f, 0, 0, d, r, w) 2168 2169 #define MMIO_GM(reg, d, r, w) \ 2170 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 2171 2172 #define MMIO_GM_RDR(reg, d, r, w) \ 2173 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 2174 2175 #define MMIO_RO(reg, d, f, rm, r, w) \ 2176 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 2177 2178 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 2179 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 2180 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 2181 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 2182 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 2183 if (HAS_ENGINE(gvt->gt, VCS1)) \ 2184 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 2185 } while (0) 2186 2187 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 2188 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 2189 2190 #define MMIO_RING_GM(prefix, d, r, w) \ 2191 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 2192 2193 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 2194 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 2195 2196 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 2197 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 2198 2199 static int init_generic_mmio_info(struct intel_gvt *gvt) 2200 { 2201 struct drm_i915_private *dev_priv = gvt->gt->i915; 2202 struct intel_display *display = &dev_priv->display; 2203 int ret; 2204 2205 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, 2206 intel_vgpu_reg_imr_handler); 2207 2208 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 2209 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 2210 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 2211 2212 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL); 2213 2214 2215 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, 2216 gamw_echo_dev_rw_ia_write); 2217 2218 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2219 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2220 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2221 2222 #define RING_REG(base) _MMIO((base) + 0x28) 2223 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2224 #undef RING_REG 2225 2226 #define RING_REG(base) _MMIO((base) + 0x134) 2227 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2228 #undef RING_REG 2229 2230 #define RING_REG(base) _MMIO((base) + 0x6c) 2231 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 2232 #undef RING_REG 2233 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 2234 2235 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 2236 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); 2237 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 2238 2239 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL); 2240 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL); 2241 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL); 2242 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL); 2243 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 2244 2245 /* RING MODE */ 2246 #define RING_REG(base) _MMIO((base) + 0x29c) 2247 MMIO_RING_DFH(RING_REG, D_ALL, 2248 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL, 2249 ring_mode_mmio_write); 2250 #undef RING_REG 2251 2252 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2253 NULL, NULL); 2254 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2255 NULL, NULL); 2256 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 2257 mmio_read_from_hw, NULL); 2258 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 2259 mmio_read_from_hw, NULL); 2260 2261 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2262 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2263 NULL, NULL); 2264 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2265 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2266 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2267 2268 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2269 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2270 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2271 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL, 2272 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2273 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2274 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 2275 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2276 NULL, NULL); 2277 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2278 NULL, NULL); 2279 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 2280 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 2281 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 2282 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 2283 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 2284 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 2285 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2286 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2287 MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2288 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2289 2290 /* display */ 2291 MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL, 2292 pipeconf_mmio_write); 2293 MMIO_DH(TRANSCONF(display, TRANSCODER_B), D_ALL, NULL, 2294 pipeconf_mmio_write); 2295 MMIO_DH(TRANSCONF(display, TRANSCODER_C), D_ALL, NULL, 2296 pipeconf_mmio_write); 2297 MMIO_DH(TRANSCONF(display, TRANSCODER_EDP), D_ALL, NULL, 2298 pipeconf_mmio_write); 2299 MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2300 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, 2301 reg50080_mmio_write); 2302 MMIO_DH(DSPSURF(display, PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2303 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, 2304 reg50080_mmio_write); 2305 MMIO_DH(DSPSURF(display, PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2306 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, 2307 reg50080_mmio_write); 2308 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 2309 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, 2310 reg50080_mmio_write); 2311 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 2312 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, 2313 reg50080_mmio_write); 2314 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 2315 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, 2316 reg50080_mmio_write); 2317 2318 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2319 gmbus_mmio_write); 2320 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2321 2322 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2323 dp_aux_ch_ctl_mmio_write); 2324 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2325 dp_aux_ch_ctl_mmio_write); 2326 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2327 dp_aux_ch_ctl_mmio_write); 2328 2329 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2330 2331 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2332 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2333 2334 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2335 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2336 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2337 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2338 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2339 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2340 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2341 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2342 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2343 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2344 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2345 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2346 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2347 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2348 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2349 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2350 2351 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2352 PORTA_HOTPLUG_STATUS_MASK 2353 | PORTB_HOTPLUG_STATUS_MASK 2354 | PORTC_HOTPLUG_STATUS_MASK 2355 | PORTD_HOTPLUG_STATUS_MASK, 2356 NULL, NULL); 2357 2358 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2359 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2360 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2361 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2362 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2363 2364 MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL, 2365 dp_aux_ch_ctl_mmio_write); 2366 2367 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2368 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2369 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2370 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2371 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2372 2373 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2374 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2375 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2376 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2377 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2378 2379 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2380 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2381 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2382 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2383 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2384 2385 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2386 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2387 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2388 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2389 2390 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2391 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2392 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2393 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2394 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2395 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2396 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2397 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); 2398 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); 2399 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); 2400 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); 2401 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2402 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2403 2404 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2405 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2406 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2407 2408 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2409 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2410 2411 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2412 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2413 2414 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2415 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2416 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2417 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2418 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2419 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2420 2421 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2422 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2423 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2424 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2425 2426 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2427 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2428 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2429 2430 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2431 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2432 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2433 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2434 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2435 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2436 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2437 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2438 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2439 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2440 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2441 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2442 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2443 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2444 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2445 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2446 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2447 2448 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2449 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL); 2450 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2451 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2452 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2453 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2454 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2455 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2456 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2457 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2458 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2459 2460 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2461 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2462 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL); 2463 2464 return 0; 2465 } 2466 2467 static int init_bdw_mmio_info(struct intel_gvt *gvt) 2468 { 2469 int ret; 2470 2471 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2472 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2473 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2474 2475 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2476 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2477 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2478 2479 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2480 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2481 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2482 2483 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2484 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2485 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2486 2487 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2488 intel_vgpu_reg_imr_handler); 2489 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2490 intel_vgpu_reg_ier_handler); 2491 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2492 intel_vgpu_reg_iir_handler); 2493 2494 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2495 intel_vgpu_reg_imr_handler); 2496 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2497 intel_vgpu_reg_ier_handler); 2498 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2499 intel_vgpu_reg_iir_handler); 2500 2501 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2502 intel_vgpu_reg_imr_handler); 2503 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2504 intel_vgpu_reg_ier_handler); 2505 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2506 intel_vgpu_reg_iir_handler); 2507 2508 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2509 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2510 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2511 2512 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2513 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2514 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2515 2516 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2517 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2518 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2519 2520 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2521 intel_vgpu_reg_master_irq_handler); 2522 2523 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0, 2524 mmio_read_from_hw, NULL); 2525 2526 #define RING_REG(base) _MMIO((base) + 0xd0) 2527 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2528 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2529 ring_reset_ctl_write); 2530 #undef RING_REG 2531 2532 #define RING_REG(base) _MMIO((base) + 0x230) 2533 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2534 #undef RING_REG 2535 2536 #define RING_REG(base) _MMIO((base) + 0x234) 2537 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, 2538 NULL, NULL); 2539 #undef RING_REG 2540 2541 #define RING_REG(base) _MMIO((base) + 0x244) 2542 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2543 #undef RING_REG 2544 2545 #define RING_REG(base) _MMIO((base) + 0x370) 2546 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2547 #undef RING_REG 2548 2549 #define RING_REG(base) _MMIO((base) + 0x3a0) 2550 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2551 #undef RING_REG 2552 2553 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2554 2555 #define RING_REG(base) _MMIO((base) + 0x270) 2556 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2557 #undef RING_REG 2558 2559 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2560 2561 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2562 2563 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2564 NULL, NULL); 2565 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2566 NULL, NULL); 2567 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2568 2569 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2570 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2571 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2572 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2573 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2574 2575 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0, 2576 D_BDW_PLUS, NULL, force_nonpriv_write); 2577 2578 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2579 2580 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2581 2582 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2583 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2584 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2585 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2586 2587 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2588 2589 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2590 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2591 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2592 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2593 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2594 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2595 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2596 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2597 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2598 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2599 return 0; 2600 } 2601 2602 static int init_skl_mmio_info(struct intel_gvt *gvt) 2603 { 2604 int ret; 2605 2606 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2607 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2608 MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2609 MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL); 2610 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2611 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2612 2613 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2614 dp_aux_ch_ctl_mmio_write); 2615 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2616 dp_aux_ch_ctl_mmio_write); 2617 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2618 dp_aux_ch_ctl_mmio_write); 2619 2620 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); 2621 2622 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 2623 2624 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2625 MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2626 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL); 2627 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2628 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2629 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL); 2630 2631 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2632 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2633 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2634 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2635 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2636 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2637 2638 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2639 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2640 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2641 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2642 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2643 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2644 2645 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2646 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2647 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2648 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2649 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2650 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2651 2652 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2653 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2654 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2655 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2656 2657 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2658 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2659 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2660 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2661 2662 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2663 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2664 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2665 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2666 2667 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2668 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2669 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2670 2671 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2672 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2673 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2674 2675 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2676 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2677 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2678 2679 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2680 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2681 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2682 2683 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2684 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2685 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2686 2687 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2688 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2689 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2690 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2691 2692 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2693 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2694 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2695 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2696 2697 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2698 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2699 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2700 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2701 2702 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2703 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2704 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2705 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2706 2707 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2708 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2709 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2710 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2711 2712 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2713 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2714 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2715 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2716 2717 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2718 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2719 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2720 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2721 2722 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2723 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2724 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2725 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2726 2727 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2728 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2729 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2730 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2731 2732 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2733 2734 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2735 NULL, NULL); 2736 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2737 NULL, NULL); 2738 2739 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, 2740 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2741 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2742 NULL, NULL); 2743 2744 /* TRTT */ 2745 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2746 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2747 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2748 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2749 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2750 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE, 2751 NULL, gen9_trtte_write); 2752 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE, 2753 NULL, gen9_trtt_chicken_write); 2754 2755 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2756 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2757 2758 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) 2759 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2760 NULL, csfe_chicken1_mmio_write); 2761 #undef CSFE_CHICKEN1_REG 2762 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2763 NULL, NULL); 2764 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2765 NULL, NULL); 2766 2767 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL); 2768 MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2769 2770 return 0; 2771 } 2772 2773 static int init_bxt_mmio_info(struct intel_gvt *gvt) 2774 { 2775 int ret; 2776 2777 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 2778 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 2779 NULL, bxt_phy_ctl_family_write); 2780 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 2781 NULL, bxt_phy_ctl_family_write); 2782 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 2783 NULL, bxt_port_pll_enable_write); 2784 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 2785 NULL, bxt_port_pll_enable_write); 2786 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 2787 bxt_port_pll_enable_write); 2788 2789 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 2790 NULL, bxt_pcs_dw12_grp_write); 2791 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT, 2792 bxt_port_tx_dw3_read, NULL); 2793 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 2794 NULL, bxt_pcs_dw12_grp_write); 2795 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT, 2796 bxt_port_tx_dw3_read, NULL); 2797 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 2798 NULL, bxt_pcs_dw12_grp_write); 2799 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT, 2800 bxt_port_tx_dw3_read, NULL); 2801 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 2802 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); 2803 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL); 2804 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL); 2805 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2806 0, 0, D_BXT, NULL, NULL); 2807 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2808 0, 0, D_BXT, NULL, NULL); 2809 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2810 0, 0, D_BXT, NULL, NULL); 2811 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2812 0, 0, D_BXT, NULL, NULL); 2813 2814 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 2815 2816 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write); 2817 2818 return 0; 2819 } 2820 2821 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 2822 unsigned int offset) 2823 { 2824 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2825 int num = gvt->mmio.num_mmio_block; 2826 int i; 2827 2828 for (i = 0; i < num; i++, block++) { 2829 if (offset >= i915_mmio_reg_offset(block->offset) && 2830 offset < i915_mmio_reg_offset(block->offset) + block->size) 2831 return block; 2832 } 2833 return NULL; 2834 } 2835 2836 /** 2837 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2838 * @gvt: GVT device 2839 * 2840 * This function is called at the driver unloading stage, to clean up the MMIO 2841 * information table of GVT device 2842 * 2843 */ 2844 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2845 { 2846 struct hlist_node *tmp; 2847 struct intel_gvt_mmio_info *e; 2848 int i; 2849 2850 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2851 kfree(e); 2852 2853 kfree(gvt->mmio.mmio_block); 2854 gvt->mmio.mmio_block = NULL; 2855 gvt->mmio.num_mmio_block = 0; 2856 2857 vfree(gvt->mmio.mmio_attribute); 2858 gvt->mmio.mmio_attribute = NULL; 2859 } 2860 2861 static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset, 2862 u32 size) 2863 { 2864 struct intel_gvt *gvt = iter->data; 2865 struct intel_gvt_mmio_info *info, *p; 2866 u32 start, end, i; 2867 2868 if (WARN_ON(!IS_ALIGNED(offset, 4))) 2869 return -EINVAL; 2870 2871 start = offset; 2872 end = offset + size; 2873 2874 for (i = start; i < end; i += 4) { 2875 p = intel_gvt_find_mmio_info(gvt, i); 2876 if (p) { 2877 WARN(1, "dup mmio definition offset %x\n", i); 2878 2879 /* We return -EEXIST here to make GVT-g load fail. 2880 * So duplicated MMIO can be found as soon as 2881 * possible. 2882 */ 2883 return -EEXIST; 2884 } 2885 2886 info = kzalloc(sizeof(*info), GFP_KERNEL); 2887 if (!info) 2888 return -ENOMEM; 2889 2890 info->offset = i; 2891 info->read = intel_vgpu_default_mmio_read; 2892 info->write = intel_vgpu_default_mmio_write; 2893 INIT_HLIST_NODE(&info->node); 2894 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 2895 gvt->mmio.num_tracked_mmio++; 2896 } 2897 return 0; 2898 } 2899 2900 static int handle_mmio_block(struct intel_gvt_mmio_table_iter *iter, 2901 u32 offset, u32 size) 2902 { 2903 struct intel_gvt *gvt = iter->data; 2904 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2905 void *ret; 2906 2907 ret = krealloc(block, 2908 (gvt->mmio.num_mmio_block + 1) * sizeof(*block), 2909 GFP_KERNEL); 2910 if (!ret) 2911 return -ENOMEM; 2912 2913 gvt->mmio.mmio_block = block = ret; 2914 2915 block += gvt->mmio.num_mmio_block; 2916 2917 memset(block, 0, sizeof(*block)); 2918 2919 block->offset = _MMIO(offset); 2920 block->size = size; 2921 2922 gvt->mmio.num_mmio_block++; 2923 2924 return 0; 2925 } 2926 2927 static int handle_mmio_cb(struct intel_gvt_mmio_table_iter *iter, u32 offset, 2928 u32 size) 2929 { 2930 if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0))) 2931 return handle_mmio(iter, offset, size); 2932 else 2933 return handle_mmio_block(iter, offset, size); 2934 } 2935 2936 static int init_mmio_info(struct intel_gvt *gvt) 2937 { 2938 struct intel_gvt_mmio_table_iter iter = { 2939 .i915 = gvt->gt->i915, 2940 .data = gvt, 2941 .handle_mmio_cb = handle_mmio_cb, 2942 }; 2943 2944 return intel_gvt_iterate_mmio_table(&iter); 2945 } 2946 2947 static int init_mmio_block_handlers(struct intel_gvt *gvt) 2948 { 2949 struct gvt_mmio_block *block; 2950 2951 block = find_mmio_block(gvt, VGT_PVINFO_PAGE); 2952 if (!block) { 2953 WARN(1, "fail to assign handlers to mmio block %x\n", 2954 i915_mmio_reg_offset(gvt->mmio.mmio_block->offset)); 2955 return -ENODEV; 2956 } 2957 2958 block->read = pvinfo_mmio_read; 2959 block->write = pvinfo_mmio_write; 2960 2961 return 0; 2962 } 2963 2964 /** 2965 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2966 * @gvt: GVT device 2967 * 2968 * This function is called at the initialization stage, to setup the MMIO 2969 * information table for GVT device 2970 * 2971 * Returns: 2972 * zero on success, negative if failed. 2973 */ 2974 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2975 { 2976 struct intel_gvt_device_info *info = &gvt->device_info; 2977 struct drm_i915_private *i915 = gvt->gt->i915; 2978 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 2979 int ret; 2980 2981 gvt->mmio.mmio_attribute = vzalloc(size); 2982 if (!gvt->mmio.mmio_attribute) 2983 return -ENOMEM; 2984 2985 ret = init_mmio_info(gvt); 2986 if (ret) 2987 goto err; 2988 2989 ret = init_mmio_block_handlers(gvt); 2990 if (ret) 2991 goto err; 2992 2993 ret = init_generic_mmio_info(gvt); 2994 if (ret) 2995 goto err; 2996 2997 if (IS_BROADWELL(i915)) { 2998 ret = init_bdw_mmio_info(gvt); 2999 if (ret) 3000 goto err; 3001 } else if (IS_SKYLAKE(i915) || 3002 IS_KABYLAKE(i915) || 3003 IS_COFFEELAKE(i915) || 3004 IS_COMETLAKE(i915)) { 3005 ret = init_bdw_mmio_info(gvt); 3006 if (ret) 3007 goto err; 3008 ret = init_skl_mmio_info(gvt); 3009 if (ret) 3010 goto err; 3011 } else if (IS_BROXTON(i915)) { 3012 ret = init_bdw_mmio_info(gvt); 3013 if (ret) 3014 goto err; 3015 ret = init_skl_mmio_info(gvt); 3016 if (ret) 3017 goto err; 3018 ret = init_bxt_mmio_info(gvt); 3019 if (ret) 3020 goto err; 3021 } 3022 3023 return 0; 3024 err: 3025 intel_gvt_clean_mmio_info(gvt); 3026 return ret; 3027 } 3028 3029 /** 3030 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 3031 * @gvt: a GVT device 3032 * @handler: the handler 3033 * @data: private data given to handler 3034 * 3035 * Returns: 3036 * Zero on success, negative error code if failed. 3037 */ 3038 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3039 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3040 void *data) 3041 { 3042 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3043 struct intel_gvt_mmio_info *e; 3044 int i, j, ret; 3045 3046 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3047 ret = handler(gvt, e->offset, data); 3048 if (ret) 3049 return ret; 3050 } 3051 3052 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3053 /* pvinfo data doesn't come from hw mmio */ 3054 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE) 3055 continue; 3056 3057 for (j = 0; j < block->size; j += 4) { 3058 ret = handler(gvt, i915_mmio_reg_offset(block->offset) + j, data); 3059 if (ret) 3060 return ret; 3061 } 3062 } 3063 return 0; 3064 } 3065 3066 /** 3067 * intel_vgpu_default_mmio_read - default MMIO read handler 3068 * @vgpu: a vGPU 3069 * @offset: access offset 3070 * @p_data: data return buffer 3071 * @bytes: access data length 3072 * 3073 * Returns: 3074 * Zero on success, negative error code if failed. 3075 */ 3076 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3077 void *p_data, unsigned int bytes) 3078 { 3079 read_vreg(vgpu, offset, p_data, bytes); 3080 return 0; 3081 } 3082 3083 /** 3084 * intel_vgpu_default_mmio_write() - default MMIO write handler 3085 * @vgpu: a vGPU 3086 * @offset: access offset 3087 * @p_data: write data buffer 3088 * @bytes: access data length 3089 * 3090 * Returns: 3091 * Zero on success, negative error code if failed. 3092 */ 3093 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3094 void *p_data, unsigned int bytes) 3095 { 3096 write_vreg(vgpu, offset, p_data, bytes); 3097 return 0; 3098 } 3099 3100 /** 3101 * intel_vgpu_mask_mmio_write - write mask register 3102 * @vgpu: a vGPU 3103 * @offset: access offset 3104 * @p_data: write data buffer 3105 * @bytes: access data length 3106 * 3107 * Returns: 3108 * Zero on success, negative error code if failed. 3109 */ 3110 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3111 void *p_data, unsigned int bytes) 3112 { 3113 u32 mask, old_vreg; 3114 3115 old_vreg = vgpu_vreg(vgpu, offset); 3116 write_vreg(vgpu, offset, p_data, bytes); 3117 mask = vgpu_vreg(vgpu, offset) >> 16; 3118 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | 3119 (vgpu_vreg(vgpu, offset) & mask); 3120 3121 return 0; 3122 } 3123 3124 /** 3125 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3126 * @vgpu: a vGPU 3127 * @offset: register offset 3128 * @pdata: data buffer 3129 * @bytes: data length 3130 * @is_read: read or write 3131 * 3132 * Returns: 3133 * Zero on success, negative error code if failed. 3134 */ 3135 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3136 void *pdata, unsigned int bytes, bool is_read) 3137 { 3138 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 3139 struct intel_gvt *gvt = vgpu->gvt; 3140 struct intel_gvt_mmio_info *mmio_info; 3141 struct gvt_mmio_block *mmio_block; 3142 gvt_mmio_func func; 3143 int ret; 3144 3145 if (drm_WARN_ON(&i915->drm, bytes > 8)) 3146 return -EINVAL; 3147 3148 /* 3149 * Handle special MMIO blocks. 3150 */ 3151 mmio_block = find_mmio_block(gvt, offset); 3152 if (mmio_block) { 3153 func = is_read ? mmio_block->read : mmio_block->write; 3154 if (func) 3155 return func(vgpu, offset, pdata, bytes); 3156 goto default_rw; 3157 } 3158 3159 /* 3160 * Normal tracked MMIOs. 3161 */ 3162 mmio_info = intel_gvt_find_mmio_info(gvt, offset); 3163 if (!mmio_info) { 3164 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3165 goto default_rw; 3166 } 3167 3168 if (is_read) 3169 return mmio_info->read(vgpu, offset, pdata, bytes); 3170 else { 3171 u64 ro_mask = mmio_info->ro_mask; 3172 u32 old_vreg = 0; 3173 u64 data = 0; 3174 3175 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3176 old_vreg = vgpu_vreg(vgpu, offset); 3177 } 3178 3179 if (likely(!ro_mask)) 3180 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3181 else if (!~ro_mask) { 3182 gvt_vgpu_err("try to write RO reg %x\n", offset); 3183 return 0; 3184 } else { 3185 /* keep the RO bits in the virtual register */ 3186 memcpy(&data, pdata, bytes); 3187 data &= ~ro_mask; 3188 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3189 ret = mmio_info->write(vgpu, offset, &data, bytes); 3190 } 3191 3192 /* higher 16bits of mode ctl regs are mask bits for change */ 3193 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3194 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3195 3196 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3197 | (vgpu_vreg(vgpu, offset) & mask); 3198 } 3199 } 3200 3201 return ret; 3202 3203 default_rw: 3204 return is_read ? 3205 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3206 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3207 } 3208 3209 void intel_gvt_restore_fence(struct intel_gvt *gvt) 3210 { 3211 struct intel_vgpu *vgpu; 3212 int i, id; 3213 3214 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3215 intel_wakeref_t wakeref; 3216 3217 wakeref = mmio_hw_access_pre(gvt->gt); 3218 for (i = 0; i < vgpu_fence_sz(vgpu); i++) 3219 intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i))); 3220 mmio_hw_access_post(gvt->gt, wakeref); 3221 } 3222 } 3223 3224 static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data) 3225 { 3226 struct intel_vgpu *vgpu = data; 3227 struct drm_i915_private *dev_priv = gvt->gt->i915; 3228 3229 if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE) 3230 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset)); 3231 3232 return 0; 3233 } 3234 3235 void intel_gvt_restore_mmio(struct intel_gvt *gvt) 3236 { 3237 struct intel_vgpu *vgpu; 3238 int id; 3239 3240 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3241 intel_wakeref_t wakeref; 3242 3243 wakeref = mmio_hw_access_pre(gvt->gt); 3244 intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu); 3245 mmio_hw_access_post(gvt->gt, wakeref); 3246 } 3247 } 3248