1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 /* Register contains RO bits */ 51 #define F_RO (1 << 0) 52 /* Register contains graphics address */ 53 #define F_GMADR (1 << 1) 54 /* Mode mask registers with high 16 bits as the mask bits */ 55 #define F_MODE_MASK (1 << 2) 56 /* This reg can be accessed by GPU commands */ 57 #define F_CMD_ACCESS (1 << 3) 58 /* This reg has been accessed by a VM */ 59 #define F_ACCESSED (1 << 4) 60 /* This reg has been accessed through GPU commands */ 61 #define F_CMD_ACCESSED (1 << 5) 62 /* This reg could be accessed by unaligned address */ 63 #define F_UNALIGN (1 << 6) 64 65 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 66 { 67 if (IS_BROADWELL(gvt->dev_priv)) 68 return D_BDW; 69 else if (IS_SKYLAKE(gvt->dev_priv)) 70 return D_SKL; 71 72 return 0; 73 } 74 75 bool intel_gvt_match_device(struct intel_gvt *gvt, 76 unsigned long device) 77 { 78 return intel_gvt_get_device_type(gvt) & device; 79 } 80 81 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 82 void *p_data, unsigned int bytes) 83 { 84 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 85 } 86 87 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 88 void *p_data, unsigned int bytes) 89 { 90 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 91 } 92 93 static int new_mmio_info(struct intel_gvt *gvt, 94 u32 offset, u32 flags, u32 size, 95 u32 addr_mask, u32 ro_mask, u32 device, 96 void *read, void *write) 97 { 98 struct intel_gvt_mmio_info *info, *p; 99 u32 start, end, i; 100 101 if (!intel_gvt_match_device(gvt, device)) 102 return 0; 103 104 if (WARN_ON(!IS_ALIGNED(offset, 4))) 105 return -EINVAL; 106 107 start = offset; 108 end = offset + size; 109 110 for (i = start; i < end; i += 4) { 111 info = kzalloc(sizeof(*info), GFP_KERNEL); 112 if (!info) 113 return -ENOMEM; 114 115 info->offset = i; 116 p = intel_gvt_find_mmio_info(gvt, info->offset); 117 if (p) 118 gvt_err("dup mmio definition offset %x\n", 119 info->offset); 120 info->size = size; 121 info->length = (i + 4) < end ? 4 : (end - i); 122 info->addr_mask = addr_mask; 123 info->device = device; 124 info->read = read ? read : intel_vgpu_default_mmio_read; 125 info->write = write ? write : intel_vgpu_default_mmio_write; 126 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 127 INIT_HLIST_NODE(&info->node); 128 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 129 } 130 return 0; 131 } 132 133 static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) 134 { 135 enum intel_engine_id id; 136 struct intel_engine_cs *engine; 137 138 reg &= ~GENMASK(11, 0); 139 for_each_engine(engine, gvt->dev_priv, id) { 140 if (engine->mmio_base == reg) 141 return id; 142 } 143 return -1; 144 } 145 146 #define offset_to_fence_num(offset) \ 147 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 148 149 #define fence_num_to_offset(num) \ 150 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 151 152 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 153 unsigned int fence_num, void *p_data, unsigned int bytes) 154 { 155 if (fence_num >= vgpu_fence_sz(vgpu)) { 156 gvt_err("vgpu%d: found oob fence register access\n", 157 vgpu->id); 158 gvt_err("vgpu%d: total fence num %d access fence num %d\n", 159 vgpu->id, vgpu_fence_sz(vgpu), fence_num); 160 memset(p_data, 0, bytes); 161 } 162 return 0; 163 } 164 165 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 166 void *p_data, unsigned int bytes) 167 { 168 int ret; 169 170 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 171 p_data, bytes); 172 if (ret) 173 return ret; 174 read_vreg(vgpu, off, p_data, bytes); 175 return 0; 176 } 177 178 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 179 void *p_data, unsigned int bytes) 180 { 181 unsigned int fence_num = offset_to_fence_num(off); 182 int ret; 183 184 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 185 if (ret) 186 return ret; 187 write_vreg(vgpu, off, p_data, bytes); 188 189 intel_vgpu_write_fence(vgpu, fence_num, 190 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 191 return 0; 192 } 193 194 #define CALC_MODE_MASK_REG(old, new) \ 195 (((new) & GENMASK(31, 16)) \ 196 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 197 | ((new) & ((new) >> 16)))) 198 199 static int mul_force_wake_write(struct intel_vgpu *vgpu, 200 unsigned int offset, void *p_data, unsigned int bytes) 201 { 202 u32 old, new; 203 uint32_t ack_reg_offset; 204 205 old = vgpu_vreg(vgpu, offset); 206 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 207 208 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) { 209 switch (offset) { 210 case FORCEWAKE_RENDER_GEN9_REG: 211 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 212 break; 213 case FORCEWAKE_BLITTER_GEN9_REG: 214 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 215 break; 216 case FORCEWAKE_MEDIA_GEN9_REG: 217 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 218 break; 219 default: 220 /*should not hit here*/ 221 gvt_err("invalid forcewake offset 0x%x\n", offset); 222 return 1; 223 } 224 } else { 225 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 226 } 227 228 vgpu_vreg(vgpu, offset) = new; 229 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 230 return 0; 231 } 232 233 static int handle_device_reset(struct intel_vgpu *vgpu, unsigned int offset, 234 void *p_data, unsigned int bytes, unsigned long bitmap) 235 { 236 struct intel_gvt_workload_scheduler *scheduler = 237 &vgpu->gvt->scheduler; 238 239 vgpu->resetting = true; 240 241 intel_vgpu_stop_schedule(vgpu); 242 /* 243 * The current_vgpu will set to NULL after stopping the 244 * scheduler when the reset is triggered by current vgpu. 245 */ 246 if (scheduler->current_vgpu == NULL) { 247 mutex_unlock(&vgpu->gvt->lock); 248 intel_gvt_wait_vgpu_idle(vgpu); 249 mutex_lock(&vgpu->gvt->lock); 250 } 251 252 intel_vgpu_reset_execlist(vgpu, bitmap); 253 254 /* full GPU reset */ 255 if (bitmap == 0xff) { 256 mutex_unlock(&vgpu->gvt->lock); 257 intel_vgpu_clean_gtt(vgpu); 258 mutex_lock(&vgpu->gvt->lock); 259 setup_vgpu_mmio(vgpu); 260 populate_pvinfo_page(vgpu); 261 intel_vgpu_init_gtt(vgpu); 262 } 263 264 vgpu->resetting = false; 265 266 return 0; 267 } 268 269 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 270 void *p_data, unsigned int bytes) 271 { 272 u32 data; 273 u64 bitmap = 0; 274 275 write_vreg(vgpu, offset, p_data, bytes); 276 data = vgpu_vreg(vgpu, offset); 277 278 if (data & GEN6_GRDOM_FULL) { 279 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 280 bitmap = 0xff; 281 } 282 if (data & GEN6_GRDOM_RENDER) { 283 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 284 bitmap |= (1 << RCS); 285 } 286 if (data & GEN6_GRDOM_MEDIA) { 287 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 288 bitmap |= (1 << VCS); 289 } 290 if (data & GEN6_GRDOM_BLT) { 291 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 292 bitmap |= (1 << BCS); 293 } 294 if (data & GEN6_GRDOM_VECS) { 295 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 296 bitmap |= (1 << VECS); 297 } 298 if (data & GEN8_GRDOM_MEDIA2) { 299 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 300 if (HAS_BSD2(vgpu->gvt->dev_priv)) 301 bitmap |= (1 << VCS2); 302 } 303 return handle_device_reset(vgpu, offset, p_data, bytes, bitmap); 304 } 305 306 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 307 void *p_data, unsigned int bytes) 308 { 309 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 310 } 311 312 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 313 void *p_data, unsigned int bytes) 314 { 315 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 316 } 317 318 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 319 unsigned int offset, void *p_data, unsigned int bytes) 320 { 321 write_vreg(vgpu, offset, p_data, bytes); 322 323 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 324 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; 325 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 326 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 327 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 328 329 } else 330 vgpu_vreg(vgpu, PCH_PP_STATUS) &= 331 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 332 | PP_CYCLE_DELAY_ACTIVE); 333 return 0; 334 } 335 336 static int transconf_mmio_write(struct intel_vgpu *vgpu, 337 unsigned int offset, void *p_data, unsigned int bytes) 338 { 339 write_vreg(vgpu, offset, p_data, bytes); 340 341 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 342 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 343 else 344 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 345 return 0; 346 } 347 348 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 349 void *p_data, unsigned int bytes) 350 { 351 write_vreg(vgpu, offset, p_data, bytes); 352 353 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 354 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 355 else 356 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 357 358 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 359 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 360 else 361 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 362 363 return 0; 364 } 365 366 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 367 void *p_data, unsigned int bytes) 368 { 369 *(u32 *)p_data = (1 << 17); 370 return 0; 371 } 372 373 static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset, 374 void *p_data, unsigned int bytes) 375 { 376 *(u32 *)p_data = 3; 377 return 0; 378 } 379 380 static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset, 381 void *p_data, unsigned int bytes) 382 { 383 *(u32 *)p_data = (0x2f << 16); 384 return 0; 385 } 386 387 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 388 void *p_data, unsigned int bytes) 389 { 390 u32 data; 391 392 write_vreg(vgpu, offset, p_data, bytes); 393 data = vgpu_vreg(vgpu, offset); 394 395 if (data & PIPECONF_ENABLE) 396 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 397 else 398 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 399 intel_gvt_check_vblank_emulation(vgpu->gvt); 400 return 0; 401 } 402 403 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 404 void *p_data, unsigned int bytes) 405 { 406 write_vreg(vgpu, offset, p_data, bytes); 407 408 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 409 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 410 } else { 411 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 412 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 413 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) 414 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 415 } 416 return 0; 417 } 418 419 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 420 unsigned int offset, void *p_data, unsigned int bytes) 421 { 422 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 423 return 0; 424 } 425 426 #define FDI_LINK_TRAIN_PATTERN1 0 427 #define FDI_LINK_TRAIN_PATTERN2 1 428 429 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 430 { 431 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); 432 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 433 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); 434 435 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 436 (rx_ctl & FDI_RX_ENABLE) && 437 (rx_ctl & FDI_AUTO_TRAINING) && 438 (tx_ctl & DP_TP_CTL_ENABLE) && 439 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 440 return 1; 441 else 442 return 0; 443 } 444 445 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 446 enum pipe pipe, unsigned int train_pattern) 447 { 448 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 449 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 450 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 451 unsigned int fdi_iir_check_bits; 452 453 fdi_rx_imr = FDI_RX_IMR(pipe); 454 fdi_tx_ctl = FDI_TX_CTL(pipe); 455 fdi_rx_ctl = FDI_RX_CTL(pipe); 456 457 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 458 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 459 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 460 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 461 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 462 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 463 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 464 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 465 } else { 466 gvt_err("Invalid train pattern %d\n", train_pattern); 467 return -EINVAL; 468 } 469 470 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 471 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 472 473 /* If imr bit has been masked */ 474 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 475 return 0; 476 477 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 478 == fdi_tx_check_bits) 479 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 480 == fdi_rx_check_bits)) 481 return 1; 482 else 483 return 0; 484 } 485 486 #define INVALID_INDEX (~0U) 487 488 static unsigned int calc_index(unsigned int offset, unsigned int start, 489 unsigned int next, unsigned int end, i915_reg_t i915_end) 490 { 491 unsigned int range = next - start; 492 493 if (!end) 494 end = i915_mmio_reg_offset(i915_end); 495 if (offset < start || offset > end) 496 return INVALID_INDEX; 497 offset -= start; 498 return offset / range; 499 } 500 501 #define FDI_RX_CTL_TO_PIPE(offset) \ 502 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 503 504 #define FDI_TX_CTL_TO_PIPE(offset) \ 505 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 506 507 #define FDI_RX_IMR_TO_PIPE(offset) \ 508 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 509 510 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 511 unsigned int offset, void *p_data, unsigned int bytes) 512 { 513 i915_reg_t fdi_rx_iir; 514 unsigned int index; 515 int ret; 516 517 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 518 index = FDI_RX_CTL_TO_PIPE(offset); 519 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 520 index = FDI_TX_CTL_TO_PIPE(offset); 521 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 522 index = FDI_RX_IMR_TO_PIPE(offset); 523 else { 524 gvt_err("Unsupport registers %x\n", offset); 525 return -EINVAL; 526 } 527 528 write_vreg(vgpu, offset, p_data, bytes); 529 530 fdi_rx_iir = FDI_RX_IIR(index); 531 532 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 533 if (ret < 0) 534 return ret; 535 if (ret) 536 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 537 538 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 539 if (ret < 0) 540 return ret; 541 if (ret) 542 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 543 544 if (offset == _FDI_RXA_CTL) 545 if (fdi_auto_training_started(vgpu)) 546 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= 547 DP_TP_STATUS_AUTOTRAIN_DONE; 548 return 0; 549 } 550 551 #define DP_TP_CTL_TO_PORT(offset) \ 552 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 553 554 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 555 void *p_data, unsigned int bytes) 556 { 557 i915_reg_t status_reg; 558 unsigned int index; 559 u32 data; 560 561 write_vreg(vgpu, offset, p_data, bytes); 562 563 index = DP_TP_CTL_TO_PORT(offset); 564 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 565 if (data == 0x2) { 566 status_reg = DP_TP_STATUS(index); 567 vgpu_vreg(vgpu, status_reg) |= (1 << 25); 568 } 569 return 0; 570 } 571 572 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 573 unsigned int offset, void *p_data, unsigned int bytes) 574 { 575 u32 reg_val; 576 u32 sticky_mask; 577 578 reg_val = *((u32 *)p_data); 579 sticky_mask = GENMASK(27, 26) | (1 << 24); 580 581 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 582 (vgpu_vreg(vgpu, offset) & sticky_mask); 583 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 584 return 0; 585 } 586 587 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 588 unsigned int offset, void *p_data, unsigned int bytes) 589 { 590 u32 data; 591 592 write_vreg(vgpu, offset, p_data, bytes); 593 data = vgpu_vreg(vgpu, offset); 594 595 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 596 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 597 return 0; 598 } 599 600 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 601 unsigned int offset, void *p_data, unsigned int bytes) 602 { 603 u32 data; 604 605 write_vreg(vgpu, offset, p_data, bytes); 606 data = vgpu_vreg(vgpu, offset); 607 608 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 609 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 610 else 611 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 612 return 0; 613 } 614 615 #define DSPSURF_TO_PIPE(offset) \ 616 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 617 618 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 619 void *p_data, unsigned int bytes) 620 { 621 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 622 unsigned int index = DSPSURF_TO_PIPE(offset); 623 i915_reg_t surflive_reg = DSPSURFLIVE(index); 624 int flip_event[] = { 625 [PIPE_A] = PRIMARY_A_FLIP_DONE, 626 [PIPE_B] = PRIMARY_B_FLIP_DONE, 627 [PIPE_C] = PRIMARY_C_FLIP_DONE, 628 }; 629 630 write_vreg(vgpu, offset, p_data, bytes); 631 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 632 633 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 634 return 0; 635 } 636 637 #define SPRSURF_TO_PIPE(offset) \ 638 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 639 640 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 641 void *p_data, unsigned int bytes) 642 { 643 unsigned int index = SPRSURF_TO_PIPE(offset); 644 i915_reg_t surflive_reg = SPRSURFLIVE(index); 645 int flip_event[] = { 646 [PIPE_A] = SPRITE_A_FLIP_DONE, 647 [PIPE_B] = SPRITE_B_FLIP_DONE, 648 [PIPE_C] = SPRITE_C_FLIP_DONE, 649 }; 650 651 write_vreg(vgpu, offset, p_data, bytes); 652 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 653 654 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 655 return 0; 656 } 657 658 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 659 unsigned int reg) 660 { 661 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 662 enum intel_gvt_event_type event; 663 664 if (reg == _DPA_AUX_CH_CTL) 665 event = AUX_CHANNEL_A; 666 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 667 event = AUX_CHANNEL_B; 668 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 669 event = AUX_CHANNEL_C; 670 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 671 event = AUX_CHANNEL_D; 672 else { 673 WARN_ON(true); 674 return -EINVAL; 675 } 676 677 intel_vgpu_trigger_virtual_event(vgpu, event); 678 return 0; 679 } 680 681 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 682 unsigned int reg, int len, bool data_valid) 683 { 684 /* mark transaction done */ 685 value |= DP_AUX_CH_CTL_DONE; 686 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 687 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 688 689 if (data_valid) 690 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 691 else 692 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 693 694 /* message size */ 695 value &= ~(0xf << 20); 696 value |= (len << 20); 697 vgpu_vreg(vgpu, reg) = value; 698 699 if (value & DP_AUX_CH_CTL_INTERRUPT) 700 return trigger_aux_channel_interrupt(vgpu, reg); 701 return 0; 702 } 703 704 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 705 uint8_t t) 706 { 707 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 708 /* training pattern 1 for CR */ 709 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 710 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 711 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 712 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 713 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 714 DPCD_TRAINING_PATTERN_2) { 715 /* training pattern 2 for EQ */ 716 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 717 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 718 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 719 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 720 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 721 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 722 /* set INTERLANE_ALIGN_DONE */ 723 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 724 DPCD_INTERLANE_ALIGN_DONE; 725 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 726 DPCD_LINK_TRAINING_DISABLED) { 727 /* finish link training */ 728 /* set sink status as synchronized */ 729 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 730 } 731 } 732 733 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 734 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 735 736 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 737 738 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 739 740 #define dpy_is_valid_port(port) \ 741 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 742 743 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 744 unsigned int offset, void *p_data, unsigned int bytes) 745 { 746 struct intel_vgpu_display *display = &vgpu->display; 747 int msg, addr, ctrl, op, len; 748 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 749 struct intel_vgpu_dpcd_data *dpcd = NULL; 750 struct intel_vgpu_port *port = NULL; 751 u32 data; 752 753 if (!dpy_is_valid_port(port_index)) { 754 gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id); 755 return 0; 756 } 757 758 write_vreg(vgpu, offset, p_data, bytes); 759 data = vgpu_vreg(vgpu, offset); 760 761 if (IS_SKYLAKE(vgpu->gvt->dev_priv) && 762 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 763 /* SKL DPB/C/D aux ctl register changed */ 764 return 0; 765 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 766 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 767 /* write to the data registers */ 768 return 0; 769 } 770 771 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 772 /* just want to clear the sticky bits */ 773 vgpu_vreg(vgpu, offset) = 0; 774 return 0; 775 } 776 777 port = &display->ports[port_index]; 778 dpcd = port->dpcd; 779 780 /* read out message from DATA1 register */ 781 msg = vgpu_vreg(vgpu, offset + 4); 782 addr = (msg >> 8) & 0xffff; 783 ctrl = (msg >> 24) & 0xff; 784 len = msg & 0xff; 785 op = ctrl >> 4; 786 787 if (op == GVT_AUX_NATIVE_WRITE) { 788 int t; 789 uint8_t buf[16]; 790 791 if ((addr + len + 1) >= DPCD_SIZE) { 792 /* 793 * Write request exceeds what we supported, 794 * DCPD spec: When a Source Device is writing a DPCD 795 * address not supported by the Sink Device, the Sink 796 * Device shall reply with AUX NACK and “M” equal to 797 * zero. 798 */ 799 800 /* NAK the write */ 801 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 802 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 803 return 0; 804 } 805 806 /* 807 * Write request format: (command + address) occupies 808 * 3 bytes, followed by (len + 1) bytes of data. 809 */ 810 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 811 return -EINVAL; 812 813 /* unpack data from vreg to buf */ 814 for (t = 0; t < 4; t++) { 815 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 816 817 buf[t * 4] = (r >> 24) & 0xff; 818 buf[t * 4 + 1] = (r >> 16) & 0xff; 819 buf[t * 4 + 2] = (r >> 8) & 0xff; 820 buf[t * 4 + 3] = r & 0xff; 821 } 822 823 /* write to virtual DPCD */ 824 if (dpcd && dpcd->data_valid) { 825 for (t = 0; t <= len; t++) { 826 int p = addr + t; 827 828 dpcd->data[p] = buf[t]; 829 /* check for link training */ 830 if (p == DPCD_TRAINING_PATTERN_SET) 831 dp_aux_ch_ctl_link_training(dpcd, 832 buf[t]); 833 } 834 } 835 836 /* ACK the write */ 837 vgpu_vreg(vgpu, offset + 4) = 0; 838 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 839 dpcd && dpcd->data_valid); 840 return 0; 841 } 842 843 if (op == GVT_AUX_NATIVE_READ) { 844 int idx, i, ret = 0; 845 846 if ((addr + len + 1) >= DPCD_SIZE) { 847 /* 848 * read request exceeds what we supported 849 * DPCD spec: A Sink Device receiving a Native AUX CH 850 * read request for an unsupported DPCD address must 851 * reply with an AUX ACK and read data set equal to 852 * zero instead of replying with AUX NACK. 853 */ 854 855 /* ACK the READ*/ 856 vgpu_vreg(vgpu, offset + 4) = 0; 857 vgpu_vreg(vgpu, offset + 8) = 0; 858 vgpu_vreg(vgpu, offset + 12) = 0; 859 vgpu_vreg(vgpu, offset + 16) = 0; 860 vgpu_vreg(vgpu, offset + 20) = 0; 861 862 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 863 true); 864 return 0; 865 } 866 867 for (idx = 1; idx <= 5; idx++) { 868 /* clear the data registers */ 869 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 870 } 871 872 /* 873 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 874 */ 875 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 876 return -EINVAL; 877 878 /* read from virtual DPCD to vreg */ 879 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 880 if (dpcd && dpcd->data_valid) { 881 for (i = 1; i <= (len + 1); i++) { 882 int t; 883 884 t = dpcd->data[addr + i - 1]; 885 t <<= (24 - 8 * (i % 4)); 886 ret |= t; 887 888 if ((i % 4 == 3) || (i == (len + 1))) { 889 vgpu_vreg(vgpu, offset + 890 (i / 4 + 1) * 4) = ret; 891 ret = 0; 892 } 893 } 894 } 895 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 896 dpcd && dpcd->data_valid); 897 return 0; 898 } 899 900 /* i2c transaction starts */ 901 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 902 903 if (data & DP_AUX_CH_CTL_INTERRUPT) 904 trigger_aux_channel_interrupt(vgpu, offset); 905 return 0; 906 } 907 908 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 909 void *p_data, unsigned int bytes) 910 { 911 bool vga_disable; 912 913 write_vreg(vgpu, offset, p_data, bytes); 914 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 915 916 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 917 vga_disable ? "Disable" : "Enable"); 918 return 0; 919 } 920 921 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 922 unsigned int sbi_offset) 923 { 924 struct intel_vgpu_display *display = &vgpu->display; 925 int num = display->sbi.number; 926 int i; 927 928 for (i = 0; i < num; ++i) 929 if (display->sbi.registers[i].offset == sbi_offset) 930 break; 931 932 if (i == num) 933 return 0; 934 935 return display->sbi.registers[i].value; 936 } 937 938 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 939 unsigned int offset, u32 value) 940 { 941 struct intel_vgpu_display *display = &vgpu->display; 942 int num = display->sbi.number; 943 int i; 944 945 for (i = 0; i < num; ++i) { 946 if (display->sbi.registers[i].offset == offset) 947 break; 948 } 949 950 if (i == num) { 951 if (num == SBI_REG_MAX) { 952 gvt_err("vgpu%d: SBI caching meets maximum limits\n", 953 vgpu->id); 954 return; 955 } 956 display->sbi.number++; 957 } 958 959 display->sbi.registers[i].offset = offset; 960 display->sbi.registers[i].value = value; 961 } 962 963 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 964 void *p_data, unsigned int bytes) 965 { 966 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 967 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 968 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 969 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 970 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 971 sbi_offset); 972 } 973 read_vreg(vgpu, offset, p_data, bytes); 974 return 0; 975 } 976 977 static bool sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 978 void *p_data, unsigned int bytes) 979 { 980 u32 data; 981 982 write_vreg(vgpu, offset, p_data, bytes); 983 data = vgpu_vreg(vgpu, offset); 984 985 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 986 data |= SBI_READY; 987 988 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 989 data |= SBI_RESPONSE_SUCCESS; 990 991 vgpu_vreg(vgpu, offset) = data; 992 993 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 994 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 995 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 996 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 997 998 write_virtual_sbi_register(vgpu, sbi_offset, 999 vgpu_vreg(vgpu, SBI_DATA)); 1000 } 1001 return 0; 1002 } 1003 1004 #define _vgtif_reg(x) \ 1005 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1006 1007 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1008 void *p_data, unsigned int bytes) 1009 { 1010 bool invalid_read = false; 1011 1012 read_vreg(vgpu, offset, p_data, bytes); 1013 1014 switch (offset) { 1015 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1016 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1017 invalid_read = true; 1018 break; 1019 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1020 _vgtif_reg(avail_rs.fence_num): 1021 if (offset + bytes > 1022 _vgtif_reg(avail_rs.fence_num) + 4) 1023 invalid_read = true; 1024 break; 1025 case 0x78010: /* vgt_caps */ 1026 case 0x7881c: 1027 break; 1028 default: 1029 invalid_read = true; 1030 break; 1031 } 1032 if (invalid_read) 1033 gvt_err("invalid pvinfo read: [%x:%x] = %x\n", 1034 offset, bytes, *(u32 *)p_data); 1035 return 0; 1036 } 1037 1038 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1039 { 1040 int ret = 0; 1041 1042 switch (notification) { 1043 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1044 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); 1045 break; 1046 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1047 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); 1048 break; 1049 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1050 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); 1051 break; 1052 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1053 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); 1054 break; 1055 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1056 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1057 case 1: /* Remove this in guest driver. */ 1058 break; 1059 default: 1060 gvt_err("Invalid PV notification %d\n", notification); 1061 } 1062 return ret; 1063 } 1064 1065 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1066 { 1067 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1068 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1069 char *env[3] = {NULL, NULL, NULL}; 1070 char vmid_str[20]; 1071 char display_ready_str[20]; 1072 1073 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready); 1074 env[0] = display_ready_str; 1075 1076 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1077 env[1] = vmid_str; 1078 1079 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1080 } 1081 1082 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1083 void *p_data, unsigned int bytes) 1084 { 1085 u32 data; 1086 int ret; 1087 1088 write_vreg(vgpu, offset, p_data, bytes); 1089 data = vgpu_vreg(vgpu, offset); 1090 1091 switch (offset) { 1092 case _vgtif_reg(display_ready): 1093 send_display_ready_uevent(vgpu, data ? 1 : 0); 1094 break; 1095 case _vgtif_reg(g2v_notify): 1096 ret = handle_g2v_notification(vgpu, data); 1097 break; 1098 /* add xhot and yhot to handled list to avoid error log */ 1099 case 0x78830: 1100 case 0x78834: 1101 case _vgtif_reg(pdp[0].lo): 1102 case _vgtif_reg(pdp[0].hi): 1103 case _vgtif_reg(pdp[1].lo): 1104 case _vgtif_reg(pdp[1].hi): 1105 case _vgtif_reg(pdp[2].lo): 1106 case _vgtif_reg(pdp[2].hi): 1107 case _vgtif_reg(pdp[3].lo): 1108 case _vgtif_reg(pdp[3].hi): 1109 case _vgtif_reg(execlist_context_descriptor_lo): 1110 case _vgtif_reg(execlist_context_descriptor_hi): 1111 break; 1112 default: 1113 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n", 1114 offset, bytes, data); 1115 break; 1116 } 1117 return 0; 1118 } 1119 1120 static int pf_write(struct intel_vgpu *vgpu, 1121 unsigned int offset, void *p_data, unsigned int bytes) 1122 { 1123 u32 val = *(u32 *)p_data; 1124 1125 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1126 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1127 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1128 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1129 vgpu->id); 1130 return 0; 1131 } 1132 1133 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1134 } 1135 1136 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1137 unsigned int offset, void *p_data, unsigned int bytes) 1138 { 1139 write_vreg(vgpu, offset, p_data, bytes); 1140 1141 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) 1142 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; 1143 else 1144 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; 1145 return 0; 1146 } 1147 1148 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1149 unsigned int offset, void *p_data, unsigned int bytes) 1150 { 1151 write_vreg(vgpu, offset, p_data, bytes); 1152 1153 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1154 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1155 return 0; 1156 } 1157 1158 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1159 void *p_data, unsigned int bytes) 1160 { 1161 u32 mode; 1162 1163 write_vreg(vgpu, offset, p_data, bytes); 1164 mode = vgpu_vreg(vgpu, offset); 1165 1166 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1167 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n", 1168 vgpu->id); 1169 return 0; 1170 } 1171 1172 return 0; 1173 } 1174 1175 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1176 void *p_data, unsigned int bytes) 1177 { 1178 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1179 u32 trtte = *(u32 *)p_data; 1180 1181 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1182 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1183 vgpu->id); 1184 return -EINVAL; 1185 } 1186 write_vreg(vgpu, offset, p_data, bytes); 1187 /* TRTTE is not per-context */ 1188 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1189 1190 return 0; 1191 } 1192 1193 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1194 void *p_data, unsigned int bytes) 1195 { 1196 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1197 u32 val = *(u32 *)p_data; 1198 1199 if (val & 1) { 1200 /* unblock hw logic */ 1201 I915_WRITE(_MMIO(offset), val); 1202 } 1203 write_vreg(vgpu, offset, p_data, bytes); 1204 return 0; 1205 } 1206 1207 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1208 void *p_data, unsigned int bytes) 1209 { 1210 u32 v = 0; 1211 1212 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1213 v |= (1 << 0); 1214 1215 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1216 v |= (1 << 8); 1217 1218 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1219 v |= (1 << 16); 1220 1221 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1222 v |= (1 << 24); 1223 1224 vgpu_vreg(vgpu, offset) = v; 1225 1226 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1227 } 1228 1229 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1230 void *p_data, unsigned int bytes) 1231 { 1232 u32 value = *(u32 *)p_data; 1233 u32 cmd = value & 0xff; 1234 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); 1235 1236 switch (cmd) { 1237 case 0x6: 1238 /** 1239 * "Read memory latency" command on gen9. 1240 * Below memory latency values are read 1241 * from skylake platform. 1242 */ 1243 if (!*data0) 1244 *data0 = 0x1e1a1100; 1245 else 1246 *data0 = 0x61514b3d; 1247 break; 1248 case 0x5: 1249 *data0 |= 0x1; 1250 break; 1251 } 1252 1253 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1254 vgpu->id, value, *data0); 1255 1256 value &= ~(1 << 31); 1257 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1258 } 1259 1260 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1261 unsigned int offset, void *p_data, unsigned int bytes) 1262 { 1263 u32 v = *(u32 *)p_data; 1264 1265 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1266 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1267 v |= (v >> 1); 1268 1269 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1270 } 1271 1272 static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1273 void *p_data, unsigned int bytes) 1274 { 1275 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1276 i915_reg_t reg = {.reg = offset}; 1277 1278 switch (offset) { 1279 case 0x4ddc: 1280 vgpu_vreg(vgpu, offset) = 0x8000003c; 1281 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */ 1282 I915_WRITE(reg, vgpu_vreg(vgpu, offset)); 1283 break; 1284 case 0x42080: 1285 vgpu_vreg(vgpu, offset) = 0x8000; 1286 /* WaCompressedResourceDisplayNewHashMode:skl */ 1287 I915_WRITE(reg, vgpu_vreg(vgpu, offset)); 1288 break; 1289 default: 1290 return -EINVAL; 1291 } 1292 1293 return 0; 1294 } 1295 1296 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1297 void *p_data, unsigned int bytes) 1298 { 1299 u32 v = *(u32 *)p_data; 1300 1301 /* other bits are MBZ. */ 1302 v &= (1 << 31) | (1 << 30); 1303 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1304 1305 vgpu_vreg(vgpu, offset) = v; 1306 1307 return 0; 1308 } 1309 1310 static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu, 1311 unsigned int offset, void *p_data, unsigned int bytes) 1312 { 1313 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1314 1315 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1316 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1317 } 1318 1319 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1320 void *p_data, unsigned int bytes) 1321 { 1322 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1323 struct intel_vgpu_execlist *execlist; 1324 u32 data = *(u32 *)p_data; 1325 int ret = 0; 1326 1327 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1)) 1328 return -EINVAL; 1329 1330 execlist = &vgpu->execlist[ring_id]; 1331 1332 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data; 1333 if (execlist->elsp_dwords.index == 3) { 1334 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1335 if(ret) 1336 gvt_err("fail submit workload on ring %d\n", ring_id); 1337 } 1338 1339 ++execlist->elsp_dwords.index; 1340 execlist->elsp_dwords.index &= 0x3; 1341 return ret; 1342 } 1343 1344 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1345 void *p_data, unsigned int bytes) 1346 { 1347 u32 data = *(u32 *)p_data; 1348 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1349 bool enable_execlist; 1350 1351 write_vreg(vgpu, offset, p_data, bytes); 1352 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1353 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1354 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1355 1356 gvt_dbg_core("EXECLIST %s on ring %d\n", 1357 (enable_execlist ? "enabling" : "disabling"), 1358 ring_id); 1359 1360 if (enable_execlist) 1361 intel_vgpu_start_schedule(vgpu); 1362 } 1363 return 0; 1364 } 1365 1366 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1367 unsigned int offset, void *p_data, unsigned int bytes) 1368 { 1369 int rc = 0; 1370 unsigned int id = 0; 1371 1372 write_vreg(vgpu, offset, p_data, bytes); 1373 vgpu_vreg(vgpu, offset) = 0; 1374 1375 switch (offset) { 1376 case 0x4260: 1377 id = RCS; 1378 break; 1379 case 0x4264: 1380 id = VCS; 1381 break; 1382 case 0x4268: 1383 id = VCS2; 1384 break; 1385 case 0x426c: 1386 id = BCS; 1387 break; 1388 case 0x4270: 1389 id = VECS; 1390 break; 1391 default: 1392 rc = -EINVAL; 1393 break; 1394 } 1395 set_bit(id, (void *)vgpu->tlb_handle_pending); 1396 1397 return rc; 1398 } 1399 1400 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 1401 unsigned int offset, void *p_data, unsigned int bytes) 1402 { 1403 u32 data; 1404 1405 write_vreg(vgpu, offset, p_data, bytes); 1406 data = vgpu_vreg(vgpu, offset); 1407 1408 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) 1409 data |= RESET_CTL_READY_TO_RESET; 1410 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 1411 data &= ~RESET_CTL_READY_TO_RESET; 1412 1413 vgpu_vreg(vgpu, offset) = data; 1414 return 0; 1415 } 1416 1417 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1418 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 1419 f, s, am, rm, d, r, w); \ 1420 if (ret) \ 1421 return ret; \ 1422 } while (0) 1423 1424 #define MMIO_D(reg, d) \ 1425 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1426 1427 #define MMIO_DH(reg, d, r, w) \ 1428 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1429 1430 #define MMIO_DFH(reg, d, f, r, w) \ 1431 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1432 1433 #define MMIO_GM(reg, d, r, w) \ 1434 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1435 1436 #define MMIO_RO(reg, d, f, rm, r, w) \ 1437 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1438 1439 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1440 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1441 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1442 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1443 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1444 } while (0) 1445 1446 #define MMIO_RING_D(prefix, d) \ 1447 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1448 1449 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1450 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1451 1452 #define MMIO_RING_GM(prefix, d, r, w) \ 1453 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1454 1455 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1456 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1457 1458 static int init_generic_mmio_info(struct intel_gvt *gvt) 1459 { 1460 struct drm_i915_private *dev_priv = gvt->dev_priv; 1461 int ret; 1462 1463 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1464 1465 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1466 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1467 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1468 MMIO_D(SDEISR, D_ALL); 1469 1470 MMIO_RING_D(RING_HWSTAM, D_ALL); 1471 1472 MMIO_GM(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1473 MMIO_GM(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1474 MMIO_GM(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1475 MMIO_GM(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1476 1477 #define RING_REG(base) (base + 0x28) 1478 MMIO_RING_D(RING_REG, D_ALL); 1479 #undef RING_REG 1480 1481 #define RING_REG(base) (base + 0x134) 1482 MMIO_RING_D(RING_REG, D_ALL); 1483 #undef RING_REG 1484 1485 MMIO_GM(0x2148, D_ALL, NULL, NULL); 1486 MMIO_GM(CCID, D_ALL, NULL, NULL); 1487 MMIO_GM(0x12198, D_ALL, NULL, NULL); 1488 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1489 1490 MMIO_RING_D(RING_TAIL, D_ALL); 1491 MMIO_RING_D(RING_HEAD, D_ALL); 1492 MMIO_RING_D(RING_CTL, D_ALL); 1493 MMIO_RING_D(RING_ACTHD, D_ALL); 1494 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 1495 1496 /* RING MODE */ 1497 #define RING_REG(base) (base + 0x29c) 1498 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK, NULL, ring_mode_mmio_write); 1499 #undef RING_REG 1500 1501 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1502 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL); 1503 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1504 ring_timestamp_mmio_read, NULL); 1505 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1506 ring_timestamp_mmio_read, NULL); 1507 1508 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1509 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL); 1510 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1511 1512 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL); 1513 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL); 1514 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK, NULL, NULL); 1515 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK, NULL, NULL); 1516 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK, NULL, NULL); 1517 MMIO_D(GAM_ECOCHK, D_ALL); 1518 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK, NULL, NULL); 1519 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1520 MMIO_D(0x9030, D_ALL); 1521 MMIO_D(0x20a0, D_ALL); 1522 MMIO_D(0x2420, D_ALL); 1523 MMIO_D(0x2430, D_ALL); 1524 MMIO_D(0x2434, D_ALL); 1525 MMIO_D(0x2438, D_ALL); 1526 MMIO_D(0x243c, D_ALL); 1527 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK, NULL, NULL); 1528 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1529 MMIO_DFH(0xe100, D_ALL, F_MODE_MASK, NULL, NULL); 1530 1531 /* display */ 1532 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1533 MMIO_D(0x602a0, D_ALL); 1534 1535 MMIO_D(0x65050, D_ALL); 1536 MMIO_D(0x650b4, D_ALL); 1537 1538 MMIO_D(0xc4040, D_ALL); 1539 MMIO_D(DERRMR, D_ALL); 1540 1541 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1542 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1543 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1544 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1545 1546 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1547 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1548 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1549 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1550 1551 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1552 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1553 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1554 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1555 1556 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1557 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1558 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1559 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1560 1561 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1562 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1563 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1564 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1565 1566 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1567 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1568 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1569 1570 MMIO_D(CURPOS(PIPE_A), D_ALL); 1571 MMIO_D(CURPOS(PIPE_B), D_ALL); 1572 MMIO_D(CURPOS(PIPE_C), D_ALL); 1573 1574 MMIO_D(CURBASE(PIPE_A), D_ALL); 1575 MMIO_D(CURBASE(PIPE_B), D_ALL); 1576 MMIO_D(CURBASE(PIPE_C), D_ALL); 1577 1578 MMIO_D(0x700ac, D_ALL); 1579 MMIO_D(0x710ac, D_ALL); 1580 MMIO_D(0x720ac, D_ALL); 1581 1582 MMIO_D(0x70090, D_ALL); 1583 MMIO_D(0x70094, D_ALL); 1584 MMIO_D(0x70098, D_ALL); 1585 MMIO_D(0x7009c, D_ALL); 1586 1587 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1588 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1589 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1590 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1591 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1592 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1593 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1594 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1595 1596 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1597 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1598 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1599 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1600 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1601 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1602 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1603 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1604 1605 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1606 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1607 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1608 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1609 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1610 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1611 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1612 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1613 1614 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1615 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1616 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1617 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1618 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1619 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1620 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1621 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1622 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1623 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1624 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1625 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1626 1627 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1628 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1629 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1630 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1631 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1632 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1633 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1634 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1635 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1636 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1637 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1638 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1639 1640 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1641 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1642 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1643 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1644 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1645 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1646 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1647 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1648 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1649 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1650 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1651 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1652 1653 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1654 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1655 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1656 1657 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1658 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1659 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1660 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1661 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1662 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1663 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1664 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1665 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1666 1667 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1668 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1669 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1670 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1671 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1672 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1673 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1674 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1675 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1676 1677 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1678 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1679 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1680 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1681 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1682 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1683 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1684 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1685 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1686 1687 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1688 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1689 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1690 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1691 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1692 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1693 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1694 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1695 1696 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1697 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1698 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1699 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1700 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1701 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1702 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1703 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1704 1705 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1706 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1707 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1708 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1709 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1710 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1711 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1712 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1713 1714 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1715 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1716 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1717 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1718 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1719 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1720 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1721 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1722 1723 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1724 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1725 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1726 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1727 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1728 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1729 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1730 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1731 1732 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1733 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1734 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1735 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1736 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1737 1738 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1739 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1740 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1741 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1742 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1743 1744 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1745 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1746 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1747 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1748 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1749 1750 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1751 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1752 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1753 MMIO_D(WM1_LP_ILK, D_ALL); 1754 MMIO_D(WM2_LP_ILK, D_ALL); 1755 MMIO_D(WM3_LP_ILK, D_ALL); 1756 MMIO_D(WM1S_LP_ILK, D_ALL); 1757 MMIO_D(WM2S_LP_IVB, D_ALL); 1758 MMIO_D(WM3S_LP_IVB, D_ALL); 1759 1760 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1761 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1762 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1763 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1764 1765 MMIO_D(0x48268, D_ALL); 1766 1767 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1768 gmbus_mmio_write); 1769 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1770 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1771 1772 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1773 dp_aux_ch_ctl_mmio_write); 1774 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1775 dp_aux_ch_ctl_mmio_write); 1776 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1777 dp_aux_ch_ctl_mmio_write); 1778 1779 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write); 1780 1781 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); 1782 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); 1783 1784 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1785 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1786 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1787 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1788 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1789 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1790 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1791 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1792 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1793 1794 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 1795 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 1796 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 1797 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 1798 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 1799 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 1800 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 1801 1802 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 1803 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 1804 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 1805 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 1806 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 1807 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 1808 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 1809 1810 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 1811 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 1812 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 1813 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 1814 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 1815 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 1816 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 1817 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 1818 1819 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 1820 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 1821 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 1822 1823 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 1824 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 1825 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 1826 1827 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 1828 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 1829 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 1830 1831 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 1832 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 1833 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 1834 1835 MMIO_D(_FDI_RXA_MISC, D_ALL); 1836 MMIO_D(_FDI_RXB_MISC, D_ALL); 1837 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 1838 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 1839 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 1840 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 1841 1842 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 1843 MMIO_D(PCH_PP_DIVISOR, D_ALL); 1844 MMIO_D(PCH_PP_STATUS, D_ALL); 1845 MMIO_D(PCH_LVDS, D_ALL); 1846 MMIO_D(_PCH_DPLL_A, D_ALL); 1847 MMIO_D(_PCH_DPLL_B, D_ALL); 1848 MMIO_D(_PCH_FPA0, D_ALL); 1849 MMIO_D(_PCH_FPA1, D_ALL); 1850 MMIO_D(_PCH_FPB0, D_ALL); 1851 MMIO_D(_PCH_FPB1, D_ALL); 1852 MMIO_D(PCH_DREF_CONTROL, D_ALL); 1853 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 1854 MMIO_D(PCH_DPLL_SEL, D_ALL); 1855 1856 MMIO_D(0x61208, D_ALL); 1857 MMIO_D(0x6120c, D_ALL); 1858 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 1859 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 1860 1861 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); 1862 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); 1863 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); 1864 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); 1865 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL); 1866 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL); 1867 1868 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 1869 PORTA_HOTPLUG_STATUS_MASK 1870 | PORTB_HOTPLUG_STATUS_MASK 1871 | PORTC_HOTPLUG_STATUS_MASK 1872 | PORTD_HOTPLUG_STATUS_MASK, 1873 NULL, NULL); 1874 1875 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 1876 MMIO_D(FUSE_STRAP, D_ALL); 1877 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 1878 1879 MMIO_D(DISP_ARB_CTL, D_ALL); 1880 MMIO_D(DISP_ARB_CTL2, D_ALL); 1881 1882 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 1883 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 1884 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 1885 1886 MMIO_D(SOUTH_CHICKEN1, D_ALL); 1887 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 1888 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 1889 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 1890 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 1891 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 1892 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 1893 1894 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 1895 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 1896 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 1897 MMIO_D(ILK_DPFC_STATUS, D_ALL); 1898 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 1899 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 1900 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 1901 1902 MMIO_D(IPS_CTL, D_ALL); 1903 1904 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 1905 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 1906 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 1907 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 1908 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 1909 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 1910 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 1911 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 1912 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 1913 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 1914 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 1915 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 1916 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 1917 1918 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 1919 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 1920 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 1921 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 1922 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 1923 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 1924 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 1925 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 1926 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 1927 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 1928 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 1929 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 1930 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 1931 1932 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 1933 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 1934 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 1935 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 1936 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 1937 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 1938 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 1939 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 1940 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 1941 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 1942 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 1943 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 1944 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 1945 1946 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 1947 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 1948 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1949 1950 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 1951 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 1952 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1953 1954 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 1955 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 1956 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1957 1958 MMIO_D(0x60110, D_ALL); 1959 MMIO_D(0x61110, D_ALL); 1960 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1961 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1962 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1963 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1964 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1965 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1966 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1967 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1968 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1969 1970 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 1971 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 1972 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 1973 MMIO_D(SPLL_CTL, D_ALL); 1974 MMIO_D(_WRPLL_CTL1, D_ALL); 1975 MMIO_D(_WRPLL_CTL2, D_ALL); 1976 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 1977 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 1978 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 1979 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 1980 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 1981 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 1982 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 1983 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 1984 1985 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 1986 MMIO_D(0x46508, D_ALL); 1987 1988 MMIO_D(0x49080, D_ALL); 1989 MMIO_D(0x49180, D_ALL); 1990 MMIO_D(0x49280, D_ALL); 1991 1992 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1993 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1994 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1995 1996 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 1997 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 1998 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 1999 2000 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2001 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2002 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2003 2004 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2005 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2006 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2007 2008 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2009 MMIO_D(SBI_ADDR, D_ALL); 2010 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2011 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2012 MMIO_D(PIXCLK_GATE, D_ALL); 2013 2014 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, 2015 dp_aux_ch_ctl_mmio_write); 2016 2017 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2018 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2019 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2020 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2021 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2022 2023 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2024 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2025 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2026 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2027 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2028 2029 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2030 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2031 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2032 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2033 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2034 2035 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2036 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2037 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2038 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2039 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2040 2041 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2042 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2043 2044 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 2045 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 2046 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 2047 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 2048 2049 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 2050 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 2051 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 2052 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 2053 2054 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2055 MMIO_D(FORCEWAKE_ACK, D_ALL); 2056 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2057 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2058 MMIO_D(GTFIFODBG, D_ALL); 2059 MMIO_D(GTFIFOCTL, D_ALL); 2060 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2061 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL); 2062 MMIO_D(ECOBUS, D_ALL); 2063 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2064 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2065 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2066 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2067 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2068 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2069 MMIO_D(GEN6_RPSTAT1, D_ALL); 2070 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2071 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2072 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2073 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2074 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2075 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2076 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2077 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2078 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2079 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2080 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2081 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2082 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2083 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2084 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2085 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2086 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2087 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2088 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2089 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2090 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2091 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2092 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2093 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2094 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2095 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2096 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2097 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2098 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2099 2100 MMIO_D(RSTDBYCTL, D_ALL); 2101 2102 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2103 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2104 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write); 2105 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2106 2107 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL); 2108 2109 MMIO_D(TILECTL, D_ALL); 2110 2111 MMIO_D(GEN6_UCGCTL1, D_ALL); 2112 MMIO_D(GEN6_UCGCTL2, D_ALL); 2113 2114 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2115 2116 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_SKL); 2117 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2118 MMIO_D(0x13812c, D_ALL); 2119 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2120 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2121 MMIO_D(HSW_IDICR, D_ALL); 2122 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2123 2124 MMIO_D(0x3c, D_ALL); 2125 MMIO_D(0x860, D_ALL); 2126 MMIO_D(ECOSKPD, D_ALL); 2127 MMIO_D(0x121d0, D_ALL); 2128 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2129 MMIO_D(0x41d0, D_ALL); 2130 MMIO_D(GAC_ECO_BITS, D_ALL); 2131 MMIO_D(0x6200, D_ALL); 2132 MMIO_D(0x6204, D_ALL); 2133 MMIO_D(0x6208, D_ALL); 2134 MMIO_D(0x7118, D_ALL); 2135 MMIO_D(0x7180, D_ALL); 2136 MMIO_D(0x7408, D_ALL); 2137 MMIO_D(0x7c00, D_ALL); 2138 MMIO_D(GEN6_MBCTL, D_ALL); 2139 MMIO_D(0x911c, D_ALL); 2140 MMIO_D(0x9120, D_ALL); 2141 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2142 2143 MMIO_D(GAB_CTL, D_ALL); 2144 MMIO_D(0x48800, D_ALL); 2145 MMIO_D(0xce044, D_ALL); 2146 MMIO_D(0xe6500, D_ALL); 2147 MMIO_D(0xe6504, D_ALL); 2148 MMIO_D(0xe6600, D_ALL); 2149 MMIO_D(0xe6604, D_ALL); 2150 MMIO_D(0xe6700, D_ALL); 2151 MMIO_D(0xe6704, D_ALL); 2152 MMIO_D(0xe6800, D_ALL); 2153 MMIO_D(0xe6804, D_ALL); 2154 MMIO_D(PCH_GMBUS4, D_ALL); 2155 MMIO_D(PCH_GMBUS5, D_ALL); 2156 2157 MMIO_D(0x902c, D_ALL); 2158 MMIO_D(0xec008, D_ALL); 2159 MMIO_D(0xec00c, D_ALL); 2160 MMIO_D(0xec008 + 0x18, D_ALL); 2161 MMIO_D(0xec00c + 0x18, D_ALL); 2162 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 2163 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 2164 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 2165 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 2166 MMIO_D(0xec408, D_ALL); 2167 MMIO_D(0xec40c, D_ALL); 2168 MMIO_D(0xec408 + 0x18, D_ALL); 2169 MMIO_D(0xec40c + 0x18, D_ALL); 2170 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 2171 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 2172 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 2173 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 2174 MMIO_D(0xfc810, D_ALL); 2175 MMIO_D(0xfc81c, D_ALL); 2176 MMIO_D(0xfc828, D_ALL); 2177 MMIO_D(0xfc834, D_ALL); 2178 MMIO_D(0xfcc00, D_ALL); 2179 MMIO_D(0xfcc0c, D_ALL); 2180 MMIO_D(0xfcc18, D_ALL); 2181 MMIO_D(0xfcc24, D_ALL); 2182 MMIO_D(0xfd000, D_ALL); 2183 MMIO_D(0xfd00c, D_ALL); 2184 MMIO_D(0xfd018, D_ALL); 2185 MMIO_D(0xfd024, D_ALL); 2186 MMIO_D(0xfd034, D_ALL); 2187 2188 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2189 MMIO_D(0x2054, D_ALL); 2190 MMIO_D(0x12054, D_ALL); 2191 MMIO_D(0x22054, D_ALL); 2192 MMIO_D(0x1a054, D_ALL); 2193 2194 MMIO_D(0x44070, D_ALL); 2195 2196 MMIO_D(0x215c, D_HSW_PLUS); 2197 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2198 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2199 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2200 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2201 2202 MMIO_F(0x2290, 8, 0, 0, 0, D_HSW_PLUS, NULL, NULL); 2203 MMIO_D(OACONTROL, D_HSW); 2204 MMIO_D(0x2b00, D_BDW_PLUS); 2205 MMIO_D(0x2360, D_BDW_PLUS); 2206 MMIO_F(0x5200, 32, 0, 0, 0, D_ALL, NULL, NULL); 2207 MMIO_F(0x5240, 32, 0, 0, 0, D_ALL, NULL, NULL); 2208 MMIO_F(0x5280, 16, 0, 0, 0, D_ALL, NULL, NULL); 2209 2210 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2211 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2212 MMIO_D(BCS_SWCTRL, D_ALL); 2213 2214 MMIO_F(HS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2215 MMIO_F(DS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2216 MMIO_F(IA_VERTICES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2217 MMIO_F(IA_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2218 MMIO_F(VS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2219 MMIO_F(GS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2220 MMIO_F(GS_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2221 MMIO_F(CL_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2222 MMIO_F(CL_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2223 MMIO_F(PS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2224 MMIO_F(PS_DEPTH_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2225 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2226 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2227 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2228 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2229 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2230 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2231 2232 return 0; 2233 } 2234 2235 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2236 { 2237 struct drm_i915_private *dev_priv = gvt->dev_priv; 2238 int ret; 2239 2240 MMIO_DH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, 2241 intel_vgpu_reg_imr_handler); 2242 2243 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2244 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2245 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2246 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2247 2248 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2249 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2250 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2251 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2252 2253 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2254 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2255 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2256 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2257 2258 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2259 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2260 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2261 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2262 2263 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2264 intel_vgpu_reg_imr_handler); 2265 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2266 intel_vgpu_reg_ier_handler); 2267 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2268 intel_vgpu_reg_iir_handler); 2269 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2270 2271 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2272 intel_vgpu_reg_imr_handler); 2273 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2274 intel_vgpu_reg_ier_handler); 2275 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2276 intel_vgpu_reg_iir_handler); 2277 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2278 2279 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2280 intel_vgpu_reg_imr_handler); 2281 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2282 intel_vgpu_reg_ier_handler); 2283 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2284 intel_vgpu_reg_iir_handler); 2285 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2286 2287 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2288 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2289 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2290 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2291 2292 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2293 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2294 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2295 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2296 2297 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2298 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2299 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2300 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2301 2302 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2303 intel_vgpu_reg_master_irq_handler); 2304 2305 MMIO_D(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2306 MMIO_D(0x1c134, D_BDW_PLUS); 2307 2308 MMIO_D(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2309 MMIO_D(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2310 MMIO_GM(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2311 MMIO_D(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2312 MMIO_D(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2313 MMIO_D(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2314 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK, NULL, ring_mode_mmio_write); 2315 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2316 NULL, NULL); 2317 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2318 NULL, NULL); 2319 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2320 ring_timestamp_mmio_read, NULL); 2321 2322 MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS); 2323 2324 #define RING_REG(base) (base + 0xd0) 2325 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2326 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2327 ring_reset_ctl_write); 2328 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, 2329 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2330 ring_reset_ctl_write); 2331 #undef RING_REG 2332 2333 #define RING_REG(base) (base + 0x230) 2334 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2335 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write); 2336 #undef RING_REG 2337 2338 #define RING_REG(base) (base + 0x234) 2339 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2340 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, ~0LL, D_BDW_PLUS, NULL, NULL); 2341 #undef RING_REG 2342 2343 #define RING_REG(base) (base + 0x244) 2344 MMIO_RING_D(RING_REG, D_BDW_PLUS); 2345 MMIO_D(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2346 #undef RING_REG 2347 2348 #define RING_REG(base) (base + 0x370) 2349 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2350 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS, 2351 NULL, NULL); 2352 #undef RING_REG 2353 2354 #define RING_REG(base) (base + 0x3a0) 2355 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2356 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2357 #undef RING_REG 2358 2359 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2360 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2361 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2362 MMIO_D(0x1c1d0, D_BDW_PLUS); 2363 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2364 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2365 MMIO_D(0x1c054, D_BDW_PLUS); 2366 2367 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2368 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2369 2370 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2371 2372 #define RING_REG(base) (base + 0x270) 2373 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2374 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2375 #undef RING_REG 2376 2377 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); 2378 MMIO_GM(0x1c080, D_BDW_PLUS, NULL, NULL); 2379 2380 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2381 2382 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW); 2383 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW); 2384 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW); 2385 2386 MMIO_D(WM_MISC, D_BDW); 2387 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 2388 2389 MMIO_D(0x66c00, D_BDW_PLUS); 2390 MMIO_D(0x66c04, D_BDW_PLUS); 2391 2392 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2393 2394 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2395 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2396 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2397 2398 MMIO_D(0xfdc, D_BDW); 2399 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2400 MMIO_D(GEN7_ROW_CHICKEN2, D_BDW_PLUS); 2401 MMIO_D(GEN8_UCGCTL6, D_BDW_PLUS); 2402 2403 MMIO_D(0xb1f0, D_BDW); 2404 MMIO_D(0xb1c0, D_BDW); 2405 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2406 MMIO_D(0xb100, D_BDW); 2407 MMIO_D(0xb10c, D_BDW); 2408 MMIO_D(0xb110, D_BDW); 2409 2410 MMIO_DFH(0x24d0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2411 MMIO_DFH(0x24d4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2412 MMIO_DFH(0x24d8, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2413 MMIO_DFH(0x24dc, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2414 2415 MMIO_D(0x83a4, D_BDW); 2416 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2417 2418 MMIO_D(0x8430, D_BDW); 2419 2420 MMIO_D(0x110000, D_BDW_PLUS); 2421 2422 MMIO_D(0x48400, D_BDW_PLUS); 2423 2424 MMIO_D(0x6e570, D_BDW_PLUS); 2425 MMIO_D(0x65f10, D_BDW_PLUS); 2426 2427 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2428 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2429 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2430 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2431 2432 MMIO_D(0x2248, D_BDW); 2433 2434 return 0; 2435 } 2436 2437 static int init_skl_mmio_info(struct intel_gvt *gvt) 2438 { 2439 struct drm_i915_private *dev_priv = gvt->dev_priv; 2440 int ret; 2441 2442 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2443 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2444 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2445 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2446 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2447 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2448 2449 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2450 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2451 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2452 2453 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL); 2454 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write); 2455 2456 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, mailbox_write); 2457 MMIO_D(0xa210, D_SKL_PLUS); 2458 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2459 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2460 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2461 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write); 2462 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write); 2463 MMIO_D(0x45504, D_SKL); 2464 MMIO_D(0x45520, D_SKL); 2465 MMIO_D(0x46000, D_SKL); 2466 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write); 2467 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write); 2468 MMIO_D(0x6C040, D_SKL); 2469 MMIO_D(0x6C048, D_SKL); 2470 MMIO_D(0x6C050, D_SKL); 2471 MMIO_D(0x6C044, D_SKL); 2472 MMIO_D(0x6C04C, D_SKL); 2473 MMIO_D(0x6C054, D_SKL); 2474 MMIO_D(0x6c058, D_SKL); 2475 MMIO_D(0x6c05c, D_SKL); 2476 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL); 2477 2478 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write); 2479 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write); 2480 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write); 2481 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write); 2482 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write); 2483 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write); 2484 2485 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write); 2486 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write); 2487 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write); 2488 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write); 2489 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write); 2490 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write); 2491 2492 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write); 2493 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write); 2494 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write); 2495 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write); 2496 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write); 2497 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write); 2498 2499 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2500 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2501 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2502 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2503 2504 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2505 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2506 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2507 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2508 2509 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2510 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2511 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2512 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2513 2514 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL); 2515 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL); 2516 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL); 2517 2518 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2519 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2520 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2521 2522 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2523 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2524 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2525 2526 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2527 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2528 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2529 2530 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2531 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2532 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2533 2534 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL); 2535 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL); 2536 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL); 2537 2538 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL); 2539 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL); 2540 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL); 2541 2542 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL); 2543 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL); 2544 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL); 2545 2546 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL); 2547 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL); 2548 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL); 2549 2550 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2551 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2552 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2553 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2554 2555 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2556 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2557 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2558 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2559 2560 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2561 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2562 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2563 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2564 2565 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL); 2566 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL); 2567 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL); 2568 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL); 2569 2570 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL); 2571 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL); 2572 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL); 2573 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL); 2574 2575 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL); 2576 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL); 2577 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL); 2578 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL); 2579 2580 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL); 2581 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL); 2582 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL); 2583 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL); 2584 2585 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL); 2586 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL); 2587 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL); 2588 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL); 2589 2590 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL); 2591 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL); 2592 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL); 2593 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL); 2594 2595 MMIO_D(0x70380, D_SKL); 2596 MMIO_D(0x71380, D_SKL); 2597 MMIO_D(0x72380, D_SKL); 2598 MMIO_D(0x7039c, D_SKL); 2599 2600 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL); 2601 MMIO_D(0x8f074, D_SKL); 2602 MMIO_D(0x8f004, D_SKL); 2603 MMIO_D(0x8f034, D_SKL); 2604 2605 MMIO_D(0xb11c, D_SKL); 2606 2607 MMIO_D(0x51000, D_SKL); 2608 MMIO_D(0x6c00c, D_SKL); 2609 2610 MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL); 2611 MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL); 2612 2613 MMIO_D(0xd08, D_SKL); 2614 MMIO_D(0x20e0, D_SKL); 2615 MMIO_D(0x20ec, D_SKL); 2616 2617 /* TRTT */ 2618 MMIO_D(0x4de0, D_SKL); 2619 MMIO_D(0x4de4, D_SKL); 2620 MMIO_D(0x4de8, D_SKL); 2621 MMIO_D(0x4dec, D_SKL); 2622 MMIO_D(0x4df0, D_SKL); 2623 MMIO_DH(0x4df4, D_SKL, NULL, gen9_trtte_write); 2624 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write); 2625 2626 MMIO_D(0x45008, D_SKL); 2627 2628 MMIO_D(0x46430, D_SKL); 2629 2630 MMIO_D(0x46520, D_SKL); 2631 2632 MMIO_D(0xc403c, D_SKL); 2633 MMIO_D(0xb004, D_SKL); 2634 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2635 2636 MMIO_D(0x65900, D_SKL); 2637 MMIO_D(0x1082c0, D_SKL); 2638 MMIO_D(0x4068, D_SKL); 2639 MMIO_D(0x67054, D_SKL); 2640 MMIO_D(0x6e560, D_SKL); 2641 MMIO_D(0x6e554, D_SKL); 2642 MMIO_D(0x2b20, D_SKL); 2643 MMIO_D(0x65f00, D_SKL); 2644 MMIO_D(0x65f08, D_SKL); 2645 MMIO_D(0x320f0, D_SKL); 2646 2647 MMIO_D(_REG_VCS2_EXCC, D_SKL); 2648 MMIO_D(0x70034, D_SKL); 2649 MMIO_D(0x71034, D_SKL); 2650 MMIO_D(0x72034, D_SKL); 2651 2652 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL); 2653 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL); 2654 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL); 2655 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL); 2656 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL); 2657 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL); 2658 2659 MMIO_D(0x44500, D_SKL); 2660 return 0; 2661 } 2662 2663 /** 2664 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset 2665 * @gvt: GVT device 2666 * @offset: register offset 2667 * 2668 * This function is used to find the MMIO information entry from hash table 2669 * 2670 * Returns: 2671 * pointer to MMIO information entry, NULL if not exists 2672 */ 2673 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 2674 unsigned int offset) 2675 { 2676 struct intel_gvt_mmio_info *e; 2677 2678 WARN_ON(!IS_ALIGNED(offset, 4)); 2679 2680 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 2681 if (e->offset == offset) 2682 return e; 2683 } 2684 return NULL; 2685 } 2686 2687 /** 2688 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2689 * @gvt: GVT device 2690 * 2691 * This function is called at the driver unloading stage, to clean up the MMIO 2692 * information table of GVT device 2693 * 2694 */ 2695 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2696 { 2697 struct hlist_node *tmp; 2698 struct intel_gvt_mmio_info *e; 2699 int i; 2700 2701 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2702 kfree(e); 2703 2704 vfree(gvt->mmio.mmio_attribute); 2705 gvt->mmio.mmio_attribute = NULL; 2706 } 2707 2708 /** 2709 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2710 * @gvt: GVT device 2711 * 2712 * This function is called at the initialization stage, to setup the MMIO 2713 * information table for GVT device 2714 * 2715 * Returns: 2716 * zero on success, negative if failed. 2717 */ 2718 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2719 { 2720 struct intel_gvt_device_info *info = &gvt->device_info; 2721 struct drm_i915_private *dev_priv = gvt->dev_priv; 2722 int ret; 2723 2724 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size); 2725 if (!gvt->mmio.mmio_attribute) 2726 return -ENOMEM; 2727 2728 ret = init_generic_mmio_info(gvt); 2729 if (ret) 2730 goto err; 2731 2732 if (IS_BROADWELL(dev_priv)) { 2733 ret = init_broadwell_mmio_info(gvt); 2734 if (ret) 2735 goto err; 2736 } else if (IS_SKYLAKE(dev_priv)) { 2737 ret = init_broadwell_mmio_info(gvt); 2738 if (ret) 2739 goto err; 2740 ret = init_skl_mmio_info(gvt); 2741 if (ret) 2742 goto err; 2743 } 2744 return 0; 2745 err: 2746 intel_gvt_clean_mmio_info(gvt); 2747 return ret; 2748 } 2749 2750 /** 2751 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 2752 * @gvt: a GVT device 2753 * @offset: register offset 2754 * 2755 */ 2756 void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset) 2757 { 2758 gvt->mmio.mmio_attribute[offset >> 2] |= 2759 F_ACCESSED; 2760 } 2761 2762 /** 2763 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 2764 * @gvt: a GVT device 2765 * @offset: register offset 2766 * 2767 */ 2768 bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt, 2769 unsigned int offset) 2770 { 2771 return gvt->mmio.mmio_attribute[offset >> 2] & 2772 F_CMD_ACCESS; 2773 } 2774 2775 /** 2776 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 2777 * @gvt: a GVT device 2778 * @offset: register offset 2779 * 2780 */ 2781 bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, 2782 unsigned int offset) 2783 { 2784 return gvt->mmio.mmio_attribute[offset >> 2] & 2785 F_UNALIGN; 2786 } 2787 2788 /** 2789 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 2790 * @gvt: a GVT device 2791 * @offset: register offset 2792 * 2793 */ 2794 void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt, 2795 unsigned int offset) 2796 { 2797 gvt->mmio.mmio_attribute[offset >> 2] |= 2798 F_CMD_ACCESSED; 2799 } 2800 2801 /** 2802 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 2803 * @gvt: a GVT device 2804 * @offset: register offset 2805 * 2806 * Returns: 2807 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 2808 * 2809 */ 2810 bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset) 2811 { 2812 return gvt->mmio.mmio_attribute[offset >> 2] & 2813 F_MODE_MASK; 2814 } 2815 2816 /** 2817 * intel_vgpu_default_mmio_read - default MMIO read handler 2818 * @vgpu: a vGPU 2819 * @offset: access offset 2820 * @p_data: data return buffer 2821 * @bytes: access data length 2822 * 2823 * Returns: 2824 * Zero on success, negative error code if failed. 2825 */ 2826 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 2827 void *p_data, unsigned int bytes) 2828 { 2829 read_vreg(vgpu, offset, p_data, bytes); 2830 return 0; 2831 } 2832 2833 /** 2834 * intel_t_default_mmio_write - default MMIO write handler 2835 * @vgpu: a vGPU 2836 * @offset: access offset 2837 * @p_data: write data buffer 2838 * @bytes: access data length 2839 * 2840 * Returns: 2841 * Zero on success, negative error code if failed. 2842 */ 2843 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2844 void *p_data, unsigned int bytes) 2845 { 2846 write_vreg(vgpu, offset, p_data, bytes); 2847 return 0; 2848 } 2849