1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "i915_reg.h" 41 #include "gvt.h" 42 #include "i915_pvinfo.h" 43 #include "intel_mchbar_regs.h" 44 #include "display/intel_display_types.h" 45 #include "display/intel_dmc_regs.h" 46 #include "display/intel_dp_aux_regs.h" 47 #include "display/intel_dpio_phy.h" 48 #include "display/intel_fbc.h" 49 #include "display/intel_fdi_regs.h" 50 #include "display/intel_pps_regs.h" 51 #include "display/intel_psr_regs.h" 52 #include "display/skl_watermark_regs.h" 53 #include "display/vlv_dsi_pll_regs.h" 54 #include "gt/intel_gt_regs.h" 55 #include <linux/vmalloc.h> 56 57 /* XXX FIXME i915 has changed PP_XXX definition */ 58 #define PCH_PP_STATUS _MMIO(0xc7200) 59 #define PCH_PP_CONTROL _MMIO(0xc7204) 60 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 61 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 62 #define PCH_PP_DIVISOR _MMIO(0xc7210) 63 64 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 65 { 66 struct drm_i915_private *i915 = gvt->gt->i915; 67 68 if (IS_BROADWELL(i915)) 69 return D_BDW; 70 else if (IS_SKYLAKE(i915)) 71 return D_SKL; 72 else if (IS_KABYLAKE(i915)) 73 return D_KBL; 74 else if (IS_BROXTON(i915)) 75 return D_BXT; 76 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 77 return D_CFL; 78 79 return 0; 80 } 81 82 static bool intel_gvt_match_device(struct intel_gvt *gvt, 83 unsigned long device) 84 { 85 return intel_gvt_get_device_type(gvt) & device; 86 } 87 88 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 89 void *p_data, unsigned int bytes) 90 { 91 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 92 } 93 94 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 95 void *p_data, unsigned int bytes) 96 { 97 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 98 } 99 100 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 101 unsigned int offset) 102 { 103 struct intel_gvt_mmio_info *e; 104 105 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 106 if (e->offset == offset) 107 return e; 108 } 109 return NULL; 110 } 111 112 static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size, 113 u16 flags, u32 addr_mask, u32 ro_mask, u32 device, 114 gvt_mmio_func read, gvt_mmio_func write) 115 { 116 struct intel_gvt_mmio_info *p; 117 u32 start, end, i; 118 119 if (!intel_gvt_match_device(gvt, device)) 120 return 0; 121 122 if (WARN_ON(!IS_ALIGNED(offset, 4))) 123 return -EINVAL; 124 125 start = offset; 126 end = offset + size; 127 128 for (i = start; i < end; i += 4) { 129 p = intel_gvt_find_mmio_info(gvt, i); 130 if (!p) { 131 WARN(1, "assign a handler to a non-tracked mmio %x\n", 132 i); 133 return -ENODEV; 134 } 135 p->ro_mask = ro_mask; 136 gvt->mmio.mmio_attribute[i / 4] = flags; 137 if (read) 138 p->read = read; 139 if (write) 140 p->write = write; 141 } 142 return 0; 143 } 144 145 /** 146 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine 147 * @gvt: a GVT device 148 * @offset: register offset 149 * 150 * Returns: 151 * The engine containing the offset within its mmio page. 152 */ 153 const struct intel_engine_cs * 154 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset) 155 { 156 struct intel_engine_cs *engine; 157 enum intel_engine_id id; 158 159 offset &= ~GENMASK(11, 0); 160 for_each_engine(engine, gvt->gt, id) 161 if (engine->mmio_base == offset) 162 return engine; 163 164 return NULL; 165 } 166 167 #define offset_to_fence_num(offset) \ 168 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 169 170 #define fence_num_to_offset(num) \ 171 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 172 173 174 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 175 { 176 switch (reason) { 177 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 178 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 179 break; 180 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 181 pr_err("Graphics resource is not enough for the guest\n"); 182 break; 183 case GVT_FAILSAFE_GUEST_ERR: 184 pr_err("GVT Internal error for the guest\n"); 185 break; 186 default: 187 break; 188 } 189 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 190 vgpu->failsafe = true; 191 } 192 193 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 194 unsigned int fence_num, void *p_data, unsigned int bytes) 195 { 196 unsigned int max_fence = vgpu_fence_sz(vgpu); 197 198 if (fence_num >= max_fence) { 199 gvt_vgpu_err("access oob fence reg %d/%d\n", 200 fence_num, max_fence); 201 202 /* When guest access oob fence regs without access 203 * pv_info first, we treat guest not supporting GVT, 204 * and we will let vgpu enter failsafe mode. 205 */ 206 if (!vgpu->pv_notified) 207 enter_failsafe_mode(vgpu, 208 GVT_FAILSAFE_UNSUPPORTED_GUEST); 209 210 memset(p_data, 0, bytes); 211 return -EINVAL; 212 } 213 return 0; 214 } 215 216 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 217 unsigned int offset, void *p_data, unsigned int bytes) 218 { 219 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; 220 221 if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) { 222 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) 223 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); 224 else if (!ips) 225 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); 226 else { 227 /* All engines must be enabled together for vGPU, 228 * since we don't know which engine the ppgtt will 229 * bind to when shadowing. 230 */ 231 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", 232 ips); 233 return -EINVAL; 234 } 235 } 236 237 write_vreg(vgpu, offset, p_data, bytes); 238 return 0; 239 } 240 241 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 242 void *p_data, unsigned int bytes) 243 { 244 int ret; 245 246 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 247 p_data, bytes); 248 if (ret) 249 return ret; 250 read_vreg(vgpu, off, p_data, bytes); 251 return 0; 252 } 253 254 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 255 void *p_data, unsigned int bytes) 256 { 257 struct intel_gvt *gvt = vgpu->gvt; 258 unsigned int fence_num = offset_to_fence_num(off); 259 int ret; 260 261 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 262 if (ret) 263 return ret; 264 write_vreg(vgpu, off, p_data, bytes); 265 266 mmio_hw_access_pre(gvt->gt); 267 intel_vgpu_write_fence(vgpu, fence_num, 268 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 269 mmio_hw_access_post(gvt->gt); 270 return 0; 271 } 272 273 #define CALC_MODE_MASK_REG(old, new) \ 274 (((new) & GENMASK(31, 16)) \ 275 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 276 | ((new) & ((new) >> 16)))) 277 278 static int mul_force_wake_write(struct intel_vgpu *vgpu, 279 unsigned int offset, void *p_data, unsigned int bytes) 280 { 281 u32 old, new; 282 u32 ack_reg_offset; 283 284 old = vgpu_vreg(vgpu, offset); 285 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 286 287 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) { 288 switch (offset) { 289 case FORCEWAKE_RENDER_GEN9_REG: 290 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 291 break; 292 case FORCEWAKE_GT_GEN9_REG: 293 ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG; 294 break; 295 case FORCEWAKE_MEDIA_GEN9_REG: 296 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 297 break; 298 default: 299 /*should not hit here*/ 300 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 301 return -EINVAL; 302 } 303 } else { 304 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 305 } 306 307 vgpu_vreg(vgpu, offset) = new; 308 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 309 return 0; 310 } 311 312 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 313 void *p_data, unsigned int bytes) 314 { 315 intel_engine_mask_t engine_mask = 0; 316 u32 data; 317 318 write_vreg(vgpu, offset, p_data, bytes); 319 data = vgpu_vreg(vgpu, offset); 320 321 if (data & GEN6_GRDOM_FULL) { 322 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 323 engine_mask = ALL_ENGINES; 324 } else { 325 if (data & GEN6_GRDOM_RENDER) { 326 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 327 engine_mask |= BIT(RCS0); 328 } 329 if (data & GEN6_GRDOM_MEDIA) { 330 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 331 engine_mask |= BIT(VCS0); 332 } 333 if (data & GEN6_GRDOM_BLT) { 334 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 335 engine_mask |= BIT(BCS0); 336 } 337 if (data & GEN6_GRDOM_VECS) { 338 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 339 engine_mask |= BIT(VECS0); 340 } 341 if (data & GEN8_GRDOM_MEDIA2) { 342 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 343 engine_mask |= BIT(VCS1); 344 } 345 if (data & GEN9_GRDOM_GUC) { 346 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); 347 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; 348 } 349 engine_mask &= vgpu->gvt->gt->info.engine_mask; 350 } 351 352 /* vgpu_lock already hold by emulate mmio r/w */ 353 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 354 355 /* sw will wait for the device to ack the reset request */ 356 vgpu_vreg(vgpu, offset) = 0; 357 358 return 0; 359 } 360 361 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 362 void *p_data, unsigned int bytes) 363 { 364 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 365 } 366 367 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 368 void *p_data, unsigned int bytes) 369 { 370 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 371 } 372 373 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 374 unsigned int offset, void *p_data, unsigned int bytes) 375 { 376 write_vreg(vgpu, offset, p_data, bytes); 377 378 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 379 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 380 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 381 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 382 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 383 384 } else 385 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 386 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 387 | PP_CYCLE_DELAY_ACTIVE); 388 return 0; 389 } 390 391 static int transconf_mmio_write(struct intel_vgpu *vgpu, 392 unsigned int offset, void *p_data, unsigned int bytes) 393 { 394 write_vreg(vgpu, offset, p_data, bytes); 395 396 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 397 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 398 else 399 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 400 return 0; 401 } 402 403 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 404 void *p_data, unsigned int bytes) 405 { 406 write_vreg(vgpu, offset, p_data, bytes); 407 408 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 409 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 410 else 411 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 412 413 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 414 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 415 else 416 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 417 418 return 0; 419 } 420 421 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 422 void *p_data, unsigned int bytes) 423 { 424 switch (offset) { 425 case 0xe651c: 426 case 0xe661c: 427 case 0xe671c: 428 case 0xe681c: 429 vgpu_vreg(vgpu, offset) = 1 << 17; 430 break; 431 case 0xe6c04: 432 vgpu_vreg(vgpu, offset) = 0x3; 433 break; 434 case 0xe6e1c: 435 vgpu_vreg(vgpu, offset) = 0x2f << 16; 436 break; 437 default: 438 return -EINVAL; 439 } 440 441 read_vreg(vgpu, offset, p_data, bytes); 442 return 0; 443 } 444 445 /* 446 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to 447 * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on 448 * setup_virtual_dp_monitor(). 449 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled 450 * DPLL. Later guest driver may setup a different DPLLx when setting mode. 451 * So the correct sequence to find DP stream clock is: 452 * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x. 453 * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate. 454 * Then Refresh rate then can be calculated based on follow equations: 455 * Pixel clock = h_total * v_total * refresh_rate 456 * stream clock = Pixel clock 457 * ls_clk = DP bitrate 458 * Link M/N = strm_clk / ls_clk 459 */ 460 461 static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 462 { 463 u32 dp_br = 0; 464 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); 465 466 switch (ddi_pll_sel) { 467 case PORT_CLK_SEL_LCPLL_2700: 468 dp_br = 270000 * 2; 469 break; 470 case PORT_CLK_SEL_LCPLL_1350: 471 dp_br = 135000 * 2; 472 break; 473 case PORT_CLK_SEL_LCPLL_810: 474 dp_br = 81000 * 2; 475 break; 476 case PORT_CLK_SEL_SPLL: 477 { 478 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { 479 case SPLL_FREQ_810MHz: 480 dp_br = 81000 * 2; 481 break; 482 case SPLL_FREQ_1350MHz: 483 dp_br = 135000 * 2; 484 break; 485 case SPLL_FREQ_2700MHz: 486 dp_br = 270000 * 2; 487 break; 488 default: 489 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n", 490 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); 491 break; 492 } 493 break; 494 } 495 case PORT_CLK_SEL_WRPLL1: 496 case PORT_CLK_SEL_WRPLL2: 497 { 498 u32 wrpll_ctl; 499 int refclk, n, p, r; 500 501 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1) 502 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); 503 else 504 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2)); 505 506 switch (wrpll_ctl & WRPLL_REF_MASK) { 507 case WRPLL_REF_PCH_SSC: 508 refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc; 509 break; 510 case WRPLL_REF_LCPLL: 511 refclk = 2700000; 512 break; 513 default: 514 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n", 515 vgpu->id, port_name(port), wrpll_ctl); 516 goto out; 517 } 518 519 r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK; 520 p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 521 n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 522 523 dp_br = (refclk * n / 10) / (p * r) * 2; 524 break; 525 } 526 default: 527 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", 528 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port))); 529 break; 530 } 531 532 out: 533 return dp_br; 534 } 535 536 static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 537 { 538 u32 dp_br = 0; 539 int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc; 540 enum dpio_phy phy = DPIO_PHY0; 541 enum dpio_channel ch = DPIO_CH0; 542 struct dpll clock = {}; 543 u32 temp; 544 545 /* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */ 546 switch (port) { 547 case PORT_A: 548 phy = DPIO_PHY1; 549 ch = DPIO_CH0; 550 break; 551 case PORT_B: 552 phy = DPIO_PHY0; 553 ch = DPIO_CH0; 554 break; 555 case PORT_C: 556 phy = DPIO_PHY0; 557 ch = DPIO_CH1; 558 break; 559 default: 560 gvt_dbg_dpy("vgpu-%d no PHY for PORT_%c\n", vgpu->id, port_name(port)); 561 goto out; 562 } 563 564 temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)); 565 if (!(temp & PORT_PLL_ENABLE) || !(temp & PORT_PLL_LOCK)) { 566 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n", 567 vgpu->id, port_name(port), temp); 568 goto out; 569 } 570 571 clock.m1 = 2; 572 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, 573 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22; 574 if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE) 575 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, 576 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2))); 577 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, 578 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1))); 579 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, 580 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); 581 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, 582 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); 583 clock.m = clock.m1 * clock.m2; 584 clock.p = clock.p1 * clock.p2 * 5; 585 586 if (clock.n == 0 || clock.p == 0) { 587 gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port)); 588 goto out; 589 } 590 591 clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22); 592 clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p); 593 594 dp_br = clock.dot; 595 596 out: 597 return dp_br; 598 } 599 600 static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 601 { 602 u32 dp_br = 0; 603 enum intel_dpll_id dpll_id = DPLL_ID_SKL_DPLL0; 604 605 /* Find the enabled DPLL for the DDI/PORT */ 606 if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) && 607 (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) { 608 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) & 609 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 610 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 611 } else { 612 gvt_dbg_dpy("vgpu-%d DPLL for PORT_%c isn't turned on\n", 613 vgpu->id, port_name(port)); 614 return dp_br; 615 } 616 617 /* Find PLL output frequency from correct DPLL, and get bir rate */ 618 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) & 619 DPLL_CTRL1_LINK_RATE_MASK(dpll_id)) >> 620 DPLL_CTRL1_LINK_RATE_SHIFT(dpll_id)) { 621 case DPLL_CTRL1_LINK_RATE_810: 622 dp_br = 81000 * 2; 623 break; 624 case DPLL_CTRL1_LINK_RATE_1080: 625 dp_br = 108000 * 2; 626 break; 627 case DPLL_CTRL1_LINK_RATE_1350: 628 dp_br = 135000 * 2; 629 break; 630 case DPLL_CTRL1_LINK_RATE_1620: 631 dp_br = 162000 * 2; 632 break; 633 case DPLL_CTRL1_LINK_RATE_2160: 634 dp_br = 216000 * 2; 635 break; 636 case DPLL_CTRL1_LINK_RATE_2700: 637 dp_br = 270000 * 2; 638 break; 639 default: 640 dp_br = 0; 641 gvt_dbg_dpy("vgpu-%d PORT_%c fail to get DPLL-%d freq\n", 642 vgpu->id, port_name(port), dpll_id); 643 } 644 645 return dp_br; 646 } 647 648 static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) 649 { 650 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 651 enum port port; 652 u32 dp_br, link_m, link_n, htotal, vtotal; 653 654 /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */ 655 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) & 656 TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 657 if (port != PORT_B && port != PORT_D) { 658 gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port)); 659 return; 660 } 661 662 /* Calculate DP bitrate from PLL */ 663 if (IS_BROADWELL(dev_priv)) 664 dp_br = bdw_vgpu_get_dp_bitrate(vgpu, port); 665 else if (IS_BROXTON(dev_priv)) 666 dp_br = bxt_vgpu_get_dp_bitrate(vgpu, port); 667 else 668 dp_br = skl_vgpu_get_dp_bitrate(vgpu, port); 669 670 /* Get DP link symbol clock M/N */ 671 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)); 672 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)); 673 674 /* Get H/V total from transcoder timing */ 675 htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); 676 vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); 677 678 if (dp_br && link_n && htotal && vtotal) { 679 u64 pixel_clk = 0; 680 u32 new_rate = 0; 681 u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k); 682 683 /* Calcuate pixel clock by (ls_clk * M / N) */ 684 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); 685 pixel_clk *= MSEC_PER_SEC; 686 687 /* Calcuate refresh rate by (pixel_clk / (h_total * v_total)) */ 688 new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1)); 689 690 if (*old_rate != new_rate) 691 *old_rate = new_rate; 692 693 gvt_dbg_dpy("vgpu-%d PIPE_%c refresh rate updated to %d\n", 694 vgpu->id, pipe_name(PIPE_A), new_rate); 695 } 696 } 697 698 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 699 void *p_data, unsigned int bytes) 700 { 701 u32 data; 702 703 write_vreg(vgpu, offset, p_data, bytes); 704 data = vgpu_vreg(vgpu, offset); 705 706 if (data & TRANSCONF_ENABLE) { 707 vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE; 708 vgpu_update_refresh_rate(vgpu); 709 vgpu_update_vblank_emulation(vgpu, true); 710 } else { 711 vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE; 712 vgpu_update_vblank_emulation(vgpu, false); 713 } 714 return 0; 715 } 716 717 /* sorted in ascending order */ 718 static i915_reg_t force_nonpriv_white_list[] = { 719 _MMIO(0xd80), 720 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 721 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 722 CL_PRIMITIVES_COUNT, //_MMIO(0x2340) 723 PS_INVOCATION_COUNT, //_MMIO(0x2348) 724 PS_DEPTH_COUNT, //_MMIO(0x2350) 725 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 726 _MMIO(0x2690), 727 _MMIO(0x2694), 728 _MMIO(0x2698), 729 _MMIO(0x2754), 730 _MMIO(0x28a0), 731 _MMIO(0x4de0), 732 _MMIO(0x4de4), 733 _MMIO(0x4dfc), 734 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 735 _MMIO(0x7014), 736 HDC_CHICKEN0,//_MMIO(0x7300) 737 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 738 _MMIO(0x7700), 739 _MMIO(0x7704), 740 _MMIO(0x7708), 741 _MMIO(0x770c), 742 _MMIO(0x83a8), 743 _MMIO(0xb110), 744 _MMIO(0xb118), 745 _MMIO(0xe100), 746 _MMIO(0xe18c), 747 _MMIO(0xe48c), 748 _MMIO(0xe5f4), 749 _MMIO(0x64844), 750 }; 751 752 /* a simple bsearch */ 753 static inline bool in_whitelist(u32 reg) 754 { 755 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 756 i915_reg_t *array = force_nonpriv_white_list; 757 758 while (left < right) { 759 int mid = (left + right)/2; 760 761 if (reg > array[mid].reg) 762 left = mid + 1; 763 else if (reg < array[mid].reg) 764 right = mid; 765 else 766 return true; 767 } 768 return false; 769 } 770 771 static int force_nonpriv_write(struct intel_vgpu *vgpu, 772 unsigned int offset, void *p_data, unsigned int bytes) 773 { 774 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2); 775 const struct intel_engine_cs *engine = 776 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 777 778 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) { 779 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 780 vgpu->id, offset, bytes); 781 return -EINVAL; 782 } 783 784 if (!in_whitelist(reg_nonpriv) && 785 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) { 786 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 787 vgpu->id, reg_nonpriv, offset); 788 } else 789 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 790 791 return 0; 792 } 793 794 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 795 void *p_data, unsigned int bytes) 796 { 797 write_vreg(vgpu, offset, p_data, bytes); 798 799 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 800 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 801 } else { 802 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 803 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 804 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 805 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 806 } 807 return 0; 808 } 809 810 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 811 unsigned int offset, void *p_data, unsigned int bytes) 812 { 813 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 814 return 0; 815 } 816 817 #define FDI_LINK_TRAIN_PATTERN1 0 818 #define FDI_LINK_TRAIN_PATTERN2 1 819 820 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 821 { 822 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 823 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 824 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 825 826 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 827 (rx_ctl & FDI_RX_ENABLE) && 828 (rx_ctl & FDI_AUTO_TRAINING) && 829 (tx_ctl & DP_TP_CTL_ENABLE) && 830 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 831 return 1; 832 else 833 return 0; 834 } 835 836 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 837 enum pipe pipe, unsigned int train_pattern) 838 { 839 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 840 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 841 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 842 unsigned int fdi_iir_check_bits; 843 844 fdi_rx_imr = FDI_RX_IMR(pipe); 845 fdi_tx_ctl = FDI_TX_CTL(pipe); 846 fdi_rx_ctl = FDI_RX_CTL(pipe); 847 848 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 849 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 850 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 851 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 852 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 853 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 854 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 855 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 856 } else { 857 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 858 return -EINVAL; 859 } 860 861 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 862 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 863 864 /* If imr bit has been masked */ 865 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 866 return 0; 867 868 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 869 == fdi_tx_check_bits) 870 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 871 == fdi_rx_check_bits)) 872 return 1; 873 else 874 return 0; 875 } 876 877 #define INVALID_INDEX (~0U) 878 879 static unsigned int calc_index(unsigned int offset, unsigned int start, 880 unsigned int next, unsigned int end, i915_reg_t i915_end) 881 { 882 unsigned int range = next - start; 883 884 if (!end) 885 end = i915_mmio_reg_offset(i915_end); 886 if (offset < start || offset > end) 887 return INVALID_INDEX; 888 offset -= start; 889 return offset / range; 890 } 891 892 #define FDI_RX_CTL_TO_PIPE(offset) \ 893 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 894 895 #define FDI_TX_CTL_TO_PIPE(offset) \ 896 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 897 898 #define FDI_RX_IMR_TO_PIPE(offset) \ 899 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 900 901 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 902 unsigned int offset, void *p_data, unsigned int bytes) 903 { 904 i915_reg_t fdi_rx_iir; 905 unsigned int index; 906 int ret; 907 908 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 909 index = FDI_RX_CTL_TO_PIPE(offset); 910 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 911 index = FDI_TX_CTL_TO_PIPE(offset); 912 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 913 index = FDI_RX_IMR_TO_PIPE(offset); 914 else { 915 gvt_vgpu_err("Unsupported registers %x\n", offset); 916 return -EINVAL; 917 } 918 919 write_vreg(vgpu, offset, p_data, bytes); 920 921 fdi_rx_iir = FDI_RX_IIR(index); 922 923 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 924 if (ret < 0) 925 return ret; 926 if (ret) 927 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 928 929 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 930 if (ret < 0) 931 return ret; 932 if (ret) 933 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 934 935 if (offset == _FDI_RXA_CTL) 936 if (fdi_auto_training_started(vgpu)) 937 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 938 DP_TP_STATUS_AUTOTRAIN_DONE; 939 return 0; 940 } 941 942 #define DP_TP_CTL_TO_PORT(offset) \ 943 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 944 945 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 946 void *p_data, unsigned int bytes) 947 { 948 i915_reg_t status_reg; 949 unsigned int index; 950 u32 data; 951 952 write_vreg(vgpu, offset, p_data, bytes); 953 954 index = DP_TP_CTL_TO_PORT(offset); 955 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 956 if (data == 0x2) { 957 status_reg = DP_TP_STATUS(index); 958 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 959 } 960 return 0; 961 } 962 963 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 964 unsigned int offset, void *p_data, unsigned int bytes) 965 { 966 u32 reg_val; 967 u32 sticky_mask; 968 969 reg_val = *((u32 *)p_data); 970 sticky_mask = GENMASK(27, 26) | (1 << 24); 971 972 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 973 (vgpu_vreg(vgpu, offset) & sticky_mask); 974 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 975 return 0; 976 } 977 978 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 979 unsigned int offset, void *p_data, unsigned int bytes) 980 { 981 u32 data; 982 983 write_vreg(vgpu, offset, p_data, bytes); 984 data = vgpu_vreg(vgpu, offset); 985 986 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 987 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 988 return 0; 989 } 990 991 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 992 unsigned int offset, void *p_data, unsigned int bytes) 993 { 994 u32 data; 995 996 write_vreg(vgpu, offset, p_data, bytes); 997 data = vgpu_vreg(vgpu, offset); 998 999 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 1000 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 1001 else 1002 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 1003 return 0; 1004 } 1005 1006 #define DSPSURF_TO_PIPE(offset) \ 1007 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 1008 1009 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1010 void *p_data, unsigned int bytes) 1011 { 1012 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1013 u32 pipe = DSPSURF_TO_PIPE(offset); 1014 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); 1015 1016 write_vreg(vgpu, offset, p_data, bytes); 1017 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1018 1019 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 1020 1021 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) 1022 intel_vgpu_trigger_virtual_event(vgpu, event); 1023 else 1024 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1025 1026 return 0; 1027 } 1028 1029 #define SPRSURF_TO_PIPE(offset) \ 1030 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 1031 1032 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1033 void *p_data, unsigned int bytes) 1034 { 1035 u32 pipe = SPRSURF_TO_PIPE(offset); 1036 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0); 1037 1038 write_vreg(vgpu, offset, p_data, bytes); 1039 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1040 1041 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) 1042 intel_vgpu_trigger_virtual_event(vgpu, event); 1043 else 1044 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1045 1046 return 0; 1047 } 1048 1049 static int reg50080_mmio_write(struct intel_vgpu *vgpu, 1050 unsigned int offset, void *p_data, 1051 unsigned int bytes) 1052 { 1053 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1054 enum pipe pipe = REG_50080_TO_PIPE(offset); 1055 enum plane_id plane = REG_50080_TO_PLANE(offset); 1056 int event = SKL_FLIP_EVENT(pipe, plane); 1057 1058 write_vreg(vgpu, offset, p_data, bytes); 1059 if (plane == PLANE_PRIMARY) { 1060 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1061 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 1062 } else { 1063 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1064 } 1065 1066 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) 1067 intel_vgpu_trigger_virtual_event(vgpu, event); 1068 else 1069 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1070 1071 return 0; 1072 } 1073 1074 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 1075 unsigned int reg) 1076 { 1077 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1078 enum intel_gvt_event_type event; 1079 1080 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) 1081 event = AUX_CHANNEL_A; 1082 else if (reg == _PCH_DPB_AUX_CH_CTL || 1083 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) 1084 event = AUX_CHANNEL_B; 1085 else if (reg == _PCH_DPC_AUX_CH_CTL || 1086 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) 1087 event = AUX_CHANNEL_C; 1088 else if (reg == _PCH_DPD_AUX_CH_CTL || 1089 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) 1090 event = AUX_CHANNEL_D; 1091 else { 1092 drm_WARN_ON(&dev_priv->drm, true); 1093 return -EINVAL; 1094 } 1095 1096 intel_vgpu_trigger_virtual_event(vgpu, event); 1097 return 0; 1098 } 1099 1100 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 1101 unsigned int reg, int len, bool data_valid) 1102 { 1103 /* mark transaction done */ 1104 value |= DP_AUX_CH_CTL_DONE; 1105 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 1106 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 1107 1108 if (data_valid) 1109 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 1110 else 1111 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 1112 1113 /* message size */ 1114 value &= ~(0xf << 20); 1115 value |= (len << 20); 1116 vgpu_vreg(vgpu, reg) = value; 1117 1118 if (value & DP_AUX_CH_CTL_INTERRUPT) 1119 return trigger_aux_channel_interrupt(vgpu, reg); 1120 return 0; 1121 } 1122 1123 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 1124 u8 t) 1125 { 1126 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 1127 /* training pattern 1 for CR */ 1128 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 1129 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 1130 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 1131 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 1132 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 1133 DPCD_TRAINING_PATTERN_2) { 1134 /* training pattern 2 for EQ */ 1135 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 1136 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 1137 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 1138 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 1139 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 1140 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 1141 /* set INTERLANE_ALIGN_DONE */ 1142 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 1143 DPCD_INTERLANE_ALIGN_DONE; 1144 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 1145 DPCD_LINK_TRAINING_DISABLED) { 1146 /* finish link training */ 1147 /* set sink status as synchronized */ 1148 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 1149 } 1150 } 1151 1152 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 1153 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 1154 1155 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 1156 1157 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 1158 1159 #define dpy_is_valid_port(port) \ 1160 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 1161 1162 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 1163 unsigned int offset, void *p_data, unsigned int bytes) 1164 { 1165 struct intel_vgpu_display *display = &vgpu->display; 1166 int msg, addr, ctrl, op, len; 1167 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 1168 struct intel_vgpu_dpcd_data *dpcd = NULL; 1169 struct intel_vgpu_port *port = NULL; 1170 u32 data; 1171 1172 if (!dpy_is_valid_port(port_index)) { 1173 gvt_vgpu_err("Unsupported DP port access!\n"); 1174 return 0; 1175 } 1176 1177 write_vreg(vgpu, offset, p_data, bytes); 1178 data = vgpu_vreg(vgpu, offset); 1179 1180 if ((GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) 1181 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 1182 /* SKL DPB/C/D aux ctl register changed */ 1183 return 0; 1184 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) && 1185 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 1186 /* write to the data registers */ 1187 return 0; 1188 } 1189 1190 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 1191 /* just want to clear the sticky bits */ 1192 vgpu_vreg(vgpu, offset) = 0; 1193 return 0; 1194 } 1195 1196 port = &display->ports[port_index]; 1197 dpcd = port->dpcd; 1198 1199 /* read out message from DATA1 register */ 1200 msg = vgpu_vreg(vgpu, offset + 4); 1201 addr = (msg >> 8) & 0xffff; 1202 ctrl = (msg >> 24) & 0xff; 1203 len = msg & 0xff; 1204 op = ctrl >> 4; 1205 1206 if (op == GVT_AUX_NATIVE_WRITE) { 1207 int t; 1208 u8 buf[16]; 1209 1210 if ((addr + len + 1) >= DPCD_SIZE) { 1211 /* 1212 * Write request exceeds what we supported, 1213 * DCPD spec: When a Source Device is writing a DPCD 1214 * address not supported by the Sink Device, the Sink 1215 * Device shall reply with AUX NACK and “M” equal to 1216 * zero. 1217 */ 1218 1219 /* NAK the write */ 1220 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 1221 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 1222 return 0; 1223 } 1224 1225 /* 1226 * Write request format: Headr (command + address + size) occupies 1227 * 4 bytes, followed by (len + 1) bytes of data. See details at 1228 * intel_dp_aux_transfer(). 1229 */ 1230 if ((len + 1 + 4) > AUX_BURST_SIZE) { 1231 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1232 return -EINVAL; 1233 } 1234 1235 /* unpack data from vreg to buf */ 1236 for (t = 0; t < 4; t++) { 1237 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 1238 1239 buf[t * 4] = (r >> 24) & 0xff; 1240 buf[t * 4 + 1] = (r >> 16) & 0xff; 1241 buf[t * 4 + 2] = (r >> 8) & 0xff; 1242 buf[t * 4 + 3] = r & 0xff; 1243 } 1244 1245 /* write to virtual DPCD */ 1246 if (dpcd && dpcd->data_valid) { 1247 for (t = 0; t <= len; t++) { 1248 int p = addr + t; 1249 1250 dpcd->data[p] = buf[t]; 1251 /* check for link training */ 1252 if (p == DPCD_TRAINING_PATTERN_SET) 1253 dp_aux_ch_ctl_link_training(dpcd, 1254 buf[t]); 1255 } 1256 } 1257 1258 /* ACK the write */ 1259 vgpu_vreg(vgpu, offset + 4) = 0; 1260 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 1261 dpcd && dpcd->data_valid); 1262 return 0; 1263 } 1264 1265 if (op == GVT_AUX_NATIVE_READ) { 1266 int idx, i, ret = 0; 1267 1268 if ((addr + len + 1) >= DPCD_SIZE) { 1269 /* 1270 * read request exceeds what we supported 1271 * DPCD spec: A Sink Device receiving a Native AUX CH 1272 * read request for an unsupported DPCD address must 1273 * reply with an AUX ACK and read data set equal to 1274 * zero instead of replying with AUX NACK. 1275 */ 1276 1277 /* ACK the READ*/ 1278 vgpu_vreg(vgpu, offset + 4) = 0; 1279 vgpu_vreg(vgpu, offset + 8) = 0; 1280 vgpu_vreg(vgpu, offset + 12) = 0; 1281 vgpu_vreg(vgpu, offset + 16) = 0; 1282 vgpu_vreg(vgpu, offset + 20) = 0; 1283 1284 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1285 true); 1286 return 0; 1287 } 1288 1289 for (idx = 1; idx <= 5; idx++) { 1290 /* clear the data registers */ 1291 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 1292 } 1293 1294 /* 1295 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1296 */ 1297 if ((len + 2) > AUX_BURST_SIZE) { 1298 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1299 return -EINVAL; 1300 } 1301 1302 /* read from virtual DPCD to vreg */ 1303 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1304 if (dpcd && dpcd->data_valid) { 1305 for (i = 1; i <= (len + 1); i++) { 1306 int t; 1307 1308 t = dpcd->data[addr + i - 1]; 1309 t <<= (24 - 8 * (i % 4)); 1310 ret |= t; 1311 1312 if ((i % 4 == 3) || (i == (len + 1))) { 1313 vgpu_vreg(vgpu, offset + 1314 (i / 4 + 1) * 4) = ret; 1315 ret = 0; 1316 } 1317 } 1318 } 1319 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1320 dpcd && dpcd->data_valid); 1321 return 0; 1322 } 1323 1324 /* i2c transaction starts */ 1325 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1326 1327 if (data & DP_AUX_CH_CTL_INTERRUPT) 1328 trigger_aux_channel_interrupt(vgpu, offset); 1329 return 0; 1330 } 1331 1332 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1333 void *p_data, unsigned int bytes) 1334 { 1335 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1336 write_vreg(vgpu, offset, p_data, bytes); 1337 return 0; 1338 } 1339 1340 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1341 void *p_data, unsigned int bytes) 1342 { 1343 bool vga_disable; 1344 1345 write_vreg(vgpu, offset, p_data, bytes); 1346 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1347 1348 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1349 vga_disable ? "Disable" : "Enable"); 1350 return 0; 1351 } 1352 1353 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1354 unsigned int sbi_offset) 1355 { 1356 struct intel_vgpu_display *display = &vgpu->display; 1357 int num = display->sbi.number; 1358 int i; 1359 1360 for (i = 0; i < num; ++i) 1361 if (display->sbi.registers[i].offset == sbi_offset) 1362 break; 1363 1364 if (i == num) 1365 return 0; 1366 1367 return display->sbi.registers[i].value; 1368 } 1369 1370 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1371 unsigned int offset, u32 value) 1372 { 1373 struct intel_vgpu_display *display = &vgpu->display; 1374 int num = display->sbi.number; 1375 int i; 1376 1377 for (i = 0; i < num; ++i) { 1378 if (display->sbi.registers[i].offset == offset) 1379 break; 1380 } 1381 1382 if (i == num) { 1383 if (num == SBI_REG_MAX) { 1384 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1385 return; 1386 } 1387 display->sbi.number++; 1388 } 1389 1390 display->sbi.registers[i].offset = offset; 1391 display->sbi.registers[i].value = value; 1392 } 1393 1394 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1395 void *p_data, unsigned int bytes) 1396 { 1397 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1398 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1399 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1400 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1401 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1402 sbi_offset); 1403 } 1404 read_vreg(vgpu, offset, p_data, bytes); 1405 return 0; 1406 } 1407 1408 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1409 void *p_data, unsigned int bytes) 1410 { 1411 u32 data; 1412 1413 write_vreg(vgpu, offset, p_data, bytes); 1414 data = vgpu_vreg(vgpu, offset); 1415 1416 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1417 data |= SBI_READY; 1418 1419 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1420 data |= SBI_RESPONSE_SUCCESS; 1421 1422 vgpu_vreg(vgpu, offset) = data; 1423 1424 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1425 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1426 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1427 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1428 1429 write_virtual_sbi_register(vgpu, sbi_offset, 1430 vgpu_vreg_t(vgpu, SBI_DATA)); 1431 } 1432 return 0; 1433 } 1434 1435 #define _vgtif_reg(x) \ 1436 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1437 1438 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1439 void *p_data, unsigned int bytes) 1440 { 1441 bool invalid_read = false; 1442 1443 read_vreg(vgpu, offset, p_data, bytes); 1444 1445 switch (offset) { 1446 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1447 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1448 invalid_read = true; 1449 break; 1450 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1451 _vgtif_reg(avail_rs.fence_num): 1452 if (offset + bytes > 1453 _vgtif_reg(avail_rs.fence_num) + 4) 1454 invalid_read = true; 1455 break; 1456 case 0x78010: /* vgt_caps */ 1457 case 0x7881c: 1458 break; 1459 default: 1460 invalid_read = true; 1461 break; 1462 } 1463 if (invalid_read) 1464 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1465 offset, bytes, *(u32 *)p_data); 1466 vgpu->pv_notified = true; 1467 return 0; 1468 } 1469 1470 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1471 { 1472 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1473 struct intel_vgpu_mm *mm; 1474 u64 *pdps; 1475 1476 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1477 1478 switch (notification) { 1479 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1480 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1481 fallthrough; 1482 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1483 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1484 return PTR_ERR_OR_ZERO(mm); 1485 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1486 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1487 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1488 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1489 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1490 case 1: /* Remove this in guest driver. */ 1491 break; 1492 default: 1493 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1494 } 1495 return 0; 1496 } 1497 1498 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1499 { 1500 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj; 1501 char *env[3] = {NULL, NULL, NULL}; 1502 char vmid_str[20]; 1503 char display_ready_str[20]; 1504 1505 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1506 env[0] = display_ready_str; 1507 1508 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1509 env[1] = vmid_str; 1510 1511 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1512 } 1513 1514 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1515 void *p_data, unsigned int bytes) 1516 { 1517 u32 data = *(u32 *)p_data; 1518 bool invalid_write = false; 1519 1520 switch (offset) { 1521 case _vgtif_reg(display_ready): 1522 send_display_ready_uevent(vgpu, data ? 1 : 0); 1523 break; 1524 case _vgtif_reg(g2v_notify): 1525 handle_g2v_notification(vgpu, data); 1526 break; 1527 /* add xhot and yhot to handled list to avoid error log */ 1528 case _vgtif_reg(cursor_x_hot): 1529 case _vgtif_reg(cursor_y_hot): 1530 case _vgtif_reg(pdp[0].lo): 1531 case _vgtif_reg(pdp[0].hi): 1532 case _vgtif_reg(pdp[1].lo): 1533 case _vgtif_reg(pdp[1].hi): 1534 case _vgtif_reg(pdp[2].lo): 1535 case _vgtif_reg(pdp[2].hi): 1536 case _vgtif_reg(pdp[3].lo): 1537 case _vgtif_reg(pdp[3].hi): 1538 case _vgtif_reg(execlist_context_descriptor_lo): 1539 case _vgtif_reg(execlist_context_descriptor_hi): 1540 break; 1541 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1542 invalid_write = true; 1543 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1544 break; 1545 default: 1546 invalid_write = true; 1547 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1548 offset, bytes, data); 1549 break; 1550 } 1551 1552 if (!invalid_write) 1553 write_vreg(vgpu, offset, p_data, bytes); 1554 1555 return 0; 1556 } 1557 1558 static int pf_write(struct intel_vgpu *vgpu, 1559 unsigned int offset, void *p_data, unsigned int bytes) 1560 { 1561 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1562 u32 val = *(u32 *)p_data; 1563 1564 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1565 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1566 offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) { 1567 drm_WARN_ONCE(&i915->drm, true, 1568 "VM(%d): guest is trying to scaling a plane\n", 1569 vgpu->id); 1570 return 0; 1571 } 1572 1573 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1574 } 1575 1576 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1577 unsigned int offset, void *p_data, unsigned int bytes) 1578 { 1579 write_vreg(vgpu, offset, p_data, bytes); 1580 1581 if (vgpu_vreg(vgpu, offset) & 1582 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL)) 1583 vgpu_vreg(vgpu, offset) |= 1584 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1585 else 1586 vgpu_vreg(vgpu, offset) &= 1587 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1588 return 0; 1589 } 1590 1591 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1592 unsigned int offset, void *p_data, unsigned int bytes) 1593 { 1594 write_vreg(vgpu, offset, p_data, bytes); 1595 1596 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1597 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1598 else 1599 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1600 1601 return 0; 1602 } 1603 1604 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1605 unsigned int offset, void *p_data, unsigned int bytes) 1606 { 1607 write_vreg(vgpu, offset, p_data, bytes); 1608 1609 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1610 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1611 return 0; 1612 } 1613 1614 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1615 void *p_data, unsigned int bytes) 1616 { 1617 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1618 u32 mode; 1619 1620 write_vreg(vgpu, offset, p_data, bytes); 1621 mode = vgpu_vreg(vgpu, offset); 1622 1623 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1624 drm_WARN_ONCE(&i915->drm, 1, 1625 "VM(%d): iGVT-g doesn't support GuC\n", 1626 vgpu->id); 1627 return 0; 1628 } 1629 1630 return 0; 1631 } 1632 1633 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1634 void *p_data, unsigned int bytes) 1635 { 1636 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1637 u32 trtte = *(u32 *)p_data; 1638 1639 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1640 drm_WARN(&i915->drm, 1, 1641 "VM(%d): Use physical address for TRTT!\n", 1642 vgpu->id); 1643 return -EINVAL; 1644 } 1645 write_vreg(vgpu, offset, p_data, bytes); 1646 1647 return 0; 1648 } 1649 1650 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1651 void *p_data, unsigned int bytes) 1652 { 1653 write_vreg(vgpu, offset, p_data, bytes); 1654 return 0; 1655 } 1656 1657 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1658 void *p_data, unsigned int bytes) 1659 { 1660 u32 v = 0; 1661 1662 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1663 v |= (1 << 0); 1664 1665 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1666 v |= (1 << 8); 1667 1668 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1669 v |= (1 << 16); 1670 1671 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1672 v |= (1 << 24); 1673 1674 vgpu_vreg(vgpu, offset) = v; 1675 1676 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1677 } 1678 1679 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1680 void *p_data, unsigned int bytes) 1681 { 1682 u32 value = *(u32 *)p_data; 1683 u32 cmd = value & 0xff; 1684 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1685 1686 switch (cmd) { 1687 case GEN9_PCODE_READ_MEM_LATENCY: 1688 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1689 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1690 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1691 IS_COMETLAKE(vgpu->gvt->gt->i915)) { 1692 /** 1693 * "Read memory latency" command on gen9. 1694 * Below memory latency values are read 1695 * from skylake platform. 1696 */ 1697 if (!*data0) 1698 *data0 = 0x1e1a1100; 1699 else 1700 *data0 = 0x61514b3d; 1701 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) { 1702 /** 1703 * "Read memory latency" command on gen9. 1704 * Below memory latency values are read 1705 * from Broxton MRB. 1706 */ 1707 if (!*data0) 1708 *data0 = 0x16080707; 1709 else 1710 *data0 = 0x16161616; 1711 } 1712 break; 1713 case SKL_PCODE_CDCLK_CONTROL: 1714 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1715 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1716 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1717 IS_COMETLAKE(vgpu->gvt->gt->i915)) 1718 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1719 break; 1720 case GEN6_PCODE_READ_RC6VIDS: 1721 *data0 |= 0x1; 1722 break; 1723 } 1724 1725 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1726 vgpu->id, value, *data0); 1727 /** 1728 * PCODE_READY clear means ready for pcode read/write, 1729 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1730 * always emulate as pcode read/write success and ready for access 1731 * anytime, since we don't touch real physical registers here. 1732 */ 1733 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1734 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1735 } 1736 1737 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1738 void *p_data, unsigned int bytes) 1739 { 1740 u32 value = *(u32 *)p_data; 1741 const struct intel_engine_cs *engine = 1742 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1743 1744 if (value != 0 && 1745 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1746 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1747 offset, value); 1748 return -EINVAL; 1749 } 1750 1751 /* 1752 * Need to emulate all the HWSP register write to ensure host can 1753 * update the VM CSB status correctly. Here listed registers can 1754 * support BDW, SKL or other platforms with same HWSP registers. 1755 */ 1756 if (unlikely(!engine)) { 1757 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1758 offset); 1759 return -EINVAL; 1760 } 1761 vgpu->hws_pga[engine->id] = value; 1762 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1763 vgpu->id, value, offset); 1764 1765 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1766 } 1767 1768 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1769 unsigned int offset, void *p_data, unsigned int bytes) 1770 { 1771 u32 v = *(u32 *)p_data; 1772 1773 if (IS_BROXTON(vgpu->gvt->gt->i915)) 1774 v &= (1 << 31) | (1 << 29); 1775 else 1776 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1777 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1778 v |= (v >> 1); 1779 1780 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1781 } 1782 1783 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1784 void *p_data, unsigned int bytes) 1785 { 1786 u32 v = *(u32 *)p_data; 1787 1788 /* other bits are MBZ. */ 1789 v &= (1 << 31) | (1 << 30); 1790 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1791 1792 vgpu_vreg(vgpu, offset) = v; 1793 1794 return 0; 1795 } 1796 1797 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1798 unsigned int offset, void *p_data, unsigned int bytes) 1799 { 1800 u32 v = *(u32 *)p_data; 1801 1802 if (v & BXT_DE_PLL_PLL_ENABLE) 1803 v |= BXT_DE_PLL_LOCK; 1804 1805 vgpu_vreg(vgpu, offset) = v; 1806 1807 return 0; 1808 } 1809 1810 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1811 unsigned int offset, void *p_data, unsigned int bytes) 1812 { 1813 u32 v = *(u32 *)p_data; 1814 1815 if (v & PORT_PLL_ENABLE) 1816 v |= PORT_PLL_LOCK; 1817 1818 vgpu_vreg(vgpu, offset) = v; 1819 1820 return 0; 1821 } 1822 1823 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1824 unsigned int offset, void *p_data, unsigned int bytes) 1825 { 1826 u32 v = *(u32 *)p_data; 1827 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1828 1829 switch (offset) { 1830 case _PHY_CTL_FAMILY_EDP: 1831 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1832 break; 1833 case _PHY_CTL_FAMILY_DDI: 1834 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1835 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1836 break; 1837 } 1838 1839 vgpu_vreg(vgpu, offset) = v; 1840 1841 return 0; 1842 } 1843 1844 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1845 unsigned int offset, void *p_data, unsigned int bytes) 1846 { 1847 u32 v = vgpu_vreg(vgpu, offset); 1848 1849 v &= ~UNIQUE_TRANGE_EN_METHOD; 1850 1851 vgpu_vreg(vgpu, offset) = v; 1852 1853 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1854 } 1855 1856 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1857 unsigned int offset, void *p_data, unsigned int bytes) 1858 { 1859 u32 v = *(u32 *)p_data; 1860 1861 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1862 vgpu_vreg(vgpu, offset - 0x600) = v; 1863 vgpu_vreg(vgpu, offset - 0x800) = v; 1864 } else { 1865 vgpu_vreg(vgpu, offset - 0x400) = v; 1866 vgpu_vreg(vgpu, offset - 0x600) = v; 1867 } 1868 1869 vgpu_vreg(vgpu, offset) = v; 1870 1871 return 0; 1872 } 1873 1874 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1875 unsigned int offset, void *p_data, unsigned int bytes) 1876 { 1877 u32 v = *(u32 *)p_data; 1878 1879 if (v & BIT(0)) { 1880 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1881 ~PHY_RESERVED; 1882 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1883 PHY_POWER_GOOD; 1884 } 1885 1886 if (v & BIT(1)) { 1887 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1888 ~PHY_RESERVED; 1889 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1890 PHY_POWER_GOOD; 1891 } 1892 1893 1894 vgpu_vreg(vgpu, offset) = v; 1895 1896 return 0; 1897 } 1898 1899 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1900 unsigned int offset, void *p_data, unsigned int bytes) 1901 { 1902 vgpu_vreg(vgpu, offset) = 0; 1903 return 0; 1904 } 1905 1906 /* 1907 * FixMe: 1908 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did: 1909 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.) 1910 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing 1911 * these MI_BATCH_BUFFER. 1912 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT 1913 * PML4 PTE: PAT(0) PCD(1) PWT(1). 1914 * The performance is still expected to be low, will need further improvement. 1915 */ 1916 static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset, 1917 void *p_data, unsigned int bytes) 1918 { 1919 u64 pat = 1920 GEN8_PPAT(0, CHV_PPAT_SNOOP) | 1921 GEN8_PPAT(1, 0) | 1922 GEN8_PPAT(2, 0) | 1923 GEN8_PPAT(3, CHV_PPAT_SNOOP) | 1924 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 1925 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 1926 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 1927 GEN8_PPAT(7, CHV_PPAT_SNOOP); 1928 1929 vgpu_vreg(vgpu, offset) = lower_32_bits(pat); 1930 1931 return 0; 1932 } 1933 1934 static int guc_status_read(struct intel_vgpu *vgpu, 1935 unsigned int offset, void *p_data, 1936 unsigned int bytes) 1937 { 1938 /* keep MIA_IN_RESET before clearing */ 1939 read_vreg(vgpu, offset, p_data, bytes); 1940 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET; 1941 return 0; 1942 } 1943 1944 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1945 unsigned int offset, void *p_data, unsigned int bytes) 1946 { 1947 struct intel_gvt *gvt = vgpu->gvt; 1948 const struct intel_engine_cs *engine = 1949 intel_gvt_render_mmio_to_engine(gvt, offset); 1950 1951 /** 1952 * Read HW reg in following case 1953 * a. the offset isn't a ring mmio 1954 * b. the offset's ring is running on hw. 1955 * c. the offset is ring time stamp mmio 1956 */ 1957 1958 if (!engine || 1959 vgpu == gvt->scheduler.engine_owner[engine->id] || 1960 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) || 1961 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) { 1962 mmio_hw_access_pre(gvt->gt); 1963 vgpu_vreg(vgpu, offset) = 1964 intel_uncore_read(gvt->gt->uncore, _MMIO(offset)); 1965 mmio_hw_access_post(gvt->gt); 1966 } 1967 1968 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1969 } 1970 1971 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1972 void *p_data, unsigned int bytes) 1973 { 1974 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1975 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1976 struct intel_vgpu_execlist *execlist; 1977 u32 data = *(u32 *)p_data; 1978 int ret = 0; 1979 1980 if (drm_WARN_ON(&i915->drm, !engine)) 1981 return -EINVAL; 1982 1983 /* 1984 * Due to d3_entered is used to indicate skipping PPGTT invalidation on 1985 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after 1986 * vGPU reset if in resuming. 1987 * In S0ix exit, the device power state also transite from D3 to D0 as 1988 * S3 resume, but no vGPU reset (triggered by QEMU devic model). After 1989 * S0ix exit, all engines continue to work. However the d3_entered 1990 * remains set which will break next vGPU reset logic (miss the expected 1991 * PPGTT invalidation). 1992 * Engines can only work in D0. Thus the 1st elsp write gives GVT a 1993 * chance to clear d3_entered. 1994 */ 1995 if (vgpu->d3_entered) 1996 vgpu->d3_entered = false; 1997 1998 execlist = &vgpu->submission.execlist[engine->id]; 1999 2000 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 2001 if (execlist->elsp_dwords.index == 3) { 2002 ret = intel_vgpu_submit_execlist(vgpu, engine); 2003 if(ret) 2004 gvt_vgpu_err("fail submit workload on ring %s\n", 2005 engine->name); 2006 } 2007 2008 ++execlist->elsp_dwords.index; 2009 execlist->elsp_dwords.index &= 0x3; 2010 return ret; 2011 } 2012 2013 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2014 void *p_data, unsigned int bytes) 2015 { 2016 u32 data = *(u32 *)p_data; 2017 const struct intel_engine_cs *engine = 2018 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 2019 bool enable_execlist; 2020 int ret; 2021 2022 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); 2023 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2024 IS_COMETLAKE(vgpu->gvt->gt->i915)) 2025 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); 2026 write_vreg(vgpu, offset, p_data, bytes); 2027 2028 if (IS_MASKED_BITS_ENABLED(data, 1)) { 2029 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2030 return 0; 2031 } 2032 2033 if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2034 IS_COMETLAKE(vgpu->gvt->gt->i915)) && 2035 IS_MASKED_BITS_ENABLED(data, 2)) { 2036 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2037 return 0; 2038 } 2039 2040 /* when PPGTT mode enabled, we will check if guest has called 2041 * pvinfo, if not, we will treat this guest as non-gvtg-aware 2042 * guest, and stop emulating its cfg space, mmio, gtt, etc. 2043 */ 2044 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) || 2045 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) && 2046 !vgpu->pv_notified) { 2047 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2048 return 0; 2049 } 2050 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) || 2051 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) { 2052 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 2053 2054 gvt_dbg_core("EXECLIST %s on ring %s\n", 2055 (enable_execlist ? "enabling" : "disabling"), 2056 engine->name); 2057 2058 if (!enable_execlist) 2059 return 0; 2060 2061 ret = intel_vgpu_select_submission_ops(vgpu, 2062 engine->mask, 2063 INTEL_VGPU_EXECLIST_SUBMISSION); 2064 if (ret) 2065 return ret; 2066 2067 intel_vgpu_start_schedule(vgpu); 2068 } 2069 return 0; 2070 } 2071 2072 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 2073 unsigned int offset, void *p_data, unsigned int bytes) 2074 { 2075 unsigned int id = 0; 2076 2077 write_vreg(vgpu, offset, p_data, bytes); 2078 vgpu_vreg(vgpu, offset) = 0; 2079 2080 switch (offset) { 2081 case 0x4260: 2082 id = RCS0; 2083 break; 2084 case 0x4264: 2085 id = VCS0; 2086 break; 2087 case 0x4268: 2088 id = VCS1; 2089 break; 2090 case 0x426c: 2091 id = BCS0; 2092 break; 2093 case 0x4270: 2094 id = VECS0; 2095 break; 2096 default: 2097 return -EINVAL; 2098 } 2099 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 2100 2101 return 0; 2102 } 2103 2104 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 2105 unsigned int offset, void *p_data, unsigned int bytes) 2106 { 2107 u32 data; 2108 2109 write_vreg(vgpu, offset, p_data, bytes); 2110 data = vgpu_vreg(vgpu, offset); 2111 2112 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET)) 2113 data |= RESET_CTL_READY_TO_RESET; 2114 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 2115 data &= ~RESET_CTL_READY_TO_RESET; 2116 2117 vgpu_vreg(vgpu, offset) = data; 2118 return 0; 2119 } 2120 2121 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, 2122 unsigned int offset, void *p_data, 2123 unsigned int bytes) 2124 { 2125 u32 data = *(u32 *)p_data; 2126 2127 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); 2128 write_vreg(vgpu, offset, p_data, bytes); 2129 2130 if (IS_MASKED_BITS_ENABLED(data, 0x10) || 2131 IS_MASKED_BITS_ENABLED(data, 0x8)) 2132 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2133 2134 return 0; 2135 } 2136 2137 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 2138 ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 2139 s, f, am, rm, d, r, w); \ 2140 if (ret) \ 2141 return ret; \ 2142 } while (0) 2143 2144 #define MMIO_DH(reg, d, r, w) \ 2145 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 2146 2147 #define MMIO_DFH(reg, d, f, r, w) \ 2148 MMIO_F(reg, 4, f, 0, 0, d, r, w) 2149 2150 #define MMIO_GM(reg, d, r, w) \ 2151 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 2152 2153 #define MMIO_GM_RDR(reg, d, r, w) \ 2154 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 2155 2156 #define MMIO_RO(reg, d, f, rm, r, w) \ 2157 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 2158 2159 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 2160 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 2161 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 2162 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 2163 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 2164 if (HAS_ENGINE(gvt->gt, VCS1)) \ 2165 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 2166 } while (0) 2167 2168 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 2169 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 2170 2171 #define MMIO_RING_GM(prefix, d, r, w) \ 2172 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 2173 2174 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 2175 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 2176 2177 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 2178 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 2179 2180 static int init_generic_mmio_info(struct intel_gvt *gvt) 2181 { 2182 struct drm_i915_private *dev_priv = gvt->gt->i915; 2183 int ret; 2184 2185 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, 2186 intel_vgpu_reg_imr_handler); 2187 2188 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 2189 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 2190 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 2191 2192 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL); 2193 2194 2195 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, 2196 gamw_echo_dev_rw_ia_write); 2197 2198 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2199 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2200 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2201 2202 #define RING_REG(base) _MMIO((base) + 0x28) 2203 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2204 #undef RING_REG 2205 2206 #define RING_REG(base) _MMIO((base) + 0x134) 2207 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2208 #undef RING_REG 2209 2210 #define RING_REG(base) _MMIO((base) + 0x6c) 2211 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 2212 #undef RING_REG 2213 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 2214 2215 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 2216 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); 2217 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 2218 2219 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL); 2220 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL); 2221 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL); 2222 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL); 2223 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 2224 2225 /* RING MODE */ 2226 #define RING_REG(base) _MMIO((base) + 0x29c) 2227 MMIO_RING_DFH(RING_REG, D_ALL, 2228 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL, 2229 ring_mode_mmio_write); 2230 #undef RING_REG 2231 2232 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2233 NULL, NULL); 2234 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2235 NULL, NULL); 2236 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 2237 mmio_read_from_hw, NULL); 2238 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 2239 mmio_read_from_hw, NULL); 2240 2241 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2242 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2243 NULL, NULL); 2244 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2245 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2246 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2247 2248 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2249 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2250 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2251 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL, 2252 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2253 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2254 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 2255 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2256 NULL, NULL); 2257 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2258 NULL, NULL); 2259 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 2260 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 2261 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 2262 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 2263 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 2264 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 2265 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2266 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2267 MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2268 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2269 2270 /* display */ 2271 MMIO_DH(TRANSCONF(TRANSCODER_A), D_ALL, NULL, pipeconf_mmio_write); 2272 MMIO_DH(TRANSCONF(TRANSCODER_B), D_ALL, NULL, pipeconf_mmio_write); 2273 MMIO_DH(TRANSCONF(TRANSCODER_C), D_ALL, NULL, pipeconf_mmio_write); 2274 MMIO_DH(TRANSCONF(TRANSCODER_EDP), D_ALL, NULL, pipeconf_mmio_write); 2275 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2276 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, 2277 reg50080_mmio_write); 2278 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2279 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, 2280 reg50080_mmio_write); 2281 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2282 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, 2283 reg50080_mmio_write); 2284 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 2285 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, 2286 reg50080_mmio_write); 2287 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 2288 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, 2289 reg50080_mmio_write); 2290 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 2291 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, 2292 reg50080_mmio_write); 2293 2294 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2295 gmbus_mmio_write); 2296 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2297 2298 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2299 dp_aux_ch_ctl_mmio_write); 2300 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2301 dp_aux_ch_ctl_mmio_write); 2302 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2303 dp_aux_ch_ctl_mmio_write); 2304 2305 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2306 2307 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2308 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2309 2310 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2311 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2312 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2313 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2314 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2315 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2316 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2317 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2318 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2319 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2320 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2321 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2322 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2323 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2324 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2325 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2326 2327 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2328 PORTA_HOTPLUG_STATUS_MASK 2329 | PORTB_HOTPLUG_STATUS_MASK 2330 | PORTC_HOTPLUG_STATUS_MASK 2331 | PORTD_HOTPLUG_STATUS_MASK, 2332 NULL, NULL); 2333 2334 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2335 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2336 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2337 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2338 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2339 2340 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2341 dp_aux_ch_ctl_mmio_write); 2342 2343 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2344 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2345 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2346 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2347 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2348 2349 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2350 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2351 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2352 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2353 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2354 2355 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2356 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2357 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2358 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2359 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2360 2361 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2362 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2363 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2364 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2365 2366 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2367 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2368 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2369 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2370 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2371 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2372 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2373 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); 2374 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); 2375 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); 2376 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); 2377 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2378 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2379 2380 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2381 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2382 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2383 2384 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2385 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2386 2387 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2388 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2389 2390 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2391 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2392 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2393 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2394 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2395 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2396 2397 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2398 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2399 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2400 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2401 2402 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2403 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2404 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2405 2406 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2407 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2408 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2409 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2410 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2411 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2412 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2413 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2414 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2415 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2416 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2417 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2418 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2419 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2420 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2421 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2422 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2423 2424 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2425 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL); 2426 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2427 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2428 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2429 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2430 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2431 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2432 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2433 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2434 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2435 2436 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2437 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2438 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL); 2439 2440 return 0; 2441 } 2442 2443 static int init_bdw_mmio_info(struct intel_gvt *gvt) 2444 { 2445 int ret; 2446 2447 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2448 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2449 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2450 2451 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2452 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2453 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2454 2455 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2456 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2457 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2458 2459 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2460 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2461 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2462 2463 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2464 intel_vgpu_reg_imr_handler); 2465 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2466 intel_vgpu_reg_ier_handler); 2467 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2468 intel_vgpu_reg_iir_handler); 2469 2470 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2471 intel_vgpu_reg_imr_handler); 2472 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2473 intel_vgpu_reg_ier_handler); 2474 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2475 intel_vgpu_reg_iir_handler); 2476 2477 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2478 intel_vgpu_reg_imr_handler); 2479 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2480 intel_vgpu_reg_ier_handler); 2481 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2482 intel_vgpu_reg_iir_handler); 2483 2484 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2485 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2486 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2487 2488 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2489 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2490 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2491 2492 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2493 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2494 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2495 2496 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2497 intel_vgpu_reg_master_irq_handler); 2498 2499 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0, 2500 mmio_read_from_hw, NULL); 2501 2502 #define RING_REG(base) _MMIO((base) + 0xd0) 2503 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2504 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2505 ring_reset_ctl_write); 2506 #undef RING_REG 2507 2508 #define RING_REG(base) _MMIO((base) + 0x230) 2509 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2510 #undef RING_REG 2511 2512 #define RING_REG(base) _MMIO((base) + 0x234) 2513 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, 2514 NULL, NULL); 2515 #undef RING_REG 2516 2517 #define RING_REG(base) _MMIO((base) + 0x244) 2518 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2519 #undef RING_REG 2520 2521 #define RING_REG(base) _MMIO((base) + 0x370) 2522 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2523 #undef RING_REG 2524 2525 #define RING_REG(base) _MMIO((base) + 0x3a0) 2526 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2527 #undef RING_REG 2528 2529 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2530 2531 #define RING_REG(base) _MMIO((base) + 0x270) 2532 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2533 #undef RING_REG 2534 2535 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2536 2537 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2538 2539 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2540 NULL, NULL); 2541 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2542 NULL, NULL); 2543 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2544 2545 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2546 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2547 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2548 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2549 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2550 2551 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0, 2552 D_BDW_PLUS, NULL, force_nonpriv_write); 2553 2554 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2555 2556 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2557 2558 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2559 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2560 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2561 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2562 2563 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2564 2565 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2566 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2567 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2568 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2569 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2570 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2571 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2572 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2573 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2574 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2575 return 0; 2576 } 2577 2578 static int init_skl_mmio_info(struct intel_gvt *gvt) 2579 { 2580 int ret; 2581 2582 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2583 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2584 MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2585 MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL); 2586 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2587 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2588 2589 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2590 dp_aux_ch_ctl_mmio_write); 2591 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2592 dp_aux_ch_ctl_mmio_write); 2593 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2594 dp_aux_ch_ctl_mmio_write); 2595 2596 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); 2597 2598 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 2599 2600 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2601 MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2602 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL); 2603 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2604 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2605 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL); 2606 2607 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2608 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2609 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2610 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2611 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2612 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2613 2614 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2615 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2616 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2617 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2618 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2619 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2620 2621 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2622 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2623 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2624 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2625 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2626 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2627 2628 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2629 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2630 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2631 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2632 2633 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2634 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2635 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2636 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2637 2638 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2639 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2640 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2641 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2642 2643 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2644 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2645 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2646 2647 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2648 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2649 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2650 2651 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2652 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2653 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2654 2655 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2656 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2657 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2658 2659 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2660 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2661 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2662 2663 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2664 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2665 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2666 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2667 2668 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2669 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2670 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2671 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2672 2673 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2674 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2675 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2676 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2677 2678 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2679 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2680 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2681 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2682 2683 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2684 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2685 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2686 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2687 2688 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2689 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2690 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2691 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2692 2693 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2694 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2695 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2696 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2697 2698 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2699 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2700 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2701 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2702 2703 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2704 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2705 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2706 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2707 2708 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2709 2710 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2711 NULL, NULL); 2712 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2713 NULL, NULL); 2714 2715 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, 2716 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2717 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2718 NULL, NULL); 2719 2720 /* TRTT */ 2721 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2722 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2723 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2724 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2725 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2726 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE, 2727 NULL, gen9_trtte_write); 2728 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE, 2729 NULL, gen9_trtt_chicken_write); 2730 2731 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2732 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2733 2734 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) 2735 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2736 NULL, csfe_chicken1_mmio_write); 2737 #undef CSFE_CHICKEN1_REG 2738 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2739 NULL, NULL); 2740 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2741 NULL, NULL); 2742 2743 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL); 2744 MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2745 2746 return 0; 2747 } 2748 2749 static int init_bxt_mmio_info(struct intel_gvt *gvt) 2750 { 2751 int ret; 2752 2753 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 2754 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 2755 NULL, bxt_phy_ctl_family_write); 2756 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 2757 NULL, bxt_phy_ctl_family_write); 2758 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 2759 NULL, bxt_port_pll_enable_write); 2760 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 2761 NULL, bxt_port_pll_enable_write); 2762 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 2763 bxt_port_pll_enable_write); 2764 2765 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 2766 NULL, bxt_pcs_dw12_grp_write); 2767 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, 2768 bxt_port_tx_dw3_read, NULL); 2769 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 2770 NULL, bxt_pcs_dw12_grp_write); 2771 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, 2772 bxt_port_tx_dw3_read, NULL); 2773 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 2774 NULL, bxt_pcs_dw12_grp_write); 2775 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, 2776 bxt_port_tx_dw3_read, NULL); 2777 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 2778 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); 2779 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL); 2780 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL); 2781 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2782 0, 0, D_BXT, NULL, NULL); 2783 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2784 0, 0, D_BXT, NULL, NULL); 2785 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2786 0, 0, D_BXT, NULL, NULL); 2787 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2788 0, 0, D_BXT, NULL, NULL); 2789 2790 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 2791 2792 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write); 2793 2794 return 0; 2795 } 2796 2797 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 2798 unsigned int offset) 2799 { 2800 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2801 int num = gvt->mmio.num_mmio_block; 2802 int i; 2803 2804 for (i = 0; i < num; i++, block++) { 2805 if (offset >= i915_mmio_reg_offset(block->offset) && 2806 offset < i915_mmio_reg_offset(block->offset) + block->size) 2807 return block; 2808 } 2809 return NULL; 2810 } 2811 2812 /** 2813 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2814 * @gvt: GVT device 2815 * 2816 * This function is called at the driver unloading stage, to clean up the MMIO 2817 * information table of GVT device 2818 * 2819 */ 2820 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2821 { 2822 struct hlist_node *tmp; 2823 struct intel_gvt_mmio_info *e; 2824 int i; 2825 2826 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2827 kfree(e); 2828 2829 kfree(gvt->mmio.mmio_block); 2830 gvt->mmio.mmio_block = NULL; 2831 gvt->mmio.num_mmio_block = 0; 2832 2833 vfree(gvt->mmio.mmio_attribute); 2834 gvt->mmio.mmio_attribute = NULL; 2835 } 2836 2837 static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset, 2838 u32 size) 2839 { 2840 struct intel_gvt *gvt = iter->data; 2841 struct intel_gvt_mmio_info *info, *p; 2842 u32 start, end, i; 2843 2844 if (WARN_ON(!IS_ALIGNED(offset, 4))) 2845 return -EINVAL; 2846 2847 start = offset; 2848 end = offset + size; 2849 2850 for (i = start; i < end; i += 4) { 2851 p = intel_gvt_find_mmio_info(gvt, i); 2852 if (p) { 2853 WARN(1, "dup mmio definition offset %x\n", i); 2854 2855 /* We return -EEXIST here to make GVT-g load fail. 2856 * So duplicated MMIO can be found as soon as 2857 * possible. 2858 */ 2859 return -EEXIST; 2860 } 2861 2862 info = kzalloc(sizeof(*info), GFP_KERNEL); 2863 if (!info) 2864 return -ENOMEM; 2865 2866 info->offset = i; 2867 info->read = intel_vgpu_default_mmio_read; 2868 info->write = intel_vgpu_default_mmio_write; 2869 INIT_HLIST_NODE(&info->node); 2870 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 2871 gvt->mmio.num_tracked_mmio++; 2872 } 2873 return 0; 2874 } 2875 2876 static int handle_mmio_block(struct intel_gvt_mmio_table_iter *iter, 2877 u32 offset, u32 size) 2878 { 2879 struct intel_gvt *gvt = iter->data; 2880 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2881 void *ret; 2882 2883 ret = krealloc(block, 2884 (gvt->mmio.num_mmio_block + 1) * sizeof(*block), 2885 GFP_KERNEL); 2886 if (!ret) 2887 return -ENOMEM; 2888 2889 gvt->mmio.mmio_block = block = ret; 2890 2891 block += gvt->mmio.num_mmio_block; 2892 2893 memset(block, 0, sizeof(*block)); 2894 2895 block->offset = _MMIO(offset); 2896 block->size = size; 2897 2898 gvt->mmio.num_mmio_block++; 2899 2900 return 0; 2901 } 2902 2903 static int handle_mmio_cb(struct intel_gvt_mmio_table_iter *iter, u32 offset, 2904 u32 size) 2905 { 2906 if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0))) 2907 return handle_mmio(iter, offset, size); 2908 else 2909 return handle_mmio_block(iter, offset, size); 2910 } 2911 2912 static int init_mmio_info(struct intel_gvt *gvt) 2913 { 2914 struct intel_gvt_mmio_table_iter iter = { 2915 .i915 = gvt->gt->i915, 2916 .data = gvt, 2917 .handle_mmio_cb = handle_mmio_cb, 2918 }; 2919 2920 return intel_gvt_iterate_mmio_table(&iter); 2921 } 2922 2923 static int init_mmio_block_handlers(struct intel_gvt *gvt) 2924 { 2925 struct gvt_mmio_block *block; 2926 2927 block = find_mmio_block(gvt, VGT_PVINFO_PAGE); 2928 if (!block) { 2929 WARN(1, "fail to assign handlers to mmio block %x\n", 2930 i915_mmio_reg_offset(gvt->mmio.mmio_block->offset)); 2931 return -ENODEV; 2932 } 2933 2934 block->read = pvinfo_mmio_read; 2935 block->write = pvinfo_mmio_write; 2936 2937 return 0; 2938 } 2939 2940 /** 2941 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2942 * @gvt: GVT device 2943 * 2944 * This function is called at the initialization stage, to setup the MMIO 2945 * information table for GVT device 2946 * 2947 * Returns: 2948 * zero on success, negative if failed. 2949 */ 2950 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2951 { 2952 struct intel_gvt_device_info *info = &gvt->device_info; 2953 struct drm_i915_private *i915 = gvt->gt->i915; 2954 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 2955 int ret; 2956 2957 gvt->mmio.mmio_attribute = vzalloc(size); 2958 if (!gvt->mmio.mmio_attribute) 2959 return -ENOMEM; 2960 2961 ret = init_mmio_info(gvt); 2962 if (ret) 2963 goto err; 2964 2965 ret = init_mmio_block_handlers(gvt); 2966 if (ret) 2967 goto err; 2968 2969 ret = init_generic_mmio_info(gvt); 2970 if (ret) 2971 goto err; 2972 2973 if (IS_BROADWELL(i915)) { 2974 ret = init_bdw_mmio_info(gvt); 2975 if (ret) 2976 goto err; 2977 } else if (IS_SKYLAKE(i915) || 2978 IS_KABYLAKE(i915) || 2979 IS_COFFEELAKE(i915) || 2980 IS_COMETLAKE(i915)) { 2981 ret = init_bdw_mmio_info(gvt); 2982 if (ret) 2983 goto err; 2984 ret = init_skl_mmio_info(gvt); 2985 if (ret) 2986 goto err; 2987 } else if (IS_BROXTON(i915)) { 2988 ret = init_bdw_mmio_info(gvt); 2989 if (ret) 2990 goto err; 2991 ret = init_skl_mmio_info(gvt); 2992 if (ret) 2993 goto err; 2994 ret = init_bxt_mmio_info(gvt); 2995 if (ret) 2996 goto err; 2997 } 2998 2999 return 0; 3000 err: 3001 intel_gvt_clean_mmio_info(gvt); 3002 return ret; 3003 } 3004 3005 /** 3006 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 3007 * @gvt: a GVT device 3008 * @handler: the handler 3009 * @data: private data given to handler 3010 * 3011 * Returns: 3012 * Zero on success, negative error code if failed. 3013 */ 3014 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3015 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3016 void *data) 3017 { 3018 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3019 struct intel_gvt_mmio_info *e; 3020 int i, j, ret; 3021 3022 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3023 ret = handler(gvt, e->offset, data); 3024 if (ret) 3025 return ret; 3026 } 3027 3028 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3029 /* pvinfo data doesn't come from hw mmio */ 3030 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE) 3031 continue; 3032 3033 for (j = 0; j < block->size; j += 4) { 3034 ret = handler(gvt, i915_mmio_reg_offset(block->offset) + j, data); 3035 if (ret) 3036 return ret; 3037 } 3038 } 3039 return 0; 3040 } 3041 3042 /** 3043 * intel_vgpu_default_mmio_read - default MMIO read handler 3044 * @vgpu: a vGPU 3045 * @offset: access offset 3046 * @p_data: data return buffer 3047 * @bytes: access data length 3048 * 3049 * Returns: 3050 * Zero on success, negative error code if failed. 3051 */ 3052 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3053 void *p_data, unsigned int bytes) 3054 { 3055 read_vreg(vgpu, offset, p_data, bytes); 3056 return 0; 3057 } 3058 3059 /** 3060 * intel_vgpu_default_mmio_write() - default MMIO write handler 3061 * @vgpu: a vGPU 3062 * @offset: access offset 3063 * @p_data: write data buffer 3064 * @bytes: access data length 3065 * 3066 * Returns: 3067 * Zero on success, negative error code if failed. 3068 */ 3069 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3070 void *p_data, unsigned int bytes) 3071 { 3072 write_vreg(vgpu, offset, p_data, bytes); 3073 return 0; 3074 } 3075 3076 /** 3077 * intel_vgpu_mask_mmio_write - write mask register 3078 * @vgpu: a vGPU 3079 * @offset: access offset 3080 * @p_data: write data buffer 3081 * @bytes: access data length 3082 * 3083 * Returns: 3084 * Zero on success, negative error code if failed. 3085 */ 3086 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3087 void *p_data, unsigned int bytes) 3088 { 3089 u32 mask, old_vreg; 3090 3091 old_vreg = vgpu_vreg(vgpu, offset); 3092 write_vreg(vgpu, offset, p_data, bytes); 3093 mask = vgpu_vreg(vgpu, offset) >> 16; 3094 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | 3095 (vgpu_vreg(vgpu, offset) & mask); 3096 3097 return 0; 3098 } 3099 3100 /** 3101 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3102 * force-nopriv register 3103 * 3104 * @gvt: a GVT device 3105 * @offset: register offset 3106 * 3107 * Returns: 3108 * True if the register is in force-nonpriv whitelist; 3109 * False if outside; 3110 */ 3111 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3112 unsigned int offset) 3113 { 3114 return in_whitelist(offset); 3115 } 3116 3117 /** 3118 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3119 * @vgpu: a vGPU 3120 * @offset: register offset 3121 * @pdata: data buffer 3122 * @bytes: data length 3123 * @is_read: read or write 3124 * 3125 * Returns: 3126 * Zero on success, negative error code if failed. 3127 */ 3128 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3129 void *pdata, unsigned int bytes, bool is_read) 3130 { 3131 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 3132 struct intel_gvt *gvt = vgpu->gvt; 3133 struct intel_gvt_mmio_info *mmio_info; 3134 struct gvt_mmio_block *mmio_block; 3135 gvt_mmio_func func; 3136 int ret; 3137 3138 if (drm_WARN_ON(&i915->drm, bytes > 8)) 3139 return -EINVAL; 3140 3141 /* 3142 * Handle special MMIO blocks. 3143 */ 3144 mmio_block = find_mmio_block(gvt, offset); 3145 if (mmio_block) { 3146 func = is_read ? mmio_block->read : mmio_block->write; 3147 if (func) 3148 return func(vgpu, offset, pdata, bytes); 3149 goto default_rw; 3150 } 3151 3152 /* 3153 * Normal tracked MMIOs. 3154 */ 3155 mmio_info = intel_gvt_find_mmio_info(gvt, offset); 3156 if (!mmio_info) { 3157 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3158 goto default_rw; 3159 } 3160 3161 if (is_read) 3162 return mmio_info->read(vgpu, offset, pdata, bytes); 3163 else { 3164 u64 ro_mask = mmio_info->ro_mask; 3165 u32 old_vreg = 0; 3166 u64 data = 0; 3167 3168 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3169 old_vreg = vgpu_vreg(vgpu, offset); 3170 } 3171 3172 if (likely(!ro_mask)) 3173 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3174 else if (!~ro_mask) { 3175 gvt_vgpu_err("try to write RO reg %x\n", offset); 3176 return 0; 3177 } else { 3178 /* keep the RO bits in the virtual register */ 3179 memcpy(&data, pdata, bytes); 3180 data &= ~ro_mask; 3181 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3182 ret = mmio_info->write(vgpu, offset, &data, bytes); 3183 } 3184 3185 /* higher 16bits of mode ctl regs are mask bits for change */ 3186 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3187 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3188 3189 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3190 | (vgpu_vreg(vgpu, offset) & mask); 3191 } 3192 } 3193 3194 return ret; 3195 3196 default_rw: 3197 return is_read ? 3198 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3199 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3200 } 3201 3202 void intel_gvt_restore_fence(struct intel_gvt *gvt) 3203 { 3204 struct intel_vgpu *vgpu; 3205 int i, id; 3206 3207 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3208 mmio_hw_access_pre(gvt->gt); 3209 for (i = 0; i < vgpu_fence_sz(vgpu); i++) 3210 intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i))); 3211 mmio_hw_access_post(gvt->gt); 3212 } 3213 } 3214 3215 static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data) 3216 { 3217 struct intel_vgpu *vgpu = data; 3218 struct drm_i915_private *dev_priv = gvt->gt->i915; 3219 3220 if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE) 3221 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset)); 3222 3223 return 0; 3224 } 3225 3226 void intel_gvt_restore_mmio(struct intel_gvt *gvt) 3227 { 3228 struct intel_vgpu *vgpu; 3229 int id; 3230 3231 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3232 mmio_hw_access_pre(gvt->gt); 3233 intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu); 3234 mmio_hw_access_post(gvt->gt); 3235 } 3236 } 3237