1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 /* Register contains RO bits */ 51 #define F_RO (1 << 0) 52 /* Register contains graphics address */ 53 #define F_GMADR (1 << 1) 54 /* Mode mask registers with high 16 bits as the mask bits */ 55 #define F_MODE_MASK (1 << 2) 56 /* This reg can be accessed by GPU commands */ 57 #define F_CMD_ACCESS (1 << 3) 58 /* This reg has been accessed by a VM */ 59 #define F_ACCESSED (1 << 4) 60 /* This reg has been accessed through GPU commands */ 61 #define F_CMD_ACCESSED (1 << 5) 62 /* This reg could be accessed by unaligned address */ 63 #define F_UNALIGN (1 << 6) 64 65 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 66 { 67 if (IS_BROADWELL(gvt->dev_priv)) 68 return D_BDW; 69 else if (IS_SKYLAKE(gvt->dev_priv)) 70 return D_SKL; 71 72 return 0; 73 } 74 75 bool intel_gvt_match_device(struct intel_gvt *gvt, 76 unsigned long device) 77 { 78 return intel_gvt_get_device_type(gvt) & device; 79 } 80 81 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 82 void *p_data, unsigned int bytes) 83 { 84 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 85 } 86 87 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 88 void *p_data, unsigned int bytes) 89 { 90 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 91 } 92 93 static int new_mmio_info(struct intel_gvt *gvt, 94 u32 offset, u32 flags, u32 size, 95 u32 addr_mask, u32 ro_mask, u32 device, 96 void *read, void *write) 97 { 98 struct intel_gvt_mmio_info *info, *p; 99 u32 start, end, i; 100 101 if (!intel_gvt_match_device(gvt, device)) 102 return 0; 103 104 if (WARN_ON(!IS_ALIGNED(offset, 4))) 105 return -EINVAL; 106 107 start = offset; 108 end = offset + size; 109 110 for (i = start; i < end; i += 4) { 111 info = kzalloc(sizeof(*info), GFP_KERNEL); 112 if (!info) 113 return -ENOMEM; 114 115 info->offset = i; 116 p = intel_gvt_find_mmio_info(gvt, info->offset); 117 if (p) 118 gvt_err("dup mmio definition offset %x\n", 119 info->offset); 120 info->size = size; 121 info->length = (i + 4) < end ? 4 : (end - i); 122 info->addr_mask = addr_mask; 123 info->device = device; 124 info->read = read ? read : intel_vgpu_default_mmio_read; 125 info->write = write ? write : intel_vgpu_default_mmio_write; 126 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 127 INIT_HLIST_NODE(&info->node); 128 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 129 } 130 return 0; 131 } 132 133 static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) 134 { 135 enum intel_engine_id id; 136 struct intel_engine_cs *engine; 137 138 reg &= ~GENMASK(11, 0); 139 for_each_engine(engine, gvt->dev_priv, id) { 140 if (engine->mmio_base == reg) 141 return id; 142 } 143 return -1; 144 } 145 146 #define offset_to_fence_num(offset) \ 147 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 148 149 #define fence_num_to_offset(num) \ 150 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 151 152 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 153 unsigned int fence_num, void *p_data, unsigned int bytes) 154 { 155 if (fence_num >= vgpu_fence_sz(vgpu)) { 156 gvt_err("vgpu%d: found oob fence register access\n", 157 vgpu->id); 158 gvt_err("vgpu%d: total fence num %d access fence num %d\n", 159 vgpu->id, vgpu_fence_sz(vgpu), fence_num); 160 memset(p_data, 0, bytes); 161 } 162 return 0; 163 } 164 165 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 166 void *p_data, unsigned int bytes) 167 { 168 int ret; 169 170 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 171 p_data, bytes); 172 if (ret) 173 return ret; 174 read_vreg(vgpu, off, p_data, bytes); 175 return 0; 176 } 177 178 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 179 void *p_data, unsigned int bytes) 180 { 181 unsigned int fence_num = offset_to_fence_num(off); 182 int ret; 183 184 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 185 if (ret) 186 return ret; 187 write_vreg(vgpu, off, p_data, bytes); 188 189 intel_vgpu_write_fence(vgpu, fence_num, 190 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 191 return 0; 192 } 193 194 #define CALC_MODE_MASK_REG(old, new) \ 195 (((new) & GENMASK(31, 16)) \ 196 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 197 | ((new) & ((new) >> 16)))) 198 199 static int mul_force_wake_write(struct intel_vgpu *vgpu, 200 unsigned int offset, void *p_data, unsigned int bytes) 201 { 202 u32 old, new; 203 uint32_t ack_reg_offset; 204 205 old = vgpu_vreg(vgpu, offset); 206 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 207 208 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) { 209 switch (offset) { 210 case FORCEWAKE_RENDER_GEN9_REG: 211 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 212 break; 213 case FORCEWAKE_BLITTER_GEN9_REG: 214 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 215 break; 216 case FORCEWAKE_MEDIA_GEN9_REG: 217 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 218 break; 219 default: 220 /*should not hit here*/ 221 gvt_err("invalid forcewake offset 0x%x\n", offset); 222 return 1; 223 } 224 } else { 225 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 226 } 227 228 vgpu_vreg(vgpu, offset) = new; 229 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 230 return 0; 231 } 232 233 static int handle_device_reset(struct intel_vgpu *vgpu, unsigned int offset, 234 void *p_data, unsigned int bytes, unsigned long bitmap) 235 { 236 struct intel_gvt_workload_scheduler *scheduler = 237 &vgpu->gvt->scheduler; 238 239 vgpu->resetting = true; 240 241 intel_vgpu_stop_schedule(vgpu); 242 if (scheduler->current_vgpu == vgpu) { 243 mutex_unlock(&vgpu->gvt->lock); 244 intel_gvt_wait_vgpu_idle(vgpu); 245 mutex_lock(&vgpu->gvt->lock); 246 } 247 248 intel_vgpu_reset_execlist(vgpu, bitmap); 249 250 vgpu->resetting = false; 251 252 return 0; 253 } 254 255 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 256 void *p_data, unsigned int bytes) 257 { 258 u32 data; 259 u64 bitmap = 0; 260 261 write_vreg(vgpu, offset, p_data, bytes); 262 data = vgpu_vreg(vgpu, offset); 263 264 if (data & GEN6_GRDOM_FULL) { 265 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 266 bitmap = 0xff; 267 } 268 if (data & GEN6_GRDOM_RENDER) { 269 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 270 bitmap |= (1 << RCS); 271 } 272 if (data & GEN6_GRDOM_MEDIA) { 273 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 274 bitmap |= (1 << VCS); 275 } 276 if (data & GEN6_GRDOM_BLT) { 277 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 278 bitmap |= (1 << BCS); 279 } 280 if (data & GEN6_GRDOM_VECS) { 281 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 282 bitmap |= (1 << VECS); 283 } 284 if (data & GEN8_GRDOM_MEDIA2) { 285 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 286 if (HAS_BSD2(vgpu->gvt->dev_priv)) 287 bitmap |= (1 << VCS2); 288 } 289 return handle_device_reset(vgpu, offset, p_data, bytes, bitmap); 290 } 291 292 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 293 void *p_data, unsigned int bytes) 294 { 295 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 296 } 297 298 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 299 void *p_data, unsigned int bytes) 300 { 301 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 302 } 303 304 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 305 unsigned int offset, void *p_data, unsigned int bytes) 306 { 307 write_vreg(vgpu, offset, p_data, bytes); 308 309 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 310 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; 311 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 312 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 313 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 314 315 } else 316 vgpu_vreg(vgpu, PCH_PP_STATUS) &= 317 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 318 | PP_CYCLE_DELAY_ACTIVE); 319 return 0; 320 } 321 322 static int transconf_mmio_write(struct intel_vgpu *vgpu, 323 unsigned int offset, void *p_data, unsigned int bytes) 324 { 325 write_vreg(vgpu, offset, p_data, bytes); 326 327 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 328 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 329 else 330 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 331 return 0; 332 } 333 334 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 335 void *p_data, unsigned int bytes) 336 { 337 write_vreg(vgpu, offset, p_data, bytes); 338 339 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 340 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 341 else 342 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 343 344 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 345 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 346 else 347 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 348 349 return 0; 350 } 351 352 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 353 void *p_data, unsigned int bytes) 354 { 355 *(u32 *)p_data = (1 << 17); 356 return 0; 357 } 358 359 static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset, 360 void *p_data, unsigned int bytes) 361 { 362 *(u32 *)p_data = 3; 363 return 0; 364 } 365 366 static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset, 367 void *p_data, unsigned int bytes) 368 { 369 *(u32 *)p_data = (0x2f << 16); 370 return 0; 371 } 372 373 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 374 void *p_data, unsigned int bytes) 375 { 376 u32 data; 377 378 write_vreg(vgpu, offset, p_data, bytes); 379 data = vgpu_vreg(vgpu, offset); 380 381 if (data & PIPECONF_ENABLE) 382 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 383 else 384 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 385 intel_gvt_check_vblank_emulation(vgpu->gvt); 386 return 0; 387 } 388 389 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 390 void *p_data, unsigned int bytes) 391 { 392 write_vreg(vgpu, offset, p_data, bytes); 393 394 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 395 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 396 } else { 397 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 398 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 399 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) 400 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 401 } 402 return 0; 403 } 404 405 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 406 unsigned int offset, void *p_data, unsigned int bytes) 407 { 408 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 409 return 0; 410 } 411 412 #define FDI_LINK_TRAIN_PATTERN1 0 413 #define FDI_LINK_TRAIN_PATTERN2 1 414 415 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 416 { 417 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); 418 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 419 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); 420 421 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 422 (rx_ctl & FDI_RX_ENABLE) && 423 (rx_ctl & FDI_AUTO_TRAINING) && 424 (tx_ctl & DP_TP_CTL_ENABLE) && 425 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 426 return 1; 427 else 428 return 0; 429 } 430 431 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 432 enum pipe pipe, unsigned int train_pattern) 433 { 434 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 435 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 436 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 437 unsigned int fdi_iir_check_bits; 438 439 fdi_rx_imr = FDI_RX_IMR(pipe); 440 fdi_tx_ctl = FDI_TX_CTL(pipe); 441 fdi_rx_ctl = FDI_RX_CTL(pipe); 442 443 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 444 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 445 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 446 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 447 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 448 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 449 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 450 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 451 } else { 452 gvt_err("Invalid train pattern %d\n", train_pattern); 453 return -EINVAL; 454 } 455 456 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 457 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 458 459 /* If imr bit has been masked */ 460 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 461 return 0; 462 463 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 464 == fdi_tx_check_bits) 465 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 466 == fdi_rx_check_bits)) 467 return 1; 468 else 469 return 0; 470 } 471 472 #define INVALID_INDEX (~0U) 473 474 static unsigned int calc_index(unsigned int offset, unsigned int start, 475 unsigned int next, unsigned int end, i915_reg_t i915_end) 476 { 477 unsigned int range = next - start; 478 479 if (!end) 480 end = i915_mmio_reg_offset(i915_end); 481 if (offset < start || offset > end) 482 return INVALID_INDEX; 483 offset -= start; 484 return offset / range; 485 } 486 487 #define FDI_RX_CTL_TO_PIPE(offset) \ 488 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 489 490 #define FDI_TX_CTL_TO_PIPE(offset) \ 491 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 492 493 #define FDI_RX_IMR_TO_PIPE(offset) \ 494 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 495 496 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 497 unsigned int offset, void *p_data, unsigned int bytes) 498 { 499 i915_reg_t fdi_rx_iir; 500 unsigned int index; 501 int ret; 502 503 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 504 index = FDI_RX_CTL_TO_PIPE(offset); 505 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 506 index = FDI_TX_CTL_TO_PIPE(offset); 507 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 508 index = FDI_RX_IMR_TO_PIPE(offset); 509 else { 510 gvt_err("Unsupport registers %x\n", offset); 511 return -EINVAL; 512 } 513 514 write_vreg(vgpu, offset, p_data, bytes); 515 516 fdi_rx_iir = FDI_RX_IIR(index); 517 518 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 519 if (ret < 0) 520 return ret; 521 if (ret) 522 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 523 524 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 525 if (ret < 0) 526 return ret; 527 if (ret) 528 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 529 530 if (offset == _FDI_RXA_CTL) 531 if (fdi_auto_training_started(vgpu)) 532 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= 533 DP_TP_STATUS_AUTOTRAIN_DONE; 534 return 0; 535 } 536 537 #define DP_TP_CTL_TO_PORT(offset) \ 538 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 539 540 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 541 void *p_data, unsigned int bytes) 542 { 543 i915_reg_t status_reg; 544 unsigned int index; 545 u32 data; 546 547 write_vreg(vgpu, offset, p_data, bytes); 548 549 index = DP_TP_CTL_TO_PORT(offset); 550 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 551 if (data == 0x2) { 552 status_reg = DP_TP_STATUS(index); 553 vgpu_vreg(vgpu, status_reg) |= (1 << 25); 554 } 555 return 0; 556 } 557 558 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 559 unsigned int offset, void *p_data, unsigned int bytes) 560 { 561 u32 reg_val; 562 u32 sticky_mask; 563 564 reg_val = *((u32 *)p_data); 565 sticky_mask = GENMASK(27, 26) | (1 << 24); 566 567 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 568 (vgpu_vreg(vgpu, offset) & sticky_mask); 569 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 570 return 0; 571 } 572 573 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 574 unsigned int offset, void *p_data, unsigned int bytes) 575 { 576 u32 data; 577 578 write_vreg(vgpu, offset, p_data, bytes); 579 data = vgpu_vreg(vgpu, offset); 580 581 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 582 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 583 return 0; 584 } 585 586 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 587 unsigned int offset, void *p_data, unsigned int bytes) 588 { 589 u32 data; 590 591 write_vreg(vgpu, offset, p_data, bytes); 592 data = vgpu_vreg(vgpu, offset); 593 594 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 595 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 596 else 597 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 598 return 0; 599 } 600 601 #define DSPSURF_TO_PIPE(offset) \ 602 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 603 604 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 605 void *p_data, unsigned int bytes) 606 { 607 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 608 unsigned int index = DSPSURF_TO_PIPE(offset); 609 i915_reg_t surflive_reg = DSPSURFLIVE(index); 610 int flip_event[] = { 611 [PIPE_A] = PRIMARY_A_FLIP_DONE, 612 [PIPE_B] = PRIMARY_B_FLIP_DONE, 613 [PIPE_C] = PRIMARY_C_FLIP_DONE, 614 }; 615 616 write_vreg(vgpu, offset, p_data, bytes); 617 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 618 619 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 620 return 0; 621 } 622 623 #define SPRSURF_TO_PIPE(offset) \ 624 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 625 626 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 627 void *p_data, unsigned int bytes) 628 { 629 unsigned int index = SPRSURF_TO_PIPE(offset); 630 i915_reg_t surflive_reg = SPRSURFLIVE(index); 631 int flip_event[] = { 632 [PIPE_A] = SPRITE_A_FLIP_DONE, 633 [PIPE_B] = SPRITE_B_FLIP_DONE, 634 [PIPE_C] = SPRITE_C_FLIP_DONE, 635 }; 636 637 write_vreg(vgpu, offset, p_data, bytes); 638 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 639 640 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 641 return 0; 642 } 643 644 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 645 unsigned int reg) 646 { 647 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 648 enum intel_gvt_event_type event; 649 650 if (reg == _DPA_AUX_CH_CTL) 651 event = AUX_CHANNEL_A; 652 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 653 event = AUX_CHANNEL_B; 654 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 655 event = AUX_CHANNEL_C; 656 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 657 event = AUX_CHANNEL_D; 658 else { 659 WARN_ON(true); 660 return -EINVAL; 661 } 662 663 intel_vgpu_trigger_virtual_event(vgpu, event); 664 return 0; 665 } 666 667 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 668 unsigned int reg, int len, bool data_valid) 669 { 670 /* mark transaction done */ 671 value |= DP_AUX_CH_CTL_DONE; 672 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 673 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 674 675 if (data_valid) 676 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 677 else 678 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 679 680 /* message size */ 681 value &= ~(0xf << 20); 682 value |= (len << 20); 683 vgpu_vreg(vgpu, reg) = value; 684 685 if (value & DP_AUX_CH_CTL_INTERRUPT) 686 return trigger_aux_channel_interrupt(vgpu, reg); 687 return 0; 688 } 689 690 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 691 uint8_t t) 692 { 693 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 694 /* training pattern 1 for CR */ 695 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 696 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 697 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 698 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 699 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 700 DPCD_TRAINING_PATTERN_2) { 701 /* training pattern 2 for EQ */ 702 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 703 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 704 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 705 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 706 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 707 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 708 /* set INTERLANE_ALIGN_DONE */ 709 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 710 DPCD_INTERLANE_ALIGN_DONE; 711 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 712 DPCD_LINK_TRAINING_DISABLED) { 713 /* finish link training */ 714 /* set sink status as synchronized */ 715 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 716 } 717 } 718 719 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 720 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 721 722 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 723 724 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 725 726 #define dpy_is_valid_port(port) \ 727 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 728 729 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 730 unsigned int offset, void *p_data, unsigned int bytes) 731 { 732 struct intel_vgpu_display *display = &vgpu->display; 733 int msg, addr, ctrl, op, len; 734 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 735 struct intel_vgpu_dpcd_data *dpcd = NULL; 736 struct intel_vgpu_port *port = NULL; 737 u32 data; 738 739 if (!dpy_is_valid_port(port_index)) { 740 gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id); 741 return 0; 742 } 743 744 write_vreg(vgpu, offset, p_data, bytes); 745 data = vgpu_vreg(vgpu, offset); 746 747 if (IS_SKYLAKE(vgpu->gvt->dev_priv) && 748 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 749 /* SKL DPB/C/D aux ctl register changed */ 750 return 0; 751 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 752 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 753 /* write to the data registers */ 754 return 0; 755 } 756 757 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 758 /* just want to clear the sticky bits */ 759 vgpu_vreg(vgpu, offset) = 0; 760 return 0; 761 } 762 763 port = &display->ports[port_index]; 764 dpcd = port->dpcd; 765 766 /* read out message from DATA1 register */ 767 msg = vgpu_vreg(vgpu, offset + 4); 768 addr = (msg >> 8) & 0xffff; 769 ctrl = (msg >> 24) & 0xff; 770 len = msg & 0xff; 771 op = ctrl >> 4; 772 773 if (op == GVT_AUX_NATIVE_WRITE) { 774 int t; 775 uint8_t buf[16]; 776 777 if ((addr + len + 1) >= DPCD_SIZE) { 778 /* 779 * Write request exceeds what we supported, 780 * DCPD spec: When a Source Device is writing a DPCD 781 * address not supported by the Sink Device, the Sink 782 * Device shall reply with AUX NACK and “M” equal to 783 * zero. 784 */ 785 786 /* NAK the write */ 787 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 788 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 789 return 0; 790 } 791 792 /* 793 * Write request format: (command + address) occupies 794 * 3 bytes, followed by (len + 1) bytes of data. 795 */ 796 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 797 return -EINVAL; 798 799 /* unpack data from vreg to buf */ 800 for (t = 0; t < 4; t++) { 801 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 802 803 buf[t * 4] = (r >> 24) & 0xff; 804 buf[t * 4 + 1] = (r >> 16) & 0xff; 805 buf[t * 4 + 2] = (r >> 8) & 0xff; 806 buf[t * 4 + 3] = r & 0xff; 807 } 808 809 /* write to virtual DPCD */ 810 if (dpcd && dpcd->data_valid) { 811 for (t = 0; t <= len; t++) { 812 int p = addr + t; 813 814 dpcd->data[p] = buf[t]; 815 /* check for link training */ 816 if (p == DPCD_TRAINING_PATTERN_SET) 817 dp_aux_ch_ctl_link_training(dpcd, 818 buf[t]); 819 } 820 } 821 822 /* ACK the write */ 823 vgpu_vreg(vgpu, offset + 4) = 0; 824 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 825 dpcd && dpcd->data_valid); 826 return 0; 827 } 828 829 if (op == GVT_AUX_NATIVE_READ) { 830 int idx, i, ret = 0; 831 832 if ((addr + len + 1) >= DPCD_SIZE) { 833 /* 834 * read request exceeds what we supported 835 * DPCD spec: A Sink Device receiving a Native AUX CH 836 * read request for an unsupported DPCD address must 837 * reply with an AUX ACK and read data set equal to 838 * zero instead of replying with AUX NACK. 839 */ 840 841 /* ACK the READ*/ 842 vgpu_vreg(vgpu, offset + 4) = 0; 843 vgpu_vreg(vgpu, offset + 8) = 0; 844 vgpu_vreg(vgpu, offset + 12) = 0; 845 vgpu_vreg(vgpu, offset + 16) = 0; 846 vgpu_vreg(vgpu, offset + 20) = 0; 847 848 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 849 true); 850 return 0; 851 } 852 853 for (idx = 1; idx <= 5; idx++) { 854 /* clear the data registers */ 855 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 856 } 857 858 /* 859 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 860 */ 861 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 862 return -EINVAL; 863 864 /* read from virtual DPCD to vreg */ 865 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 866 if (dpcd && dpcd->data_valid) { 867 for (i = 1; i <= (len + 1); i++) { 868 int t; 869 870 t = dpcd->data[addr + i - 1]; 871 t <<= (24 - 8 * (i % 4)); 872 ret |= t; 873 874 if ((i % 4 == 3) || (i == (len + 1))) { 875 vgpu_vreg(vgpu, offset + 876 (i / 4 + 1) * 4) = ret; 877 ret = 0; 878 } 879 } 880 } 881 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 882 dpcd && dpcd->data_valid); 883 return 0; 884 } 885 886 /* i2c transaction starts */ 887 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 888 889 if (data & DP_AUX_CH_CTL_INTERRUPT) 890 trigger_aux_channel_interrupt(vgpu, offset); 891 return 0; 892 } 893 894 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 895 void *p_data, unsigned int bytes) 896 { 897 bool vga_disable; 898 899 write_vreg(vgpu, offset, p_data, bytes); 900 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 901 902 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 903 vga_disable ? "Disable" : "Enable"); 904 return 0; 905 } 906 907 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 908 unsigned int sbi_offset) 909 { 910 struct intel_vgpu_display *display = &vgpu->display; 911 int num = display->sbi.number; 912 int i; 913 914 for (i = 0; i < num; ++i) 915 if (display->sbi.registers[i].offset == sbi_offset) 916 break; 917 918 if (i == num) 919 return 0; 920 921 return display->sbi.registers[i].value; 922 } 923 924 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 925 unsigned int offset, u32 value) 926 { 927 struct intel_vgpu_display *display = &vgpu->display; 928 int num = display->sbi.number; 929 int i; 930 931 for (i = 0; i < num; ++i) { 932 if (display->sbi.registers[i].offset == offset) 933 break; 934 } 935 936 if (i == num) { 937 if (num == SBI_REG_MAX) { 938 gvt_err("vgpu%d: SBI caching meets maximum limits\n", 939 vgpu->id); 940 return; 941 } 942 display->sbi.number++; 943 } 944 945 display->sbi.registers[i].offset = offset; 946 display->sbi.registers[i].value = value; 947 } 948 949 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 950 void *p_data, unsigned int bytes) 951 { 952 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 953 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 954 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 955 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 956 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 957 sbi_offset); 958 } 959 read_vreg(vgpu, offset, p_data, bytes); 960 return 0; 961 } 962 963 static bool sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 964 void *p_data, unsigned int bytes) 965 { 966 u32 data; 967 968 write_vreg(vgpu, offset, p_data, bytes); 969 data = vgpu_vreg(vgpu, offset); 970 971 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 972 data |= SBI_READY; 973 974 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 975 data |= SBI_RESPONSE_SUCCESS; 976 977 vgpu_vreg(vgpu, offset) = data; 978 979 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 980 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 981 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 982 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 983 984 write_virtual_sbi_register(vgpu, sbi_offset, 985 vgpu_vreg(vgpu, SBI_DATA)); 986 } 987 return 0; 988 } 989 990 #define _vgtif_reg(x) \ 991 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 992 993 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 994 void *p_data, unsigned int bytes) 995 { 996 bool invalid_read = false; 997 998 read_vreg(vgpu, offset, p_data, bytes); 999 1000 switch (offset) { 1001 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1002 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1003 invalid_read = true; 1004 break; 1005 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1006 _vgtif_reg(avail_rs.fence_num): 1007 if (offset + bytes > 1008 _vgtif_reg(avail_rs.fence_num) + 4) 1009 invalid_read = true; 1010 break; 1011 case 0x78010: /* vgt_caps */ 1012 case 0x7881c: 1013 break; 1014 default: 1015 invalid_read = true; 1016 break; 1017 } 1018 if (invalid_read) 1019 gvt_err("invalid pvinfo read: [%x:%x] = %x\n", 1020 offset, bytes, *(u32 *)p_data); 1021 return 0; 1022 } 1023 1024 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1025 { 1026 int ret = 0; 1027 1028 switch (notification) { 1029 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1030 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); 1031 break; 1032 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1033 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); 1034 break; 1035 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1036 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); 1037 break; 1038 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1039 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); 1040 break; 1041 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1042 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1043 case 1: /* Remove this in guest driver. */ 1044 break; 1045 default: 1046 gvt_err("Invalid PV notification %d\n", notification); 1047 } 1048 return ret; 1049 } 1050 1051 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1052 { 1053 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1054 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1055 char *env[3] = {NULL, NULL, NULL}; 1056 char vmid_str[20]; 1057 char display_ready_str[20]; 1058 1059 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready); 1060 env[0] = display_ready_str; 1061 1062 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1063 env[1] = vmid_str; 1064 1065 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1066 } 1067 1068 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1069 void *p_data, unsigned int bytes) 1070 { 1071 u32 data; 1072 int ret; 1073 1074 write_vreg(vgpu, offset, p_data, bytes); 1075 data = vgpu_vreg(vgpu, offset); 1076 1077 switch (offset) { 1078 case _vgtif_reg(display_ready): 1079 send_display_ready_uevent(vgpu, data ? 1 : 0); 1080 break; 1081 case _vgtif_reg(g2v_notify): 1082 ret = handle_g2v_notification(vgpu, data); 1083 break; 1084 /* add xhot and yhot to handled list to avoid error log */ 1085 case 0x78830: 1086 case 0x78834: 1087 case _vgtif_reg(pdp[0].lo): 1088 case _vgtif_reg(pdp[0].hi): 1089 case _vgtif_reg(pdp[1].lo): 1090 case _vgtif_reg(pdp[1].hi): 1091 case _vgtif_reg(pdp[2].lo): 1092 case _vgtif_reg(pdp[2].hi): 1093 case _vgtif_reg(pdp[3].lo): 1094 case _vgtif_reg(pdp[3].hi): 1095 case _vgtif_reg(execlist_context_descriptor_lo): 1096 case _vgtif_reg(execlist_context_descriptor_hi): 1097 break; 1098 default: 1099 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n", 1100 offset, bytes, data); 1101 break; 1102 } 1103 return 0; 1104 } 1105 1106 static int pf_write(struct intel_vgpu *vgpu, 1107 unsigned int offset, void *p_data, unsigned int bytes) 1108 { 1109 u32 val = *(u32 *)p_data; 1110 1111 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1112 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1113 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1114 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1115 vgpu->id); 1116 return 0; 1117 } 1118 1119 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1120 } 1121 1122 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1123 unsigned int offset, void *p_data, unsigned int bytes) 1124 { 1125 write_vreg(vgpu, offset, p_data, bytes); 1126 1127 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) 1128 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; 1129 else 1130 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; 1131 return 0; 1132 } 1133 1134 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1135 unsigned int offset, void *p_data, unsigned int bytes) 1136 { 1137 write_vreg(vgpu, offset, p_data, bytes); 1138 1139 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1140 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1141 return 0; 1142 } 1143 1144 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1145 void *p_data, unsigned int bytes) 1146 { 1147 u32 mode = *(u32 *)p_data; 1148 1149 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1150 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n", 1151 vgpu->id); 1152 return 0; 1153 } 1154 1155 return 0; 1156 } 1157 1158 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1159 void *p_data, unsigned int bytes) 1160 { 1161 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1162 u32 trtte = *(u32 *)p_data; 1163 1164 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1165 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1166 vgpu->id); 1167 return -EINVAL; 1168 } 1169 write_vreg(vgpu, offset, p_data, bytes); 1170 /* TRTTE is not per-context */ 1171 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1172 1173 return 0; 1174 } 1175 1176 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1177 void *p_data, unsigned int bytes) 1178 { 1179 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1180 u32 val = *(u32 *)p_data; 1181 1182 if (val & 1) { 1183 /* unblock hw logic */ 1184 I915_WRITE(_MMIO(offset), val); 1185 } 1186 write_vreg(vgpu, offset, p_data, bytes); 1187 return 0; 1188 } 1189 1190 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1191 void *p_data, unsigned int bytes) 1192 { 1193 u32 v = 0; 1194 1195 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1196 v |= (1 << 0); 1197 1198 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1199 v |= (1 << 8); 1200 1201 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1202 v |= (1 << 16); 1203 1204 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1205 v |= (1 << 24); 1206 1207 vgpu_vreg(vgpu, offset) = v; 1208 1209 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1210 } 1211 1212 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1213 void *p_data, unsigned int bytes) 1214 { 1215 u32 value = *(u32 *)p_data; 1216 u32 cmd = value & 0xff; 1217 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); 1218 1219 switch (cmd) { 1220 case 0x6: 1221 /** 1222 * "Read memory latency" command on gen9. 1223 * Below memory latency values are read 1224 * from skylake platform. 1225 */ 1226 if (!*data0) 1227 *data0 = 0x1e1a1100; 1228 else 1229 *data0 = 0x61514b3d; 1230 break; 1231 case 0x5: 1232 *data0 |= 0x1; 1233 break; 1234 } 1235 1236 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1237 vgpu->id, value, *data0); 1238 1239 value &= ~(1 << 31); 1240 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1241 } 1242 1243 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1244 unsigned int offset, void *p_data, unsigned int bytes) 1245 { 1246 u32 v = *(u32 *)p_data; 1247 1248 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1249 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1250 v |= (v >> 1); 1251 1252 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1253 } 1254 1255 static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1256 void *p_data, unsigned int bytes) 1257 { 1258 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1259 i915_reg_t reg = {.reg = offset}; 1260 1261 switch (offset) { 1262 case 0x4ddc: 1263 vgpu_vreg(vgpu, offset) = 0x8000003c; 1264 break; 1265 case 0x42080: 1266 vgpu_vreg(vgpu, offset) = 0x8000; 1267 break; 1268 default: 1269 return -EINVAL; 1270 } 1271 1272 /** 1273 * TODO: need detect stepping info after gvt contain such information 1274 * 0x4ddc enabled after C0, 0x42080 enabled after E0. 1275 */ 1276 I915_WRITE(reg, vgpu_vreg(vgpu, offset)); 1277 return 0; 1278 } 1279 1280 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1281 void *p_data, unsigned int bytes) 1282 { 1283 u32 v = *(u32 *)p_data; 1284 1285 /* other bits are MBZ. */ 1286 v &= (1 << 31) | (1 << 30); 1287 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1288 1289 vgpu_vreg(vgpu, offset) = v; 1290 1291 return 0; 1292 } 1293 1294 static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu, 1295 unsigned int offset, void *p_data, unsigned int bytes) 1296 { 1297 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1298 1299 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1300 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1301 } 1302 1303 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1304 void *p_data, unsigned int bytes) 1305 { 1306 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1307 struct intel_vgpu_execlist *execlist; 1308 u32 data = *(u32 *)p_data; 1309 int ret; 1310 1311 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1)) 1312 return -EINVAL; 1313 1314 execlist = &vgpu->execlist[ring_id]; 1315 1316 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data; 1317 if (execlist->elsp_dwords.index == 3) 1318 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1319 1320 ++execlist->elsp_dwords.index; 1321 execlist->elsp_dwords.index &= 0x3; 1322 return 0; 1323 } 1324 1325 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1326 void *p_data, unsigned int bytes) 1327 { 1328 u32 data = *(u32 *)p_data; 1329 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1330 bool enable_execlist; 1331 1332 write_vreg(vgpu, offset, p_data, bytes); 1333 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1334 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1335 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1336 1337 gvt_dbg_core("EXECLIST %s on ring %d\n", 1338 (enable_execlist ? "enabling" : "disabling"), 1339 ring_id); 1340 1341 if (enable_execlist) 1342 intel_vgpu_start_schedule(vgpu); 1343 } 1344 return 0; 1345 } 1346 1347 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1348 unsigned int offset, void *p_data, unsigned int bytes) 1349 { 1350 int rc = 0; 1351 unsigned int id = 0; 1352 1353 switch (offset) { 1354 case 0x4260: 1355 id = RCS; 1356 break; 1357 case 0x4264: 1358 id = VCS; 1359 break; 1360 case 0x4268: 1361 id = VCS2; 1362 break; 1363 case 0x426c: 1364 id = BCS; 1365 break; 1366 case 0x4270: 1367 id = VECS; 1368 break; 1369 default: 1370 rc = -EINVAL; 1371 break; 1372 } 1373 set_bit(id, (void *)vgpu->tlb_handle_pending); 1374 1375 return rc; 1376 } 1377 1378 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1379 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 1380 f, s, am, rm, d, r, w); \ 1381 if (ret) \ 1382 return ret; \ 1383 } while (0) 1384 1385 #define MMIO_D(reg, d) \ 1386 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1387 1388 #define MMIO_DH(reg, d, r, w) \ 1389 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1390 1391 #define MMIO_DFH(reg, d, f, r, w) \ 1392 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1393 1394 #define MMIO_GM(reg, d, r, w) \ 1395 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1396 1397 #define MMIO_RO(reg, d, f, rm, r, w) \ 1398 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1399 1400 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1401 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1402 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1403 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1404 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1405 } while (0) 1406 1407 #define MMIO_RING_D(prefix, d) \ 1408 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1409 1410 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1411 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1412 1413 #define MMIO_RING_GM(prefix, d, r, w) \ 1414 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1415 1416 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1417 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1418 1419 static int init_generic_mmio_info(struct intel_gvt *gvt) 1420 { 1421 struct drm_i915_private *dev_priv = gvt->dev_priv; 1422 int ret; 1423 1424 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1425 1426 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1427 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1428 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1429 MMIO_D(SDEISR, D_ALL); 1430 1431 MMIO_RING_D(RING_HWSTAM, D_ALL); 1432 1433 MMIO_GM(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1434 MMIO_GM(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1435 MMIO_GM(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1436 MMIO_GM(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1437 1438 #define RING_REG(base) (base + 0x28) 1439 MMIO_RING_D(RING_REG, D_ALL); 1440 #undef RING_REG 1441 1442 #define RING_REG(base) (base + 0x134) 1443 MMIO_RING_D(RING_REG, D_ALL); 1444 #undef RING_REG 1445 1446 MMIO_GM(0x2148, D_ALL, NULL, NULL); 1447 MMIO_GM(CCID, D_ALL, NULL, NULL); 1448 MMIO_GM(0x12198, D_ALL, NULL, NULL); 1449 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1450 1451 MMIO_RING_D(RING_TAIL, D_ALL); 1452 MMIO_RING_D(RING_HEAD, D_ALL); 1453 MMIO_RING_D(RING_CTL, D_ALL); 1454 MMIO_RING_D(RING_ACTHD, D_ALL); 1455 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 1456 1457 /* RING MODE */ 1458 #define RING_REG(base) (base + 0x29c) 1459 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK, NULL, ring_mode_mmio_write); 1460 #undef RING_REG 1461 1462 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1463 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL); 1464 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1465 ring_timestamp_mmio_read, NULL); 1466 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1467 ring_timestamp_mmio_read, NULL); 1468 1469 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1470 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL); 1471 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK, NULL, NULL); 1472 1473 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL); 1474 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL); 1475 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK, NULL, NULL); 1476 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK, NULL, NULL); 1477 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK, NULL, NULL); 1478 MMIO_D(GAM_ECOCHK, D_ALL); 1479 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK, NULL, NULL); 1480 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK, NULL, NULL); 1481 MMIO_D(0x9030, D_ALL); 1482 MMIO_D(0x20a0, D_ALL); 1483 MMIO_D(0x2420, D_ALL); 1484 MMIO_D(0x2430, D_ALL); 1485 MMIO_D(0x2434, D_ALL); 1486 MMIO_D(0x2438, D_ALL); 1487 MMIO_D(0x243c, D_ALL); 1488 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK, NULL, NULL); 1489 MMIO_DFH(0xe184, D_ALL, F_MODE_MASK, NULL, NULL); 1490 MMIO_DFH(0xe100, D_ALL, F_MODE_MASK, NULL, NULL); 1491 1492 /* display */ 1493 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1494 MMIO_D(0x602a0, D_ALL); 1495 1496 MMIO_D(0x65050, D_ALL); 1497 MMIO_D(0x650b4, D_ALL); 1498 1499 MMIO_D(0xc4040, D_ALL); 1500 MMIO_D(DERRMR, D_ALL); 1501 1502 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1503 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1504 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1505 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1506 1507 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1508 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1509 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1510 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1511 1512 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1513 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1514 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1515 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1516 1517 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1518 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1519 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1520 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1521 1522 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1523 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1524 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1525 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1526 1527 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1528 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1529 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1530 1531 MMIO_D(CURPOS(PIPE_A), D_ALL); 1532 MMIO_D(CURPOS(PIPE_B), D_ALL); 1533 MMIO_D(CURPOS(PIPE_C), D_ALL); 1534 1535 MMIO_D(CURBASE(PIPE_A), D_ALL); 1536 MMIO_D(CURBASE(PIPE_B), D_ALL); 1537 MMIO_D(CURBASE(PIPE_C), D_ALL); 1538 1539 MMIO_D(0x700ac, D_ALL); 1540 MMIO_D(0x710ac, D_ALL); 1541 MMIO_D(0x720ac, D_ALL); 1542 1543 MMIO_D(0x70090, D_ALL); 1544 MMIO_D(0x70094, D_ALL); 1545 MMIO_D(0x70098, D_ALL); 1546 MMIO_D(0x7009c, D_ALL); 1547 1548 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1549 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1550 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1551 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1552 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1553 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1554 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1555 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1556 1557 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1558 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1559 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1560 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1561 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1562 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1563 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1564 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1565 1566 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1567 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1568 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1569 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1570 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1571 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1572 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1573 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1574 1575 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1576 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1577 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1578 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1579 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1580 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1581 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1582 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1583 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1584 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1585 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1586 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1587 1588 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1589 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1590 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1591 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1592 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1593 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1594 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1595 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1596 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1597 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1598 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1599 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1600 1601 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1602 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1603 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1604 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1605 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1606 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1607 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1608 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1609 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1610 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1611 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1612 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1613 1614 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1615 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1616 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1617 1618 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1619 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1620 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1621 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1622 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1623 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1624 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1625 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1626 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1627 1628 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1629 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1630 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1631 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1632 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1633 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1634 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1635 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1636 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1637 1638 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1639 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1640 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1641 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1642 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1643 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1644 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1645 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1646 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1647 1648 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1649 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1650 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1651 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1652 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1653 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1654 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1655 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1656 1657 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1658 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1659 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1660 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1661 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1662 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1663 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1664 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1665 1666 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1667 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1668 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1669 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1670 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1671 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1672 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1673 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1674 1675 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1676 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1677 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1678 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1679 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1680 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1681 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1682 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1683 1684 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1685 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1686 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1687 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1688 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1689 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1690 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1691 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1692 1693 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1694 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1695 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1696 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1697 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1698 1699 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1700 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1701 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1702 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1703 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1704 1705 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1706 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1707 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1708 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1709 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1710 1711 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1712 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1713 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1714 MMIO_D(WM1_LP_ILK, D_ALL); 1715 MMIO_D(WM2_LP_ILK, D_ALL); 1716 MMIO_D(WM3_LP_ILK, D_ALL); 1717 MMIO_D(WM1S_LP_ILK, D_ALL); 1718 MMIO_D(WM2S_LP_IVB, D_ALL); 1719 MMIO_D(WM3S_LP_IVB, D_ALL); 1720 1721 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1722 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1723 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1724 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1725 1726 MMIO_D(0x48268, D_ALL); 1727 1728 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1729 gmbus_mmio_write); 1730 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1731 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1732 1733 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1734 dp_aux_ch_ctl_mmio_write); 1735 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1736 dp_aux_ch_ctl_mmio_write); 1737 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1738 dp_aux_ch_ctl_mmio_write); 1739 1740 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write); 1741 1742 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); 1743 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); 1744 1745 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1746 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1747 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1748 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1749 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1750 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1751 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1752 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1753 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1754 1755 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 1756 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 1757 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 1758 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 1759 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 1760 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 1761 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 1762 1763 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 1764 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 1765 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 1766 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 1767 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 1768 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 1769 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 1770 1771 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 1772 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 1773 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 1774 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 1775 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 1776 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 1777 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 1778 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 1779 1780 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 1781 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 1782 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 1783 1784 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 1785 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 1786 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 1787 1788 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 1789 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 1790 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 1791 1792 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 1793 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 1794 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 1795 1796 MMIO_D(_FDI_RXA_MISC, D_ALL); 1797 MMIO_D(_FDI_RXB_MISC, D_ALL); 1798 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 1799 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 1800 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 1801 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 1802 1803 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 1804 MMIO_D(PCH_PP_DIVISOR, D_ALL); 1805 MMIO_D(PCH_PP_STATUS, D_ALL); 1806 MMIO_D(PCH_LVDS, D_ALL); 1807 MMIO_D(_PCH_DPLL_A, D_ALL); 1808 MMIO_D(_PCH_DPLL_B, D_ALL); 1809 MMIO_D(_PCH_FPA0, D_ALL); 1810 MMIO_D(_PCH_FPA1, D_ALL); 1811 MMIO_D(_PCH_FPB0, D_ALL); 1812 MMIO_D(_PCH_FPB1, D_ALL); 1813 MMIO_D(PCH_DREF_CONTROL, D_ALL); 1814 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 1815 MMIO_D(PCH_DPLL_SEL, D_ALL); 1816 1817 MMIO_D(0x61208, D_ALL); 1818 MMIO_D(0x6120c, D_ALL); 1819 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 1820 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 1821 1822 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); 1823 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); 1824 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); 1825 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); 1826 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL); 1827 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL); 1828 1829 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 1830 PORTA_HOTPLUG_STATUS_MASK 1831 | PORTB_HOTPLUG_STATUS_MASK 1832 | PORTC_HOTPLUG_STATUS_MASK 1833 | PORTD_HOTPLUG_STATUS_MASK, 1834 NULL, NULL); 1835 1836 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 1837 MMIO_D(FUSE_STRAP, D_ALL); 1838 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 1839 1840 MMIO_D(DISP_ARB_CTL, D_ALL); 1841 MMIO_D(DISP_ARB_CTL2, D_ALL); 1842 1843 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 1844 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 1845 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 1846 1847 MMIO_D(SOUTH_CHICKEN1, D_ALL); 1848 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 1849 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 1850 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 1851 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 1852 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 1853 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 1854 1855 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 1856 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 1857 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 1858 MMIO_D(ILK_DPFC_STATUS, D_ALL); 1859 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 1860 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 1861 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 1862 1863 MMIO_D(IPS_CTL, D_ALL); 1864 1865 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 1866 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 1867 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 1868 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 1869 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 1870 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 1871 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 1872 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 1873 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 1874 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 1875 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 1876 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 1877 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 1878 1879 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 1880 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 1881 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 1882 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 1883 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 1884 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 1885 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 1886 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 1887 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 1888 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 1889 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 1890 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 1891 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 1892 1893 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 1894 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 1895 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 1896 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 1897 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 1898 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 1899 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 1900 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 1901 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 1902 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 1903 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 1904 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 1905 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 1906 1907 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 1908 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 1909 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1910 1911 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 1912 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 1913 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1914 1915 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 1916 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 1917 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1918 1919 MMIO_D(0x60110, D_ALL); 1920 MMIO_D(0x61110, D_ALL); 1921 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1922 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1923 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1924 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1925 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1926 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1927 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1928 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1929 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1930 1931 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 1932 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 1933 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 1934 MMIO_D(SPLL_CTL, D_ALL); 1935 MMIO_D(_WRPLL_CTL1, D_ALL); 1936 MMIO_D(_WRPLL_CTL2, D_ALL); 1937 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 1938 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 1939 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 1940 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 1941 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 1942 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 1943 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 1944 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 1945 1946 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 1947 MMIO_D(0x46508, D_ALL); 1948 1949 MMIO_D(0x49080, D_ALL); 1950 MMIO_D(0x49180, D_ALL); 1951 MMIO_D(0x49280, D_ALL); 1952 1953 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1954 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1955 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1956 1957 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 1958 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 1959 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 1960 1961 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 1962 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 1963 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 1964 1965 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 1966 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 1967 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 1968 1969 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 1970 MMIO_D(SBI_ADDR, D_ALL); 1971 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 1972 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 1973 MMIO_D(PIXCLK_GATE, D_ALL); 1974 1975 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, 1976 dp_aux_ch_ctl_mmio_write); 1977 1978 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1979 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1980 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1981 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1982 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1983 1984 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 1985 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 1986 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 1987 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 1988 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 1989 1990 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 1991 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 1992 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 1993 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 1994 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 1995 1996 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1997 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1998 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1999 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2000 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2001 2002 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2003 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2004 2005 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 2006 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 2007 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 2008 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 2009 2010 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 2011 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 2012 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 2013 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 2014 2015 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2016 MMIO_D(FORCEWAKE_ACK, D_ALL); 2017 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2018 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2019 MMIO_D(GTFIFODBG, D_ALL); 2020 MMIO_D(GTFIFOCTL, D_ALL); 2021 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2022 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL); 2023 MMIO_D(ECOBUS, D_ALL); 2024 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2025 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2026 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2027 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2028 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2029 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2030 MMIO_D(GEN6_RPSTAT1, D_ALL); 2031 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2032 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2033 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2034 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2035 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2036 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2037 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2038 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2039 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2040 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2041 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2042 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2043 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2044 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2045 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2046 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2047 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2048 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2049 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2050 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2051 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2052 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2053 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2054 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2055 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2056 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2057 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2058 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2059 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2060 2061 MMIO_D(RSTDBYCTL, D_ALL); 2062 2063 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2064 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2065 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write); 2066 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2067 2068 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL); 2069 2070 MMIO_D(TILECTL, D_ALL); 2071 2072 MMIO_D(GEN6_UCGCTL1, D_ALL); 2073 MMIO_D(GEN6_UCGCTL2, D_ALL); 2074 2075 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2076 2077 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_SKL); 2078 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2079 MMIO_D(0x13812c, D_ALL); 2080 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2081 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2082 MMIO_D(HSW_IDICR, D_ALL); 2083 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2084 2085 MMIO_D(0x3c, D_ALL); 2086 MMIO_D(0x860, D_ALL); 2087 MMIO_D(ECOSKPD, D_ALL); 2088 MMIO_D(0x121d0, D_ALL); 2089 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2090 MMIO_D(0x41d0, D_ALL); 2091 MMIO_D(GAC_ECO_BITS, D_ALL); 2092 MMIO_D(0x6200, D_ALL); 2093 MMIO_D(0x6204, D_ALL); 2094 MMIO_D(0x6208, D_ALL); 2095 MMIO_D(0x7118, D_ALL); 2096 MMIO_D(0x7180, D_ALL); 2097 MMIO_D(0x7408, D_ALL); 2098 MMIO_D(0x7c00, D_ALL); 2099 MMIO_D(GEN6_MBCTL, D_ALL); 2100 MMIO_D(0x911c, D_ALL); 2101 MMIO_D(0x9120, D_ALL); 2102 2103 MMIO_D(GAB_CTL, D_ALL); 2104 MMIO_D(0x48800, D_ALL); 2105 MMIO_D(0xce044, D_ALL); 2106 MMIO_D(0xe6500, D_ALL); 2107 MMIO_D(0xe6504, D_ALL); 2108 MMIO_D(0xe6600, D_ALL); 2109 MMIO_D(0xe6604, D_ALL); 2110 MMIO_D(0xe6700, D_ALL); 2111 MMIO_D(0xe6704, D_ALL); 2112 MMIO_D(0xe6800, D_ALL); 2113 MMIO_D(0xe6804, D_ALL); 2114 MMIO_D(PCH_GMBUS4, D_ALL); 2115 MMIO_D(PCH_GMBUS5, D_ALL); 2116 2117 MMIO_D(0x902c, D_ALL); 2118 MMIO_D(0xec008, D_ALL); 2119 MMIO_D(0xec00c, D_ALL); 2120 MMIO_D(0xec008 + 0x18, D_ALL); 2121 MMIO_D(0xec00c + 0x18, D_ALL); 2122 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 2123 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 2124 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 2125 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 2126 MMIO_D(0xec408, D_ALL); 2127 MMIO_D(0xec40c, D_ALL); 2128 MMIO_D(0xec408 + 0x18, D_ALL); 2129 MMIO_D(0xec40c + 0x18, D_ALL); 2130 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 2131 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 2132 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 2133 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 2134 MMIO_D(0xfc810, D_ALL); 2135 MMIO_D(0xfc81c, D_ALL); 2136 MMIO_D(0xfc828, D_ALL); 2137 MMIO_D(0xfc834, D_ALL); 2138 MMIO_D(0xfcc00, D_ALL); 2139 MMIO_D(0xfcc0c, D_ALL); 2140 MMIO_D(0xfcc18, D_ALL); 2141 MMIO_D(0xfcc24, D_ALL); 2142 MMIO_D(0xfd000, D_ALL); 2143 MMIO_D(0xfd00c, D_ALL); 2144 MMIO_D(0xfd018, D_ALL); 2145 MMIO_D(0xfd024, D_ALL); 2146 MMIO_D(0xfd034, D_ALL); 2147 2148 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2149 MMIO_D(0x2054, D_ALL); 2150 MMIO_D(0x12054, D_ALL); 2151 MMIO_D(0x22054, D_ALL); 2152 MMIO_D(0x1a054, D_ALL); 2153 2154 MMIO_D(0x44070, D_ALL); 2155 2156 MMIO_D(0x215c, D_HSW_PLUS); 2157 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2158 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2159 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2160 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2161 2162 MMIO_F(0x2290, 8, 0, 0, 0, D_HSW_PLUS, NULL, NULL); 2163 MMIO_D(OACONTROL, D_HSW); 2164 MMIO_D(0x2b00, D_BDW_PLUS); 2165 MMIO_D(0x2360, D_BDW_PLUS); 2166 MMIO_F(0x5200, 32, 0, 0, 0, D_ALL, NULL, NULL); 2167 MMIO_F(0x5240, 32, 0, 0, 0, D_ALL, NULL, NULL); 2168 MMIO_F(0x5280, 16, 0, 0, 0, D_ALL, NULL, NULL); 2169 2170 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2171 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2172 MMIO_D(BCS_SWCTRL, D_ALL); 2173 2174 MMIO_F(HS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2175 MMIO_F(DS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2176 MMIO_F(IA_VERTICES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2177 MMIO_F(IA_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2178 MMIO_F(VS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2179 MMIO_F(GS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2180 MMIO_F(GS_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2181 MMIO_F(CL_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2182 MMIO_F(CL_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2183 MMIO_F(PS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2184 MMIO_F(PS_DEPTH_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2185 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2186 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2187 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2188 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2189 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2190 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2191 2192 return 0; 2193 } 2194 2195 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2196 { 2197 struct drm_i915_private *dev_priv = gvt->dev_priv; 2198 int ret; 2199 2200 MMIO_DH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, 2201 intel_vgpu_reg_imr_handler); 2202 2203 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2204 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2205 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2206 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2207 2208 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2209 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2210 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2211 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2212 2213 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2214 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2215 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2216 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2217 2218 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2219 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2220 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2221 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2222 2223 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2224 intel_vgpu_reg_imr_handler); 2225 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2226 intel_vgpu_reg_ier_handler); 2227 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2228 intel_vgpu_reg_iir_handler); 2229 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2230 2231 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2232 intel_vgpu_reg_imr_handler); 2233 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2234 intel_vgpu_reg_ier_handler); 2235 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2236 intel_vgpu_reg_iir_handler); 2237 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2238 2239 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2240 intel_vgpu_reg_imr_handler); 2241 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2242 intel_vgpu_reg_ier_handler); 2243 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2244 intel_vgpu_reg_iir_handler); 2245 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2246 2247 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2248 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2249 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2250 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2251 2252 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2253 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2254 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2255 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2256 2257 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2258 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2259 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2260 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2261 2262 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2263 intel_vgpu_reg_master_irq_handler); 2264 2265 MMIO_D(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2266 MMIO_D(0x1c134, D_BDW_PLUS); 2267 2268 MMIO_D(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2269 MMIO_D(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2270 MMIO_GM(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2271 MMIO_D(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2272 MMIO_D(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2273 MMIO_D(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2274 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK, NULL, ring_mode_mmio_write); 2275 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2276 NULL, NULL); 2277 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2278 NULL, NULL); 2279 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2280 ring_timestamp_mmio_read, NULL); 2281 2282 MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS); 2283 2284 #define RING_REG(base) (base + 0x230) 2285 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2286 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write); 2287 #undef RING_REG 2288 2289 #define RING_REG(base) (base + 0x234) 2290 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2291 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, ~0LL, D_BDW_PLUS, NULL, NULL); 2292 #undef RING_REG 2293 2294 #define RING_REG(base) (base + 0x244) 2295 MMIO_RING_D(RING_REG, D_BDW_PLUS); 2296 MMIO_D(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2297 #undef RING_REG 2298 2299 #define RING_REG(base) (base + 0x370) 2300 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2301 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS, 2302 NULL, NULL); 2303 #undef RING_REG 2304 2305 #define RING_REG(base) (base + 0x3a0) 2306 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2307 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2308 #undef RING_REG 2309 2310 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2311 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2312 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2313 MMIO_D(0x1c1d0, D_BDW_PLUS); 2314 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2315 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2316 MMIO_D(0x1c054, D_BDW_PLUS); 2317 2318 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2319 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2320 2321 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2322 2323 #define RING_REG(base) (base + 0x270) 2324 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2325 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2326 #undef RING_REG 2327 2328 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); 2329 MMIO_GM(0x1c080, D_BDW_PLUS, NULL, NULL); 2330 2331 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2332 2333 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW); 2334 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW); 2335 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW); 2336 2337 MMIO_D(WM_MISC, D_BDW); 2338 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 2339 2340 MMIO_D(0x66c00, D_BDW_PLUS); 2341 MMIO_D(0x66c04, D_BDW_PLUS); 2342 2343 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2344 2345 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2346 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2347 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2348 2349 MMIO_D(0xfdc, D_BDW); 2350 MMIO_D(GEN8_ROW_CHICKEN, D_BDW_PLUS); 2351 MMIO_D(GEN7_ROW_CHICKEN2, D_BDW_PLUS); 2352 MMIO_D(GEN8_UCGCTL6, D_BDW_PLUS); 2353 2354 MMIO_D(0xb1f0, D_BDW); 2355 MMIO_D(0xb1c0, D_BDW); 2356 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2357 MMIO_D(0xb100, D_BDW); 2358 MMIO_D(0xb10c, D_BDW); 2359 MMIO_D(0xb110, D_BDW); 2360 2361 MMIO_DH(0x24d0, D_BDW_PLUS, NULL, NULL); 2362 MMIO_DH(0x24d4, D_BDW_PLUS, NULL, NULL); 2363 MMIO_DH(0x24d8, D_BDW_PLUS, NULL, NULL); 2364 MMIO_DH(0x24dc, D_BDW_PLUS, NULL, NULL); 2365 2366 MMIO_D(0x83a4, D_BDW); 2367 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2368 2369 MMIO_D(0x8430, D_BDW); 2370 2371 MMIO_D(0x110000, D_BDW_PLUS); 2372 2373 MMIO_D(0x48400, D_BDW_PLUS); 2374 2375 MMIO_D(0x6e570, D_BDW_PLUS); 2376 MMIO_D(0x65f10, D_BDW_PLUS); 2377 2378 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2379 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2380 MMIO_DFH(0xe180, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2381 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2382 2383 MMIO_D(0x2248, D_BDW); 2384 2385 return 0; 2386 } 2387 2388 static int init_skl_mmio_info(struct intel_gvt *gvt) 2389 { 2390 struct drm_i915_private *dev_priv = gvt->dev_priv; 2391 int ret; 2392 2393 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2394 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2395 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2396 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2397 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2398 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2399 2400 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2401 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2402 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2403 2404 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL); 2405 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write); 2406 2407 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, mailbox_write); 2408 MMIO_D(0xa210, D_SKL_PLUS); 2409 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2410 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2411 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write); 2412 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write); 2413 MMIO_D(0x45504, D_SKL); 2414 MMIO_D(0x45520, D_SKL); 2415 MMIO_D(0x46000, D_SKL); 2416 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write); 2417 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write); 2418 MMIO_D(0x6C040, D_SKL); 2419 MMIO_D(0x6C048, D_SKL); 2420 MMIO_D(0x6C050, D_SKL); 2421 MMIO_D(0x6C044, D_SKL); 2422 MMIO_D(0x6C04C, D_SKL); 2423 MMIO_D(0x6C054, D_SKL); 2424 MMIO_D(0x6c058, D_SKL); 2425 MMIO_D(0x6c05c, D_SKL); 2426 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL); 2427 2428 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write); 2429 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write); 2430 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write); 2431 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write); 2432 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write); 2433 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write); 2434 2435 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write); 2436 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write); 2437 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write); 2438 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write); 2439 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write); 2440 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write); 2441 2442 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write); 2443 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write); 2444 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write); 2445 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write); 2446 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write); 2447 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write); 2448 2449 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2450 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2451 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2452 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2453 2454 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2455 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2456 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2457 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2458 2459 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2460 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2461 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2462 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2463 2464 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL); 2465 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL); 2466 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL); 2467 2468 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2469 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2470 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2471 2472 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2473 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2474 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2475 2476 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2477 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2478 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2479 2480 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2481 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2482 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2483 2484 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL); 2485 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL); 2486 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL); 2487 2488 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL); 2489 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL); 2490 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL); 2491 2492 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL); 2493 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL); 2494 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL); 2495 2496 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL); 2497 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL); 2498 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL); 2499 2500 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2501 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2502 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2503 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2504 2505 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2506 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2507 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2508 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2509 2510 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2511 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2512 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2513 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2514 2515 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL); 2516 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL); 2517 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL); 2518 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL); 2519 2520 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL); 2521 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL); 2522 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL); 2523 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL); 2524 2525 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL); 2526 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL); 2527 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL); 2528 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL); 2529 2530 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL); 2531 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL); 2532 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL); 2533 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL); 2534 2535 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL); 2536 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL); 2537 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL); 2538 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL); 2539 2540 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL); 2541 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL); 2542 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL); 2543 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL); 2544 2545 MMIO_D(0x70380, D_SKL); 2546 MMIO_D(0x71380, D_SKL); 2547 MMIO_D(0x72380, D_SKL); 2548 MMIO_D(0x7039c, D_SKL); 2549 2550 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL); 2551 MMIO_D(0x8f074, D_SKL); 2552 MMIO_D(0x8f004, D_SKL); 2553 MMIO_D(0x8f034, D_SKL); 2554 2555 MMIO_D(0xb11c, D_SKL); 2556 2557 MMIO_D(0x51000, D_SKL); 2558 MMIO_D(0x6c00c, D_SKL); 2559 2560 MMIO_F(0xc800, 0x7f8, 0, 0, 0, D_SKL, NULL, NULL); 2561 MMIO_F(0xb020, 0x80, 0, 0, 0, D_SKL, NULL, NULL); 2562 2563 MMIO_D(0xd08, D_SKL); 2564 MMIO_D(0x20e0, D_SKL); 2565 MMIO_D(0x20ec, D_SKL); 2566 2567 /* TRTT */ 2568 MMIO_D(0x4de0, D_SKL); 2569 MMIO_D(0x4de4, D_SKL); 2570 MMIO_D(0x4de8, D_SKL); 2571 MMIO_D(0x4dec, D_SKL); 2572 MMIO_D(0x4df0, D_SKL); 2573 MMIO_DH(0x4df4, D_SKL, NULL, gen9_trtte_write); 2574 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write); 2575 2576 MMIO_D(0x45008, D_SKL); 2577 2578 MMIO_D(0x46430, D_SKL); 2579 2580 MMIO_D(0x46520, D_SKL); 2581 2582 MMIO_D(0xc403c, D_SKL); 2583 MMIO_D(0xb004, D_SKL); 2584 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2585 2586 MMIO_D(0x65900, D_SKL); 2587 MMIO_D(0x1082c0, D_SKL); 2588 MMIO_D(0x4068, D_SKL); 2589 MMIO_D(0x67054, D_SKL); 2590 MMIO_D(0x6e560, D_SKL); 2591 MMIO_D(0x6e554, D_SKL); 2592 MMIO_D(0x2b20, D_SKL); 2593 MMIO_D(0x65f00, D_SKL); 2594 MMIO_D(0x65f08, D_SKL); 2595 MMIO_D(0x320f0, D_SKL); 2596 2597 MMIO_D(_REG_VCS2_EXCC, D_SKL); 2598 MMIO_D(0x70034, D_SKL); 2599 MMIO_D(0x71034, D_SKL); 2600 MMIO_D(0x72034, D_SKL); 2601 2602 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL); 2603 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL); 2604 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL); 2605 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL); 2606 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL); 2607 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL); 2608 2609 MMIO_D(0x44500, D_SKL); 2610 return 0; 2611 } 2612 2613 /** 2614 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset 2615 * @gvt: GVT device 2616 * @offset: register offset 2617 * 2618 * This function is used to find the MMIO information entry from hash table 2619 * 2620 * Returns: 2621 * pointer to MMIO information entry, NULL if not exists 2622 */ 2623 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 2624 unsigned int offset) 2625 { 2626 struct intel_gvt_mmio_info *e; 2627 2628 WARN_ON(!IS_ALIGNED(offset, 4)); 2629 2630 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 2631 if (e->offset == offset) 2632 return e; 2633 } 2634 return NULL; 2635 } 2636 2637 /** 2638 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2639 * @gvt: GVT device 2640 * 2641 * This function is called at the driver unloading stage, to clean up the MMIO 2642 * information table of GVT device 2643 * 2644 */ 2645 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2646 { 2647 struct hlist_node *tmp; 2648 struct intel_gvt_mmio_info *e; 2649 int i; 2650 2651 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2652 kfree(e); 2653 2654 vfree(gvt->mmio.mmio_attribute); 2655 gvt->mmio.mmio_attribute = NULL; 2656 } 2657 2658 /** 2659 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2660 * @gvt: GVT device 2661 * 2662 * This function is called at the initialization stage, to setup the MMIO 2663 * information table for GVT device 2664 * 2665 * Returns: 2666 * zero on success, negative if failed. 2667 */ 2668 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2669 { 2670 struct intel_gvt_device_info *info = &gvt->device_info; 2671 struct drm_i915_private *dev_priv = gvt->dev_priv; 2672 int ret; 2673 2674 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size); 2675 if (!gvt->mmio.mmio_attribute) 2676 return -ENOMEM; 2677 2678 ret = init_generic_mmio_info(gvt); 2679 if (ret) 2680 goto err; 2681 2682 if (IS_BROADWELL(dev_priv)) { 2683 ret = init_broadwell_mmio_info(gvt); 2684 if (ret) 2685 goto err; 2686 } else if (IS_SKYLAKE(dev_priv)) { 2687 ret = init_broadwell_mmio_info(gvt); 2688 if (ret) 2689 goto err; 2690 ret = init_skl_mmio_info(gvt); 2691 if (ret) 2692 goto err; 2693 } 2694 return 0; 2695 err: 2696 intel_gvt_clean_mmio_info(gvt); 2697 return ret; 2698 } 2699 2700 /** 2701 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 2702 * @gvt: a GVT device 2703 * @offset: register offset 2704 * 2705 */ 2706 void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset) 2707 { 2708 gvt->mmio.mmio_attribute[offset >> 2] |= 2709 F_ACCESSED; 2710 } 2711 2712 /** 2713 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 2714 * @gvt: a GVT device 2715 * @offset: register offset 2716 * 2717 */ 2718 bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt, 2719 unsigned int offset) 2720 { 2721 return gvt->mmio.mmio_attribute[offset >> 2] & 2722 F_CMD_ACCESS; 2723 } 2724 2725 /** 2726 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 2727 * @gvt: a GVT device 2728 * @offset: register offset 2729 * 2730 */ 2731 bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, 2732 unsigned int offset) 2733 { 2734 return gvt->mmio.mmio_attribute[offset >> 2] & 2735 F_UNALIGN; 2736 } 2737 2738 /** 2739 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 2740 * @gvt: a GVT device 2741 * @offset: register offset 2742 * 2743 */ 2744 void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt, 2745 unsigned int offset) 2746 { 2747 gvt->mmio.mmio_attribute[offset >> 2] |= 2748 F_CMD_ACCESSED; 2749 } 2750 2751 /** 2752 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 2753 * @gvt: a GVT device 2754 * @offset: register offset 2755 * 2756 * Returns: 2757 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 2758 * 2759 */ 2760 bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset) 2761 { 2762 return gvt->mmio.mmio_attribute[offset >> 2] & 2763 F_MODE_MASK; 2764 } 2765 2766 /** 2767 * intel_vgpu_default_mmio_read - default MMIO read handler 2768 * @vgpu: a vGPU 2769 * @offset: access offset 2770 * @p_data: data return buffer 2771 * @bytes: access data length 2772 * 2773 * Returns: 2774 * Zero on success, negative error code if failed. 2775 */ 2776 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 2777 void *p_data, unsigned int bytes) 2778 { 2779 read_vreg(vgpu, offset, p_data, bytes); 2780 return 0; 2781 } 2782 2783 /** 2784 * intel_t_default_mmio_write - default MMIO write handler 2785 * @vgpu: a vGPU 2786 * @offset: access offset 2787 * @p_data: write data buffer 2788 * @bytes: access data length 2789 * 2790 * Returns: 2791 * Zero on success, negative error code if failed. 2792 */ 2793 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2794 void *p_data, unsigned int bytes) 2795 { 2796 write_vreg(vgpu, offset, p_data, bytes); 2797 return 0; 2798 } 2799