1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 41 /* XXX FIXME i915 has changed PP_XXX definition */ 42 #define PCH_PP_STATUS _MMIO(0xc7200) 43 #define PCH_PP_CONTROL _MMIO(0xc7204) 44 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 45 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 46 #define PCH_PP_DIVISOR _MMIO(0xc7210) 47 48 /* Register contains RO bits */ 49 #define F_RO (1 << 0) 50 /* Register contains graphics address */ 51 #define F_GMADR (1 << 1) 52 /* Mode mask registers with high 16 bits as the mask bits */ 53 #define F_MODE_MASK (1 << 2) 54 /* This reg can be accessed by GPU commands */ 55 #define F_CMD_ACCESS (1 << 3) 56 /* This reg has been accessed by a VM */ 57 #define F_ACCESSED (1 << 4) 58 /* This reg has been accessed through GPU commands */ 59 #define F_CMD_ACCESSED (1 << 5) 60 /* This reg could be accessed by unaligned address */ 61 #define F_UNALIGN (1 << 6) 62 63 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 64 { 65 if (IS_BROADWELL(gvt->dev_priv)) 66 return D_BDW; 67 else if (IS_SKYLAKE(gvt->dev_priv)) 68 return D_SKL; 69 70 return 0; 71 } 72 73 bool intel_gvt_match_device(struct intel_gvt *gvt, 74 unsigned long device) 75 { 76 return intel_gvt_get_device_type(gvt) & device; 77 } 78 79 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 80 void *p_data, unsigned int bytes) 81 { 82 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 83 } 84 85 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 86 void *p_data, unsigned int bytes) 87 { 88 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 89 } 90 91 static int new_mmio_info(struct intel_gvt *gvt, 92 u32 offset, u32 flags, u32 size, 93 u32 addr_mask, u32 ro_mask, u32 device, 94 void *read, void *write) 95 { 96 struct intel_gvt_mmio_info *info, *p; 97 u32 start, end, i; 98 99 if (!intel_gvt_match_device(gvt, device)) 100 return 0; 101 102 if (WARN_ON(!IS_ALIGNED(offset, 4))) 103 return -EINVAL; 104 105 start = offset; 106 end = offset + size; 107 108 for (i = start; i < end; i += 4) { 109 info = kzalloc(sizeof(*info), GFP_KERNEL); 110 if (!info) 111 return -ENOMEM; 112 113 info->offset = i; 114 p = intel_gvt_find_mmio_info(gvt, info->offset); 115 if (p) 116 gvt_err("dup mmio definition offset %x\n", 117 info->offset); 118 info->size = size; 119 info->length = (i + 4) < end ? 4 : (end - i); 120 info->addr_mask = addr_mask; 121 info->device = device; 122 info->read = read ? read : intel_vgpu_default_mmio_read; 123 info->write = write ? write : intel_vgpu_default_mmio_write; 124 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 125 INIT_HLIST_NODE(&info->node); 126 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 127 } 128 return 0; 129 } 130 131 static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) 132 { 133 int i; 134 135 reg &= ~GENMASK(11, 0); 136 for (i = 0; i < I915_NUM_ENGINES; i++) { 137 if (gvt->dev_priv->engine[i].mmio_base == reg) 138 return i; 139 } 140 return -1; 141 } 142 143 #define offset_to_fence_num(offset) \ 144 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 145 146 #define fence_num_to_offset(num) \ 147 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 148 149 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 150 unsigned int fence_num, void *p_data, unsigned int bytes) 151 { 152 if (fence_num >= vgpu_fence_sz(vgpu)) { 153 gvt_err("vgpu%d: found oob fence register access\n", 154 vgpu->id); 155 gvt_err("vgpu%d: total fence num %d access fence num %d\n", 156 vgpu->id, vgpu_fence_sz(vgpu), fence_num); 157 memset(p_data, 0, bytes); 158 } 159 return 0; 160 } 161 162 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 163 void *p_data, unsigned int bytes) 164 { 165 int ret; 166 167 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 168 p_data, bytes); 169 if (ret) 170 return ret; 171 read_vreg(vgpu, off, p_data, bytes); 172 return 0; 173 } 174 175 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 176 void *p_data, unsigned int bytes) 177 { 178 unsigned int fence_num = offset_to_fence_num(off); 179 int ret; 180 181 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 182 if (ret) 183 return ret; 184 write_vreg(vgpu, off, p_data, bytes); 185 186 intel_vgpu_write_fence(vgpu, fence_num, 187 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 188 return 0; 189 } 190 191 #define CALC_MODE_MASK_REG(old, new) \ 192 (((new) & GENMASK(31, 16)) \ 193 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 194 | ((new) & ((new) >> 16)))) 195 196 static int mul_force_wake_write(struct intel_vgpu *vgpu, 197 unsigned int offset, void *p_data, unsigned int bytes) 198 { 199 u32 old, new; 200 uint32_t ack_reg_offset; 201 202 old = vgpu_vreg(vgpu, offset); 203 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 204 205 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) { 206 switch (offset) { 207 case FORCEWAKE_RENDER_GEN9_REG: 208 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 209 break; 210 case FORCEWAKE_BLITTER_GEN9_REG: 211 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 212 break; 213 case FORCEWAKE_MEDIA_GEN9_REG: 214 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 215 break; 216 default: 217 /*should not hit here*/ 218 gvt_err("invalid forcewake offset 0x%x\n", offset); 219 return 1; 220 } 221 } else { 222 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 223 } 224 225 vgpu_vreg(vgpu, offset) = new; 226 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 227 return 0; 228 } 229 230 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 231 void *p_data, unsigned int bytes) 232 { 233 u32 data; 234 u32 bitmap = 0; 235 236 data = vgpu_vreg(vgpu, offset); 237 238 if (data & GEN6_GRDOM_FULL) { 239 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 240 bitmap = 0xff; 241 } 242 if (data & GEN6_GRDOM_RENDER) { 243 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 244 bitmap |= (1 << RCS); 245 } 246 if (data & GEN6_GRDOM_MEDIA) { 247 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 248 bitmap |= (1 << VCS); 249 } 250 if (data & GEN6_GRDOM_BLT) { 251 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 252 bitmap |= (1 << BCS); 253 } 254 if (data & GEN6_GRDOM_VECS) { 255 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 256 bitmap |= (1 << VECS); 257 } 258 if (data & GEN8_GRDOM_MEDIA2) { 259 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 260 if (HAS_BSD2(vgpu->gvt->dev_priv)) 261 bitmap |= (1 << VCS2); 262 } 263 return 0; 264 } 265 266 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 267 void *p_data, unsigned int bytes) 268 { 269 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 270 } 271 272 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 273 void *p_data, unsigned int bytes) 274 { 275 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 276 } 277 278 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 279 unsigned int offset, void *p_data, unsigned int bytes) 280 { 281 write_vreg(vgpu, offset, p_data, bytes); 282 283 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 284 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; 285 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 286 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 287 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 288 289 } else 290 vgpu_vreg(vgpu, PCH_PP_STATUS) &= 291 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 292 | PP_CYCLE_DELAY_ACTIVE); 293 return 0; 294 } 295 296 static int transconf_mmio_write(struct intel_vgpu *vgpu, 297 unsigned int offset, void *p_data, unsigned int bytes) 298 { 299 write_vreg(vgpu, offset, p_data, bytes); 300 301 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 302 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 303 else 304 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 305 return 0; 306 } 307 308 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 309 void *p_data, unsigned int bytes) 310 { 311 write_vreg(vgpu, offset, p_data, bytes); 312 313 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 314 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 315 else 316 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 317 318 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 319 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 320 else 321 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 322 323 return 0; 324 } 325 326 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 327 void *p_data, unsigned int bytes) 328 { 329 *(u32 *)p_data = (1 << 17); 330 return 0; 331 } 332 333 static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset, 334 void *p_data, unsigned int bytes) 335 { 336 *(u32 *)p_data = 3; 337 return 0; 338 } 339 340 static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset, 341 void *p_data, unsigned int bytes) 342 { 343 *(u32 *)p_data = (0x2f << 16); 344 return 0; 345 } 346 347 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 348 void *p_data, unsigned int bytes) 349 { 350 u32 data; 351 352 write_vreg(vgpu, offset, p_data, bytes); 353 data = vgpu_vreg(vgpu, offset); 354 355 if (data & PIPECONF_ENABLE) 356 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 357 else 358 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 359 intel_gvt_check_vblank_emulation(vgpu->gvt); 360 return 0; 361 } 362 363 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 364 void *p_data, unsigned int bytes) 365 { 366 write_vreg(vgpu, offset, p_data, bytes); 367 368 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 369 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 370 } else { 371 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 372 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 373 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) 374 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 375 } 376 return 0; 377 } 378 379 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 380 unsigned int offset, void *p_data, unsigned int bytes) 381 { 382 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 383 return 0; 384 } 385 386 #define FDI_LINK_TRAIN_PATTERN1 0 387 #define FDI_LINK_TRAIN_PATTERN2 1 388 389 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 390 { 391 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); 392 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 393 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); 394 395 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 396 (rx_ctl & FDI_RX_ENABLE) && 397 (rx_ctl & FDI_AUTO_TRAINING) && 398 (tx_ctl & DP_TP_CTL_ENABLE) && 399 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 400 return 1; 401 else 402 return 0; 403 } 404 405 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 406 enum pipe pipe, unsigned int train_pattern) 407 { 408 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 409 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 410 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 411 unsigned int fdi_iir_check_bits; 412 413 fdi_rx_imr = FDI_RX_IMR(pipe); 414 fdi_tx_ctl = FDI_TX_CTL(pipe); 415 fdi_rx_ctl = FDI_RX_CTL(pipe); 416 417 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 418 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 419 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 420 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 421 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 422 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 423 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 424 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 425 } else { 426 gvt_err("Invalid train pattern %d\n", train_pattern); 427 return -EINVAL; 428 } 429 430 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 431 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 432 433 /* If imr bit has been masked */ 434 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 435 return 0; 436 437 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 438 == fdi_tx_check_bits) 439 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 440 == fdi_rx_check_bits)) 441 return 1; 442 else 443 return 0; 444 } 445 446 #define INVALID_INDEX (~0U) 447 448 static unsigned int calc_index(unsigned int offset, unsigned int start, 449 unsigned int next, unsigned int end, i915_reg_t i915_end) 450 { 451 unsigned int range = next - start; 452 453 if (!end) 454 end = i915_mmio_reg_offset(i915_end); 455 if (offset < start || offset > end) 456 return INVALID_INDEX; 457 offset -= start; 458 return offset / range; 459 } 460 461 #define FDI_RX_CTL_TO_PIPE(offset) \ 462 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 463 464 #define FDI_TX_CTL_TO_PIPE(offset) \ 465 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 466 467 #define FDI_RX_IMR_TO_PIPE(offset) \ 468 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 469 470 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 471 unsigned int offset, void *p_data, unsigned int bytes) 472 { 473 i915_reg_t fdi_rx_iir; 474 unsigned int index; 475 int ret; 476 477 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 478 index = FDI_RX_CTL_TO_PIPE(offset); 479 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 480 index = FDI_TX_CTL_TO_PIPE(offset); 481 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 482 index = FDI_RX_IMR_TO_PIPE(offset); 483 else { 484 gvt_err("Unsupport registers %x\n", offset); 485 return -EINVAL; 486 } 487 488 write_vreg(vgpu, offset, p_data, bytes); 489 490 fdi_rx_iir = FDI_RX_IIR(index); 491 492 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 493 if (ret < 0) 494 return ret; 495 if (ret) 496 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 497 498 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 499 if (ret < 0) 500 return ret; 501 if (ret) 502 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 503 504 if (offset == _FDI_RXA_CTL) 505 if (fdi_auto_training_started(vgpu)) 506 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= 507 DP_TP_STATUS_AUTOTRAIN_DONE; 508 return 0; 509 } 510 511 #define DP_TP_CTL_TO_PORT(offset) \ 512 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 513 514 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 515 void *p_data, unsigned int bytes) 516 { 517 i915_reg_t status_reg; 518 unsigned int index; 519 u32 data; 520 521 write_vreg(vgpu, offset, p_data, bytes); 522 523 index = DP_TP_CTL_TO_PORT(offset); 524 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 525 if (data == 0x2) { 526 status_reg = DP_TP_STATUS(index); 527 vgpu_vreg(vgpu, status_reg) |= (1 << 25); 528 } 529 return 0; 530 } 531 532 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 533 unsigned int offset, void *p_data, unsigned int bytes) 534 { 535 u32 reg_val; 536 u32 sticky_mask; 537 538 reg_val = *((u32 *)p_data); 539 sticky_mask = GENMASK(27, 26) | (1 << 24); 540 541 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 542 (vgpu_vreg(vgpu, offset) & sticky_mask); 543 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 544 return 0; 545 } 546 547 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 548 unsigned int offset, void *p_data, unsigned int bytes) 549 { 550 u32 data; 551 552 write_vreg(vgpu, offset, p_data, bytes); 553 data = vgpu_vreg(vgpu, offset); 554 555 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 556 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 557 return 0; 558 } 559 560 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 561 unsigned int offset, void *p_data, unsigned int bytes) 562 { 563 u32 data; 564 565 write_vreg(vgpu, offset, p_data, bytes); 566 data = vgpu_vreg(vgpu, offset); 567 568 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 569 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 570 else 571 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 572 return 0; 573 } 574 575 #define DSPSURF_TO_PIPE(offset) \ 576 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 577 578 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 579 void *p_data, unsigned int bytes) 580 { 581 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 582 unsigned int index = DSPSURF_TO_PIPE(offset); 583 i915_reg_t surflive_reg = DSPSURFLIVE(index); 584 int flip_event[] = { 585 [PIPE_A] = PRIMARY_A_FLIP_DONE, 586 [PIPE_B] = PRIMARY_B_FLIP_DONE, 587 [PIPE_C] = PRIMARY_C_FLIP_DONE, 588 }; 589 590 write_vreg(vgpu, offset, p_data, bytes); 591 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 592 593 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 594 return 0; 595 } 596 597 #define SPRSURF_TO_PIPE(offset) \ 598 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 599 600 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 601 void *p_data, unsigned int bytes) 602 { 603 unsigned int index = SPRSURF_TO_PIPE(offset); 604 i915_reg_t surflive_reg = SPRSURFLIVE(index); 605 int flip_event[] = { 606 [PIPE_A] = SPRITE_A_FLIP_DONE, 607 [PIPE_B] = SPRITE_B_FLIP_DONE, 608 [PIPE_C] = SPRITE_C_FLIP_DONE, 609 }; 610 611 write_vreg(vgpu, offset, p_data, bytes); 612 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 613 614 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 615 return 0; 616 } 617 618 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 619 unsigned int reg) 620 { 621 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 622 enum intel_gvt_event_type event; 623 624 if (reg == _DPA_AUX_CH_CTL) 625 event = AUX_CHANNEL_A; 626 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 627 event = AUX_CHANNEL_B; 628 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 629 event = AUX_CHANNEL_C; 630 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 631 event = AUX_CHANNEL_D; 632 else { 633 WARN_ON(true); 634 return -EINVAL; 635 } 636 637 intel_vgpu_trigger_virtual_event(vgpu, event); 638 return 0; 639 } 640 641 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 642 unsigned int reg, int len, bool data_valid) 643 { 644 /* mark transaction done */ 645 value |= DP_AUX_CH_CTL_DONE; 646 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 647 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 648 649 if (data_valid) 650 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 651 else 652 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 653 654 /* message size */ 655 value &= ~(0xf << 20); 656 value |= (len << 20); 657 vgpu_vreg(vgpu, reg) = value; 658 659 if (value & DP_AUX_CH_CTL_INTERRUPT) 660 return trigger_aux_channel_interrupt(vgpu, reg); 661 return 0; 662 } 663 664 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 665 uint8_t t) 666 { 667 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 668 /* training pattern 1 for CR */ 669 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 670 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 671 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 672 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 673 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 674 DPCD_TRAINING_PATTERN_2) { 675 /* training pattern 2 for EQ */ 676 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 677 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 678 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 679 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 680 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 681 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 682 /* set INTERLANE_ALIGN_DONE */ 683 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 684 DPCD_INTERLANE_ALIGN_DONE; 685 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 686 DPCD_LINK_TRAINING_DISABLED) { 687 /* finish link training */ 688 /* set sink status as synchronized */ 689 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 690 } 691 } 692 693 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 694 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 695 696 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 697 698 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 699 700 #define dpy_is_valid_port(port) \ 701 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 702 703 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 704 unsigned int offset, void *p_data, unsigned int bytes) 705 { 706 struct intel_vgpu_display *display = &vgpu->display; 707 int msg, addr, ctrl, op, len; 708 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 709 struct intel_vgpu_dpcd_data *dpcd = NULL; 710 struct intel_vgpu_port *port = NULL; 711 u32 data; 712 713 if (!dpy_is_valid_port(port_index)) { 714 gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id); 715 return 0; 716 } 717 718 write_vreg(vgpu, offset, p_data, bytes); 719 data = vgpu_vreg(vgpu, offset); 720 721 if (IS_SKYLAKE(vgpu->gvt->dev_priv) && 722 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 723 /* SKL DPB/C/D aux ctl register changed */ 724 return 0; 725 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 726 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 727 /* write to the data registers */ 728 return 0; 729 } 730 731 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 732 /* just want to clear the sticky bits */ 733 vgpu_vreg(vgpu, offset) = 0; 734 return 0; 735 } 736 737 port = &display->ports[port_index]; 738 dpcd = port->dpcd; 739 740 /* read out message from DATA1 register */ 741 msg = vgpu_vreg(vgpu, offset + 4); 742 addr = (msg >> 8) & 0xffff; 743 ctrl = (msg >> 24) & 0xff; 744 len = msg & 0xff; 745 op = ctrl >> 4; 746 747 if (op == GVT_AUX_NATIVE_WRITE) { 748 int t; 749 uint8_t buf[16]; 750 751 if ((addr + len + 1) >= DPCD_SIZE) { 752 /* 753 * Write request exceeds what we supported, 754 * DCPD spec: When a Source Device is writing a DPCD 755 * address not supported by the Sink Device, the Sink 756 * Device shall reply with AUX NACK and “M” equal to 757 * zero. 758 */ 759 760 /* NAK the write */ 761 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 762 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 763 return 0; 764 } 765 766 /* 767 * Write request format: (command + address) occupies 768 * 3 bytes, followed by (len + 1) bytes of data. 769 */ 770 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 771 return -EINVAL; 772 773 /* unpack data from vreg to buf */ 774 for (t = 0; t < 4; t++) { 775 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 776 777 buf[t * 4] = (r >> 24) & 0xff; 778 buf[t * 4 + 1] = (r >> 16) & 0xff; 779 buf[t * 4 + 2] = (r >> 8) & 0xff; 780 buf[t * 4 + 3] = r & 0xff; 781 } 782 783 /* write to virtual DPCD */ 784 if (dpcd && dpcd->data_valid) { 785 for (t = 0; t <= len; t++) { 786 int p = addr + t; 787 788 dpcd->data[p] = buf[t]; 789 /* check for link training */ 790 if (p == DPCD_TRAINING_PATTERN_SET) 791 dp_aux_ch_ctl_link_training(dpcd, 792 buf[t]); 793 } 794 } 795 796 /* ACK the write */ 797 vgpu_vreg(vgpu, offset + 4) = 0; 798 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 799 dpcd && dpcd->data_valid); 800 return 0; 801 } 802 803 if (op == GVT_AUX_NATIVE_READ) { 804 int idx, i, ret = 0; 805 806 if ((addr + len + 1) >= DPCD_SIZE) { 807 /* 808 * read request exceeds what we supported 809 * DPCD spec: A Sink Device receiving a Native AUX CH 810 * read request for an unsupported DPCD address must 811 * reply with an AUX ACK and read data set equal to 812 * zero instead of replying with AUX NACK. 813 */ 814 815 /* ACK the READ*/ 816 vgpu_vreg(vgpu, offset + 4) = 0; 817 vgpu_vreg(vgpu, offset + 8) = 0; 818 vgpu_vreg(vgpu, offset + 12) = 0; 819 vgpu_vreg(vgpu, offset + 16) = 0; 820 vgpu_vreg(vgpu, offset + 20) = 0; 821 822 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 823 true); 824 return 0; 825 } 826 827 for (idx = 1; idx <= 5; idx++) { 828 /* clear the data registers */ 829 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 830 } 831 832 /* 833 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 834 */ 835 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 836 return -EINVAL; 837 838 /* read from virtual DPCD to vreg */ 839 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 840 if (dpcd && dpcd->data_valid) { 841 for (i = 1; i <= (len + 1); i++) { 842 int t; 843 844 t = dpcd->data[addr + i - 1]; 845 t <<= (24 - 8 * (i % 4)); 846 ret |= t; 847 848 if ((i % 4 == 3) || (i == (len + 1))) { 849 vgpu_vreg(vgpu, offset + 850 (i / 4 + 1) * 4) = ret; 851 ret = 0; 852 } 853 } 854 } 855 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 856 dpcd && dpcd->data_valid); 857 return 0; 858 } 859 860 /* i2c transaction starts */ 861 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 862 863 if (data & DP_AUX_CH_CTL_INTERRUPT) 864 trigger_aux_channel_interrupt(vgpu, offset); 865 return 0; 866 } 867 868 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 869 void *p_data, unsigned int bytes) 870 { 871 bool vga_disable; 872 873 write_vreg(vgpu, offset, p_data, bytes); 874 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 875 876 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 877 vga_disable ? "Disable" : "Enable"); 878 return 0; 879 } 880 881 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 882 unsigned int sbi_offset) 883 { 884 struct intel_vgpu_display *display = &vgpu->display; 885 int num = display->sbi.number; 886 int i; 887 888 for (i = 0; i < num; ++i) 889 if (display->sbi.registers[i].offset == sbi_offset) 890 break; 891 892 if (i == num) 893 return 0; 894 895 return display->sbi.registers[i].value; 896 } 897 898 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 899 unsigned int offset, u32 value) 900 { 901 struct intel_vgpu_display *display = &vgpu->display; 902 int num = display->sbi.number; 903 int i; 904 905 for (i = 0; i < num; ++i) { 906 if (display->sbi.registers[i].offset == offset) 907 break; 908 } 909 910 if (i == num) { 911 if (num == SBI_REG_MAX) { 912 gvt_err("vgpu%d: SBI caching meets maximum limits\n", 913 vgpu->id); 914 return; 915 } 916 display->sbi.number++; 917 } 918 919 display->sbi.registers[i].offset = offset; 920 display->sbi.registers[i].value = value; 921 } 922 923 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 924 void *p_data, unsigned int bytes) 925 { 926 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 927 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 928 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 929 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 930 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 931 sbi_offset); 932 } 933 read_vreg(vgpu, offset, p_data, bytes); 934 return 0; 935 } 936 937 static bool sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 938 void *p_data, unsigned int bytes) 939 { 940 u32 data; 941 942 write_vreg(vgpu, offset, p_data, bytes); 943 data = vgpu_vreg(vgpu, offset); 944 945 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 946 data |= SBI_READY; 947 948 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 949 data |= SBI_RESPONSE_SUCCESS; 950 951 vgpu_vreg(vgpu, offset) = data; 952 953 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 954 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 955 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 956 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 957 958 write_virtual_sbi_register(vgpu, sbi_offset, 959 vgpu_vreg(vgpu, SBI_DATA)); 960 } 961 return 0; 962 } 963 964 #define _vgtif_reg(x) \ 965 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 966 967 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 968 void *p_data, unsigned int bytes) 969 { 970 bool invalid_read = false; 971 972 read_vreg(vgpu, offset, p_data, bytes); 973 974 switch (offset) { 975 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 976 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 977 invalid_read = true; 978 break; 979 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 980 _vgtif_reg(avail_rs.fence_num): 981 if (offset + bytes > 982 _vgtif_reg(avail_rs.fence_num) + 4) 983 invalid_read = true; 984 break; 985 case 0x78010: /* vgt_caps */ 986 case 0x7881c: 987 break; 988 default: 989 invalid_read = true; 990 break; 991 } 992 if (invalid_read) 993 gvt_err("invalid pvinfo read: [%x:%x] = %x\n", 994 offset, bytes, *(u32 *)p_data); 995 return 0; 996 } 997 998 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 999 { 1000 int ret = 0; 1001 1002 switch (notification) { 1003 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1004 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); 1005 break; 1006 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1007 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); 1008 break; 1009 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1010 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); 1011 break; 1012 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1013 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); 1014 break; 1015 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1016 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1017 case 1: /* Remove this in guest driver. */ 1018 break; 1019 default: 1020 gvt_err("Invalid PV notification %d\n", notification); 1021 } 1022 return ret; 1023 } 1024 1025 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1026 { 1027 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1028 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1029 char *env[3] = {NULL, NULL, NULL}; 1030 char vmid_str[20]; 1031 char display_ready_str[20]; 1032 1033 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready); 1034 env[0] = display_ready_str; 1035 1036 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1037 env[1] = vmid_str; 1038 1039 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1040 } 1041 1042 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1043 void *p_data, unsigned int bytes) 1044 { 1045 u32 data; 1046 int ret; 1047 1048 write_vreg(vgpu, offset, p_data, bytes); 1049 data = vgpu_vreg(vgpu, offset); 1050 1051 switch (offset) { 1052 case _vgtif_reg(display_ready): 1053 send_display_ready_uevent(vgpu, data ? 1 : 0); 1054 break; 1055 case _vgtif_reg(g2v_notify): 1056 ret = handle_g2v_notification(vgpu, data); 1057 break; 1058 /* add xhot and yhot to handled list to avoid error log */ 1059 case 0x78830: 1060 case 0x78834: 1061 case _vgtif_reg(pdp[0].lo): 1062 case _vgtif_reg(pdp[0].hi): 1063 case _vgtif_reg(pdp[1].lo): 1064 case _vgtif_reg(pdp[1].hi): 1065 case _vgtif_reg(pdp[2].lo): 1066 case _vgtif_reg(pdp[2].hi): 1067 case _vgtif_reg(pdp[3].lo): 1068 case _vgtif_reg(pdp[3].hi): 1069 case _vgtif_reg(execlist_context_descriptor_lo): 1070 case _vgtif_reg(execlist_context_descriptor_hi): 1071 break; 1072 default: 1073 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n", 1074 offset, bytes, data); 1075 break; 1076 } 1077 return 0; 1078 } 1079 1080 static int pf_write(struct intel_vgpu *vgpu, 1081 unsigned int offset, void *p_data, unsigned int bytes) 1082 { 1083 u32 val = *(u32 *)p_data; 1084 1085 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1086 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1087 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1088 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1089 vgpu->id); 1090 return 0; 1091 } 1092 1093 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1094 } 1095 1096 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1097 unsigned int offset, void *p_data, unsigned int bytes) 1098 { 1099 write_vreg(vgpu, offset, p_data, bytes); 1100 1101 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) 1102 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; 1103 else 1104 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; 1105 return 0; 1106 } 1107 1108 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1109 unsigned int offset, void *p_data, unsigned int bytes) 1110 { 1111 write_vreg(vgpu, offset, p_data, bytes); 1112 1113 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1114 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1115 return 0; 1116 } 1117 1118 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1119 void *p_data, unsigned int bytes) 1120 { 1121 u32 mode = *(u32 *)p_data; 1122 1123 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1124 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n", 1125 vgpu->id); 1126 return 0; 1127 } 1128 1129 return 0; 1130 } 1131 1132 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1133 void *p_data, unsigned int bytes) 1134 { 1135 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1136 u32 trtte = *(u32 *)p_data; 1137 1138 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1139 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1140 vgpu->id); 1141 return -EINVAL; 1142 } 1143 write_vreg(vgpu, offset, p_data, bytes); 1144 /* TRTTE is not per-context */ 1145 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1146 1147 return 0; 1148 } 1149 1150 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1151 void *p_data, unsigned int bytes) 1152 { 1153 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1154 u32 val = *(u32 *)p_data; 1155 1156 if (val & 1) { 1157 /* unblock hw logic */ 1158 I915_WRITE(_MMIO(offset), val); 1159 } 1160 write_vreg(vgpu, offset, p_data, bytes); 1161 return 0; 1162 } 1163 1164 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1165 void *p_data, unsigned int bytes) 1166 { 1167 u32 v = 0; 1168 1169 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1170 v |= (1 << 0); 1171 1172 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1173 v |= (1 << 8); 1174 1175 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1176 v |= (1 << 16); 1177 1178 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1179 v |= (1 << 24); 1180 1181 vgpu_vreg(vgpu, offset) = v; 1182 1183 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1184 } 1185 1186 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1187 void *p_data, unsigned int bytes) 1188 { 1189 u32 value = *(u32 *)p_data; 1190 u32 cmd = value & 0xff; 1191 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); 1192 1193 switch (cmd) { 1194 case 0x6: 1195 /** 1196 * "Read memory latency" command on gen9. 1197 * Below memory latency values are read 1198 * from skylake platform. 1199 */ 1200 if (!*data0) 1201 *data0 = 0x1e1a1100; 1202 else 1203 *data0 = 0x61514b3d; 1204 break; 1205 case 0x5: 1206 *data0 |= 0x1; 1207 break; 1208 } 1209 1210 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1211 vgpu->id, value, *data0); 1212 1213 value &= ~(1 << 31); 1214 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1215 } 1216 1217 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1218 unsigned int offset, void *p_data, unsigned int bytes) 1219 { 1220 u32 v = *(u32 *)p_data; 1221 1222 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1223 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1224 v |= (v >> 1); 1225 1226 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1227 } 1228 1229 static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1230 void *p_data, unsigned int bytes) 1231 { 1232 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1233 i915_reg_t reg = {.reg = offset}; 1234 1235 switch (offset) { 1236 case 0x4ddc: 1237 vgpu_vreg(vgpu, offset) = 0x8000003c; 1238 break; 1239 case 0x42080: 1240 vgpu_vreg(vgpu, offset) = 0x8000; 1241 break; 1242 default: 1243 return -EINVAL; 1244 } 1245 1246 /** 1247 * TODO: need detect stepping info after gvt contain such information 1248 * 0x4ddc enabled after C0, 0x42080 enabled after E0. 1249 */ 1250 I915_WRITE(reg, vgpu_vreg(vgpu, offset)); 1251 return 0; 1252 } 1253 1254 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1255 void *p_data, unsigned int bytes) 1256 { 1257 u32 v = *(u32 *)p_data; 1258 1259 /* other bits are MBZ. */ 1260 v &= (1 << 31) | (1 << 30); 1261 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1262 1263 vgpu_vreg(vgpu, offset) = v; 1264 1265 return 0; 1266 } 1267 1268 static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu, 1269 unsigned int offset, void *p_data, unsigned int bytes) 1270 { 1271 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1272 1273 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1274 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1275 } 1276 1277 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1278 void *p_data, unsigned int bytes) 1279 { 1280 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1281 struct intel_vgpu_execlist *execlist; 1282 u32 data = *(u32 *)p_data; 1283 int ret; 1284 1285 if (WARN_ON(ring_id < 0)) 1286 return -EINVAL; 1287 1288 execlist = &vgpu->execlist[ring_id]; 1289 1290 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data; 1291 if (execlist->elsp_dwords.index == 3) 1292 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1293 1294 ++execlist->elsp_dwords.index; 1295 execlist->elsp_dwords.index &= 0x3; 1296 return 0; 1297 } 1298 1299 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1300 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 1301 f, s, am, rm, d, r, w); \ 1302 if (ret) \ 1303 return ret; \ 1304 } while (0) 1305 1306 #define MMIO_D(reg, d) \ 1307 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1308 1309 #define MMIO_DH(reg, d, r, w) \ 1310 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1311 1312 #define MMIO_DFH(reg, d, f, r, w) \ 1313 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1314 1315 #define MMIO_GM(reg, d, r, w) \ 1316 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1317 1318 #define MMIO_RO(reg, d, f, rm, r, w) \ 1319 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1320 1321 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1322 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1323 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1324 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1325 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1326 } while (0) 1327 1328 #define MMIO_RING_D(prefix, d) \ 1329 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1330 1331 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1332 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1333 1334 #define MMIO_RING_GM(prefix, d, r, w) \ 1335 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1336 1337 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1338 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1339 1340 static int init_generic_mmio_info(struct intel_gvt *gvt) 1341 { 1342 struct drm_i915_private *dev_priv = gvt->dev_priv; 1343 int ret; 1344 1345 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1346 1347 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1348 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1349 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1350 MMIO_D(SDEISR, D_ALL); 1351 1352 MMIO_RING_D(RING_HWSTAM, D_ALL); 1353 1354 MMIO_GM(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1355 MMIO_GM(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1356 MMIO_GM(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1357 MMIO_GM(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1358 1359 #define RING_REG(base) (base + 0x28) 1360 MMIO_RING_D(RING_REG, D_ALL); 1361 #undef RING_REG 1362 1363 #define RING_REG(base) (base + 0x134) 1364 MMIO_RING_D(RING_REG, D_ALL); 1365 #undef RING_REG 1366 1367 MMIO_GM(0x2148, D_ALL, NULL, NULL); 1368 MMIO_GM(CCID, D_ALL, NULL, NULL); 1369 MMIO_GM(0x12198, D_ALL, NULL, NULL); 1370 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1371 1372 MMIO_RING_D(RING_TAIL, D_ALL); 1373 MMIO_RING_D(RING_HEAD, D_ALL); 1374 MMIO_RING_D(RING_CTL, D_ALL); 1375 MMIO_RING_D(RING_ACTHD, D_ALL); 1376 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 1377 1378 /* RING MODE */ 1379 #define RING_REG(base) (base + 0x29c) 1380 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK, NULL, NULL); 1381 #undef RING_REG 1382 1383 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1384 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL); 1385 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1386 ring_timestamp_mmio_read, NULL); 1387 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1388 ring_timestamp_mmio_read, NULL); 1389 1390 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1391 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL); 1392 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK, NULL, NULL); 1393 1394 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL); 1395 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL); 1396 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK, NULL, NULL); 1397 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK, NULL, NULL); 1398 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK, NULL, NULL); 1399 MMIO_D(GAM_ECOCHK, D_ALL); 1400 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK, NULL, NULL); 1401 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK, NULL, NULL); 1402 MMIO_D(0x9030, D_ALL); 1403 MMIO_D(0x20a0, D_ALL); 1404 MMIO_D(0x2420, D_ALL); 1405 MMIO_D(0x2430, D_ALL); 1406 MMIO_D(0x2434, D_ALL); 1407 MMIO_D(0x2438, D_ALL); 1408 MMIO_D(0x243c, D_ALL); 1409 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK, NULL, NULL); 1410 MMIO_DFH(0xe184, D_ALL, F_MODE_MASK, NULL, NULL); 1411 MMIO_DFH(0xe100, D_ALL, F_MODE_MASK, NULL, NULL); 1412 1413 /* display */ 1414 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1415 MMIO_D(0x602a0, D_ALL); 1416 1417 MMIO_D(0x65050, D_ALL); 1418 MMIO_D(0x650b4, D_ALL); 1419 1420 MMIO_D(0xc4040, D_ALL); 1421 MMIO_D(DERRMR, D_ALL); 1422 1423 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1424 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1425 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1426 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1427 1428 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1429 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1430 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1431 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1432 1433 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1434 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1435 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1436 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1437 1438 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1439 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1440 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1441 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1442 1443 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1444 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1445 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1446 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1447 1448 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1449 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1450 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1451 1452 MMIO_D(CURPOS(PIPE_A), D_ALL); 1453 MMIO_D(CURPOS(PIPE_B), D_ALL); 1454 MMIO_D(CURPOS(PIPE_C), D_ALL); 1455 1456 MMIO_D(CURBASE(PIPE_A), D_ALL); 1457 MMIO_D(CURBASE(PIPE_B), D_ALL); 1458 MMIO_D(CURBASE(PIPE_C), D_ALL); 1459 1460 MMIO_D(0x700ac, D_ALL); 1461 MMIO_D(0x710ac, D_ALL); 1462 MMIO_D(0x720ac, D_ALL); 1463 1464 MMIO_D(0x70090, D_ALL); 1465 MMIO_D(0x70094, D_ALL); 1466 MMIO_D(0x70098, D_ALL); 1467 MMIO_D(0x7009c, D_ALL); 1468 1469 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1470 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1471 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1472 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1473 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1474 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1475 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1476 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1477 1478 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1479 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1480 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1481 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1482 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1483 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1484 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1485 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1486 1487 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1488 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1489 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1490 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1491 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1492 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1493 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1494 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1495 1496 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1497 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1498 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1499 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1500 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1501 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1502 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1503 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1504 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1505 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1506 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1507 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1508 1509 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1510 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1511 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1512 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1513 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1514 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1515 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1516 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1517 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1518 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1519 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1520 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1521 1522 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1523 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1524 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1525 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1526 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1527 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1528 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1529 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1530 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1531 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1532 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1533 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1534 1535 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1536 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1537 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1538 1539 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1540 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1541 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1542 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1543 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1544 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1545 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1546 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1547 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1548 1549 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1550 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1551 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1552 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1553 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1554 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1555 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1556 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1557 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1558 1559 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1560 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1561 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1562 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1563 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1564 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1565 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1566 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1567 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1568 1569 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1570 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1571 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1572 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1573 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1574 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1575 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1576 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1577 1578 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1579 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1580 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1581 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1582 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1583 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1584 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1585 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1586 1587 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1588 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1589 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1590 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1591 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1592 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1593 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1594 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1595 1596 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1597 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1598 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1599 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1600 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1601 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1602 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1603 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1604 1605 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1606 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1607 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1608 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1609 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1610 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1611 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1612 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1613 1614 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1615 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1616 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1617 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1618 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1619 1620 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1621 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1622 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1623 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1624 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1625 1626 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1627 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1628 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1629 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1630 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1631 1632 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1633 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1634 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1635 MMIO_D(WM1_LP_ILK, D_ALL); 1636 MMIO_D(WM2_LP_ILK, D_ALL); 1637 MMIO_D(WM3_LP_ILK, D_ALL); 1638 MMIO_D(WM1S_LP_ILK, D_ALL); 1639 MMIO_D(WM2S_LP_IVB, D_ALL); 1640 MMIO_D(WM3S_LP_IVB, D_ALL); 1641 1642 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1643 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1644 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1645 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1646 1647 MMIO_D(0x48268, D_ALL); 1648 1649 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1650 gmbus_mmio_write); 1651 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1652 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1653 1654 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1655 dp_aux_ch_ctl_mmio_write); 1656 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1657 dp_aux_ch_ctl_mmio_write); 1658 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1659 dp_aux_ch_ctl_mmio_write); 1660 1661 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write); 1662 1663 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); 1664 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); 1665 1666 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1667 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1668 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1669 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1670 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1671 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1672 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1673 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1674 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1675 1676 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 1677 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 1678 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 1679 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 1680 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 1681 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 1682 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 1683 1684 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 1685 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 1686 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 1687 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 1688 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 1689 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 1690 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 1691 1692 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 1693 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 1694 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 1695 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 1696 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 1697 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 1698 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 1699 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 1700 1701 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 1702 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 1703 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 1704 1705 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 1706 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 1707 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 1708 1709 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 1710 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 1711 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 1712 1713 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 1714 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 1715 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 1716 1717 MMIO_D(_FDI_RXA_MISC, D_ALL); 1718 MMIO_D(_FDI_RXB_MISC, D_ALL); 1719 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 1720 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 1721 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 1722 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 1723 1724 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 1725 MMIO_D(PCH_PP_DIVISOR, D_ALL); 1726 MMIO_D(PCH_PP_STATUS, D_ALL); 1727 MMIO_D(PCH_LVDS, D_ALL); 1728 MMIO_D(_PCH_DPLL_A, D_ALL); 1729 MMIO_D(_PCH_DPLL_B, D_ALL); 1730 MMIO_D(_PCH_FPA0, D_ALL); 1731 MMIO_D(_PCH_FPA1, D_ALL); 1732 MMIO_D(_PCH_FPB0, D_ALL); 1733 MMIO_D(_PCH_FPB1, D_ALL); 1734 MMIO_D(PCH_DREF_CONTROL, D_ALL); 1735 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 1736 MMIO_D(PCH_DPLL_SEL, D_ALL); 1737 1738 MMIO_D(0x61208, D_ALL); 1739 MMIO_D(0x6120c, D_ALL); 1740 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 1741 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 1742 1743 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); 1744 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); 1745 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); 1746 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); 1747 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL); 1748 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL); 1749 1750 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 1751 PORTA_HOTPLUG_STATUS_MASK 1752 | PORTB_HOTPLUG_STATUS_MASK 1753 | PORTC_HOTPLUG_STATUS_MASK 1754 | PORTD_HOTPLUG_STATUS_MASK, 1755 NULL, NULL); 1756 1757 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 1758 MMIO_D(FUSE_STRAP, D_ALL); 1759 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 1760 1761 MMIO_D(DISP_ARB_CTL, D_ALL); 1762 MMIO_D(DISP_ARB_CTL2, D_ALL); 1763 1764 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 1765 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 1766 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 1767 1768 MMIO_D(SOUTH_CHICKEN1, D_ALL); 1769 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 1770 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 1771 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 1772 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 1773 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 1774 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 1775 1776 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 1777 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 1778 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 1779 MMIO_D(ILK_DPFC_STATUS, D_ALL); 1780 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 1781 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 1782 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 1783 1784 MMIO_D(IPS_CTL, D_ALL); 1785 1786 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 1787 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 1788 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 1789 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 1790 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 1791 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 1792 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 1793 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 1794 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 1795 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 1796 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 1797 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 1798 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 1799 1800 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 1801 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 1802 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 1803 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 1804 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 1805 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 1806 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 1807 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 1808 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 1809 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 1810 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 1811 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 1812 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 1813 1814 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 1815 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 1816 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 1817 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 1818 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 1819 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 1820 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 1821 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 1822 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 1823 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 1824 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 1825 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 1826 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 1827 1828 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 1829 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 1830 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1831 1832 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 1833 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 1834 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1835 1836 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 1837 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 1838 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1839 1840 MMIO_D(0x60110, D_ALL); 1841 MMIO_D(0x61110, D_ALL); 1842 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1843 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1844 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1845 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1846 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1847 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1848 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1849 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1850 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1851 1852 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 1853 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 1854 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 1855 MMIO_D(SPLL_CTL, D_ALL); 1856 MMIO_D(_WRPLL_CTL1, D_ALL); 1857 MMIO_D(_WRPLL_CTL2, D_ALL); 1858 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 1859 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 1860 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 1861 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 1862 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 1863 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 1864 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 1865 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 1866 1867 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 1868 MMIO_D(0x46508, D_ALL); 1869 1870 MMIO_D(0x49080, D_ALL); 1871 MMIO_D(0x49180, D_ALL); 1872 MMIO_D(0x49280, D_ALL); 1873 1874 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1875 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1876 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1877 1878 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 1879 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 1880 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 1881 1882 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 1883 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 1884 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 1885 1886 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 1887 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 1888 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 1889 1890 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 1891 MMIO_D(SBI_ADDR, D_ALL); 1892 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 1893 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 1894 MMIO_D(PIXCLK_GATE, D_ALL); 1895 1896 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, 1897 dp_aux_ch_ctl_mmio_write); 1898 1899 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1900 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1901 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1902 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1903 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1904 1905 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 1906 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 1907 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 1908 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 1909 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 1910 1911 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 1912 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 1913 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 1914 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 1915 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 1916 1917 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1918 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1919 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1920 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1921 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1922 1923 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 1924 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 1925 1926 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 1927 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 1928 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 1929 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 1930 1931 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 1932 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 1933 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 1934 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 1935 1936 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 1937 MMIO_D(FORCEWAKE_ACK, D_ALL); 1938 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 1939 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 1940 MMIO_D(GTFIFODBG, D_ALL); 1941 MMIO_D(GTFIFOCTL, D_ALL); 1942 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 1943 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL); 1944 MMIO_D(ECOBUS, D_ALL); 1945 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 1946 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 1947 MMIO_D(GEN6_RPNSWREQ, D_ALL); 1948 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 1949 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 1950 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 1951 MMIO_D(GEN6_RPSTAT1, D_ALL); 1952 MMIO_D(GEN6_RP_CONTROL, D_ALL); 1953 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 1954 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 1955 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 1956 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 1957 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 1958 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 1959 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 1960 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 1961 MMIO_D(GEN6_RP_UP_EI, D_ALL); 1962 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 1963 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 1964 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 1965 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 1966 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 1967 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 1968 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 1969 MMIO_D(GEN6_RC_SLEEP, D_ALL); 1970 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 1971 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 1972 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 1973 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 1974 MMIO_D(GEN6_PMINTRMSK, D_ALL); 1975 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1976 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1977 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1978 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1979 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1980 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1981 1982 MMIO_D(RSTDBYCTL, D_ALL); 1983 1984 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 1985 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 1986 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write); 1987 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 1988 1989 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL); 1990 1991 MMIO_D(TILECTL, D_ALL); 1992 1993 MMIO_D(GEN6_UCGCTL1, D_ALL); 1994 MMIO_D(GEN6_UCGCTL2, D_ALL); 1995 1996 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 1997 1998 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_SKL); 1999 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2000 MMIO_D(0x13812c, D_ALL); 2001 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2002 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2003 MMIO_D(HSW_IDICR, D_ALL); 2004 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2005 2006 MMIO_D(0x3c, D_ALL); 2007 MMIO_D(0x860, D_ALL); 2008 MMIO_D(ECOSKPD, D_ALL); 2009 MMIO_D(0x121d0, D_ALL); 2010 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2011 MMIO_D(0x41d0, D_ALL); 2012 MMIO_D(GAC_ECO_BITS, D_ALL); 2013 MMIO_D(0x6200, D_ALL); 2014 MMIO_D(0x6204, D_ALL); 2015 MMIO_D(0x6208, D_ALL); 2016 MMIO_D(0x7118, D_ALL); 2017 MMIO_D(0x7180, D_ALL); 2018 MMIO_D(0x7408, D_ALL); 2019 MMIO_D(0x7c00, D_ALL); 2020 MMIO_D(GEN6_MBCTL, D_ALL); 2021 MMIO_D(0x911c, D_ALL); 2022 MMIO_D(0x9120, D_ALL); 2023 2024 MMIO_D(GAB_CTL, D_ALL); 2025 MMIO_D(0x48800, D_ALL); 2026 MMIO_D(0xce044, D_ALL); 2027 MMIO_D(0xe6500, D_ALL); 2028 MMIO_D(0xe6504, D_ALL); 2029 MMIO_D(0xe6600, D_ALL); 2030 MMIO_D(0xe6604, D_ALL); 2031 MMIO_D(0xe6700, D_ALL); 2032 MMIO_D(0xe6704, D_ALL); 2033 MMIO_D(0xe6800, D_ALL); 2034 MMIO_D(0xe6804, D_ALL); 2035 MMIO_D(PCH_GMBUS4, D_ALL); 2036 MMIO_D(PCH_GMBUS5, D_ALL); 2037 2038 MMIO_D(0x902c, D_ALL); 2039 MMIO_D(0xec008, D_ALL); 2040 MMIO_D(0xec00c, D_ALL); 2041 MMIO_D(0xec008 + 0x18, D_ALL); 2042 MMIO_D(0xec00c + 0x18, D_ALL); 2043 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 2044 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 2045 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 2046 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 2047 MMIO_D(0xec408, D_ALL); 2048 MMIO_D(0xec40c, D_ALL); 2049 MMIO_D(0xec408 + 0x18, D_ALL); 2050 MMIO_D(0xec40c + 0x18, D_ALL); 2051 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 2052 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 2053 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 2054 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 2055 MMIO_D(0xfc810, D_ALL); 2056 MMIO_D(0xfc81c, D_ALL); 2057 MMIO_D(0xfc828, D_ALL); 2058 MMIO_D(0xfc834, D_ALL); 2059 MMIO_D(0xfcc00, D_ALL); 2060 MMIO_D(0xfcc0c, D_ALL); 2061 MMIO_D(0xfcc18, D_ALL); 2062 MMIO_D(0xfcc24, D_ALL); 2063 MMIO_D(0xfd000, D_ALL); 2064 MMIO_D(0xfd00c, D_ALL); 2065 MMIO_D(0xfd018, D_ALL); 2066 MMIO_D(0xfd024, D_ALL); 2067 MMIO_D(0xfd034, D_ALL); 2068 2069 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2070 MMIO_D(0x2054, D_ALL); 2071 MMIO_D(0x12054, D_ALL); 2072 MMIO_D(0x22054, D_ALL); 2073 MMIO_D(0x1a054, D_ALL); 2074 2075 MMIO_D(0x44070, D_ALL); 2076 2077 MMIO_D(0x215c, D_HSW_PLUS); 2078 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2079 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2080 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2081 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2082 2083 MMIO_F(0x2290, 8, 0, 0, 0, D_HSW_PLUS, NULL, NULL); 2084 MMIO_D(OACONTROL, D_HSW); 2085 MMIO_D(0x2b00, D_BDW_PLUS); 2086 MMIO_D(0x2360, D_BDW_PLUS); 2087 MMIO_F(0x5200, 32, 0, 0, 0, D_ALL, NULL, NULL); 2088 MMIO_F(0x5240, 32, 0, 0, 0, D_ALL, NULL, NULL); 2089 MMIO_F(0x5280, 16, 0, 0, 0, D_ALL, NULL, NULL); 2090 2091 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2092 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2093 MMIO_D(BCS_SWCTRL, D_ALL); 2094 2095 MMIO_F(HS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2096 MMIO_F(DS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2097 MMIO_F(IA_VERTICES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2098 MMIO_F(IA_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2099 MMIO_F(VS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2100 MMIO_F(GS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2101 MMIO_F(GS_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2102 MMIO_F(CL_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2103 MMIO_F(CL_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2104 MMIO_F(PS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2105 MMIO_F(PS_DEPTH_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2106 MMIO_DH(0x4260, D_BDW_PLUS, NULL, NULL); 2107 MMIO_DH(0x4264, D_BDW_PLUS, NULL, NULL); 2108 MMIO_DH(0x4268, D_BDW_PLUS, NULL, NULL); 2109 MMIO_DH(0x426c, D_BDW_PLUS, NULL, NULL); 2110 MMIO_DH(0x4270, D_BDW_PLUS, NULL, NULL); 2111 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2112 2113 return 0; 2114 } 2115 2116 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2117 { 2118 struct drm_i915_private *dev_priv = gvt->dev_priv; 2119 int ret; 2120 2121 MMIO_DH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, 2122 intel_vgpu_reg_imr_handler); 2123 2124 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2125 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2126 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2127 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2128 2129 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2130 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2131 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2132 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2133 2134 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2135 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2136 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2137 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2138 2139 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2140 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2141 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2142 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2143 2144 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2145 intel_vgpu_reg_imr_handler); 2146 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2147 intel_vgpu_reg_ier_handler); 2148 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2149 intel_vgpu_reg_iir_handler); 2150 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2151 2152 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2153 intel_vgpu_reg_imr_handler); 2154 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2155 intel_vgpu_reg_ier_handler); 2156 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2157 intel_vgpu_reg_iir_handler); 2158 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2159 2160 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2161 intel_vgpu_reg_imr_handler); 2162 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2163 intel_vgpu_reg_ier_handler); 2164 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2165 intel_vgpu_reg_iir_handler); 2166 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2167 2168 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2169 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2170 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2171 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2172 2173 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2174 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2175 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2176 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2177 2178 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2179 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2180 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2181 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2182 2183 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2184 intel_vgpu_reg_master_irq_handler); 2185 2186 MMIO_D(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2187 MMIO_D(0x1c134, D_BDW_PLUS); 2188 2189 MMIO_D(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2190 MMIO_D(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2191 MMIO_GM(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2192 MMIO_D(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2193 MMIO_D(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2194 MMIO_D(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2195 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2196 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2197 NULL, NULL); 2198 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2199 NULL, NULL); 2200 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2201 ring_timestamp_mmio_read, NULL); 2202 2203 MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS); 2204 2205 #define RING_REG(base) (base + 0x230) 2206 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2207 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write); 2208 #undef RING_REG 2209 2210 #define RING_REG(base) (base + 0x234) 2211 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2212 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, ~0LL, D_BDW_PLUS, NULL, NULL); 2213 #undef RING_REG 2214 2215 #define RING_REG(base) (base + 0x244) 2216 MMIO_RING_D(RING_REG, D_BDW_PLUS); 2217 MMIO_D(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2218 #undef RING_REG 2219 2220 #define RING_REG(base) (base + 0x370) 2221 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2222 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS, 2223 NULL, NULL); 2224 #undef RING_REG 2225 2226 #define RING_REG(base) (base + 0x3a0) 2227 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2228 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2229 #undef RING_REG 2230 2231 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2232 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2233 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2234 MMIO_D(0x1c1d0, D_BDW_PLUS); 2235 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2236 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2237 MMIO_D(0x1c054, D_BDW_PLUS); 2238 2239 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2240 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2241 2242 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2243 2244 #define RING_REG(base) (base + 0x270) 2245 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2246 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2247 #undef RING_REG 2248 2249 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); 2250 MMIO_GM(0x1c080, D_BDW_PLUS, NULL, NULL); 2251 2252 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2253 2254 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW); 2255 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW); 2256 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW); 2257 2258 MMIO_D(WM_MISC, D_BDW); 2259 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 2260 2261 MMIO_D(0x66c00, D_BDW_PLUS); 2262 MMIO_D(0x66c04, D_BDW_PLUS); 2263 2264 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2265 2266 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2267 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2268 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2269 2270 MMIO_D(0xfdc, D_BDW); 2271 MMIO_D(GEN8_ROW_CHICKEN, D_BDW_PLUS); 2272 MMIO_D(GEN7_ROW_CHICKEN2, D_BDW_PLUS); 2273 MMIO_D(GEN8_UCGCTL6, D_BDW_PLUS); 2274 2275 MMIO_D(0xb1f0, D_BDW); 2276 MMIO_D(0xb1c0, D_BDW); 2277 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2278 MMIO_D(0xb100, D_BDW); 2279 MMIO_D(0xb10c, D_BDW); 2280 MMIO_D(0xb110, D_BDW); 2281 2282 MMIO_DH(0x24d0, D_BDW_PLUS, NULL, NULL); 2283 MMIO_DH(0x24d4, D_BDW_PLUS, NULL, NULL); 2284 MMIO_DH(0x24d8, D_BDW_PLUS, NULL, NULL); 2285 MMIO_DH(0x24dc, D_BDW_PLUS, NULL, NULL); 2286 2287 MMIO_D(0x83a4, D_BDW); 2288 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2289 2290 MMIO_D(0x8430, D_BDW); 2291 2292 MMIO_D(0x110000, D_BDW_PLUS); 2293 2294 MMIO_D(0x48400, D_BDW_PLUS); 2295 2296 MMIO_D(0x6e570, D_BDW_PLUS); 2297 MMIO_D(0x65f10, D_BDW_PLUS); 2298 2299 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2300 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2301 MMIO_DFH(0xe180, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2302 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2303 2304 MMIO_D(0x2248, D_BDW); 2305 2306 return 0; 2307 } 2308 2309 static int init_skl_mmio_info(struct intel_gvt *gvt) 2310 { 2311 struct drm_i915_private *dev_priv = gvt->dev_priv; 2312 int ret; 2313 2314 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2315 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2316 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2317 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2318 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2319 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2320 2321 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2322 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2323 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2324 2325 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL); 2326 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write); 2327 2328 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, mailbox_write); 2329 MMIO_D(0xa210, D_SKL_PLUS); 2330 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2331 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2332 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write); 2333 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write); 2334 MMIO_D(0x45504, D_SKL); 2335 MMIO_D(0x45520, D_SKL); 2336 MMIO_D(0x46000, D_SKL); 2337 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write); 2338 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write); 2339 MMIO_D(0x6C040, D_SKL); 2340 MMIO_D(0x6C048, D_SKL); 2341 MMIO_D(0x6C050, D_SKL); 2342 MMIO_D(0x6C044, D_SKL); 2343 MMIO_D(0x6C04C, D_SKL); 2344 MMIO_D(0x6C054, D_SKL); 2345 MMIO_D(0x6c058, D_SKL); 2346 MMIO_D(0x6c05c, D_SKL); 2347 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL); 2348 2349 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write); 2350 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write); 2351 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write); 2352 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write); 2353 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write); 2354 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write); 2355 2356 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write); 2357 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write); 2358 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write); 2359 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write); 2360 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write); 2361 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write); 2362 2363 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write); 2364 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write); 2365 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write); 2366 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write); 2367 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write); 2368 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write); 2369 2370 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2371 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2372 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2373 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2374 2375 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2376 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2377 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2378 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2379 2380 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2381 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2382 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2383 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2384 2385 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL); 2386 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL); 2387 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL); 2388 2389 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2390 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2391 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2392 2393 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2394 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2395 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2396 2397 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2398 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2399 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2400 2401 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2402 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2403 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2404 2405 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL); 2406 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL); 2407 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL); 2408 2409 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL); 2410 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL); 2411 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL); 2412 2413 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL); 2414 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL); 2415 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL); 2416 2417 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL); 2418 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL); 2419 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL); 2420 2421 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2422 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2423 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2424 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2425 2426 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2427 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2428 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2429 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2430 2431 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2432 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2433 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2434 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2435 2436 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL); 2437 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL); 2438 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL); 2439 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL); 2440 2441 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL); 2442 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL); 2443 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL); 2444 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL); 2445 2446 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL); 2447 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL); 2448 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL); 2449 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL); 2450 2451 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL); 2452 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL); 2453 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL); 2454 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL); 2455 2456 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL); 2457 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL); 2458 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL); 2459 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL); 2460 2461 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL); 2462 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL); 2463 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL); 2464 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL); 2465 2466 MMIO_D(0x70380, D_SKL); 2467 MMIO_D(0x71380, D_SKL); 2468 MMIO_D(0x72380, D_SKL); 2469 MMIO_D(0x7039c, D_SKL); 2470 2471 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL); 2472 MMIO_D(0x8f074, D_SKL); 2473 MMIO_D(0x8f004, D_SKL); 2474 MMIO_D(0x8f034, D_SKL); 2475 2476 MMIO_D(0xb11c, D_SKL); 2477 2478 MMIO_D(0x51000, D_SKL); 2479 MMIO_D(0x6c00c, D_SKL); 2480 2481 MMIO_F(0xc800, 0x7f8, 0, 0, 0, D_SKL, NULL, NULL); 2482 MMIO_F(0xb020, 0x80, 0, 0, 0, D_SKL, NULL, NULL); 2483 2484 MMIO_D(0xd08, D_SKL); 2485 MMIO_D(0x20e0, D_SKL); 2486 MMIO_D(0x20ec, D_SKL); 2487 2488 /* TRTT */ 2489 MMIO_D(0x4de0, D_SKL); 2490 MMIO_D(0x4de4, D_SKL); 2491 MMIO_D(0x4de8, D_SKL); 2492 MMIO_D(0x4dec, D_SKL); 2493 MMIO_D(0x4df0, D_SKL); 2494 MMIO_DH(0x4df4, D_SKL, NULL, gen9_trtte_write); 2495 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write); 2496 2497 MMIO_D(0x45008, D_SKL); 2498 2499 MMIO_D(0x46430, D_SKL); 2500 2501 MMIO_D(0x46520, D_SKL); 2502 2503 MMIO_D(0xc403c, D_SKL); 2504 MMIO_D(0xb004, D_SKL); 2505 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2506 2507 MMIO_D(0x65900, D_SKL); 2508 MMIO_D(0x1082c0, D_SKL); 2509 MMIO_D(0x4068, D_SKL); 2510 MMIO_D(0x67054, D_SKL); 2511 MMIO_D(0x6e560, D_SKL); 2512 MMIO_D(0x6e554, D_SKL); 2513 MMIO_D(0x2b20, D_SKL); 2514 MMIO_D(0x65f00, D_SKL); 2515 MMIO_D(0x65f08, D_SKL); 2516 MMIO_D(0x320f0, D_SKL); 2517 2518 MMIO_D(_REG_VCS2_EXCC, D_SKL); 2519 MMIO_D(0x70034, D_SKL); 2520 MMIO_D(0x71034, D_SKL); 2521 MMIO_D(0x72034, D_SKL); 2522 2523 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL); 2524 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL); 2525 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL); 2526 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL); 2527 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL); 2528 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL); 2529 2530 MMIO_D(0x44500, D_SKL); 2531 return 0; 2532 } 2533 2534 /** 2535 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset 2536 * @gvt: GVT device 2537 * @offset: register offset 2538 * 2539 * This function is used to find the MMIO information entry from hash table 2540 * 2541 * Returns: 2542 * pointer to MMIO information entry, NULL if not exists 2543 */ 2544 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 2545 unsigned int offset) 2546 { 2547 struct intel_gvt_mmio_info *e; 2548 2549 WARN_ON(!IS_ALIGNED(offset, 4)); 2550 2551 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 2552 if (e->offset == offset) 2553 return e; 2554 } 2555 return NULL; 2556 } 2557 2558 /** 2559 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2560 * @gvt: GVT device 2561 * 2562 * This function is called at the driver unloading stage, to clean up the MMIO 2563 * information table of GVT device 2564 * 2565 */ 2566 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2567 { 2568 struct hlist_node *tmp; 2569 struct intel_gvt_mmio_info *e; 2570 int i; 2571 2572 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2573 kfree(e); 2574 2575 vfree(gvt->mmio.mmio_attribute); 2576 gvt->mmio.mmio_attribute = NULL; 2577 } 2578 2579 /** 2580 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2581 * @gvt: GVT device 2582 * 2583 * This function is called at the initialization stage, to setup the MMIO 2584 * information table for GVT device 2585 * 2586 * Returns: 2587 * zero on success, negative if failed. 2588 */ 2589 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2590 { 2591 struct intel_gvt_device_info *info = &gvt->device_info; 2592 struct drm_i915_private *dev_priv = gvt->dev_priv; 2593 int ret; 2594 2595 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size); 2596 if (!gvt->mmio.mmio_attribute) 2597 return -ENOMEM; 2598 2599 ret = init_generic_mmio_info(gvt); 2600 if (ret) 2601 goto err; 2602 2603 if (IS_BROADWELL(dev_priv)) { 2604 ret = init_broadwell_mmio_info(gvt); 2605 if (ret) 2606 goto err; 2607 } else if (IS_SKYLAKE(dev_priv)) { 2608 ret = init_broadwell_mmio_info(gvt); 2609 if (ret) 2610 goto err; 2611 ret = init_skl_mmio_info(gvt); 2612 if (ret) 2613 goto err; 2614 } 2615 return 0; 2616 err: 2617 intel_gvt_clean_mmio_info(gvt); 2618 return ret; 2619 } 2620 2621 /** 2622 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 2623 * @gvt: a GVT device 2624 * @offset: register offset 2625 * 2626 */ 2627 void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset) 2628 { 2629 gvt->mmio.mmio_attribute[offset >> 2] |= 2630 F_ACCESSED; 2631 } 2632 2633 /** 2634 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 2635 * @gvt: a GVT device 2636 * @offset: register offset 2637 * 2638 */ 2639 bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt, 2640 unsigned int offset) 2641 { 2642 return gvt->mmio.mmio_attribute[offset >> 2] & 2643 F_CMD_ACCESS; 2644 } 2645 2646 /** 2647 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 2648 * @gvt: a GVT device 2649 * @offset: register offset 2650 * 2651 */ 2652 bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, 2653 unsigned int offset) 2654 { 2655 return gvt->mmio.mmio_attribute[offset >> 2] & 2656 F_UNALIGN; 2657 } 2658 2659 /** 2660 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 2661 * @gvt: a GVT device 2662 * @offset: register offset 2663 * 2664 */ 2665 void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt, 2666 unsigned int offset) 2667 { 2668 gvt->mmio.mmio_attribute[offset >> 2] |= 2669 F_CMD_ACCESSED; 2670 } 2671 2672 /** 2673 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 2674 * @gvt: a GVT device 2675 * @offset: register offset 2676 * 2677 * Returns: 2678 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 2679 * 2680 */ 2681 bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset) 2682 { 2683 return gvt->mmio.mmio_attribute[offset >> 2] & 2684 F_MODE_MASK; 2685 } 2686 2687 /** 2688 * intel_vgpu_default_mmio_read - default MMIO read handler 2689 * @vgpu: a vGPU 2690 * @offset: access offset 2691 * @p_data: data return buffer 2692 * @bytes: access data length 2693 * 2694 * Returns: 2695 * Zero on success, negative error code if failed. 2696 */ 2697 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 2698 void *p_data, unsigned int bytes) 2699 { 2700 read_vreg(vgpu, offset, p_data, bytes); 2701 return 0; 2702 } 2703 2704 /** 2705 * intel_t_default_mmio_write - default MMIO write handler 2706 * @vgpu: a vGPU 2707 * @offset: access offset 2708 * @p_data: write data buffer 2709 * @bytes: access data length 2710 * 2711 * Returns: 2712 * Zero on success, negative error code if failed. 2713 */ 2714 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2715 void *p_data, unsigned int bytes) 2716 { 2717 write_vreg(vgpu, offset, p_data, bytes); 2718 return 0; 2719 } 2720