1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 41 /* XXX FIXME i915 has changed PP_XXX definition */ 42 #define PCH_PP_STATUS _MMIO(0xc7200) 43 #define PCH_PP_CONTROL _MMIO(0xc7204) 44 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 45 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 46 #define PCH_PP_DIVISOR _MMIO(0xc7210) 47 48 /* Register contains RO bits */ 49 #define F_RO (1 << 0) 50 /* Register contains graphics address */ 51 #define F_GMADR (1 << 1) 52 /* Mode mask registers with high 16 bits as the mask bits */ 53 #define F_MODE_MASK (1 << 2) 54 /* This reg can be accessed by GPU commands */ 55 #define F_CMD_ACCESS (1 << 3) 56 /* This reg has been accessed by a VM */ 57 #define F_ACCESSED (1 << 4) 58 /* This reg has been accessed through GPU commands */ 59 #define F_CMD_ACCESSED (1 << 5) 60 /* This reg could be accessed by unaligned address */ 61 #define F_UNALIGN (1 << 6) 62 63 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 64 { 65 if (IS_BROADWELL(gvt->dev_priv)) 66 return D_BDW; 67 else if (IS_SKYLAKE(gvt->dev_priv)) 68 return D_SKL; 69 70 return 0; 71 } 72 73 bool intel_gvt_match_device(struct intel_gvt *gvt, 74 unsigned long device) 75 { 76 return intel_gvt_get_device_type(gvt) & device; 77 } 78 79 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 80 void *p_data, unsigned int bytes) 81 { 82 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 83 } 84 85 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 86 void *p_data, unsigned int bytes) 87 { 88 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 89 } 90 91 static int new_mmio_info(struct intel_gvt *gvt, 92 u32 offset, u32 flags, u32 size, 93 u32 addr_mask, u32 ro_mask, u32 device, 94 void *read, void *write) 95 { 96 struct intel_gvt_mmio_info *info, *p; 97 u32 start, end, i; 98 99 if (!intel_gvt_match_device(gvt, device)) 100 return 0; 101 102 if (WARN_ON(!IS_ALIGNED(offset, 4))) 103 return -EINVAL; 104 105 start = offset; 106 end = offset + size; 107 108 for (i = start; i < end; i += 4) { 109 info = kzalloc(sizeof(*info), GFP_KERNEL); 110 if (!info) 111 return -ENOMEM; 112 113 info->offset = i; 114 p = intel_gvt_find_mmio_info(gvt, info->offset); 115 if (p) 116 gvt_err("dup mmio definition offset %x\n", 117 info->offset); 118 info->size = size; 119 info->length = (i + 4) < end ? 4 : (end - i); 120 info->addr_mask = addr_mask; 121 info->device = device; 122 info->read = read ? read : intel_vgpu_default_mmio_read; 123 info->write = write ? write : intel_vgpu_default_mmio_write; 124 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 125 INIT_HLIST_NODE(&info->node); 126 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 127 } 128 return 0; 129 } 130 131 static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) 132 { 133 int i; 134 135 reg &= ~GENMASK(11, 0); 136 for (i = 0; i < I915_NUM_ENGINES; i++) { 137 if (gvt->dev_priv->engine[i]->mmio_base == reg) 138 return i; 139 } 140 return -1; 141 } 142 143 #define offset_to_fence_num(offset) \ 144 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 145 146 #define fence_num_to_offset(num) \ 147 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 148 149 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 150 unsigned int fence_num, void *p_data, unsigned int bytes) 151 { 152 if (fence_num >= vgpu_fence_sz(vgpu)) { 153 gvt_err("vgpu%d: found oob fence register access\n", 154 vgpu->id); 155 gvt_err("vgpu%d: total fence num %d access fence num %d\n", 156 vgpu->id, vgpu_fence_sz(vgpu), fence_num); 157 memset(p_data, 0, bytes); 158 } 159 return 0; 160 } 161 162 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 163 void *p_data, unsigned int bytes) 164 { 165 int ret; 166 167 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 168 p_data, bytes); 169 if (ret) 170 return ret; 171 read_vreg(vgpu, off, p_data, bytes); 172 return 0; 173 } 174 175 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 176 void *p_data, unsigned int bytes) 177 { 178 unsigned int fence_num = offset_to_fence_num(off); 179 int ret; 180 181 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 182 if (ret) 183 return ret; 184 write_vreg(vgpu, off, p_data, bytes); 185 186 intel_vgpu_write_fence(vgpu, fence_num, 187 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 188 return 0; 189 } 190 191 #define CALC_MODE_MASK_REG(old, new) \ 192 (((new) & GENMASK(31, 16)) \ 193 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 194 | ((new) & ((new) >> 16)))) 195 196 static int mul_force_wake_write(struct intel_vgpu *vgpu, 197 unsigned int offset, void *p_data, unsigned int bytes) 198 { 199 u32 old, new; 200 uint32_t ack_reg_offset; 201 202 old = vgpu_vreg(vgpu, offset); 203 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 204 205 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) { 206 switch (offset) { 207 case FORCEWAKE_RENDER_GEN9_REG: 208 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 209 break; 210 case FORCEWAKE_BLITTER_GEN9_REG: 211 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 212 break; 213 case FORCEWAKE_MEDIA_GEN9_REG: 214 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 215 break; 216 default: 217 /*should not hit here*/ 218 gvt_err("invalid forcewake offset 0x%x\n", offset); 219 return 1; 220 } 221 } else { 222 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 223 } 224 225 vgpu_vreg(vgpu, offset) = new; 226 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 227 return 0; 228 } 229 230 static int handle_device_reset(struct intel_vgpu *vgpu, unsigned int offset, 231 void *p_data, unsigned int bytes, unsigned long bitmap) 232 { 233 struct intel_gvt_workload_scheduler *scheduler = 234 &vgpu->gvt->scheduler; 235 236 vgpu->resetting = true; 237 238 intel_vgpu_stop_schedule(vgpu); 239 if (scheduler->current_vgpu == vgpu) { 240 mutex_unlock(&vgpu->gvt->lock); 241 intel_gvt_wait_vgpu_idle(vgpu); 242 mutex_lock(&vgpu->gvt->lock); 243 } 244 245 intel_vgpu_reset_execlist(vgpu, bitmap); 246 247 vgpu->resetting = false; 248 249 return 0; 250 } 251 252 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 253 void *p_data, unsigned int bytes) 254 { 255 u32 data; 256 u64 bitmap = 0; 257 258 data = vgpu_vreg(vgpu, offset); 259 260 if (data & GEN6_GRDOM_FULL) { 261 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 262 bitmap = 0xff; 263 } 264 if (data & GEN6_GRDOM_RENDER) { 265 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 266 bitmap |= (1 << RCS); 267 } 268 if (data & GEN6_GRDOM_MEDIA) { 269 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 270 bitmap |= (1 << VCS); 271 } 272 if (data & GEN6_GRDOM_BLT) { 273 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 274 bitmap |= (1 << BCS); 275 } 276 if (data & GEN6_GRDOM_VECS) { 277 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 278 bitmap |= (1 << VECS); 279 } 280 if (data & GEN8_GRDOM_MEDIA2) { 281 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 282 if (HAS_BSD2(vgpu->gvt->dev_priv)) 283 bitmap |= (1 << VCS2); 284 } 285 return handle_device_reset(vgpu, offset, p_data, bytes, bitmap); 286 } 287 288 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 289 void *p_data, unsigned int bytes) 290 { 291 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 292 } 293 294 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 295 void *p_data, unsigned int bytes) 296 { 297 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 298 } 299 300 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 301 unsigned int offset, void *p_data, unsigned int bytes) 302 { 303 write_vreg(vgpu, offset, p_data, bytes); 304 305 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 306 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; 307 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 308 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 309 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 310 311 } else 312 vgpu_vreg(vgpu, PCH_PP_STATUS) &= 313 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 314 | PP_CYCLE_DELAY_ACTIVE); 315 return 0; 316 } 317 318 static int transconf_mmio_write(struct intel_vgpu *vgpu, 319 unsigned int offset, void *p_data, unsigned int bytes) 320 { 321 write_vreg(vgpu, offset, p_data, bytes); 322 323 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 324 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 325 else 326 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 327 return 0; 328 } 329 330 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 331 void *p_data, unsigned int bytes) 332 { 333 write_vreg(vgpu, offset, p_data, bytes); 334 335 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 336 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 337 else 338 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 339 340 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 341 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 342 else 343 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 344 345 return 0; 346 } 347 348 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 349 void *p_data, unsigned int bytes) 350 { 351 *(u32 *)p_data = (1 << 17); 352 return 0; 353 } 354 355 static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset, 356 void *p_data, unsigned int bytes) 357 { 358 *(u32 *)p_data = 3; 359 return 0; 360 } 361 362 static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset, 363 void *p_data, unsigned int bytes) 364 { 365 *(u32 *)p_data = (0x2f << 16); 366 return 0; 367 } 368 369 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 370 void *p_data, unsigned int bytes) 371 { 372 u32 data; 373 374 write_vreg(vgpu, offset, p_data, bytes); 375 data = vgpu_vreg(vgpu, offset); 376 377 if (data & PIPECONF_ENABLE) 378 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 379 else 380 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 381 intel_gvt_check_vblank_emulation(vgpu->gvt); 382 return 0; 383 } 384 385 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 386 void *p_data, unsigned int bytes) 387 { 388 write_vreg(vgpu, offset, p_data, bytes); 389 390 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 391 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 392 } else { 393 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 394 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 395 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) 396 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 397 } 398 return 0; 399 } 400 401 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 402 unsigned int offset, void *p_data, unsigned int bytes) 403 { 404 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 405 return 0; 406 } 407 408 #define FDI_LINK_TRAIN_PATTERN1 0 409 #define FDI_LINK_TRAIN_PATTERN2 1 410 411 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 412 { 413 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); 414 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 415 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); 416 417 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 418 (rx_ctl & FDI_RX_ENABLE) && 419 (rx_ctl & FDI_AUTO_TRAINING) && 420 (tx_ctl & DP_TP_CTL_ENABLE) && 421 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 422 return 1; 423 else 424 return 0; 425 } 426 427 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 428 enum pipe pipe, unsigned int train_pattern) 429 { 430 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 431 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 432 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 433 unsigned int fdi_iir_check_bits; 434 435 fdi_rx_imr = FDI_RX_IMR(pipe); 436 fdi_tx_ctl = FDI_TX_CTL(pipe); 437 fdi_rx_ctl = FDI_RX_CTL(pipe); 438 439 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 440 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 441 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 442 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 443 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 444 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 445 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 446 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 447 } else { 448 gvt_err("Invalid train pattern %d\n", train_pattern); 449 return -EINVAL; 450 } 451 452 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 453 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 454 455 /* If imr bit has been masked */ 456 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 457 return 0; 458 459 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 460 == fdi_tx_check_bits) 461 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 462 == fdi_rx_check_bits)) 463 return 1; 464 else 465 return 0; 466 } 467 468 #define INVALID_INDEX (~0U) 469 470 static unsigned int calc_index(unsigned int offset, unsigned int start, 471 unsigned int next, unsigned int end, i915_reg_t i915_end) 472 { 473 unsigned int range = next - start; 474 475 if (!end) 476 end = i915_mmio_reg_offset(i915_end); 477 if (offset < start || offset > end) 478 return INVALID_INDEX; 479 offset -= start; 480 return offset / range; 481 } 482 483 #define FDI_RX_CTL_TO_PIPE(offset) \ 484 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 485 486 #define FDI_TX_CTL_TO_PIPE(offset) \ 487 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 488 489 #define FDI_RX_IMR_TO_PIPE(offset) \ 490 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 491 492 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 493 unsigned int offset, void *p_data, unsigned int bytes) 494 { 495 i915_reg_t fdi_rx_iir; 496 unsigned int index; 497 int ret; 498 499 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 500 index = FDI_RX_CTL_TO_PIPE(offset); 501 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 502 index = FDI_TX_CTL_TO_PIPE(offset); 503 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 504 index = FDI_RX_IMR_TO_PIPE(offset); 505 else { 506 gvt_err("Unsupport registers %x\n", offset); 507 return -EINVAL; 508 } 509 510 write_vreg(vgpu, offset, p_data, bytes); 511 512 fdi_rx_iir = FDI_RX_IIR(index); 513 514 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 515 if (ret < 0) 516 return ret; 517 if (ret) 518 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 519 520 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 521 if (ret < 0) 522 return ret; 523 if (ret) 524 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 525 526 if (offset == _FDI_RXA_CTL) 527 if (fdi_auto_training_started(vgpu)) 528 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= 529 DP_TP_STATUS_AUTOTRAIN_DONE; 530 return 0; 531 } 532 533 #define DP_TP_CTL_TO_PORT(offset) \ 534 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 535 536 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 537 void *p_data, unsigned int bytes) 538 { 539 i915_reg_t status_reg; 540 unsigned int index; 541 u32 data; 542 543 write_vreg(vgpu, offset, p_data, bytes); 544 545 index = DP_TP_CTL_TO_PORT(offset); 546 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 547 if (data == 0x2) { 548 status_reg = DP_TP_STATUS(index); 549 vgpu_vreg(vgpu, status_reg) |= (1 << 25); 550 } 551 return 0; 552 } 553 554 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 555 unsigned int offset, void *p_data, unsigned int bytes) 556 { 557 u32 reg_val; 558 u32 sticky_mask; 559 560 reg_val = *((u32 *)p_data); 561 sticky_mask = GENMASK(27, 26) | (1 << 24); 562 563 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 564 (vgpu_vreg(vgpu, offset) & sticky_mask); 565 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 566 return 0; 567 } 568 569 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 570 unsigned int offset, void *p_data, unsigned int bytes) 571 { 572 u32 data; 573 574 write_vreg(vgpu, offset, p_data, bytes); 575 data = vgpu_vreg(vgpu, offset); 576 577 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 578 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 579 return 0; 580 } 581 582 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 583 unsigned int offset, void *p_data, unsigned int bytes) 584 { 585 u32 data; 586 587 write_vreg(vgpu, offset, p_data, bytes); 588 data = vgpu_vreg(vgpu, offset); 589 590 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 591 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 592 else 593 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 594 return 0; 595 } 596 597 #define DSPSURF_TO_PIPE(offset) \ 598 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 599 600 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 601 void *p_data, unsigned int bytes) 602 { 603 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 604 unsigned int index = DSPSURF_TO_PIPE(offset); 605 i915_reg_t surflive_reg = DSPSURFLIVE(index); 606 int flip_event[] = { 607 [PIPE_A] = PRIMARY_A_FLIP_DONE, 608 [PIPE_B] = PRIMARY_B_FLIP_DONE, 609 [PIPE_C] = PRIMARY_C_FLIP_DONE, 610 }; 611 612 write_vreg(vgpu, offset, p_data, bytes); 613 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 614 615 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 616 return 0; 617 } 618 619 #define SPRSURF_TO_PIPE(offset) \ 620 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 621 622 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 623 void *p_data, unsigned int bytes) 624 { 625 unsigned int index = SPRSURF_TO_PIPE(offset); 626 i915_reg_t surflive_reg = SPRSURFLIVE(index); 627 int flip_event[] = { 628 [PIPE_A] = SPRITE_A_FLIP_DONE, 629 [PIPE_B] = SPRITE_B_FLIP_DONE, 630 [PIPE_C] = SPRITE_C_FLIP_DONE, 631 }; 632 633 write_vreg(vgpu, offset, p_data, bytes); 634 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 635 636 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 637 return 0; 638 } 639 640 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 641 unsigned int reg) 642 { 643 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 644 enum intel_gvt_event_type event; 645 646 if (reg == _DPA_AUX_CH_CTL) 647 event = AUX_CHANNEL_A; 648 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 649 event = AUX_CHANNEL_B; 650 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 651 event = AUX_CHANNEL_C; 652 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 653 event = AUX_CHANNEL_D; 654 else { 655 WARN_ON(true); 656 return -EINVAL; 657 } 658 659 intel_vgpu_trigger_virtual_event(vgpu, event); 660 return 0; 661 } 662 663 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 664 unsigned int reg, int len, bool data_valid) 665 { 666 /* mark transaction done */ 667 value |= DP_AUX_CH_CTL_DONE; 668 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 669 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 670 671 if (data_valid) 672 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 673 else 674 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 675 676 /* message size */ 677 value &= ~(0xf << 20); 678 value |= (len << 20); 679 vgpu_vreg(vgpu, reg) = value; 680 681 if (value & DP_AUX_CH_CTL_INTERRUPT) 682 return trigger_aux_channel_interrupt(vgpu, reg); 683 return 0; 684 } 685 686 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 687 uint8_t t) 688 { 689 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 690 /* training pattern 1 for CR */ 691 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 692 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 693 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 694 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 695 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 696 DPCD_TRAINING_PATTERN_2) { 697 /* training pattern 2 for EQ */ 698 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 699 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 700 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 701 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 702 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 703 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 704 /* set INTERLANE_ALIGN_DONE */ 705 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 706 DPCD_INTERLANE_ALIGN_DONE; 707 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 708 DPCD_LINK_TRAINING_DISABLED) { 709 /* finish link training */ 710 /* set sink status as synchronized */ 711 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 712 } 713 } 714 715 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 716 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 717 718 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 719 720 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 721 722 #define dpy_is_valid_port(port) \ 723 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 724 725 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 726 unsigned int offset, void *p_data, unsigned int bytes) 727 { 728 struct intel_vgpu_display *display = &vgpu->display; 729 int msg, addr, ctrl, op, len; 730 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 731 struct intel_vgpu_dpcd_data *dpcd = NULL; 732 struct intel_vgpu_port *port = NULL; 733 u32 data; 734 735 if (!dpy_is_valid_port(port_index)) { 736 gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id); 737 return 0; 738 } 739 740 write_vreg(vgpu, offset, p_data, bytes); 741 data = vgpu_vreg(vgpu, offset); 742 743 if (IS_SKYLAKE(vgpu->gvt->dev_priv) && 744 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 745 /* SKL DPB/C/D aux ctl register changed */ 746 return 0; 747 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 748 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 749 /* write to the data registers */ 750 return 0; 751 } 752 753 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 754 /* just want to clear the sticky bits */ 755 vgpu_vreg(vgpu, offset) = 0; 756 return 0; 757 } 758 759 port = &display->ports[port_index]; 760 dpcd = port->dpcd; 761 762 /* read out message from DATA1 register */ 763 msg = vgpu_vreg(vgpu, offset + 4); 764 addr = (msg >> 8) & 0xffff; 765 ctrl = (msg >> 24) & 0xff; 766 len = msg & 0xff; 767 op = ctrl >> 4; 768 769 if (op == GVT_AUX_NATIVE_WRITE) { 770 int t; 771 uint8_t buf[16]; 772 773 if ((addr + len + 1) >= DPCD_SIZE) { 774 /* 775 * Write request exceeds what we supported, 776 * DCPD spec: When a Source Device is writing a DPCD 777 * address not supported by the Sink Device, the Sink 778 * Device shall reply with AUX NACK and “M” equal to 779 * zero. 780 */ 781 782 /* NAK the write */ 783 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 784 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 785 return 0; 786 } 787 788 /* 789 * Write request format: (command + address) occupies 790 * 3 bytes, followed by (len + 1) bytes of data. 791 */ 792 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 793 return -EINVAL; 794 795 /* unpack data from vreg to buf */ 796 for (t = 0; t < 4; t++) { 797 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 798 799 buf[t * 4] = (r >> 24) & 0xff; 800 buf[t * 4 + 1] = (r >> 16) & 0xff; 801 buf[t * 4 + 2] = (r >> 8) & 0xff; 802 buf[t * 4 + 3] = r & 0xff; 803 } 804 805 /* write to virtual DPCD */ 806 if (dpcd && dpcd->data_valid) { 807 for (t = 0; t <= len; t++) { 808 int p = addr + t; 809 810 dpcd->data[p] = buf[t]; 811 /* check for link training */ 812 if (p == DPCD_TRAINING_PATTERN_SET) 813 dp_aux_ch_ctl_link_training(dpcd, 814 buf[t]); 815 } 816 } 817 818 /* ACK the write */ 819 vgpu_vreg(vgpu, offset + 4) = 0; 820 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 821 dpcd && dpcd->data_valid); 822 return 0; 823 } 824 825 if (op == GVT_AUX_NATIVE_READ) { 826 int idx, i, ret = 0; 827 828 if ((addr + len + 1) >= DPCD_SIZE) { 829 /* 830 * read request exceeds what we supported 831 * DPCD spec: A Sink Device receiving a Native AUX CH 832 * read request for an unsupported DPCD address must 833 * reply with an AUX ACK and read data set equal to 834 * zero instead of replying with AUX NACK. 835 */ 836 837 /* ACK the READ*/ 838 vgpu_vreg(vgpu, offset + 4) = 0; 839 vgpu_vreg(vgpu, offset + 8) = 0; 840 vgpu_vreg(vgpu, offset + 12) = 0; 841 vgpu_vreg(vgpu, offset + 16) = 0; 842 vgpu_vreg(vgpu, offset + 20) = 0; 843 844 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 845 true); 846 return 0; 847 } 848 849 for (idx = 1; idx <= 5; idx++) { 850 /* clear the data registers */ 851 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 852 } 853 854 /* 855 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 856 */ 857 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 858 return -EINVAL; 859 860 /* read from virtual DPCD to vreg */ 861 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 862 if (dpcd && dpcd->data_valid) { 863 for (i = 1; i <= (len + 1); i++) { 864 int t; 865 866 t = dpcd->data[addr + i - 1]; 867 t <<= (24 - 8 * (i % 4)); 868 ret |= t; 869 870 if ((i % 4 == 3) || (i == (len + 1))) { 871 vgpu_vreg(vgpu, offset + 872 (i / 4 + 1) * 4) = ret; 873 ret = 0; 874 } 875 } 876 } 877 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 878 dpcd && dpcd->data_valid); 879 return 0; 880 } 881 882 /* i2c transaction starts */ 883 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 884 885 if (data & DP_AUX_CH_CTL_INTERRUPT) 886 trigger_aux_channel_interrupt(vgpu, offset); 887 return 0; 888 } 889 890 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 891 void *p_data, unsigned int bytes) 892 { 893 bool vga_disable; 894 895 write_vreg(vgpu, offset, p_data, bytes); 896 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 897 898 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 899 vga_disable ? "Disable" : "Enable"); 900 return 0; 901 } 902 903 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 904 unsigned int sbi_offset) 905 { 906 struct intel_vgpu_display *display = &vgpu->display; 907 int num = display->sbi.number; 908 int i; 909 910 for (i = 0; i < num; ++i) 911 if (display->sbi.registers[i].offset == sbi_offset) 912 break; 913 914 if (i == num) 915 return 0; 916 917 return display->sbi.registers[i].value; 918 } 919 920 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 921 unsigned int offset, u32 value) 922 { 923 struct intel_vgpu_display *display = &vgpu->display; 924 int num = display->sbi.number; 925 int i; 926 927 for (i = 0; i < num; ++i) { 928 if (display->sbi.registers[i].offset == offset) 929 break; 930 } 931 932 if (i == num) { 933 if (num == SBI_REG_MAX) { 934 gvt_err("vgpu%d: SBI caching meets maximum limits\n", 935 vgpu->id); 936 return; 937 } 938 display->sbi.number++; 939 } 940 941 display->sbi.registers[i].offset = offset; 942 display->sbi.registers[i].value = value; 943 } 944 945 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 946 void *p_data, unsigned int bytes) 947 { 948 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 949 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 950 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 951 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 952 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 953 sbi_offset); 954 } 955 read_vreg(vgpu, offset, p_data, bytes); 956 return 0; 957 } 958 959 static bool sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 960 void *p_data, unsigned int bytes) 961 { 962 u32 data; 963 964 write_vreg(vgpu, offset, p_data, bytes); 965 data = vgpu_vreg(vgpu, offset); 966 967 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 968 data |= SBI_READY; 969 970 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 971 data |= SBI_RESPONSE_SUCCESS; 972 973 vgpu_vreg(vgpu, offset) = data; 974 975 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 976 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 977 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 978 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 979 980 write_virtual_sbi_register(vgpu, sbi_offset, 981 vgpu_vreg(vgpu, SBI_DATA)); 982 } 983 return 0; 984 } 985 986 #define _vgtif_reg(x) \ 987 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 988 989 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 990 void *p_data, unsigned int bytes) 991 { 992 bool invalid_read = false; 993 994 read_vreg(vgpu, offset, p_data, bytes); 995 996 switch (offset) { 997 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 998 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 999 invalid_read = true; 1000 break; 1001 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1002 _vgtif_reg(avail_rs.fence_num): 1003 if (offset + bytes > 1004 _vgtif_reg(avail_rs.fence_num) + 4) 1005 invalid_read = true; 1006 break; 1007 case 0x78010: /* vgt_caps */ 1008 case 0x7881c: 1009 break; 1010 default: 1011 invalid_read = true; 1012 break; 1013 } 1014 if (invalid_read) 1015 gvt_err("invalid pvinfo read: [%x:%x] = %x\n", 1016 offset, bytes, *(u32 *)p_data); 1017 return 0; 1018 } 1019 1020 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1021 { 1022 int ret = 0; 1023 1024 switch (notification) { 1025 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1026 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); 1027 break; 1028 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1029 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); 1030 break; 1031 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1032 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); 1033 break; 1034 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1035 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); 1036 break; 1037 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1038 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1039 case 1: /* Remove this in guest driver. */ 1040 break; 1041 default: 1042 gvt_err("Invalid PV notification %d\n", notification); 1043 } 1044 return ret; 1045 } 1046 1047 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1048 { 1049 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1050 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1051 char *env[3] = {NULL, NULL, NULL}; 1052 char vmid_str[20]; 1053 char display_ready_str[20]; 1054 1055 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready); 1056 env[0] = display_ready_str; 1057 1058 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1059 env[1] = vmid_str; 1060 1061 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1062 } 1063 1064 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1065 void *p_data, unsigned int bytes) 1066 { 1067 u32 data; 1068 int ret; 1069 1070 write_vreg(vgpu, offset, p_data, bytes); 1071 data = vgpu_vreg(vgpu, offset); 1072 1073 switch (offset) { 1074 case _vgtif_reg(display_ready): 1075 send_display_ready_uevent(vgpu, data ? 1 : 0); 1076 break; 1077 case _vgtif_reg(g2v_notify): 1078 ret = handle_g2v_notification(vgpu, data); 1079 break; 1080 /* add xhot and yhot to handled list to avoid error log */ 1081 case 0x78830: 1082 case 0x78834: 1083 case _vgtif_reg(pdp[0].lo): 1084 case _vgtif_reg(pdp[0].hi): 1085 case _vgtif_reg(pdp[1].lo): 1086 case _vgtif_reg(pdp[1].hi): 1087 case _vgtif_reg(pdp[2].lo): 1088 case _vgtif_reg(pdp[2].hi): 1089 case _vgtif_reg(pdp[3].lo): 1090 case _vgtif_reg(pdp[3].hi): 1091 case _vgtif_reg(execlist_context_descriptor_lo): 1092 case _vgtif_reg(execlist_context_descriptor_hi): 1093 break; 1094 default: 1095 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n", 1096 offset, bytes, data); 1097 break; 1098 } 1099 return 0; 1100 } 1101 1102 static int pf_write(struct intel_vgpu *vgpu, 1103 unsigned int offset, void *p_data, unsigned int bytes) 1104 { 1105 u32 val = *(u32 *)p_data; 1106 1107 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1108 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1109 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1110 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1111 vgpu->id); 1112 return 0; 1113 } 1114 1115 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1116 } 1117 1118 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1119 unsigned int offset, void *p_data, unsigned int bytes) 1120 { 1121 write_vreg(vgpu, offset, p_data, bytes); 1122 1123 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) 1124 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; 1125 else 1126 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; 1127 return 0; 1128 } 1129 1130 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1131 unsigned int offset, void *p_data, unsigned int bytes) 1132 { 1133 write_vreg(vgpu, offset, p_data, bytes); 1134 1135 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1136 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1137 return 0; 1138 } 1139 1140 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1141 void *p_data, unsigned int bytes) 1142 { 1143 u32 mode = *(u32 *)p_data; 1144 1145 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1146 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n", 1147 vgpu->id); 1148 return 0; 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1155 void *p_data, unsigned int bytes) 1156 { 1157 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1158 u32 trtte = *(u32 *)p_data; 1159 1160 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1161 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1162 vgpu->id); 1163 return -EINVAL; 1164 } 1165 write_vreg(vgpu, offset, p_data, bytes); 1166 /* TRTTE is not per-context */ 1167 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1168 1169 return 0; 1170 } 1171 1172 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1173 void *p_data, unsigned int bytes) 1174 { 1175 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1176 u32 val = *(u32 *)p_data; 1177 1178 if (val & 1) { 1179 /* unblock hw logic */ 1180 I915_WRITE(_MMIO(offset), val); 1181 } 1182 write_vreg(vgpu, offset, p_data, bytes); 1183 return 0; 1184 } 1185 1186 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1187 void *p_data, unsigned int bytes) 1188 { 1189 u32 v = 0; 1190 1191 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1192 v |= (1 << 0); 1193 1194 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1195 v |= (1 << 8); 1196 1197 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1198 v |= (1 << 16); 1199 1200 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1201 v |= (1 << 24); 1202 1203 vgpu_vreg(vgpu, offset) = v; 1204 1205 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1206 } 1207 1208 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1209 void *p_data, unsigned int bytes) 1210 { 1211 u32 value = *(u32 *)p_data; 1212 u32 cmd = value & 0xff; 1213 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); 1214 1215 switch (cmd) { 1216 case 0x6: 1217 /** 1218 * "Read memory latency" command on gen9. 1219 * Below memory latency values are read 1220 * from skylake platform. 1221 */ 1222 if (!*data0) 1223 *data0 = 0x1e1a1100; 1224 else 1225 *data0 = 0x61514b3d; 1226 break; 1227 case 0x5: 1228 *data0 |= 0x1; 1229 break; 1230 } 1231 1232 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1233 vgpu->id, value, *data0); 1234 1235 value &= ~(1 << 31); 1236 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1237 } 1238 1239 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1240 unsigned int offset, void *p_data, unsigned int bytes) 1241 { 1242 u32 v = *(u32 *)p_data; 1243 1244 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1245 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1246 v |= (v >> 1); 1247 1248 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1249 } 1250 1251 static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1252 void *p_data, unsigned int bytes) 1253 { 1254 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1255 i915_reg_t reg = {.reg = offset}; 1256 1257 switch (offset) { 1258 case 0x4ddc: 1259 vgpu_vreg(vgpu, offset) = 0x8000003c; 1260 break; 1261 case 0x42080: 1262 vgpu_vreg(vgpu, offset) = 0x8000; 1263 break; 1264 default: 1265 return -EINVAL; 1266 } 1267 1268 /** 1269 * TODO: need detect stepping info after gvt contain such information 1270 * 0x4ddc enabled after C0, 0x42080 enabled after E0. 1271 */ 1272 I915_WRITE(reg, vgpu_vreg(vgpu, offset)); 1273 return 0; 1274 } 1275 1276 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1277 void *p_data, unsigned int bytes) 1278 { 1279 u32 v = *(u32 *)p_data; 1280 1281 /* other bits are MBZ. */ 1282 v &= (1 << 31) | (1 << 30); 1283 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1284 1285 vgpu_vreg(vgpu, offset) = v; 1286 1287 return 0; 1288 } 1289 1290 static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu, 1291 unsigned int offset, void *p_data, unsigned int bytes) 1292 { 1293 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1294 1295 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1296 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1297 } 1298 1299 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1300 void *p_data, unsigned int bytes) 1301 { 1302 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1303 struct intel_vgpu_execlist *execlist; 1304 u32 data = *(u32 *)p_data; 1305 int ret; 1306 1307 if (WARN_ON(ring_id < 0)) 1308 return -EINVAL; 1309 1310 execlist = &vgpu->execlist[ring_id]; 1311 1312 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data; 1313 if (execlist->elsp_dwords.index == 3) 1314 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1315 1316 ++execlist->elsp_dwords.index; 1317 execlist->elsp_dwords.index &= 0x3; 1318 return 0; 1319 } 1320 1321 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1322 void *p_data, unsigned int bytes) 1323 { 1324 u32 data = *(u32 *)p_data; 1325 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1326 bool enable_execlist; 1327 1328 write_vreg(vgpu, offset, p_data, bytes); 1329 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1330 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1331 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1332 1333 gvt_dbg_core("EXECLIST %s on ring %d\n", 1334 (enable_execlist ? "enabling" : "disabling"), 1335 ring_id); 1336 1337 if (enable_execlist) 1338 intel_vgpu_start_schedule(vgpu); 1339 } 1340 return 0; 1341 } 1342 1343 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1344 unsigned int offset, void *p_data, unsigned int bytes) 1345 { 1346 int rc = 0; 1347 unsigned int id = 0; 1348 1349 switch (offset) { 1350 case 0x4260: 1351 id = RCS; 1352 break; 1353 case 0x4264: 1354 id = VCS; 1355 break; 1356 case 0x4268: 1357 id = VCS2; 1358 break; 1359 case 0x426c: 1360 id = BCS; 1361 break; 1362 case 0x4270: 1363 id = VECS; 1364 break; 1365 default: 1366 rc = -EINVAL; 1367 break; 1368 } 1369 set_bit(id, (void *)vgpu->tlb_handle_pending); 1370 1371 return rc; 1372 } 1373 1374 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1375 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 1376 f, s, am, rm, d, r, w); \ 1377 if (ret) \ 1378 return ret; \ 1379 } while (0) 1380 1381 #define MMIO_D(reg, d) \ 1382 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1383 1384 #define MMIO_DH(reg, d, r, w) \ 1385 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1386 1387 #define MMIO_DFH(reg, d, f, r, w) \ 1388 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1389 1390 #define MMIO_GM(reg, d, r, w) \ 1391 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1392 1393 #define MMIO_RO(reg, d, f, rm, r, w) \ 1394 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1395 1396 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1397 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1398 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1399 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1400 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1401 } while (0) 1402 1403 #define MMIO_RING_D(prefix, d) \ 1404 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1405 1406 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1407 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1408 1409 #define MMIO_RING_GM(prefix, d, r, w) \ 1410 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1411 1412 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1413 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1414 1415 static int init_generic_mmio_info(struct intel_gvt *gvt) 1416 { 1417 struct drm_i915_private *dev_priv = gvt->dev_priv; 1418 int ret; 1419 1420 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1421 1422 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1423 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1424 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1425 MMIO_D(SDEISR, D_ALL); 1426 1427 MMIO_RING_D(RING_HWSTAM, D_ALL); 1428 1429 MMIO_GM(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1430 MMIO_GM(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1431 MMIO_GM(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1432 MMIO_GM(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1433 1434 #define RING_REG(base) (base + 0x28) 1435 MMIO_RING_D(RING_REG, D_ALL); 1436 #undef RING_REG 1437 1438 #define RING_REG(base) (base + 0x134) 1439 MMIO_RING_D(RING_REG, D_ALL); 1440 #undef RING_REG 1441 1442 MMIO_GM(0x2148, D_ALL, NULL, NULL); 1443 MMIO_GM(CCID, D_ALL, NULL, NULL); 1444 MMIO_GM(0x12198, D_ALL, NULL, NULL); 1445 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1446 1447 MMIO_RING_D(RING_TAIL, D_ALL); 1448 MMIO_RING_D(RING_HEAD, D_ALL); 1449 MMIO_RING_D(RING_CTL, D_ALL); 1450 MMIO_RING_D(RING_ACTHD, D_ALL); 1451 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 1452 1453 /* RING MODE */ 1454 #define RING_REG(base) (base + 0x29c) 1455 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK, NULL, ring_mode_mmio_write); 1456 #undef RING_REG 1457 1458 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1459 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL); 1460 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1461 ring_timestamp_mmio_read, NULL); 1462 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1463 ring_timestamp_mmio_read, NULL); 1464 1465 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1466 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL); 1467 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK, NULL, NULL); 1468 1469 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL); 1470 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL); 1471 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK, NULL, NULL); 1472 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK, NULL, NULL); 1473 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK, NULL, NULL); 1474 MMIO_D(GAM_ECOCHK, D_ALL); 1475 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK, NULL, NULL); 1476 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK, NULL, NULL); 1477 MMIO_D(0x9030, D_ALL); 1478 MMIO_D(0x20a0, D_ALL); 1479 MMIO_D(0x2420, D_ALL); 1480 MMIO_D(0x2430, D_ALL); 1481 MMIO_D(0x2434, D_ALL); 1482 MMIO_D(0x2438, D_ALL); 1483 MMIO_D(0x243c, D_ALL); 1484 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK, NULL, NULL); 1485 MMIO_DFH(0xe184, D_ALL, F_MODE_MASK, NULL, NULL); 1486 MMIO_DFH(0xe100, D_ALL, F_MODE_MASK, NULL, NULL); 1487 1488 /* display */ 1489 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1490 MMIO_D(0x602a0, D_ALL); 1491 1492 MMIO_D(0x65050, D_ALL); 1493 MMIO_D(0x650b4, D_ALL); 1494 1495 MMIO_D(0xc4040, D_ALL); 1496 MMIO_D(DERRMR, D_ALL); 1497 1498 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1499 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1500 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1501 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1502 1503 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1504 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1505 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1506 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1507 1508 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1509 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1510 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1511 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1512 1513 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1514 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1515 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1516 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1517 1518 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1519 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1520 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1521 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1522 1523 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1524 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1525 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1526 1527 MMIO_D(CURPOS(PIPE_A), D_ALL); 1528 MMIO_D(CURPOS(PIPE_B), D_ALL); 1529 MMIO_D(CURPOS(PIPE_C), D_ALL); 1530 1531 MMIO_D(CURBASE(PIPE_A), D_ALL); 1532 MMIO_D(CURBASE(PIPE_B), D_ALL); 1533 MMIO_D(CURBASE(PIPE_C), D_ALL); 1534 1535 MMIO_D(0x700ac, D_ALL); 1536 MMIO_D(0x710ac, D_ALL); 1537 MMIO_D(0x720ac, D_ALL); 1538 1539 MMIO_D(0x70090, D_ALL); 1540 MMIO_D(0x70094, D_ALL); 1541 MMIO_D(0x70098, D_ALL); 1542 MMIO_D(0x7009c, D_ALL); 1543 1544 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1545 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1546 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1547 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1548 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1549 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1550 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1551 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1552 1553 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1554 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1555 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1556 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1557 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1558 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1559 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1560 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1561 1562 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1563 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1564 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1565 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1566 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1567 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1568 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1569 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1570 1571 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1572 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1573 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1574 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1575 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1576 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1577 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1578 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1579 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1580 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1581 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1582 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1583 1584 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1585 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1586 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1587 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1588 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1589 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1590 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1591 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1592 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1593 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1594 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1595 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1596 1597 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1598 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1599 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1600 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1601 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1602 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1603 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1604 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1605 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1606 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1607 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1608 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1609 1610 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1611 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1612 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1613 1614 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1615 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1616 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1617 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1618 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1619 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1620 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1621 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1622 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1623 1624 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1625 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1626 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1627 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1628 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1629 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1630 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1631 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1632 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1633 1634 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1635 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1636 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1637 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1638 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1639 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1640 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1641 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1642 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1643 1644 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1645 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1646 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1647 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1648 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1649 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1650 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1651 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1652 1653 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1654 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1655 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1656 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1657 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1658 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1659 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1660 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1661 1662 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1663 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1664 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1665 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1666 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1667 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1668 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1669 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1670 1671 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1672 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1673 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1674 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1675 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1676 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1677 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1678 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1679 1680 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1681 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1682 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1683 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1684 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1685 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1686 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1687 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1688 1689 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1690 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1691 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1692 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1693 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1694 1695 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1696 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1697 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1698 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1699 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1700 1701 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1702 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1703 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1704 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1705 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1706 1707 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1708 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1709 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1710 MMIO_D(WM1_LP_ILK, D_ALL); 1711 MMIO_D(WM2_LP_ILK, D_ALL); 1712 MMIO_D(WM3_LP_ILK, D_ALL); 1713 MMIO_D(WM1S_LP_ILK, D_ALL); 1714 MMIO_D(WM2S_LP_IVB, D_ALL); 1715 MMIO_D(WM3S_LP_IVB, D_ALL); 1716 1717 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1718 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1719 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1720 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1721 1722 MMIO_D(0x48268, D_ALL); 1723 1724 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1725 gmbus_mmio_write); 1726 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1727 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1728 1729 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1730 dp_aux_ch_ctl_mmio_write); 1731 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1732 dp_aux_ch_ctl_mmio_write); 1733 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1734 dp_aux_ch_ctl_mmio_write); 1735 1736 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write); 1737 1738 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); 1739 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); 1740 1741 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1742 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1743 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1744 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1745 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1746 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1747 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1748 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1749 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1750 1751 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 1752 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 1753 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 1754 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 1755 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 1756 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 1757 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 1758 1759 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 1760 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 1761 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 1762 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 1763 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 1764 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 1765 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 1766 1767 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 1768 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 1769 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 1770 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 1771 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 1772 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 1773 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 1774 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 1775 1776 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 1777 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 1778 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 1779 1780 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 1781 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 1782 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 1783 1784 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 1785 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 1786 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 1787 1788 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 1789 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 1790 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 1791 1792 MMIO_D(_FDI_RXA_MISC, D_ALL); 1793 MMIO_D(_FDI_RXB_MISC, D_ALL); 1794 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 1795 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 1796 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 1797 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 1798 1799 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 1800 MMIO_D(PCH_PP_DIVISOR, D_ALL); 1801 MMIO_D(PCH_PP_STATUS, D_ALL); 1802 MMIO_D(PCH_LVDS, D_ALL); 1803 MMIO_D(_PCH_DPLL_A, D_ALL); 1804 MMIO_D(_PCH_DPLL_B, D_ALL); 1805 MMIO_D(_PCH_FPA0, D_ALL); 1806 MMIO_D(_PCH_FPA1, D_ALL); 1807 MMIO_D(_PCH_FPB0, D_ALL); 1808 MMIO_D(_PCH_FPB1, D_ALL); 1809 MMIO_D(PCH_DREF_CONTROL, D_ALL); 1810 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 1811 MMIO_D(PCH_DPLL_SEL, D_ALL); 1812 1813 MMIO_D(0x61208, D_ALL); 1814 MMIO_D(0x6120c, D_ALL); 1815 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 1816 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 1817 1818 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); 1819 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); 1820 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); 1821 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); 1822 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL); 1823 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL); 1824 1825 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 1826 PORTA_HOTPLUG_STATUS_MASK 1827 | PORTB_HOTPLUG_STATUS_MASK 1828 | PORTC_HOTPLUG_STATUS_MASK 1829 | PORTD_HOTPLUG_STATUS_MASK, 1830 NULL, NULL); 1831 1832 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 1833 MMIO_D(FUSE_STRAP, D_ALL); 1834 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 1835 1836 MMIO_D(DISP_ARB_CTL, D_ALL); 1837 MMIO_D(DISP_ARB_CTL2, D_ALL); 1838 1839 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 1840 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 1841 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 1842 1843 MMIO_D(SOUTH_CHICKEN1, D_ALL); 1844 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 1845 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 1846 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 1847 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 1848 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 1849 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 1850 1851 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 1852 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 1853 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 1854 MMIO_D(ILK_DPFC_STATUS, D_ALL); 1855 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 1856 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 1857 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 1858 1859 MMIO_D(IPS_CTL, D_ALL); 1860 1861 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 1862 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 1863 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 1864 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 1865 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 1866 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 1867 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 1868 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 1869 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 1870 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 1871 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 1872 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 1873 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 1874 1875 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 1876 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 1877 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 1878 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 1879 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 1880 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 1881 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 1882 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 1883 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 1884 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 1885 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 1886 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 1887 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 1888 1889 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 1890 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 1891 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 1892 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 1893 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 1894 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 1895 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 1896 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 1897 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 1898 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 1899 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 1900 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 1901 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 1902 1903 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 1904 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 1905 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1906 1907 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 1908 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 1909 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1910 1911 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 1912 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 1913 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1914 1915 MMIO_D(0x60110, D_ALL); 1916 MMIO_D(0x61110, D_ALL); 1917 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1918 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1919 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1920 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1921 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1922 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1923 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1924 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1925 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1926 1927 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 1928 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 1929 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 1930 MMIO_D(SPLL_CTL, D_ALL); 1931 MMIO_D(_WRPLL_CTL1, D_ALL); 1932 MMIO_D(_WRPLL_CTL2, D_ALL); 1933 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 1934 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 1935 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 1936 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 1937 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 1938 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 1939 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 1940 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 1941 1942 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 1943 MMIO_D(0x46508, D_ALL); 1944 1945 MMIO_D(0x49080, D_ALL); 1946 MMIO_D(0x49180, D_ALL); 1947 MMIO_D(0x49280, D_ALL); 1948 1949 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1950 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1951 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1952 1953 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 1954 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 1955 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 1956 1957 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 1958 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 1959 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 1960 1961 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 1962 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 1963 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 1964 1965 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 1966 MMIO_D(SBI_ADDR, D_ALL); 1967 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 1968 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 1969 MMIO_D(PIXCLK_GATE, D_ALL); 1970 1971 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, 1972 dp_aux_ch_ctl_mmio_write); 1973 1974 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1975 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1976 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1977 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1978 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1979 1980 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 1981 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 1982 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 1983 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 1984 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 1985 1986 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 1987 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 1988 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 1989 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 1990 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 1991 1992 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1993 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1994 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1995 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1996 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1997 1998 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 1999 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2000 2001 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 2002 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 2003 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 2004 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 2005 2006 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 2007 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 2008 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 2009 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 2010 2011 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2012 MMIO_D(FORCEWAKE_ACK, D_ALL); 2013 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2014 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2015 MMIO_D(GTFIFODBG, D_ALL); 2016 MMIO_D(GTFIFOCTL, D_ALL); 2017 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2018 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL); 2019 MMIO_D(ECOBUS, D_ALL); 2020 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2021 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2022 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2023 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2024 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2025 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2026 MMIO_D(GEN6_RPSTAT1, D_ALL); 2027 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2028 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2029 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2030 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2031 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2032 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2033 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2034 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2035 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2036 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2037 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2038 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2039 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2040 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2041 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2042 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2043 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2044 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2045 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2046 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2047 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2048 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2049 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2050 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2051 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2052 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2053 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2054 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2055 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2056 2057 MMIO_D(RSTDBYCTL, D_ALL); 2058 2059 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2060 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2061 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write); 2062 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2063 2064 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL); 2065 2066 MMIO_D(TILECTL, D_ALL); 2067 2068 MMIO_D(GEN6_UCGCTL1, D_ALL); 2069 MMIO_D(GEN6_UCGCTL2, D_ALL); 2070 2071 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2072 2073 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_SKL); 2074 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2075 MMIO_D(0x13812c, D_ALL); 2076 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2077 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2078 MMIO_D(HSW_IDICR, D_ALL); 2079 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2080 2081 MMIO_D(0x3c, D_ALL); 2082 MMIO_D(0x860, D_ALL); 2083 MMIO_D(ECOSKPD, D_ALL); 2084 MMIO_D(0x121d0, D_ALL); 2085 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2086 MMIO_D(0x41d0, D_ALL); 2087 MMIO_D(GAC_ECO_BITS, D_ALL); 2088 MMIO_D(0x6200, D_ALL); 2089 MMIO_D(0x6204, D_ALL); 2090 MMIO_D(0x6208, D_ALL); 2091 MMIO_D(0x7118, D_ALL); 2092 MMIO_D(0x7180, D_ALL); 2093 MMIO_D(0x7408, D_ALL); 2094 MMIO_D(0x7c00, D_ALL); 2095 MMIO_D(GEN6_MBCTL, D_ALL); 2096 MMIO_D(0x911c, D_ALL); 2097 MMIO_D(0x9120, D_ALL); 2098 2099 MMIO_D(GAB_CTL, D_ALL); 2100 MMIO_D(0x48800, D_ALL); 2101 MMIO_D(0xce044, D_ALL); 2102 MMIO_D(0xe6500, D_ALL); 2103 MMIO_D(0xe6504, D_ALL); 2104 MMIO_D(0xe6600, D_ALL); 2105 MMIO_D(0xe6604, D_ALL); 2106 MMIO_D(0xe6700, D_ALL); 2107 MMIO_D(0xe6704, D_ALL); 2108 MMIO_D(0xe6800, D_ALL); 2109 MMIO_D(0xe6804, D_ALL); 2110 MMIO_D(PCH_GMBUS4, D_ALL); 2111 MMIO_D(PCH_GMBUS5, D_ALL); 2112 2113 MMIO_D(0x902c, D_ALL); 2114 MMIO_D(0xec008, D_ALL); 2115 MMIO_D(0xec00c, D_ALL); 2116 MMIO_D(0xec008 + 0x18, D_ALL); 2117 MMIO_D(0xec00c + 0x18, D_ALL); 2118 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 2119 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 2120 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 2121 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 2122 MMIO_D(0xec408, D_ALL); 2123 MMIO_D(0xec40c, D_ALL); 2124 MMIO_D(0xec408 + 0x18, D_ALL); 2125 MMIO_D(0xec40c + 0x18, D_ALL); 2126 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 2127 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 2128 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 2129 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 2130 MMIO_D(0xfc810, D_ALL); 2131 MMIO_D(0xfc81c, D_ALL); 2132 MMIO_D(0xfc828, D_ALL); 2133 MMIO_D(0xfc834, D_ALL); 2134 MMIO_D(0xfcc00, D_ALL); 2135 MMIO_D(0xfcc0c, D_ALL); 2136 MMIO_D(0xfcc18, D_ALL); 2137 MMIO_D(0xfcc24, D_ALL); 2138 MMIO_D(0xfd000, D_ALL); 2139 MMIO_D(0xfd00c, D_ALL); 2140 MMIO_D(0xfd018, D_ALL); 2141 MMIO_D(0xfd024, D_ALL); 2142 MMIO_D(0xfd034, D_ALL); 2143 2144 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2145 MMIO_D(0x2054, D_ALL); 2146 MMIO_D(0x12054, D_ALL); 2147 MMIO_D(0x22054, D_ALL); 2148 MMIO_D(0x1a054, D_ALL); 2149 2150 MMIO_D(0x44070, D_ALL); 2151 2152 MMIO_D(0x215c, D_HSW_PLUS); 2153 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2154 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2155 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2156 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2157 2158 MMIO_F(0x2290, 8, 0, 0, 0, D_HSW_PLUS, NULL, NULL); 2159 MMIO_D(OACONTROL, D_HSW); 2160 MMIO_D(0x2b00, D_BDW_PLUS); 2161 MMIO_D(0x2360, D_BDW_PLUS); 2162 MMIO_F(0x5200, 32, 0, 0, 0, D_ALL, NULL, NULL); 2163 MMIO_F(0x5240, 32, 0, 0, 0, D_ALL, NULL, NULL); 2164 MMIO_F(0x5280, 16, 0, 0, 0, D_ALL, NULL, NULL); 2165 2166 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2167 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2168 MMIO_D(BCS_SWCTRL, D_ALL); 2169 2170 MMIO_F(HS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2171 MMIO_F(DS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2172 MMIO_F(IA_VERTICES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2173 MMIO_F(IA_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2174 MMIO_F(VS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2175 MMIO_F(GS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2176 MMIO_F(GS_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2177 MMIO_F(CL_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2178 MMIO_F(CL_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2179 MMIO_F(PS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2180 MMIO_F(PS_DEPTH_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2181 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2182 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2183 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2184 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2185 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2186 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2187 2188 return 0; 2189 } 2190 2191 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2192 { 2193 struct drm_i915_private *dev_priv = gvt->dev_priv; 2194 int ret; 2195 2196 MMIO_DH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, 2197 intel_vgpu_reg_imr_handler); 2198 2199 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2200 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2201 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2202 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2203 2204 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2205 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2206 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2207 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2208 2209 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2210 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2211 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2212 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2213 2214 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2215 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2216 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2217 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2218 2219 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2220 intel_vgpu_reg_imr_handler); 2221 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2222 intel_vgpu_reg_ier_handler); 2223 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2224 intel_vgpu_reg_iir_handler); 2225 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2226 2227 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2228 intel_vgpu_reg_imr_handler); 2229 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2230 intel_vgpu_reg_ier_handler); 2231 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2232 intel_vgpu_reg_iir_handler); 2233 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2234 2235 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2236 intel_vgpu_reg_imr_handler); 2237 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2238 intel_vgpu_reg_ier_handler); 2239 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2240 intel_vgpu_reg_iir_handler); 2241 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2242 2243 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2244 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2245 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2246 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2247 2248 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2249 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2250 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2251 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2252 2253 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2254 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2255 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2256 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2257 2258 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2259 intel_vgpu_reg_master_irq_handler); 2260 2261 MMIO_D(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2262 MMIO_D(0x1c134, D_BDW_PLUS); 2263 2264 MMIO_D(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2265 MMIO_D(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2266 MMIO_GM(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2267 MMIO_D(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2268 MMIO_D(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2269 MMIO_D(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2270 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK, NULL, ring_mode_mmio_write); 2271 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2272 NULL, NULL); 2273 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2274 NULL, NULL); 2275 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2276 ring_timestamp_mmio_read, NULL); 2277 2278 MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS); 2279 2280 #define RING_REG(base) (base + 0x230) 2281 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2282 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write); 2283 #undef RING_REG 2284 2285 #define RING_REG(base) (base + 0x234) 2286 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2287 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, ~0LL, D_BDW_PLUS, NULL, NULL); 2288 #undef RING_REG 2289 2290 #define RING_REG(base) (base + 0x244) 2291 MMIO_RING_D(RING_REG, D_BDW_PLUS); 2292 MMIO_D(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2293 #undef RING_REG 2294 2295 #define RING_REG(base) (base + 0x370) 2296 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2297 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS, 2298 NULL, NULL); 2299 #undef RING_REG 2300 2301 #define RING_REG(base) (base + 0x3a0) 2302 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2303 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2304 #undef RING_REG 2305 2306 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2307 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2308 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2309 MMIO_D(0x1c1d0, D_BDW_PLUS); 2310 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2311 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2312 MMIO_D(0x1c054, D_BDW_PLUS); 2313 2314 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2315 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2316 2317 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2318 2319 #define RING_REG(base) (base + 0x270) 2320 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2321 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2322 #undef RING_REG 2323 2324 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); 2325 MMIO_GM(0x1c080, D_BDW_PLUS, NULL, NULL); 2326 2327 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2328 2329 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW); 2330 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW); 2331 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW); 2332 2333 MMIO_D(WM_MISC, D_BDW); 2334 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 2335 2336 MMIO_D(0x66c00, D_BDW_PLUS); 2337 MMIO_D(0x66c04, D_BDW_PLUS); 2338 2339 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2340 2341 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2342 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2343 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2344 2345 MMIO_D(0xfdc, D_BDW); 2346 MMIO_D(GEN8_ROW_CHICKEN, D_BDW_PLUS); 2347 MMIO_D(GEN7_ROW_CHICKEN2, D_BDW_PLUS); 2348 MMIO_D(GEN8_UCGCTL6, D_BDW_PLUS); 2349 2350 MMIO_D(0xb1f0, D_BDW); 2351 MMIO_D(0xb1c0, D_BDW); 2352 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2353 MMIO_D(0xb100, D_BDW); 2354 MMIO_D(0xb10c, D_BDW); 2355 MMIO_D(0xb110, D_BDW); 2356 2357 MMIO_DH(0x24d0, D_BDW_PLUS, NULL, NULL); 2358 MMIO_DH(0x24d4, D_BDW_PLUS, NULL, NULL); 2359 MMIO_DH(0x24d8, D_BDW_PLUS, NULL, NULL); 2360 MMIO_DH(0x24dc, D_BDW_PLUS, NULL, NULL); 2361 2362 MMIO_D(0x83a4, D_BDW); 2363 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2364 2365 MMIO_D(0x8430, D_BDW); 2366 2367 MMIO_D(0x110000, D_BDW_PLUS); 2368 2369 MMIO_D(0x48400, D_BDW_PLUS); 2370 2371 MMIO_D(0x6e570, D_BDW_PLUS); 2372 MMIO_D(0x65f10, D_BDW_PLUS); 2373 2374 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2375 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2376 MMIO_DFH(0xe180, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2377 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2378 2379 MMIO_D(0x2248, D_BDW); 2380 2381 return 0; 2382 } 2383 2384 static int init_skl_mmio_info(struct intel_gvt *gvt) 2385 { 2386 struct drm_i915_private *dev_priv = gvt->dev_priv; 2387 int ret; 2388 2389 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2390 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2391 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2392 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2393 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2394 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2395 2396 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2397 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2398 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2399 2400 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL); 2401 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write); 2402 2403 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, mailbox_write); 2404 MMIO_D(0xa210, D_SKL_PLUS); 2405 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2406 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2407 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write); 2408 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write); 2409 MMIO_D(0x45504, D_SKL); 2410 MMIO_D(0x45520, D_SKL); 2411 MMIO_D(0x46000, D_SKL); 2412 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write); 2413 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write); 2414 MMIO_D(0x6C040, D_SKL); 2415 MMIO_D(0x6C048, D_SKL); 2416 MMIO_D(0x6C050, D_SKL); 2417 MMIO_D(0x6C044, D_SKL); 2418 MMIO_D(0x6C04C, D_SKL); 2419 MMIO_D(0x6C054, D_SKL); 2420 MMIO_D(0x6c058, D_SKL); 2421 MMIO_D(0x6c05c, D_SKL); 2422 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL); 2423 2424 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write); 2425 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write); 2426 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write); 2427 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write); 2428 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write); 2429 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write); 2430 2431 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write); 2432 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write); 2433 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write); 2434 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write); 2435 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write); 2436 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write); 2437 2438 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write); 2439 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write); 2440 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write); 2441 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write); 2442 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write); 2443 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write); 2444 2445 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2446 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2447 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2448 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2449 2450 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2451 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2452 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2453 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2454 2455 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2456 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2457 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2458 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2459 2460 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL); 2461 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL); 2462 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL); 2463 2464 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2465 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2466 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2467 2468 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2469 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2470 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2471 2472 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2473 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2474 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2475 2476 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2477 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2478 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2479 2480 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL); 2481 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL); 2482 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL); 2483 2484 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL); 2485 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL); 2486 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL); 2487 2488 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL); 2489 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL); 2490 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL); 2491 2492 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL); 2493 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL); 2494 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL); 2495 2496 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2497 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2498 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2499 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2500 2501 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2502 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2503 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2504 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2505 2506 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2507 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2508 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2509 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2510 2511 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL); 2512 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL); 2513 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL); 2514 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL); 2515 2516 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL); 2517 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL); 2518 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL); 2519 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL); 2520 2521 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL); 2522 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL); 2523 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL); 2524 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL); 2525 2526 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL); 2527 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL); 2528 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL); 2529 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL); 2530 2531 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL); 2532 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL); 2533 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL); 2534 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL); 2535 2536 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL); 2537 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL); 2538 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL); 2539 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL); 2540 2541 MMIO_D(0x70380, D_SKL); 2542 MMIO_D(0x71380, D_SKL); 2543 MMIO_D(0x72380, D_SKL); 2544 MMIO_D(0x7039c, D_SKL); 2545 2546 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL); 2547 MMIO_D(0x8f074, D_SKL); 2548 MMIO_D(0x8f004, D_SKL); 2549 MMIO_D(0x8f034, D_SKL); 2550 2551 MMIO_D(0xb11c, D_SKL); 2552 2553 MMIO_D(0x51000, D_SKL); 2554 MMIO_D(0x6c00c, D_SKL); 2555 2556 MMIO_F(0xc800, 0x7f8, 0, 0, 0, D_SKL, NULL, NULL); 2557 MMIO_F(0xb020, 0x80, 0, 0, 0, D_SKL, NULL, NULL); 2558 2559 MMIO_D(0xd08, D_SKL); 2560 MMIO_D(0x20e0, D_SKL); 2561 MMIO_D(0x20ec, D_SKL); 2562 2563 /* TRTT */ 2564 MMIO_D(0x4de0, D_SKL); 2565 MMIO_D(0x4de4, D_SKL); 2566 MMIO_D(0x4de8, D_SKL); 2567 MMIO_D(0x4dec, D_SKL); 2568 MMIO_D(0x4df0, D_SKL); 2569 MMIO_DH(0x4df4, D_SKL, NULL, gen9_trtte_write); 2570 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write); 2571 2572 MMIO_D(0x45008, D_SKL); 2573 2574 MMIO_D(0x46430, D_SKL); 2575 2576 MMIO_D(0x46520, D_SKL); 2577 2578 MMIO_D(0xc403c, D_SKL); 2579 MMIO_D(0xb004, D_SKL); 2580 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2581 2582 MMIO_D(0x65900, D_SKL); 2583 MMIO_D(0x1082c0, D_SKL); 2584 MMIO_D(0x4068, D_SKL); 2585 MMIO_D(0x67054, D_SKL); 2586 MMIO_D(0x6e560, D_SKL); 2587 MMIO_D(0x6e554, D_SKL); 2588 MMIO_D(0x2b20, D_SKL); 2589 MMIO_D(0x65f00, D_SKL); 2590 MMIO_D(0x65f08, D_SKL); 2591 MMIO_D(0x320f0, D_SKL); 2592 2593 MMIO_D(_REG_VCS2_EXCC, D_SKL); 2594 MMIO_D(0x70034, D_SKL); 2595 MMIO_D(0x71034, D_SKL); 2596 MMIO_D(0x72034, D_SKL); 2597 2598 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL); 2599 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL); 2600 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL); 2601 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL); 2602 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL); 2603 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL); 2604 2605 MMIO_D(0x44500, D_SKL); 2606 return 0; 2607 } 2608 2609 /** 2610 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset 2611 * @gvt: GVT device 2612 * @offset: register offset 2613 * 2614 * This function is used to find the MMIO information entry from hash table 2615 * 2616 * Returns: 2617 * pointer to MMIO information entry, NULL if not exists 2618 */ 2619 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 2620 unsigned int offset) 2621 { 2622 struct intel_gvt_mmio_info *e; 2623 2624 WARN_ON(!IS_ALIGNED(offset, 4)); 2625 2626 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 2627 if (e->offset == offset) 2628 return e; 2629 } 2630 return NULL; 2631 } 2632 2633 /** 2634 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2635 * @gvt: GVT device 2636 * 2637 * This function is called at the driver unloading stage, to clean up the MMIO 2638 * information table of GVT device 2639 * 2640 */ 2641 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2642 { 2643 struct hlist_node *tmp; 2644 struct intel_gvt_mmio_info *e; 2645 int i; 2646 2647 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2648 kfree(e); 2649 2650 vfree(gvt->mmio.mmio_attribute); 2651 gvt->mmio.mmio_attribute = NULL; 2652 } 2653 2654 /** 2655 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2656 * @gvt: GVT device 2657 * 2658 * This function is called at the initialization stage, to setup the MMIO 2659 * information table for GVT device 2660 * 2661 * Returns: 2662 * zero on success, negative if failed. 2663 */ 2664 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2665 { 2666 struct intel_gvt_device_info *info = &gvt->device_info; 2667 struct drm_i915_private *dev_priv = gvt->dev_priv; 2668 int ret; 2669 2670 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size); 2671 if (!gvt->mmio.mmio_attribute) 2672 return -ENOMEM; 2673 2674 ret = init_generic_mmio_info(gvt); 2675 if (ret) 2676 goto err; 2677 2678 if (IS_BROADWELL(dev_priv)) { 2679 ret = init_broadwell_mmio_info(gvt); 2680 if (ret) 2681 goto err; 2682 } else if (IS_SKYLAKE(dev_priv)) { 2683 ret = init_broadwell_mmio_info(gvt); 2684 if (ret) 2685 goto err; 2686 ret = init_skl_mmio_info(gvt); 2687 if (ret) 2688 goto err; 2689 } 2690 return 0; 2691 err: 2692 intel_gvt_clean_mmio_info(gvt); 2693 return ret; 2694 } 2695 2696 /** 2697 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 2698 * @gvt: a GVT device 2699 * @offset: register offset 2700 * 2701 */ 2702 void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset) 2703 { 2704 gvt->mmio.mmio_attribute[offset >> 2] |= 2705 F_ACCESSED; 2706 } 2707 2708 /** 2709 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 2710 * @gvt: a GVT device 2711 * @offset: register offset 2712 * 2713 */ 2714 bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt, 2715 unsigned int offset) 2716 { 2717 return gvt->mmio.mmio_attribute[offset >> 2] & 2718 F_CMD_ACCESS; 2719 } 2720 2721 /** 2722 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 2723 * @gvt: a GVT device 2724 * @offset: register offset 2725 * 2726 */ 2727 bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, 2728 unsigned int offset) 2729 { 2730 return gvt->mmio.mmio_attribute[offset >> 2] & 2731 F_UNALIGN; 2732 } 2733 2734 /** 2735 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 2736 * @gvt: a GVT device 2737 * @offset: register offset 2738 * 2739 */ 2740 void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt, 2741 unsigned int offset) 2742 { 2743 gvt->mmio.mmio_attribute[offset >> 2] |= 2744 F_CMD_ACCESSED; 2745 } 2746 2747 /** 2748 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 2749 * @gvt: a GVT device 2750 * @offset: register offset 2751 * 2752 * Returns: 2753 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 2754 * 2755 */ 2756 bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset) 2757 { 2758 return gvt->mmio.mmio_attribute[offset >> 2] & 2759 F_MODE_MASK; 2760 } 2761 2762 /** 2763 * intel_vgpu_default_mmio_read - default MMIO read handler 2764 * @vgpu: a vGPU 2765 * @offset: access offset 2766 * @p_data: data return buffer 2767 * @bytes: access data length 2768 * 2769 * Returns: 2770 * Zero on success, negative error code if failed. 2771 */ 2772 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 2773 void *p_data, unsigned int bytes) 2774 { 2775 read_vreg(vgpu, offset, p_data, bytes); 2776 return 0; 2777 } 2778 2779 /** 2780 * intel_t_default_mmio_write - default MMIO write handler 2781 * @vgpu: a vGPU 2782 * @offset: access offset 2783 * @p_data: write data buffer 2784 * @bytes: access data length 2785 * 2786 * Returns: 2787 * Zero on success, negative error code if failed. 2788 */ 2789 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2790 void *p_data, unsigned int bytes) 2791 { 2792 write_vreg(vgpu, offset, p_data, bytes); 2793 return 0; 2794 } 2795