1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "i915_reg.h" 41 #include "gvt.h" 42 #include "i915_pvinfo.h" 43 #include "intel_mchbar_regs.h" 44 #include "display/intel_display_types.h" 45 #include "display/intel_dmc_regs.h" 46 #include "display/intel_dpio_phy.h" 47 #include "display/intel_fbc.h" 48 #include "display/vlv_dsi_pll_regs.h" 49 #include "gt/intel_gt_regs.h" 50 51 /* XXX FIXME i915 has changed PP_XXX definition */ 52 #define PCH_PP_STATUS _MMIO(0xc7200) 53 #define PCH_PP_CONTROL _MMIO(0xc7204) 54 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 55 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 56 #define PCH_PP_DIVISOR _MMIO(0xc7210) 57 58 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 59 { 60 struct drm_i915_private *i915 = gvt->gt->i915; 61 62 if (IS_BROADWELL(i915)) 63 return D_BDW; 64 else if (IS_SKYLAKE(i915)) 65 return D_SKL; 66 else if (IS_KABYLAKE(i915)) 67 return D_KBL; 68 else if (IS_BROXTON(i915)) 69 return D_BXT; 70 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 71 return D_CFL; 72 73 return 0; 74 } 75 76 static bool intel_gvt_match_device(struct intel_gvt *gvt, 77 unsigned long device) 78 { 79 return intel_gvt_get_device_type(gvt) & device; 80 } 81 82 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 83 void *p_data, unsigned int bytes) 84 { 85 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 86 } 87 88 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 89 void *p_data, unsigned int bytes) 90 { 91 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 92 } 93 94 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 95 unsigned int offset) 96 { 97 struct intel_gvt_mmio_info *e; 98 99 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 100 if (e->offset == offset) 101 return e; 102 } 103 return NULL; 104 } 105 106 static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size, 107 u16 flags, u32 addr_mask, u32 ro_mask, u32 device, 108 gvt_mmio_func read, gvt_mmio_func write) 109 { 110 struct intel_gvt_mmio_info *p; 111 u32 start, end, i; 112 113 if (!intel_gvt_match_device(gvt, device)) 114 return 0; 115 116 if (WARN_ON(!IS_ALIGNED(offset, 4))) 117 return -EINVAL; 118 119 start = offset; 120 end = offset + size; 121 122 for (i = start; i < end; i += 4) { 123 p = intel_gvt_find_mmio_info(gvt, i); 124 if (!p) { 125 WARN(1, "assign a handler to a non-tracked mmio %x\n", 126 i); 127 return -ENODEV; 128 } 129 p->ro_mask = ro_mask; 130 gvt->mmio.mmio_attribute[i / 4] = flags; 131 if (read) 132 p->read = read; 133 if (write) 134 p->write = write; 135 } 136 return 0; 137 } 138 139 /** 140 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine 141 * @gvt: a GVT device 142 * @offset: register offset 143 * 144 * Returns: 145 * The engine containing the offset within its mmio page. 146 */ 147 const struct intel_engine_cs * 148 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset) 149 { 150 struct intel_engine_cs *engine; 151 enum intel_engine_id id; 152 153 offset &= ~GENMASK(11, 0); 154 for_each_engine(engine, gvt->gt, id) 155 if (engine->mmio_base == offset) 156 return engine; 157 158 return NULL; 159 } 160 161 #define offset_to_fence_num(offset) \ 162 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 163 164 #define fence_num_to_offset(num) \ 165 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 166 167 168 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 169 { 170 switch (reason) { 171 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 172 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 173 break; 174 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 175 pr_err("Graphics resource is not enough for the guest\n"); 176 break; 177 case GVT_FAILSAFE_GUEST_ERR: 178 pr_err("GVT Internal error for the guest\n"); 179 break; 180 default: 181 break; 182 } 183 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 184 vgpu->failsafe = true; 185 } 186 187 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 188 unsigned int fence_num, void *p_data, unsigned int bytes) 189 { 190 unsigned int max_fence = vgpu_fence_sz(vgpu); 191 192 if (fence_num >= max_fence) { 193 gvt_vgpu_err("access oob fence reg %d/%d\n", 194 fence_num, max_fence); 195 196 /* When guest access oob fence regs without access 197 * pv_info first, we treat guest not supporting GVT, 198 * and we will let vgpu enter failsafe mode. 199 */ 200 if (!vgpu->pv_notified) 201 enter_failsafe_mode(vgpu, 202 GVT_FAILSAFE_UNSUPPORTED_GUEST); 203 204 memset(p_data, 0, bytes); 205 return -EINVAL; 206 } 207 return 0; 208 } 209 210 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 211 unsigned int offset, void *p_data, unsigned int bytes) 212 { 213 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; 214 215 if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) { 216 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) 217 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); 218 else if (!ips) 219 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); 220 else { 221 /* All engines must be enabled together for vGPU, 222 * since we don't know which engine the ppgtt will 223 * bind to when shadowing. 224 */ 225 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", 226 ips); 227 return -EINVAL; 228 } 229 } 230 231 write_vreg(vgpu, offset, p_data, bytes); 232 return 0; 233 } 234 235 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 236 void *p_data, unsigned int bytes) 237 { 238 int ret; 239 240 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 241 p_data, bytes); 242 if (ret) 243 return ret; 244 read_vreg(vgpu, off, p_data, bytes); 245 return 0; 246 } 247 248 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 249 void *p_data, unsigned int bytes) 250 { 251 struct intel_gvt *gvt = vgpu->gvt; 252 unsigned int fence_num = offset_to_fence_num(off); 253 int ret; 254 255 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 256 if (ret) 257 return ret; 258 write_vreg(vgpu, off, p_data, bytes); 259 260 mmio_hw_access_pre(gvt->gt); 261 intel_vgpu_write_fence(vgpu, fence_num, 262 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 263 mmio_hw_access_post(gvt->gt); 264 return 0; 265 } 266 267 #define CALC_MODE_MASK_REG(old, new) \ 268 (((new) & GENMASK(31, 16)) \ 269 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 270 | ((new) & ((new) >> 16)))) 271 272 static int mul_force_wake_write(struct intel_vgpu *vgpu, 273 unsigned int offset, void *p_data, unsigned int bytes) 274 { 275 u32 old, new; 276 u32 ack_reg_offset; 277 278 old = vgpu_vreg(vgpu, offset); 279 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 280 281 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) { 282 switch (offset) { 283 case FORCEWAKE_RENDER_GEN9_REG: 284 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 285 break; 286 case FORCEWAKE_GT_GEN9_REG: 287 ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG; 288 break; 289 case FORCEWAKE_MEDIA_GEN9_REG: 290 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 291 break; 292 default: 293 /*should not hit here*/ 294 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 295 return -EINVAL; 296 } 297 } else { 298 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 299 } 300 301 vgpu_vreg(vgpu, offset) = new; 302 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 303 return 0; 304 } 305 306 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 307 void *p_data, unsigned int bytes) 308 { 309 intel_engine_mask_t engine_mask = 0; 310 u32 data; 311 312 write_vreg(vgpu, offset, p_data, bytes); 313 data = vgpu_vreg(vgpu, offset); 314 315 if (data & GEN6_GRDOM_FULL) { 316 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 317 engine_mask = ALL_ENGINES; 318 } else { 319 if (data & GEN6_GRDOM_RENDER) { 320 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 321 engine_mask |= BIT(RCS0); 322 } 323 if (data & GEN6_GRDOM_MEDIA) { 324 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 325 engine_mask |= BIT(VCS0); 326 } 327 if (data & GEN6_GRDOM_BLT) { 328 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 329 engine_mask |= BIT(BCS0); 330 } 331 if (data & GEN6_GRDOM_VECS) { 332 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 333 engine_mask |= BIT(VECS0); 334 } 335 if (data & GEN8_GRDOM_MEDIA2) { 336 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 337 engine_mask |= BIT(VCS1); 338 } 339 if (data & GEN9_GRDOM_GUC) { 340 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); 341 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; 342 } 343 engine_mask &= vgpu->gvt->gt->info.engine_mask; 344 } 345 346 /* vgpu_lock already hold by emulate mmio r/w */ 347 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 348 349 /* sw will wait for the device to ack the reset request */ 350 vgpu_vreg(vgpu, offset) = 0; 351 352 return 0; 353 } 354 355 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 356 void *p_data, unsigned int bytes) 357 { 358 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 359 } 360 361 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 362 void *p_data, unsigned int bytes) 363 { 364 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 365 } 366 367 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 368 unsigned int offset, void *p_data, unsigned int bytes) 369 { 370 write_vreg(vgpu, offset, p_data, bytes); 371 372 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 373 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 374 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 375 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 376 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 377 378 } else 379 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 380 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 381 | PP_CYCLE_DELAY_ACTIVE); 382 return 0; 383 } 384 385 static int transconf_mmio_write(struct intel_vgpu *vgpu, 386 unsigned int offset, void *p_data, unsigned int bytes) 387 { 388 write_vreg(vgpu, offset, p_data, bytes); 389 390 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 391 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 392 else 393 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 394 return 0; 395 } 396 397 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 398 void *p_data, unsigned int bytes) 399 { 400 write_vreg(vgpu, offset, p_data, bytes); 401 402 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 403 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 404 else 405 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 406 407 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 408 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 409 else 410 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 411 412 return 0; 413 } 414 415 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 416 void *p_data, unsigned int bytes) 417 { 418 switch (offset) { 419 case 0xe651c: 420 case 0xe661c: 421 case 0xe671c: 422 case 0xe681c: 423 vgpu_vreg(vgpu, offset) = 1 << 17; 424 break; 425 case 0xe6c04: 426 vgpu_vreg(vgpu, offset) = 0x3; 427 break; 428 case 0xe6e1c: 429 vgpu_vreg(vgpu, offset) = 0x2f << 16; 430 break; 431 default: 432 return -EINVAL; 433 } 434 435 read_vreg(vgpu, offset, p_data, bytes); 436 return 0; 437 } 438 439 /* 440 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to 441 * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on 442 * setup_virtual_dp_monitor(). 443 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled 444 * DPLL. Later guest driver may setup a different DPLLx when setting mode. 445 * So the correct sequence to find DP stream clock is: 446 * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x. 447 * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate. 448 * Then Refresh rate then can be calculated based on follow equations: 449 * Pixel clock = h_total * v_total * refresh_rate 450 * stream clock = Pixel clock 451 * ls_clk = DP bitrate 452 * Link M/N = strm_clk / ls_clk 453 */ 454 455 static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 456 { 457 u32 dp_br = 0; 458 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); 459 460 switch (ddi_pll_sel) { 461 case PORT_CLK_SEL_LCPLL_2700: 462 dp_br = 270000 * 2; 463 break; 464 case PORT_CLK_SEL_LCPLL_1350: 465 dp_br = 135000 * 2; 466 break; 467 case PORT_CLK_SEL_LCPLL_810: 468 dp_br = 81000 * 2; 469 break; 470 case PORT_CLK_SEL_SPLL: 471 { 472 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { 473 case SPLL_FREQ_810MHz: 474 dp_br = 81000 * 2; 475 break; 476 case SPLL_FREQ_1350MHz: 477 dp_br = 135000 * 2; 478 break; 479 case SPLL_FREQ_2700MHz: 480 dp_br = 270000 * 2; 481 break; 482 default: 483 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n", 484 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); 485 break; 486 } 487 break; 488 } 489 case PORT_CLK_SEL_WRPLL1: 490 case PORT_CLK_SEL_WRPLL2: 491 { 492 u32 wrpll_ctl; 493 int refclk, n, p, r; 494 495 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1) 496 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); 497 else 498 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2)); 499 500 switch (wrpll_ctl & WRPLL_REF_MASK) { 501 case WRPLL_REF_PCH_SSC: 502 refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc; 503 break; 504 case WRPLL_REF_LCPLL: 505 refclk = 2700000; 506 break; 507 default: 508 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n", 509 vgpu->id, port_name(port), wrpll_ctl); 510 goto out; 511 } 512 513 r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK; 514 p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 515 n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 516 517 dp_br = (refclk * n / 10) / (p * r) * 2; 518 break; 519 } 520 default: 521 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", 522 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port))); 523 break; 524 } 525 526 out: 527 return dp_br; 528 } 529 530 static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 531 { 532 u32 dp_br = 0; 533 int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc; 534 enum dpio_phy phy = DPIO_PHY0; 535 enum dpio_channel ch = DPIO_CH0; 536 struct dpll clock = {0}; 537 u32 temp; 538 539 /* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */ 540 switch (port) { 541 case PORT_A: 542 phy = DPIO_PHY1; 543 ch = DPIO_CH0; 544 break; 545 case PORT_B: 546 phy = DPIO_PHY0; 547 ch = DPIO_CH0; 548 break; 549 case PORT_C: 550 phy = DPIO_PHY0; 551 ch = DPIO_CH1; 552 break; 553 default: 554 gvt_dbg_dpy("vgpu-%d no PHY for PORT_%c\n", vgpu->id, port_name(port)); 555 goto out; 556 } 557 558 temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)); 559 if (!(temp & PORT_PLL_ENABLE) || !(temp & PORT_PLL_LOCK)) { 560 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n", 561 vgpu->id, port_name(port), temp); 562 goto out; 563 } 564 565 clock.m1 = 2; 566 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, 567 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22; 568 if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE) 569 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, 570 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2))); 571 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, 572 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1))); 573 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, 574 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); 575 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, 576 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); 577 clock.m = clock.m1 * clock.m2; 578 clock.p = clock.p1 * clock.p2 * 5; 579 580 if (clock.n == 0 || clock.p == 0) { 581 gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port)); 582 goto out; 583 } 584 585 clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22); 586 clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p); 587 588 dp_br = clock.dot; 589 590 out: 591 return dp_br; 592 } 593 594 static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 595 { 596 u32 dp_br = 0; 597 enum intel_dpll_id dpll_id = DPLL_ID_SKL_DPLL0; 598 599 /* Find the enabled DPLL for the DDI/PORT */ 600 if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) && 601 (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) { 602 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) & 603 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 604 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 605 } else { 606 gvt_dbg_dpy("vgpu-%d DPLL for PORT_%c isn't turned on\n", 607 vgpu->id, port_name(port)); 608 return dp_br; 609 } 610 611 /* Find PLL output frequency from correct DPLL, and get bir rate */ 612 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) & 613 DPLL_CTRL1_LINK_RATE_MASK(dpll_id)) >> 614 DPLL_CTRL1_LINK_RATE_SHIFT(dpll_id)) { 615 case DPLL_CTRL1_LINK_RATE_810: 616 dp_br = 81000 * 2; 617 break; 618 case DPLL_CTRL1_LINK_RATE_1080: 619 dp_br = 108000 * 2; 620 break; 621 case DPLL_CTRL1_LINK_RATE_1350: 622 dp_br = 135000 * 2; 623 break; 624 case DPLL_CTRL1_LINK_RATE_1620: 625 dp_br = 162000 * 2; 626 break; 627 case DPLL_CTRL1_LINK_RATE_2160: 628 dp_br = 216000 * 2; 629 break; 630 case DPLL_CTRL1_LINK_RATE_2700: 631 dp_br = 270000 * 2; 632 break; 633 default: 634 dp_br = 0; 635 gvt_dbg_dpy("vgpu-%d PORT_%c fail to get DPLL-%d freq\n", 636 vgpu->id, port_name(port), dpll_id); 637 } 638 639 return dp_br; 640 } 641 642 static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) 643 { 644 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 645 enum port port; 646 u32 dp_br, link_m, link_n, htotal, vtotal; 647 648 /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */ 649 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) & 650 TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 651 if (port != PORT_B && port != PORT_D) { 652 gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port)); 653 return; 654 } 655 656 /* Calculate DP bitrate from PLL */ 657 if (IS_BROADWELL(dev_priv)) 658 dp_br = bdw_vgpu_get_dp_bitrate(vgpu, port); 659 else if (IS_BROXTON(dev_priv)) 660 dp_br = bxt_vgpu_get_dp_bitrate(vgpu, port); 661 else 662 dp_br = skl_vgpu_get_dp_bitrate(vgpu, port); 663 664 /* Get DP link symbol clock M/N */ 665 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)); 666 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)); 667 668 /* Get H/V total from transcoder timing */ 669 htotal = (vgpu_vreg_t(vgpu, HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); 670 vtotal = (vgpu_vreg_t(vgpu, VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); 671 672 if (dp_br && link_n && htotal && vtotal) { 673 u64 pixel_clk = 0; 674 u32 new_rate = 0; 675 u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k); 676 677 /* Calcuate pixel clock by (ls_clk * M / N) */ 678 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); 679 pixel_clk *= MSEC_PER_SEC; 680 681 /* Calcuate refresh rate by (pixel_clk / (h_total * v_total)) */ 682 new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1)); 683 684 if (*old_rate != new_rate) 685 *old_rate = new_rate; 686 687 gvt_dbg_dpy("vgpu-%d PIPE_%c refresh rate updated to %d\n", 688 vgpu->id, pipe_name(PIPE_A), new_rate); 689 } 690 } 691 692 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 693 void *p_data, unsigned int bytes) 694 { 695 u32 data; 696 697 write_vreg(vgpu, offset, p_data, bytes); 698 data = vgpu_vreg(vgpu, offset); 699 700 if (data & PIPECONF_ENABLE) { 701 vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE; 702 vgpu_update_refresh_rate(vgpu); 703 vgpu_update_vblank_emulation(vgpu, true); 704 } else { 705 vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE; 706 vgpu_update_vblank_emulation(vgpu, false); 707 } 708 return 0; 709 } 710 711 /* sorted in ascending order */ 712 static i915_reg_t force_nonpriv_white_list[] = { 713 _MMIO(0xd80), 714 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 715 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 716 CL_PRIMITIVES_COUNT, //_MMIO(0x2340) 717 PS_INVOCATION_COUNT, //_MMIO(0x2348) 718 PS_DEPTH_COUNT, //_MMIO(0x2350) 719 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 720 _MMIO(0x2690), 721 _MMIO(0x2694), 722 _MMIO(0x2698), 723 _MMIO(0x2754), 724 _MMIO(0x28a0), 725 _MMIO(0x4de0), 726 _MMIO(0x4de4), 727 _MMIO(0x4dfc), 728 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 729 _MMIO(0x7014), 730 HDC_CHICKEN0,//_MMIO(0x7300) 731 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 732 _MMIO(0x7700), 733 _MMIO(0x7704), 734 _MMIO(0x7708), 735 _MMIO(0x770c), 736 _MMIO(0x83a8), 737 _MMIO(0xb110), 738 _MMIO(0xb118), 739 _MMIO(0xe100), 740 _MMIO(0xe18c), 741 _MMIO(0xe48c), 742 _MMIO(0xe5f4), 743 _MMIO(0x64844), 744 }; 745 746 /* a simple bsearch */ 747 static inline bool in_whitelist(u32 reg) 748 { 749 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 750 i915_reg_t *array = force_nonpriv_white_list; 751 752 while (left < right) { 753 int mid = (left + right)/2; 754 755 if (reg > array[mid].reg) 756 left = mid + 1; 757 else if (reg < array[mid].reg) 758 right = mid; 759 else 760 return true; 761 } 762 return false; 763 } 764 765 static int force_nonpriv_write(struct intel_vgpu *vgpu, 766 unsigned int offset, void *p_data, unsigned int bytes) 767 { 768 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2); 769 const struct intel_engine_cs *engine = 770 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 771 772 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) { 773 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 774 vgpu->id, offset, bytes); 775 return -EINVAL; 776 } 777 778 if (!in_whitelist(reg_nonpriv) && 779 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) { 780 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 781 vgpu->id, reg_nonpriv, offset); 782 } else 783 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 784 785 return 0; 786 } 787 788 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 789 void *p_data, unsigned int bytes) 790 { 791 write_vreg(vgpu, offset, p_data, bytes); 792 793 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 794 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 795 } else { 796 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 797 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 798 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 799 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 800 } 801 return 0; 802 } 803 804 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 805 unsigned int offset, void *p_data, unsigned int bytes) 806 { 807 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 808 return 0; 809 } 810 811 #define FDI_LINK_TRAIN_PATTERN1 0 812 #define FDI_LINK_TRAIN_PATTERN2 1 813 814 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 815 { 816 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 817 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 818 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 819 820 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 821 (rx_ctl & FDI_RX_ENABLE) && 822 (rx_ctl & FDI_AUTO_TRAINING) && 823 (tx_ctl & DP_TP_CTL_ENABLE) && 824 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 825 return 1; 826 else 827 return 0; 828 } 829 830 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 831 enum pipe pipe, unsigned int train_pattern) 832 { 833 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 834 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 835 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 836 unsigned int fdi_iir_check_bits; 837 838 fdi_rx_imr = FDI_RX_IMR(pipe); 839 fdi_tx_ctl = FDI_TX_CTL(pipe); 840 fdi_rx_ctl = FDI_RX_CTL(pipe); 841 842 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 843 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 844 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 845 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 846 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 847 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 848 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 849 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 850 } else { 851 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 852 return -EINVAL; 853 } 854 855 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 856 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 857 858 /* If imr bit has been masked */ 859 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 860 return 0; 861 862 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 863 == fdi_tx_check_bits) 864 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 865 == fdi_rx_check_bits)) 866 return 1; 867 else 868 return 0; 869 } 870 871 #define INVALID_INDEX (~0U) 872 873 static unsigned int calc_index(unsigned int offset, unsigned int start, 874 unsigned int next, unsigned int end, i915_reg_t i915_end) 875 { 876 unsigned int range = next - start; 877 878 if (!end) 879 end = i915_mmio_reg_offset(i915_end); 880 if (offset < start || offset > end) 881 return INVALID_INDEX; 882 offset -= start; 883 return offset / range; 884 } 885 886 #define FDI_RX_CTL_TO_PIPE(offset) \ 887 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 888 889 #define FDI_TX_CTL_TO_PIPE(offset) \ 890 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 891 892 #define FDI_RX_IMR_TO_PIPE(offset) \ 893 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 894 895 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 896 unsigned int offset, void *p_data, unsigned int bytes) 897 { 898 i915_reg_t fdi_rx_iir; 899 unsigned int index; 900 int ret; 901 902 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 903 index = FDI_RX_CTL_TO_PIPE(offset); 904 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 905 index = FDI_TX_CTL_TO_PIPE(offset); 906 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 907 index = FDI_RX_IMR_TO_PIPE(offset); 908 else { 909 gvt_vgpu_err("Unsupported registers %x\n", offset); 910 return -EINVAL; 911 } 912 913 write_vreg(vgpu, offset, p_data, bytes); 914 915 fdi_rx_iir = FDI_RX_IIR(index); 916 917 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 918 if (ret < 0) 919 return ret; 920 if (ret) 921 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 922 923 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 924 if (ret < 0) 925 return ret; 926 if (ret) 927 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 928 929 if (offset == _FDI_RXA_CTL) 930 if (fdi_auto_training_started(vgpu)) 931 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 932 DP_TP_STATUS_AUTOTRAIN_DONE; 933 return 0; 934 } 935 936 #define DP_TP_CTL_TO_PORT(offset) \ 937 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 938 939 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 940 void *p_data, unsigned int bytes) 941 { 942 i915_reg_t status_reg; 943 unsigned int index; 944 u32 data; 945 946 write_vreg(vgpu, offset, p_data, bytes); 947 948 index = DP_TP_CTL_TO_PORT(offset); 949 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 950 if (data == 0x2) { 951 status_reg = DP_TP_STATUS(index); 952 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 953 } 954 return 0; 955 } 956 957 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 958 unsigned int offset, void *p_data, unsigned int bytes) 959 { 960 u32 reg_val; 961 u32 sticky_mask; 962 963 reg_val = *((u32 *)p_data); 964 sticky_mask = GENMASK(27, 26) | (1 << 24); 965 966 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 967 (vgpu_vreg(vgpu, offset) & sticky_mask); 968 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 969 return 0; 970 } 971 972 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 973 unsigned int offset, void *p_data, unsigned int bytes) 974 { 975 u32 data; 976 977 write_vreg(vgpu, offset, p_data, bytes); 978 data = vgpu_vreg(vgpu, offset); 979 980 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 981 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 982 return 0; 983 } 984 985 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 986 unsigned int offset, void *p_data, unsigned int bytes) 987 { 988 u32 data; 989 990 write_vreg(vgpu, offset, p_data, bytes); 991 data = vgpu_vreg(vgpu, offset); 992 993 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 994 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 995 else 996 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 997 return 0; 998 } 999 1000 #define DSPSURF_TO_PIPE(offset) \ 1001 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 1002 1003 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1004 void *p_data, unsigned int bytes) 1005 { 1006 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1007 u32 pipe = DSPSURF_TO_PIPE(offset); 1008 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); 1009 1010 write_vreg(vgpu, offset, p_data, bytes); 1011 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1012 1013 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 1014 1015 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) 1016 intel_vgpu_trigger_virtual_event(vgpu, event); 1017 else 1018 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1019 1020 return 0; 1021 } 1022 1023 #define SPRSURF_TO_PIPE(offset) \ 1024 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 1025 1026 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1027 void *p_data, unsigned int bytes) 1028 { 1029 u32 pipe = SPRSURF_TO_PIPE(offset); 1030 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0); 1031 1032 write_vreg(vgpu, offset, p_data, bytes); 1033 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1034 1035 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) 1036 intel_vgpu_trigger_virtual_event(vgpu, event); 1037 else 1038 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1039 1040 return 0; 1041 } 1042 1043 static int reg50080_mmio_write(struct intel_vgpu *vgpu, 1044 unsigned int offset, void *p_data, 1045 unsigned int bytes) 1046 { 1047 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1048 enum pipe pipe = REG_50080_TO_PIPE(offset); 1049 enum plane_id plane = REG_50080_TO_PLANE(offset); 1050 int event = SKL_FLIP_EVENT(pipe, plane); 1051 1052 write_vreg(vgpu, offset, p_data, bytes); 1053 if (plane == PLANE_PRIMARY) { 1054 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1055 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 1056 } else { 1057 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1058 } 1059 1060 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) 1061 intel_vgpu_trigger_virtual_event(vgpu, event); 1062 else 1063 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1064 1065 return 0; 1066 } 1067 1068 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 1069 unsigned int reg) 1070 { 1071 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1072 enum intel_gvt_event_type event; 1073 1074 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) 1075 event = AUX_CHANNEL_A; 1076 else if (reg == _PCH_DPB_AUX_CH_CTL || 1077 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) 1078 event = AUX_CHANNEL_B; 1079 else if (reg == _PCH_DPC_AUX_CH_CTL || 1080 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) 1081 event = AUX_CHANNEL_C; 1082 else if (reg == _PCH_DPD_AUX_CH_CTL || 1083 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) 1084 event = AUX_CHANNEL_D; 1085 else { 1086 drm_WARN_ON(&dev_priv->drm, true); 1087 return -EINVAL; 1088 } 1089 1090 intel_vgpu_trigger_virtual_event(vgpu, event); 1091 return 0; 1092 } 1093 1094 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 1095 unsigned int reg, int len, bool data_valid) 1096 { 1097 /* mark transaction done */ 1098 value |= DP_AUX_CH_CTL_DONE; 1099 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 1100 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 1101 1102 if (data_valid) 1103 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 1104 else 1105 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 1106 1107 /* message size */ 1108 value &= ~(0xf << 20); 1109 value |= (len << 20); 1110 vgpu_vreg(vgpu, reg) = value; 1111 1112 if (value & DP_AUX_CH_CTL_INTERRUPT) 1113 return trigger_aux_channel_interrupt(vgpu, reg); 1114 return 0; 1115 } 1116 1117 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 1118 u8 t) 1119 { 1120 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 1121 /* training pattern 1 for CR */ 1122 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 1123 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 1124 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 1125 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 1126 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 1127 DPCD_TRAINING_PATTERN_2) { 1128 /* training pattern 2 for EQ */ 1129 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 1130 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 1131 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 1132 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 1133 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 1134 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 1135 /* set INTERLANE_ALIGN_DONE */ 1136 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 1137 DPCD_INTERLANE_ALIGN_DONE; 1138 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 1139 DPCD_LINK_TRAINING_DISABLED) { 1140 /* finish link training */ 1141 /* set sink status as synchronized */ 1142 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 1143 } 1144 } 1145 1146 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 1147 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 1148 1149 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 1150 1151 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 1152 1153 #define dpy_is_valid_port(port) \ 1154 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 1155 1156 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 1157 unsigned int offset, void *p_data, unsigned int bytes) 1158 { 1159 struct intel_vgpu_display *display = &vgpu->display; 1160 int msg, addr, ctrl, op, len; 1161 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 1162 struct intel_vgpu_dpcd_data *dpcd = NULL; 1163 struct intel_vgpu_port *port = NULL; 1164 u32 data; 1165 1166 if (!dpy_is_valid_port(port_index)) { 1167 gvt_vgpu_err("Unsupported DP port access!\n"); 1168 return 0; 1169 } 1170 1171 write_vreg(vgpu, offset, p_data, bytes); 1172 data = vgpu_vreg(vgpu, offset); 1173 1174 if ((GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) 1175 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 1176 /* SKL DPB/C/D aux ctl register changed */ 1177 return 0; 1178 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) && 1179 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 1180 /* write to the data registers */ 1181 return 0; 1182 } 1183 1184 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 1185 /* just want to clear the sticky bits */ 1186 vgpu_vreg(vgpu, offset) = 0; 1187 return 0; 1188 } 1189 1190 port = &display->ports[port_index]; 1191 dpcd = port->dpcd; 1192 1193 /* read out message from DATA1 register */ 1194 msg = vgpu_vreg(vgpu, offset + 4); 1195 addr = (msg >> 8) & 0xffff; 1196 ctrl = (msg >> 24) & 0xff; 1197 len = msg & 0xff; 1198 op = ctrl >> 4; 1199 1200 if (op == GVT_AUX_NATIVE_WRITE) { 1201 int t; 1202 u8 buf[16]; 1203 1204 if ((addr + len + 1) >= DPCD_SIZE) { 1205 /* 1206 * Write request exceeds what we supported, 1207 * DCPD spec: When a Source Device is writing a DPCD 1208 * address not supported by the Sink Device, the Sink 1209 * Device shall reply with AUX NACK and “M” equal to 1210 * zero. 1211 */ 1212 1213 /* NAK the write */ 1214 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 1215 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 1216 return 0; 1217 } 1218 1219 /* 1220 * Write request format: Headr (command + address + size) occupies 1221 * 4 bytes, followed by (len + 1) bytes of data. See details at 1222 * intel_dp_aux_transfer(). 1223 */ 1224 if ((len + 1 + 4) > AUX_BURST_SIZE) { 1225 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1226 return -EINVAL; 1227 } 1228 1229 /* unpack data from vreg to buf */ 1230 for (t = 0; t < 4; t++) { 1231 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 1232 1233 buf[t * 4] = (r >> 24) & 0xff; 1234 buf[t * 4 + 1] = (r >> 16) & 0xff; 1235 buf[t * 4 + 2] = (r >> 8) & 0xff; 1236 buf[t * 4 + 3] = r & 0xff; 1237 } 1238 1239 /* write to virtual DPCD */ 1240 if (dpcd && dpcd->data_valid) { 1241 for (t = 0; t <= len; t++) { 1242 int p = addr + t; 1243 1244 dpcd->data[p] = buf[t]; 1245 /* check for link training */ 1246 if (p == DPCD_TRAINING_PATTERN_SET) 1247 dp_aux_ch_ctl_link_training(dpcd, 1248 buf[t]); 1249 } 1250 } 1251 1252 /* ACK the write */ 1253 vgpu_vreg(vgpu, offset + 4) = 0; 1254 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 1255 dpcd && dpcd->data_valid); 1256 return 0; 1257 } 1258 1259 if (op == GVT_AUX_NATIVE_READ) { 1260 int idx, i, ret = 0; 1261 1262 if ((addr + len + 1) >= DPCD_SIZE) { 1263 /* 1264 * read request exceeds what we supported 1265 * DPCD spec: A Sink Device receiving a Native AUX CH 1266 * read request for an unsupported DPCD address must 1267 * reply with an AUX ACK and read data set equal to 1268 * zero instead of replying with AUX NACK. 1269 */ 1270 1271 /* ACK the READ*/ 1272 vgpu_vreg(vgpu, offset + 4) = 0; 1273 vgpu_vreg(vgpu, offset + 8) = 0; 1274 vgpu_vreg(vgpu, offset + 12) = 0; 1275 vgpu_vreg(vgpu, offset + 16) = 0; 1276 vgpu_vreg(vgpu, offset + 20) = 0; 1277 1278 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1279 true); 1280 return 0; 1281 } 1282 1283 for (idx = 1; idx <= 5; idx++) { 1284 /* clear the data registers */ 1285 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 1286 } 1287 1288 /* 1289 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1290 */ 1291 if ((len + 2) > AUX_BURST_SIZE) { 1292 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1293 return -EINVAL; 1294 } 1295 1296 /* read from virtual DPCD to vreg */ 1297 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1298 if (dpcd && dpcd->data_valid) { 1299 for (i = 1; i <= (len + 1); i++) { 1300 int t; 1301 1302 t = dpcd->data[addr + i - 1]; 1303 t <<= (24 - 8 * (i % 4)); 1304 ret |= t; 1305 1306 if ((i % 4 == 3) || (i == (len + 1))) { 1307 vgpu_vreg(vgpu, offset + 1308 (i / 4 + 1) * 4) = ret; 1309 ret = 0; 1310 } 1311 } 1312 } 1313 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1314 dpcd && dpcd->data_valid); 1315 return 0; 1316 } 1317 1318 /* i2c transaction starts */ 1319 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1320 1321 if (data & DP_AUX_CH_CTL_INTERRUPT) 1322 trigger_aux_channel_interrupt(vgpu, offset); 1323 return 0; 1324 } 1325 1326 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1327 void *p_data, unsigned int bytes) 1328 { 1329 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1330 write_vreg(vgpu, offset, p_data, bytes); 1331 return 0; 1332 } 1333 1334 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1335 void *p_data, unsigned int bytes) 1336 { 1337 bool vga_disable; 1338 1339 write_vreg(vgpu, offset, p_data, bytes); 1340 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1341 1342 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1343 vga_disable ? "Disable" : "Enable"); 1344 return 0; 1345 } 1346 1347 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1348 unsigned int sbi_offset) 1349 { 1350 struct intel_vgpu_display *display = &vgpu->display; 1351 int num = display->sbi.number; 1352 int i; 1353 1354 for (i = 0; i < num; ++i) 1355 if (display->sbi.registers[i].offset == sbi_offset) 1356 break; 1357 1358 if (i == num) 1359 return 0; 1360 1361 return display->sbi.registers[i].value; 1362 } 1363 1364 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1365 unsigned int offset, u32 value) 1366 { 1367 struct intel_vgpu_display *display = &vgpu->display; 1368 int num = display->sbi.number; 1369 int i; 1370 1371 for (i = 0; i < num; ++i) { 1372 if (display->sbi.registers[i].offset == offset) 1373 break; 1374 } 1375 1376 if (i == num) { 1377 if (num == SBI_REG_MAX) { 1378 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1379 return; 1380 } 1381 display->sbi.number++; 1382 } 1383 1384 display->sbi.registers[i].offset = offset; 1385 display->sbi.registers[i].value = value; 1386 } 1387 1388 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1389 void *p_data, unsigned int bytes) 1390 { 1391 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1392 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1393 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1394 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1395 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1396 sbi_offset); 1397 } 1398 read_vreg(vgpu, offset, p_data, bytes); 1399 return 0; 1400 } 1401 1402 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1403 void *p_data, unsigned int bytes) 1404 { 1405 u32 data; 1406 1407 write_vreg(vgpu, offset, p_data, bytes); 1408 data = vgpu_vreg(vgpu, offset); 1409 1410 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1411 data |= SBI_READY; 1412 1413 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1414 data |= SBI_RESPONSE_SUCCESS; 1415 1416 vgpu_vreg(vgpu, offset) = data; 1417 1418 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1419 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1420 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1421 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1422 1423 write_virtual_sbi_register(vgpu, sbi_offset, 1424 vgpu_vreg_t(vgpu, SBI_DATA)); 1425 } 1426 return 0; 1427 } 1428 1429 #define _vgtif_reg(x) \ 1430 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1431 1432 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1433 void *p_data, unsigned int bytes) 1434 { 1435 bool invalid_read = false; 1436 1437 read_vreg(vgpu, offset, p_data, bytes); 1438 1439 switch (offset) { 1440 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1441 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1442 invalid_read = true; 1443 break; 1444 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1445 _vgtif_reg(avail_rs.fence_num): 1446 if (offset + bytes > 1447 _vgtif_reg(avail_rs.fence_num) + 4) 1448 invalid_read = true; 1449 break; 1450 case 0x78010: /* vgt_caps */ 1451 case 0x7881c: 1452 break; 1453 default: 1454 invalid_read = true; 1455 break; 1456 } 1457 if (invalid_read) 1458 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1459 offset, bytes, *(u32 *)p_data); 1460 vgpu->pv_notified = true; 1461 return 0; 1462 } 1463 1464 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1465 { 1466 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1467 struct intel_vgpu_mm *mm; 1468 u64 *pdps; 1469 1470 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1471 1472 switch (notification) { 1473 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1474 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1475 fallthrough; 1476 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1477 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1478 return PTR_ERR_OR_ZERO(mm); 1479 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1480 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1481 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1482 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1483 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1484 case 1: /* Remove this in guest driver. */ 1485 break; 1486 default: 1487 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1488 } 1489 return 0; 1490 } 1491 1492 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1493 { 1494 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj; 1495 char *env[3] = {NULL, NULL, NULL}; 1496 char vmid_str[20]; 1497 char display_ready_str[20]; 1498 1499 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1500 env[0] = display_ready_str; 1501 1502 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1503 env[1] = vmid_str; 1504 1505 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1506 } 1507 1508 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1509 void *p_data, unsigned int bytes) 1510 { 1511 u32 data = *(u32 *)p_data; 1512 bool invalid_write = false; 1513 1514 switch (offset) { 1515 case _vgtif_reg(display_ready): 1516 send_display_ready_uevent(vgpu, data ? 1 : 0); 1517 break; 1518 case _vgtif_reg(g2v_notify): 1519 handle_g2v_notification(vgpu, data); 1520 break; 1521 /* add xhot and yhot to handled list to avoid error log */ 1522 case _vgtif_reg(cursor_x_hot): 1523 case _vgtif_reg(cursor_y_hot): 1524 case _vgtif_reg(pdp[0].lo): 1525 case _vgtif_reg(pdp[0].hi): 1526 case _vgtif_reg(pdp[1].lo): 1527 case _vgtif_reg(pdp[1].hi): 1528 case _vgtif_reg(pdp[2].lo): 1529 case _vgtif_reg(pdp[2].hi): 1530 case _vgtif_reg(pdp[3].lo): 1531 case _vgtif_reg(pdp[3].hi): 1532 case _vgtif_reg(execlist_context_descriptor_lo): 1533 case _vgtif_reg(execlist_context_descriptor_hi): 1534 break; 1535 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1536 invalid_write = true; 1537 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1538 break; 1539 default: 1540 invalid_write = true; 1541 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1542 offset, bytes, data); 1543 break; 1544 } 1545 1546 if (!invalid_write) 1547 write_vreg(vgpu, offset, p_data, bytes); 1548 1549 return 0; 1550 } 1551 1552 static int pf_write(struct intel_vgpu *vgpu, 1553 unsigned int offset, void *p_data, unsigned int bytes) 1554 { 1555 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1556 u32 val = *(u32 *)p_data; 1557 1558 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1559 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1560 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1561 drm_WARN_ONCE(&i915->drm, true, 1562 "VM(%d): guest is trying to scaling a plane\n", 1563 vgpu->id); 1564 return 0; 1565 } 1566 1567 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1568 } 1569 1570 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1571 unsigned int offset, void *p_data, unsigned int bytes) 1572 { 1573 write_vreg(vgpu, offset, p_data, bytes); 1574 1575 if (vgpu_vreg(vgpu, offset) & 1576 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL)) 1577 vgpu_vreg(vgpu, offset) |= 1578 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1579 else 1580 vgpu_vreg(vgpu, offset) &= 1581 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1582 return 0; 1583 } 1584 1585 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1586 unsigned int offset, void *p_data, unsigned int bytes) 1587 { 1588 write_vreg(vgpu, offset, p_data, bytes); 1589 1590 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1591 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1592 else 1593 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1594 1595 return 0; 1596 } 1597 1598 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1599 unsigned int offset, void *p_data, unsigned int bytes) 1600 { 1601 write_vreg(vgpu, offset, p_data, bytes); 1602 1603 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1604 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1605 return 0; 1606 } 1607 1608 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1609 void *p_data, unsigned int bytes) 1610 { 1611 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1612 u32 mode; 1613 1614 write_vreg(vgpu, offset, p_data, bytes); 1615 mode = vgpu_vreg(vgpu, offset); 1616 1617 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1618 drm_WARN_ONCE(&i915->drm, 1, 1619 "VM(%d): iGVT-g doesn't support GuC\n", 1620 vgpu->id); 1621 return 0; 1622 } 1623 1624 return 0; 1625 } 1626 1627 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1628 void *p_data, unsigned int bytes) 1629 { 1630 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1631 u32 trtte = *(u32 *)p_data; 1632 1633 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1634 drm_WARN(&i915->drm, 1, 1635 "VM(%d): Use physical address for TRTT!\n", 1636 vgpu->id); 1637 return -EINVAL; 1638 } 1639 write_vreg(vgpu, offset, p_data, bytes); 1640 1641 return 0; 1642 } 1643 1644 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1645 void *p_data, unsigned int bytes) 1646 { 1647 write_vreg(vgpu, offset, p_data, bytes); 1648 return 0; 1649 } 1650 1651 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1652 void *p_data, unsigned int bytes) 1653 { 1654 u32 v = 0; 1655 1656 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1657 v |= (1 << 0); 1658 1659 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1660 v |= (1 << 8); 1661 1662 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1663 v |= (1 << 16); 1664 1665 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1666 v |= (1 << 24); 1667 1668 vgpu_vreg(vgpu, offset) = v; 1669 1670 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1671 } 1672 1673 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1674 void *p_data, unsigned int bytes) 1675 { 1676 u32 value = *(u32 *)p_data; 1677 u32 cmd = value & 0xff; 1678 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1679 1680 switch (cmd) { 1681 case GEN9_PCODE_READ_MEM_LATENCY: 1682 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1683 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1684 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1685 IS_COMETLAKE(vgpu->gvt->gt->i915)) { 1686 /** 1687 * "Read memory latency" command on gen9. 1688 * Below memory latency values are read 1689 * from skylake platform. 1690 */ 1691 if (!*data0) 1692 *data0 = 0x1e1a1100; 1693 else 1694 *data0 = 0x61514b3d; 1695 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) { 1696 /** 1697 * "Read memory latency" command on gen9. 1698 * Below memory latency values are read 1699 * from Broxton MRB. 1700 */ 1701 if (!*data0) 1702 *data0 = 0x16080707; 1703 else 1704 *data0 = 0x16161616; 1705 } 1706 break; 1707 case SKL_PCODE_CDCLK_CONTROL: 1708 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1709 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1710 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1711 IS_COMETLAKE(vgpu->gvt->gt->i915)) 1712 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1713 break; 1714 case GEN6_PCODE_READ_RC6VIDS: 1715 *data0 |= 0x1; 1716 break; 1717 } 1718 1719 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1720 vgpu->id, value, *data0); 1721 /** 1722 * PCODE_READY clear means ready for pcode read/write, 1723 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1724 * always emulate as pcode read/write success and ready for access 1725 * anytime, since we don't touch real physical registers here. 1726 */ 1727 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1728 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1729 } 1730 1731 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1732 void *p_data, unsigned int bytes) 1733 { 1734 u32 value = *(u32 *)p_data; 1735 const struct intel_engine_cs *engine = 1736 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1737 1738 if (value != 0 && 1739 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1740 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1741 offset, value); 1742 return -EINVAL; 1743 } 1744 1745 /* 1746 * Need to emulate all the HWSP register write to ensure host can 1747 * update the VM CSB status correctly. Here listed registers can 1748 * support BDW, SKL or other platforms with same HWSP registers. 1749 */ 1750 if (unlikely(!engine)) { 1751 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1752 offset); 1753 return -EINVAL; 1754 } 1755 vgpu->hws_pga[engine->id] = value; 1756 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1757 vgpu->id, value, offset); 1758 1759 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1760 } 1761 1762 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1763 unsigned int offset, void *p_data, unsigned int bytes) 1764 { 1765 u32 v = *(u32 *)p_data; 1766 1767 if (IS_BROXTON(vgpu->gvt->gt->i915)) 1768 v &= (1 << 31) | (1 << 29); 1769 else 1770 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1771 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1772 v |= (v >> 1); 1773 1774 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1775 } 1776 1777 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1778 void *p_data, unsigned int bytes) 1779 { 1780 u32 v = *(u32 *)p_data; 1781 1782 /* other bits are MBZ. */ 1783 v &= (1 << 31) | (1 << 30); 1784 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1785 1786 vgpu_vreg(vgpu, offset) = v; 1787 1788 return 0; 1789 } 1790 1791 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1792 unsigned int offset, void *p_data, unsigned int bytes) 1793 { 1794 u32 v = *(u32 *)p_data; 1795 1796 if (v & BXT_DE_PLL_PLL_ENABLE) 1797 v |= BXT_DE_PLL_LOCK; 1798 1799 vgpu_vreg(vgpu, offset) = v; 1800 1801 return 0; 1802 } 1803 1804 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1805 unsigned int offset, void *p_data, unsigned int bytes) 1806 { 1807 u32 v = *(u32 *)p_data; 1808 1809 if (v & PORT_PLL_ENABLE) 1810 v |= PORT_PLL_LOCK; 1811 1812 vgpu_vreg(vgpu, offset) = v; 1813 1814 return 0; 1815 } 1816 1817 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1818 unsigned int offset, void *p_data, unsigned int bytes) 1819 { 1820 u32 v = *(u32 *)p_data; 1821 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1822 1823 switch (offset) { 1824 case _PHY_CTL_FAMILY_EDP: 1825 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1826 break; 1827 case _PHY_CTL_FAMILY_DDI: 1828 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1829 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1830 break; 1831 } 1832 1833 vgpu_vreg(vgpu, offset) = v; 1834 1835 return 0; 1836 } 1837 1838 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1839 unsigned int offset, void *p_data, unsigned int bytes) 1840 { 1841 u32 v = vgpu_vreg(vgpu, offset); 1842 1843 v &= ~UNIQUE_TRANGE_EN_METHOD; 1844 1845 vgpu_vreg(vgpu, offset) = v; 1846 1847 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1848 } 1849 1850 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1851 unsigned int offset, void *p_data, unsigned int bytes) 1852 { 1853 u32 v = *(u32 *)p_data; 1854 1855 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1856 vgpu_vreg(vgpu, offset - 0x600) = v; 1857 vgpu_vreg(vgpu, offset - 0x800) = v; 1858 } else { 1859 vgpu_vreg(vgpu, offset - 0x400) = v; 1860 vgpu_vreg(vgpu, offset - 0x600) = v; 1861 } 1862 1863 vgpu_vreg(vgpu, offset) = v; 1864 1865 return 0; 1866 } 1867 1868 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1869 unsigned int offset, void *p_data, unsigned int bytes) 1870 { 1871 u32 v = *(u32 *)p_data; 1872 1873 if (v & BIT(0)) { 1874 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1875 ~PHY_RESERVED; 1876 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1877 PHY_POWER_GOOD; 1878 } 1879 1880 if (v & BIT(1)) { 1881 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1882 ~PHY_RESERVED; 1883 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1884 PHY_POWER_GOOD; 1885 } 1886 1887 1888 vgpu_vreg(vgpu, offset) = v; 1889 1890 return 0; 1891 } 1892 1893 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1894 unsigned int offset, void *p_data, unsigned int bytes) 1895 { 1896 vgpu_vreg(vgpu, offset) = 0; 1897 return 0; 1898 } 1899 1900 /* 1901 * FixMe: 1902 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did: 1903 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.) 1904 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing 1905 * these MI_BATCH_BUFFER. 1906 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT 1907 * PML4 PTE: PAT(0) PCD(1) PWT(1). 1908 * The performance is still expected to be low, will need further improvement. 1909 */ 1910 static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset, 1911 void *p_data, unsigned int bytes) 1912 { 1913 u64 pat = 1914 GEN8_PPAT(0, CHV_PPAT_SNOOP) | 1915 GEN8_PPAT(1, 0) | 1916 GEN8_PPAT(2, 0) | 1917 GEN8_PPAT(3, CHV_PPAT_SNOOP) | 1918 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 1919 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 1920 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 1921 GEN8_PPAT(7, CHV_PPAT_SNOOP); 1922 1923 vgpu_vreg(vgpu, offset) = lower_32_bits(pat); 1924 1925 return 0; 1926 } 1927 1928 static int guc_status_read(struct intel_vgpu *vgpu, 1929 unsigned int offset, void *p_data, 1930 unsigned int bytes) 1931 { 1932 /* keep MIA_IN_RESET before clearing */ 1933 read_vreg(vgpu, offset, p_data, bytes); 1934 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET; 1935 return 0; 1936 } 1937 1938 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1939 unsigned int offset, void *p_data, unsigned int bytes) 1940 { 1941 struct intel_gvt *gvt = vgpu->gvt; 1942 const struct intel_engine_cs *engine = 1943 intel_gvt_render_mmio_to_engine(gvt, offset); 1944 1945 /** 1946 * Read HW reg in following case 1947 * a. the offset isn't a ring mmio 1948 * b. the offset's ring is running on hw. 1949 * c. the offset is ring time stamp mmio 1950 */ 1951 1952 if (!engine || 1953 vgpu == gvt->scheduler.engine_owner[engine->id] || 1954 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) || 1955 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) { 1956 mmio_hw_access_pre(gvt->gt); 1957 vgpu_vreg(vgpu, offset) = 1958 intel_uncore_read(gvt->gt->uncore, _MMIO(offset)); 1959 mmio_hw_access_post(gvt->gt); 1960 } 1961 1962 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1963 } 1964 1965 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1966 void *p_data, unsigned int bytes) 1967 { 1968 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1969 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1970 struct intel_vgpu_execlist *execlist; 1971 u32 data = *(u32 *)p_data; 1972 int ret = 0; 1973 1974 if (drm_WARN_ON(&i915->drm, !engine)) 1975 return -EINVAL; 1976 1977 /* 1978 * Due to d3_entered is used to indicate skipping PPGTT invalidation on 1979 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after 1980 * vGPU reset if in resuming. 1981 * In S0ix exit, the device power state also transite from D3 to D0 as 1982 * S3 resume, but no vGPU reset (triggered by QEMU devic model). After 1983 * S0ix exit, all engines continue to work. However the d3_entered 1984 * remains set which will break next vGPU reset logic (miss the expected 1985 * PPGTT invalidation). 1986 * Engines can only work in D0. Thus the 1st elsp write gives GVT a 1987 * chance to clear d3_entered. 1988 */ 1989 if (vgpu->d3_entered) 1990 vgpu->d3_entered = false; 1991 1992 execlist = &vgpu->submission.execlist[engine->id]; 1993 1994 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 1995 if (execlist->elsp_dwords.index == 3) { 1996 ret = intel_vgpu_submit_execlist(vgpu, engine); 1997 if(ret) 1998 gvt_vgpu_err("fail submit workload on ring %s\n", 1999 engine->name); 2000 } 2001 2002 ++execlist->elsp_dwords.index; 2003 execlist->elsp_dwords.index &= 0x3; 2004 return ret; 2005 } 2006 2007 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2008 void *p_data, unsigned int bytes) 2009 { 2010 u32 data = *(u32 *)p_data; 2011 const struct intel_engine_cs *engine = 2012 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 2013 bool enable_execlist; 2014 int ret; 2015 2016 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); 2017 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2018 IS_COMETLAKE(vgpu->gvt->gt->i915)) 2019 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); 2020 write_vreg(vgpu, offset, p_data, bytes); 2021 2022 if (IS_MASKED_BITS_ENABLED(data, 1)) { 2023 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2024 return 0; 2025 } 2026 2027 if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2028 IS_COMETLAKE(vgpu->gvt->gt->i915)) && 2029 IS_MASKED_BITS_ENABLED(data, 2)) { 2030 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2031 return 0; 2032 } 2033 2034 /* when PPGTT mode enabled, we will check if guest has called 2035 * pvinfo, if not, we will treat this guest as non-gvtg-aware 2036 * guest, and stop emulating its cfg space, mmio, gtt, etc. 2037 */ 2038 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) || 2039 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) && 2040 !vgpu->pv_notified) { 2041 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2042 return 0; 2043 } 2044 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) || 2045 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) { 2046 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 2047 2048 gvt_dbg_core("EXECLIST %s on ring %s\n", 2049 (enable_execlist ? "enabling" : "disabling"), 2050 engine->name); 2051 2052 if (!enable_execlist) 2053 return 0; 2054 2055 ret = intel_vgpu_select_submission_ops(vgpu, 2056 engine->mask, 2057 INTEL_VGPU_EXECLIST_SUBMISSION); 2058 if (ret) 2059 return ret; 2060 2061 intel_vgpu_start_schedule(vgpu); 2062 } 2063 return 0; 2064 } 2065 2066 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 2067 unsigned int offset, void *p_data, unsigned int bytes) 2068 { 2069 unsigned int id = 0; 2070 2071 write_vreg(vgpu, offset, p_data, bytes); 2072 vgpu_vreg(vgpu, offset) = 0; 2073 2074 switch (offset) { 2075 case 0x4260: 2076 id = RCS0; 2077 break; 2078 case 0x4264: 2079 id = VCS0; 2080 break; 2081 case 0x4268: 2082 id = VCS1; 2083 break; 2084 case 0x426c: 2085 id = BCS0; 2086 break; 2087 case 0x4270: 2088 id = VECS0; 2089 break; 2090 default: 2091 return -EINVAL; 2092 } 2093 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 2094 2095 return 0; 2096 } 2097 2098 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 2099 unsigned int offset, void *p_data, unsigned int bytes) 2100 { 2101 u32 data; 2102 2103 write_vreg(vgpu, offset, p_data, bytes); 2104 data = vgpu_vreg(vgpu, offset); 2105 2106 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET)) 2107 data |= RESET_CTL_READY_TO_RESET; 2108 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 2109 data &= ~RESET_CTL_READY_TO_RESET; 2110 2111 vgpu_vreg(vgpu, offset) = data; 2112 return 0; 2113 } 2114 2115 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, 2116 unsigned int offset, void *p_data, 2117 unsigned int bytes) 2118 { 2119 u32 data = *(u32 *)p_data; 2120 2121 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); 2122 write_vreg(vgpu, offset, p_data, bytes); 2123 2124 if (IS_MASKED_BITS_ENABLED(data, 0x10) || 2125 IS_MASKED_BITS_ENABLED(data, 0x8)) 2126 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2127 2128 return 0; 2129 } 2130 2131 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 2132 ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 2133 s, f, am, rm, d, r, w); \ 2134 if (ret) \ 2135 return ret; \ 2136 } while (0) 2137 2138 #define MMIO_DH(reg, d, r, w) \ 2139 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 2140 2141 #define MMIO_DFH(reg, d, f, r, w) \ 2142 MMIO_F(reg, 4, f, 0, 0, d, r, w) 2143 2144 #define MMIO_GM(reg, d, r, w) \ 2145 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 2146 2147 #define MMIO_GM_RDR(reg, d, r, w) \ 2148 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 2149 2150 #define MMIO_RO(reg, d, f, rm, r, w) \ 2151 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 2152 2153 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 2154 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 2155 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 2156 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 2157 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 2158 if (HAS_ENGINE(gvt->gt, VCS1)) \ 2159 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 2160 } while (0) 2161 2162 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 2163 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 2164 2165 #define MMIO_RING_GM(prefix, d, r, w) \ 2166 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 2167 2168 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 2169 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 2170 2171 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 2172 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 2173 2174 static int init_generic_mmio_info(struct intel_gvt *gvt) 2175 { 2176 struct drm_i915_private *dev_priv = gvt->gt->i915; 2177 int ret; 2178 2179 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, 2180 intel_vgpu_reg_imr_handler); 2181 2182 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 2183 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 2184 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 2185 2186 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL); 2187 2188 2189 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, 2190 gamw_echo_dev_rw_ia_write); 2191 2192 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2193 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2194 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2195 2196 #define RING_REG(base) _MMIO((base) + 0x28) 2197 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2198 #undef RING_REG 2199 2200 #define RING_REG(base) _MMIO((base) + 0x134) 2201 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2202 #undef RING_REG 2203 2204 #define RING_REG(base) _MMIO((base) + 0x6c) 2205 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 2206 #undef RING_REG 2207 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 2208 2209 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 2210 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); 2211 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 2212 2213 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL); 2214 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL); 2215 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL); 2216 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL); 2217 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 2218 2219 /* RING MODE */ 2220 #define RING_REG(base) _MMIO((base) + 0x29c) 2221 MMIO_RING_DFH(RING_REG, D_ALL, 2222 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL, 2223 ring_mode_mmio_write); 2224 #undef RING_REG 2225 2226 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2227 NULL, NULL); 2228 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2229 NULL, NULL); 2230 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 2231 mmio_read_from_hw, NULL); 2232 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 2233 mmio_read_from_hw, NULL); 2234 2235 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2236 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2237 NULL, NULL); 2238 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2239 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2240 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2241 2242 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2243 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2244 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2245 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL, 2246 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2247 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2248 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 2249 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2250 NULL, NULL); 2251 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2252 NULL, NULL); 2253 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 2254 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 2255 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 2256 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 2257 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 2258 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 2259 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2260 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2261 MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2262 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2263 2264 /* display */ 2265 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 2266 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 2267 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 2268 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 2269 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2270 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, 2271 reg50080_mmio_write); 2272 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2273 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, 2274 reg50080_mmio_write); 2275 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2276 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, 2277 reg50080_mmio_write); 2278 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 2279 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, 2280 reg50080_mmio_write); 2281 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 2282 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, 2283 reg50080_mmio_write); 2284 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 2285 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, 2286 reg50080_mmio_write); 2287 2288 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2289 gmbus_mmio_write); 2290 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2291 2292 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2293 dp_aux_ch_ctl_mmio_write); 2294 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2295 dp_aux_ch_ctl_mmio_write); 2296 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2297 dp_aux_ch_ctl_mmio_write); 2298 2299 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2300 2301 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2302 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2303 2304 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2305 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2306 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2307 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2308 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2309 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2310 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2311 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2312 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2313 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2314 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2315 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2316 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2317 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2318 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2319 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2320 2321 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2322 PORTA_HOTPLUG_STATUS_MASK 2323 | PORTB_HOTPLUG_STATUS_MASK 2324 | PORTC_HOTPLUG_STATUS_MASK 2325 | PORTD_HOTPLUG_STATUS_MASK, 2326 NULL, NULL); 2327 2328 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2329 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2330 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2331 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2332 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2333 2334 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2335 dp_aux_ch_ctl_mmio_write); 2336 2337 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2338 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2339 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2340 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2341 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2342 2343 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2344 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2345 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2346 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2347 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2348 2349 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2350 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2351 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2352 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2353 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2354 2355 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2356 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2357 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2358 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2359 2360 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2361 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2362 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2363 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2364 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2365 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2366 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2367 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); 2368 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); 2369 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); 2370 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); 2371 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2372 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2373 2374 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2375 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2376 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2377 2378 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2379 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2380 2381 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2382 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2383 2384 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2385 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2386 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2387 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2388 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2389 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2390 2391 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2392 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2393 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2394 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2395 2396 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2397 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2398 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2399 2400 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2401 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2402 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2403 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2404 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2405 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2406 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2407 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2408 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2409 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2410 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2411 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2412 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2413 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2414 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2415 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2416 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2417 2418 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2419 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL); 2420 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2421 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2422 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2423 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2424 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2425 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2426 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2427 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2428 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2429 2430 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2431 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2432 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL); 2433 2434 return 0; 2435 } 2436 2437 static int init_bdw_mmio_info(struct intel_gvt *gvt) 2438 { 2439 int ret; 2440 2441 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2442 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2443 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2444 2445 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2446 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2447 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2448 2449 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2450 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2451 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2452 2453 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2454 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2455 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2456 2457 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2458 intel_vgpu_reg_imr_handler); 2459 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2460 intel_vgpu_reg_ier_handler); 2461 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2462 intel_vgpu_reg_iir_handler); 2463 2464 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2465 intel_vgpu_reg_imr_handler); 2466 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2467 intel_vgpu_reg_ier_handler); 2468 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2469 intel_vgpu_reg_iir_handler); 2470 2471 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2472 intel_vgpu_reg_imr_handler); 2473 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2474 intel_vgpu_reg_ier_handler); 2475 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2476 intel_vgpu_reg_iir_handler); 2477 2478 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2479 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2480 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2481 2482 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2483 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2484 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2485 2486 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2487 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2488 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2489 2490 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2491 intel_vgpu_reg_master_irq_handler); 2492 2493 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0, 2494 mmio_read_from_hw, NULL); 2495 2496 #define RING_REG(base) _MMIO((base) + 0xd0) 2497 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2498 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2499 ring_reset_ctl_write); 2500 #undef RING_REG 2501 2502 #define RING_REG(base) _MMIO((base) + 0x230) 2503 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2504 #undef RING_REG 2505 2506 #define RING_REG(base) _MMIO((base) + 0x234) 2507 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, 2508 NULL, NULL); 2509 #undef RING_REG 2510 2511 #define RING_REG(base) _MMIO((base) + 0x244) 2512 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2513 #undef RING_REG 2514 2515 #define RING_REG(base) _MMIO((base) + 0x370) 2516 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2517 #undef RING_REG 2518 2519 #define RING_REG(base) _MMIO((base) + 0x3a0) 2520 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2521 #undef RING_REG 2522 2523 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2524 2525 #define RING_REG(base) _MMIO((base) + 0x270) 2526 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2527 #undef RING_REG 2528 2529 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2530 2531 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2532 2533 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2534 NULL, NULL); 2535 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2536 NULL, NULL); 2537 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2538 2539 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2540 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2541 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2542 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2543 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2544 2545 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0, 2546 D_BDW_PLUS, NULL, force_nonpriv_write); 2547 2548 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2549 2550 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2551 2552 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2553 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2554 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2555 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2556 2557 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2558 2559 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2560 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2561 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2562 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2563 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2564 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2565 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2566 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2567 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2568 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2569 return 0; 2570 } 2571 2572 static int init_skl_mmio_info(struct intel_gvt *gvt) 2573 { 2574 struct drm_i915_private *dev_priv = gvt->gt->i915; 2575 int ret; 2576 2577 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2578 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2579 MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2580 MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL); 2581 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2582 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2583 2584 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2585 dp_aux_ch_ctl_mmio_write); 2586 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2587 dp_aux_ch_ctl_mmio_write); 2588 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2589 dp_aux_ch_ctl_mmio_write); 2590 2591 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); 2592 2593 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 2594 2595 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2596 MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2597 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL); 2598 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2599 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2600 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL); 2601 2602 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2603 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2604 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2605 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2606 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2607 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2608 2609 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2610 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2611 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2612 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2613 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2614 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2615 2616 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2617 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2618 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2619 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2620 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2621 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2622 2623 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2624 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2625 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2626 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2627 2628 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2629 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2630 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2631 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2632 2633 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2634 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2635 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2636 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2637 2638 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2639 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2640 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2641 2642 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2643 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2644 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2645 2646 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2647 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2648 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2649 2650 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2651 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2652 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2653 2654 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2655 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2656 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2657 2658 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2659 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2660 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2661 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2662 2663 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2664 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2665 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2666 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2667 2668 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2669 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2670 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2671 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2672 2673 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2674 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2675 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2676 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2677 2678 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2679 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2680 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2681 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2682 2683 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2684 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2685 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2686 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2687 2688 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2689 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2690 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2691 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2692 2693 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2694 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2695 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2696 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2697 2698 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2699 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2700 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2701 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2702 2703 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2704 2705 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2706 NULL, NULL); 2707 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2708 NULL, NULL); 2709 2710 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, 2711 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2712 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2713 NULL, NULL); 2714 2715 /* TRTT */ 2716 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2717 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2718 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2719 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2720 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2721 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE, 2722 NULL, gen9_trtte_write); 2723 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE, 2724 NULL, gen9_trtt_chicken_write); 2725 2726 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2727 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2728 2729 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) 2730 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2731 NULL, csfe_chicken1_mmio_write); 2732 #undef CSFE_CHICKEN1_REG 2733 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2734 NULL, NULL); 2735 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2736 NULL, NULL); 2737 2738 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL); 2739 MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2740 2741 return 0; 2742 } 2743 2744 static int init_bxt_mmio_info(struct intel_gvt *gvt) 2745 { 2746 int ret; 2747 2748 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 2749 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 2750 NULL, bxt_phy_ctl_family_write); 2751 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 2752 NULL, bxt_phy_ctl_family_write); 2753 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 2754 NULL, bxt_port_pll_enable_write); 2755 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 2756 NULL, bxt_port_pll_enable_write); 2757 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 2758 bxt_port_pll_enable_write); 2759 2760 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 2761 NULL, bxt_pcs_dw12_grp_write); 2762 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, 2763 bxt_port_tx_dw3_read, NULL); 2764 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 2765 NULL, bxt_pcs_dw12_grp_write); 2766 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, 2767 bxt_port_tx_dw3_read, NULL); 2768 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 2769 NULL, bxt_pcs_dw12_grp_write); 2770 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, 2771 bxt_port_tx_dw3_read, NULL); 2772 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 2773 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); 2774 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL); 2775 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL); 2776 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2777 0, 0, D_BXT, NULL, NULL); 2778 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2779 0, 0, D_BXT, NULL, NULL); 2780 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2781 0, 0, D_BXT, NULL, NULL); 2782 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2783 0, 0, D_BXT, NULL, NULL); 2784 2785 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 2786 2787 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write); 2788 2789 return 0; 2790 } 2791 2792 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 2793 unsigned int offset) 2794 { 2795 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2796 int num = gvt->mmio.num_mmio_block; 2797 int i; 2798 2799 for (i = 0; i < num; i++, block++) { 2800 if (offset >= i915_mmio_reg_offset(block->offset) && 2801 offset < i915_mmio_reg_offset(block->offset) + block->size) 2802 return block; 2803 } 2804 return NULL; 2805 } 2806 2807 /** 2808 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2809 * @gvt: GVT device 2810 * 2811 * This function is called at the driver unloading stage, to clean up the MMIO 2812 * information table of GVT device 2813 * 2814 */ 2815 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2816 { 2817 struct hlist_node *tmp; 2818 struct intel_gvt_mmio_info *e; 2819 int i; 2820 2821 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2822 kfree(e); 2823 2824 kfree(gvt->mmio.mmio_block); 2825 gvt->mmio.mmio_block = NULL; 2826 gvt->mmio.num_mmio_block = 0; 2827 2828 vfree(gvt->mmio.mmio_attribute); 2829 gvt->mmio.mmio_attribute = NULL; 2830 } 2831 2832 static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset, 2833 u32 size) 2834 { 2835 struct intel_gvt *gvt = iter->data; 2836 struct intel_gvt_mmio_info *info, *p; 2837 u32 start, end, i; 2838 2839 if (WARN_ON(!IS_ALIGNED(offset, 4))) 2840 return -EINVAL; 2841 2842 start = offset; 2843 end = offset + size; 2844 2845 for (i = start; i < end; i += 4) { 2846 p = intel_gvt_find_mmio_info(gvt, i); 2847 if (p) { 2848 WARN(1, "dup mmio definition offset %x\n", 2849 info->offset); 2850 2851 /* We return -EEXIST here to make GVT-g load fail. 2852 * So duplicated MMIO can be found as soon as 2853 * possible. 2854 */ 2855 return -EEXIST; 2856 } 2857 2858 info = kzalloc(sizeof(*info), GFP_KERNEL); 2859 if (!info) 2860 return -ENOMEM; 2861 2862 info->offset = i; 2863 info->read = intel_vgpu_default_mmio_read; 2864 info->write = intel_vgpu_default_mmio_write; 2865 INIT_HLIST_NODE(&info->node); 2866 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 2867 gvt->mmio.num_tracked_mmio++; 2868 } 2869 return 0; 2870 } 2871 2872 static int handle_mmio_block(struct intel_gvt_mmio_table_iter *iter, 2873 u32 offset, u32 size) 2874 { 2875 struct intel_gvt *gvt = iter->data; 2876 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2877 void *ret; 2878 2879 ret = krealloc(block, 2880 (gvt->mmio.num_mmio_block + 1) * sizeof(*block), 2881 GFP_KERNEL); 2882 if (!ret) 2883 return -ENOMEM; 2884 2885 gvt->mmio.mmio_block = block = ret; 2886 2887 block += gvt->mmio.num_mmio_block; 2888 2889 memset(block, 0, sizeof(*block)); 2890 2891 block->offset = _MMIO(offset); 2892 block->size = size; 2893 2894 gvt->mmio.num_mmio_block++; 2895 2896 return 0; 2897 } 2898 2899 static int handle_mmio_cb(struct intel_gvt_mmio_table_iter *iter, u32 offset, 2900 u32 size) 2901 { 2902 if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0))) 2903 return handle_mmio(iter, offset, size); 2904 else 2905 return handle_mmio_block(iter, offset, size); 2906 } 2907 2908 static int init_mmio_info(struct intel_gvt *gvt) 2909 { 2910 struct intel_gvt_mmio_table_iter iter = { 2911 .i915 = gvt->gt->i915, 2912 .data = gvt, 2913 .handle_mmio_cb = handle_mmio_cb, 2914 }; 2915 2916 return intel_gvt_iterate_mmio_table(&iter); 2917 } 2918 2919 static int init_mmio_block_handlers(struct intel_gvt *gvt) 2920 { 2921 struct gvt_mmio_block *block; 2922 2923 block = find_mmio_block(gvt, VGT_PVINFO_PAGE); 2924 if (!block) { 2925 WARN(1, "fail to assign handlers to mmio block %x\n", 2926 i915_mmio_reg_offset(gvt->mmio.mmio_block->offset)); 2927 return -ENODEV; 2928 } 2929 2930 block->read = pvinfo_mmio_read; 2931 block->write = pvinfo_mmio_write; 2932 2933 return 0; 2934 } 2935 2936 /** 2937 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2938 * @gvt: GVT device 2939 * 2940 * This function is called at the initialization stage, to setup the MMIO 2941 * information table for GVT device 2942 * 2943 * Returns: 2944 * zero on success, negative if failed. 2945 */ 2946 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2947 { 2948 struct intel_gvt_device_info *info = &gvt->device_info; 2949 struct drm_i915_private *i915 = gvt->gt->i915; 2950 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 2951 int ret; 2952 2953 gvt->mmio.mmio_attribute = vzalloc(size); 2954 if (!gvt->mmio.mmio_attribute) 2955 return -ENOMEM; 2956 2957 ret = init_mmio_info(gvt); 2958 if (ret) 2959 goto err; 2960 2961 ret = init_mmio_block_handlers(gvt); 2962 if (ret) 2963 goto err; 2964 2965 ret = init_generic_mmio_info(gvt); 2966 if (ret) 2967 goto err; 2968 2969 if (IS_BROADWELL(i915)) { 2970 ret = init_bdw_mmio_info(gvt); 2971 if (ret) 2972 goto err; 2973 } else if (IS_SKYLAKE(i915) || 2974 IS_KABYLAKE(i915) || 2975 IS_COFFEELAKE(i915) || 2976 IS_COMETLAKE(i915)) { 2977 ret = init_bdw_mmio_info(gvt); 2978 if (ret) 2979 goto err; 2980 ret = init_skl_mmio_info(gvt); 2981 if (ret) 2982 goto err; 2983 } else if (IS_BROXTON(i915)) { 2984 ret = init_bdw_mmio_info(gvt); 2985 if (ret) 2986 goto err; 2987 ret = init_skl_mmio_info(gvt); 2988 if (ret) 2989 goto err; 2990 ret = init_bxt_mmio_info(gvt); 2991 if (ret) 2992 goto err; 2993 } 2994 2995 return 0; 2996 err: 2997 intel_gvt_clean_mmio_info(gvt); 2998 return ret; 2999 } 3000 3001 /** 3002 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 3003 * @gvt: a GVT device 3004 * @handler: the handler 3005 * @data: private data given to handler 3006 * 3007 * Returns: 3008 * Zero on success, negative error code if failed. 3009 */ 3010 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3011 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3012 void *data) 3013 { 3014 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3015 struct intel_gvt_mmio_info *e; 3016 int i, j, ret; 3017 3018 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3019 ret = handler(gvt, e->offset, data); 3020 if (ret) 3021 return ret; 3022 } 3023 3024 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3025 /* pvinfo data doesn't come from hw mmio */ 3026 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE) 3027 continue; 3028 3029 for (j = 0; j < block->size; j += 4) { 3030 ret = handler(gvt, i915_mmio_reg_offset(block->offset) + j, data); 3031 if (ret) 3032 return ret; 3033 } 3034 } 3035 return 0; 3036 } 3037 3038 /** 3039 * intel_vgpu_default_mmio_read - default MMIO read handler 3040 * @vgpu: a vGPU 3041 * @offset: access offset 3042 * @p_data: data return buffer 3043 * @bytes: access data length 3044 * 3045 * Returns: 3046 * Zero on success, negative error code if failed. 3047 */ 3048 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3049 void *p_data, unsigned int bytes) 3050 { 3051 read_vreg(vgpu, offset, p_data, bytes); 3052 return 0; 3053 } 3054 3055 /** 3056 * intel_vgpu_default_mmio_write() - default MMIO write handler 3057 * @vgpu: a vGPU 3058 * @offset: access offset 3059 * @p_data: write data buffer 3060 * @bytes: access data length 3061 * 3062 * Returns: 3063 * Zero on success, negative error code if failed. 3064 */ 3065 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3066 void *p_data, unsigned int bytes) 3067 { 3068 write_vreg(vgpu, offset, p_data, bytes); 3069 return 0; 3070 } 3071 3072 /** 3073 * intel_vgpu_mask_mmio_write - write mask register 3074 * @vgpu: a vGPU 3075 * @offset: access offset 3076 * @p_data: write data buffer 3077 * @bytes: access data length 3078 * 3079 * Returns: 3080 * Zero on success, negative error code if failed. 3081 */ 3082 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3083 void *p_data, unsigned int bytes) 3084 { 3085 u32 mask, old_vreg; 3086 3087 old_vreg = vgpu_vreg(vgpu, offset); 3088 write_vreg(vgpu, offset, p_data, bytes); 3089 mask = vgpu_vreg(vgpu, offset) >> 16; 3090 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | 3091 (vgpu_vreg(vgpu, offset) & mask); 3092 3093 return 0; 3094 } 3095 3096 /** 3097 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3098 * force-nopriv register 3099 * 3100 * @gvt: a GVT device 3101 * @offset: register offset 3102 * 3103 * Returns: 3104 * True if the register is in force-nonpriv whitelist; 3105 * False if outside; 3106 */ 3107 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3108 unsigned int offset) 3109 { 3110 return in_whitelist(offset); 3111 } 3112 3113 /** 3114 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3115 * @vgpu: a vGPU 3116 * @offset: register offset 3117 * @pdata: data buffer 3118 * @bytes: data length 3119 * @is_read: read or write 3120 * 3121 * Returns: 3122 * Zero on success, negative error code if failed. 3123 */ 3124 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3125 void *pdata, unsigned int bytes, bool is_read) 3126 { 3127 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 3128 struct intel_gvt *gvt = vgpu->gvt; 3129 struct intel_gvt_mmio_info *mmio_info; 3130 struct gvt_mmio_block *mmio_block; 3131 gvt_mmio_func func; 3132 int ret; 3133 3134 if (drm_WARN_ON(&i915->drm, bytes > 8)) 3135 return -EINVAL; 3136 3137 /* 3138 * Handle special MMIO blocks. 3139 */ 3140 mmio_block = find_mmio_block(gvt, offset); 3141 if (mmio_block) { 3142 func = is_read ? mmio_block->read : mmio_block->write; 3143 if (func) 3144 return func(vgpu, offset, pdata, bytes); 3145 goto default_rw; 3146 } 3147 3148 /* 3149 * Normal tracked MMIOs. 3150 */ 3151 mmio_info = intel_gvt_find_mmio_info(gvt, offset); 3152 if (!mmio_info) { 3153 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3154 goto default_rw; 3155 } 3156 3157 if (is_read) 3158 return mmio_info->read(vgpu, offset, pdata, bytes); 3159 else { 3160 u64 ro_mask = mmio_info->ro_mask; 3161 u32 old_vreg = 0; 3162 u64 data = 0; 3163 3164 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3165 old_vreg = vgpu_vreg(vgpu, offset); 3166 } 3167 3168 if (likely(!ro_mask)) 3169 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3170 else if (!~ro_mask) { 3171 gvt_vgpu_err("try to write RO reg %x\n", offset); 3172 return 0; 3173 } else { 3174 /* keep the RO bits in the virtual register */ 3175 memcpy(&data, pdata, bytes); 3176 data &= ~ro_mask; 3177 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3178 ret = mmio_info->write(vgpu, offset, &data, bytes); 3179 } 3180 3181 /* higher 16bits of mode ctl regs are mask bits for change */ 3182 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3183 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3184 3185 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3186 | (vgpu_vreg(vgpu, offset) & mask); 3187 } 3188 } 3189 3190 return ret; 3191 3192 default_rw: 3193 return is_read ? 3194 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3195 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3196 } 3197 3198 void intel_gvt_restore_fence(struct intel_gvt *gvt) 3199 { 3200 struct intel_vgpu *vgpu; 3201 int i, id; 3202 3203 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3204 mmio_hw_access_pre(gvt->gt); 3205 for (i = 0; i < vgpu_fence_sz(vgpu); i++) 3206 intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i))); 3207 mmio_hw_access_post(gvt->gt); 3208 } 3209 } 3210 3211 static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data) 3212 { 3213 struct intel_vgpu *vgpu = data; 3214 struct drm_i915_private *dev_priv = gvt->gt->i915; 3215 3216 if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE) 3217 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset)); 3218 3219 return 0; 3220 } 3221 3222 void intel_gvt_restore_mmio(struct intel_gvt *gvt) 3223 { 3224 struct intel_vgpu *vgpu; 3225 int id; 3226 3227 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3228 mmio_hw_access_pre(gvt->gt); 3229 intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu); 3230 mmio_hw_access_post(gvt->gt); 3231 } 3232 } 3233