1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 41 /* XXX FIXME i915 has changed PP_XXX definition */ 42 #define PCH_PP_STATUS _MMIO(0xc7200) 43 #define PCH_PP_CONTROL _MMIO(0xc7204) 44 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 45 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 46 #define PCH_PP_DIVISOR _MMIO(0xc7210) 47 48 /* Register contains RO bits */ 49 #define F_RO (1 << 0) 50 /* Register contains graphics address */ 51 #define F_GMADR (1 << 1) 52 /* Mode mask registers with high 16 bits as the mask bits */ 53 #define F_MODE_MASK (1 << 2) 54 /* This reg can be accessed by GPU commands */ 55 #define F_CMD_ACCESS (1 << 3) 56 /* This reg has been accessed by a VM */ 57 #define F_ACCESSED (1 << 4) 58 /* This reg has been accessed through GPU commands */ 59 #define F_CMD_ACCESSED (1 << 5) 60 /* This reg could be accessed by unaligned address */ 61 #define F_UNALIGN (1 << 6) 62 63 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 64 { 65 if (IS_BROADWELL(gvt->dev_priv)) 66 return D_BDW; 67 else if (IS_SKYLAKE(gvt->dev_priv)) 68 return D_SKL; 69 70 return 0; 71 } 72 73 bool intel_gvt_match_device(struct intel_gvt *gvt, 74 unsigned long device) 75 { 76 return intel_gvt_get_device_type(gvt) & device; 77 } 78 79 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 80 void *p_data, unsigned int bytes) 81 { 82 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 83 } 84 85 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 86 void *p_data, unsigned int bytes) 87 { 88 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 89 } 90 91 static int new_mmio_info(struct intel_gvt *gvt, 92 u32 offset, u32 flags, u32 size, 93 u32 addr_mask, u32 ro_mask, u32 device, 94 void *read, void *write) 95 { 96 struct intel_gvt_mmio_info *info, *p; 97 u32 start, end, i; 98 99 if (!intel_gvt_match_device(gvt, device)) 100 return 0; 101 102 if (WARN_ON(!IS_ALIGNED(offset, 4))) 103 return -EINVAL; 104 105 start = offset; 106 end = offset + size; 107 108 for (i = start; i < end; i += 4) { 109 info = kzalloc(sizeof(*info), GFP_KERNEL); 110 if (!info) 111 return -ENOMEM; 112 113 info->offset = i; 114 p = intel_gvt_find_mmio_info(gvt, info->offset); 115 if (p) 116 gvt_err("dup mmio definition offset %x\n", 117 info->offset); 118 info->size = size; 119 info->length = (i + 4) < end ? 4 : (end - i); 120 info->addr_mask = addr_mask; 121 info->device = device; 122 info->read = read ? read : intel_vgpu_default_mmio_read; 123 info->write = write ? write : intel_vgpu_default_mmio_write; 124 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 125 INIT_HLIST_NODE(&info->node); 126 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 127 } 128 return 0; 129 } 130 131 #define offset_to_fence_num(offset) \ 132 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 133 134 #define fence_num_to_offset(num) \ 135 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 136 137 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 138 unsigned int fence_num, void *p_data, unsigned int bytes) 139 { 140 if (fence_num >= vgpu_fence_sz(vgpu)) { 141 gvt_err("vgpu%d: found oob fence register access\n", 142 vgpu->id); 143 gvt_err("vgpu%d: total fence num %d access fence num %d\n", 144 vgpu->id, vgpu_fence_sz(vgpu), fence_num); 145 memset(p_data, 0, bytes); 146 } 147 return 0; 148 } 149 150 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 151 void *p_data, unsigned int bytes) 152 { 153 int ret; 154 155 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 156 p_data, bytes); 157 if (ret) 158 return ret; 159 read_vreg(vgpu, off, p_data, bytes); 160 return 0; 161 } 162 163 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 164 void *p_data, unsigned int bytes) 165 { 166 unsigned int fence_num = offset_to_fence_num(off); 167 int ret; 168 169 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 170 if (ret) 171 return ret; 172 write_vreg(vgpu, off, p_data, bytes); 173 174 intel_vgpu_write_fence(vgpu, fence_num, 175 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 176 return 0; 177 } 178 179 #define CALC_MODE_MASK_REG(old, new) \ 180 (((new) & GENMASK(31, 16)) \ 181 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 182 | ((new) & ((new) >> 16)))) 183 184 static int mul_force_wake_write(struct intel_vgpu *vgpu, 185 unsigned int offset, void *p_data, unsigned int bytes) 186 { 187 u32 old, new; 188 uint32_t ack_reg_offset; 189 190 old = vgpu_vreg(vgpu, offset); 191 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 192 193 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) { 194 switch (offset) { 195 case FORCEWAKE_RENDER_GEN9_REG: 196 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 197 break; 198 case FORCEWAKE_BLITTER_GEN9_REG: 199 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 200 break; 201 case FORCEWAKE_MEDIA_GEN9_REG: 202 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 203 break; 204 default: 205 /*should not hit here*/ 206 gvt_err("invalid forcewake offset 0x%x\n", offset); 207 return 1; 208 } 209 } else { 210 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 211 } 212 213 vgpu_vreg(vgpu, offset) = new; 214 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 215 return 0; 216 } 217 218 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 219 void *p_data, unsigned int bytes) 220 { 221 u32 data; 222 u32 bitmap = 0; 223 224 data = vgpu_vreg(vgpu, offset); 225 226 if (data & GEN6_GRDOM_FULL) { 227 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 228 bitmap = 0xff; 229 } 230 if (data & GEN6_GRDOM_RENDER) { 231 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 232 bitmap |= (1 << RCS); 233 } 234 if (data & GEN6_GRDOM_MEDIA) { 235 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 236 bitmap |= (1 << VCS); 237 } 238 if (data & GEN6_GRDOM_BLT) { 239 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 240 bitmap |= (1 << BCS); 241 } 242 if (data & GEN6_GRDOM_VECS) { 243 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 244 bitmap |= (1 << VECS); 245 } 246 if (data & GEN8_GRDOM_MEDIA2) { 247 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 248 if (HAS_BSD2(vgpu->gvt->dev_priv)) 249 bitmap |= (1 << VCS2); 250 } 251 return 0; 252 } 253 254 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 255 void *p_data, unsigned int bytes) 256 { 257 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 258 } 259 260 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 261 void *p_data, unsigned int bytes) 262 { 263 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 264 } 265 266 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 267 unsigned int offset, void *p_data, unsigned int bytes) 268 { 269 write_vreg(vgpu, offset, p_data, bytes); 270 271 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 272 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; 273 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 274 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 275 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 276 277 } else 278 vgpu_vreg(vgpu, PCH_PP_STATUS) &= 279 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 280 | PP_CYCLE_DELAY_ACTIVE); 281 return 0; 282 } 283 284 static int transconf_mmio_write(struct intel_vgpu *vgpu, 285 unsigned int offset, void *p_data, unsigned int bytes) 286 { 287 write_vreg(vgpu, offset, p_data, bytes); 288 289 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 290 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 291 else 292 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 293 return 0; 294 } 295 296 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 297 void *p_data, unsigned int bytes) 298 { 299 write_vreg(vgpu, offset, p_data, bytes); 300 301 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 302 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 303 else 304 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 305 306 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 307 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 308 else 309 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 310 311 return 0; 312 } 313 314 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 315 void *p_data, unsigned int bytes) 316 { 317 *(u32 *)p_data = (1 << 17); 318 return 0; 319 } 320 321 static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset, 322 void *p_data, unsigned int bytes) 323 { 324 *(u32 *)p_data = 3; 325 return 0; 326 } 327 328 static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset, 329 void *p_data, unsigned int bytes) 330 { 331 *(u32 *)p_data = (0x2f << 16); 332 return 0; 333 } 334 335 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 336 void *p_data, unsigned int bytes) 337 { 338 u32 data; 339 340 write_vreg(vgpu, offset, p_data, bytes); 341 data = vgpu_vreg(vgpu, offset); 342 343 if (data & PIPECONF_ENABLE) 344 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 345 else 346 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 347 intel_gvt_check_vblank_emulation(vgpu->gvt); 348 return 0; 349 } 350 351 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 352 void *p_data, unsigned int bytes) 353 { 354 write_vreg(vgpu, offset, p_data, bytes); 355 356 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 357 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 358 } else { 359 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 360 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 361 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) 362 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 363 } 364 return 0; 365 } 366 367 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 368 unsigned int offset, void *p_data, unsigned int bytes) 369 { 370 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 371 return 0; 372 } 373 374 #define FDI_LINK_TRAIN_PATTERN1 0 375 #define FDI_LINK_TRAIN_PATTERN2 1 376 377 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 378 { 379 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); 380 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 381 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); 382 383 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 384 (rx_ctl & FDI_RX_ENABLE) && 385 (rx_ctl & FDI_AUTO_TRAINING) && 386 (tx_ctl & DP_TP_CTL_ENABLE) && 387 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 388 return 1; 389 else 390 return 0; 391 } 392 393 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 394 enum pipe pipe, unsigned int train_pattern) 395 { 396 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 397 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 398 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 399 unsigned int fdi_iir_check_bits; 400 401 fdi_rx_imr = FDI_RX_IMR(pipe); 402 fdi_tx_ctl = FDI_TX_CTL(pipe); 403 fdi_rx_ctl = FDI_RX_CTL(pipe); 404 405 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 406 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 407 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 408 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 409 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 410 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 411 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 412 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 413 } else { 414 gvt_err("Invalid train pattern %d\n", train_pattern); 415 return -EINVAL; 416 } 417 418 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 419 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 420 421 /* If imr bit has been masked */ 422 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 423 return 0; 424 425 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 426 == fdi_tx_check_bits) 427 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 428 == fdi_rx_check_bits)) 429 return 1; 430 else 431 return 0; 432 } 433 434 #define INVALID_INDEX (~0U) 435 436 static unsigned int calc_index(unsigned int offset, unsigned int start, 437 unsigned int next, unsigned int end, i915_reg_t i915_end) 438 { 439 unsigned int range = next - start; 440 441 if (!end) 442 end = i915_mmio_reg_offset(i915_end); 443 if (offset < start || offset > end) 444 return INVALID_INDEX; 445 offset -= start; 446 return offset / range; 447 } 448 449 #define FDI_RX_CTL_TO_PIPE(offset) \ 450 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 451 452 #define FDI_TX_CTL_TO_PIPE(offset) \ 453 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 454 455 #define FDI_RX_IMR_TO_PIPE(offset) \ 456 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 457 458 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 459 unsigned int offset, void *p_data, unsigned int bytes) 460 { 461 i915_reg_t fdi_rx_iir; 462 unsigned int index; 463 int ret; 464 465 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 466 index = FDI_RX_CTL_TO_PIPE(offset); 467 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 468 index = FDI_TX_CTL_TO_PIPE(offset); 469 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 470 index = FDI_RX_IMR_TO_PIPE(offset); 471 else { 472 gvt_err("Unsupport registers %x\n", offset); 473 return -EINVAL; 474 } 475 476 write_vreg(vgpu, offset, p_data, bytes); 477 478 fdi_rx_iir = FDI_RX_IIR(index); 479 480 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 481 if (ret < 0) 482 return ret; 483 if (ret) 484 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 485 486 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 487 if (ret < 0) 488 return ret; 489 if (ret) 490 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 491 492 if (offset == _FDI_RXA_CTL) 493 if (fdi_auto_training_started(vgpu)) 494 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= 495 DP_TP_STATUS_AUTOTRAIN_DONE; 496 return 0; 497 } 498 499 #define DP_TP_CTL_TO_PORT(offset) \ 500 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 501 502 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 503 void *p_data, unsigned int bytes) 504 { 505 i915_reg_t status_reg; 506 unsigned int index; 507 u32 data; 508 509 write_vreg(vgpu, offset, p_data, bytes); 510 511 index = DP_TP_CTL_TO_PORT(offset); 512 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 513 if (data == 0x2) { 514 status_reg = DP_TP_STATUS(index); 515 vgpu_vreg(vgpu, status_reg) |= (1 << 25); 516 } 517 return 0; 518 } 519 520 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 521 unsigned int offset, void *p_data, unsigned int bytes) 522 { 523 u32 reg_val; 524 u32 sticky_mask; 525 526 reg_val = *((u32 *)p_data); 527 sticky_mask = GENMASK(27, 26) | (1 << 24); 528 529 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 530 (vgpu_vreg(vgpu, offset) & sticky_mask); 531 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 532 return 0; 533 } 534 535 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 536 unsigned int offset, void *p_data, unsigned int bytes) 537 { 538 u32 data; 539 540 write_vreg(vgpu, offset, p_data, bytes); 541 data = vgpu_vreg(vgpu, offset); 542 543 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 544 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 545 return 0; 546 } 547 548 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 549 unsigned int offset, void *p_data, unsigned int bytes) 550 { 551 u32 data; 552 553 write_vreg(vgpu, offset, p_data, bytes); 554 data = vgpu_vreg(vgpu, offset); 555 556 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 557 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 558 else 559 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 560 return 0; 561 } 562 563 #define DSPSURF_TO_PIPE(offset) \ 564 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 565 566 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 567 void *p_data, unsigned int bytes) 568 { 569 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 570 unsigned int index = DSPSURF_TO_PIPE(offset); 571 i915_reg_t surflive_reg = DSPSURFLIVE(index); 572 int flip_event[] = { 573 [PIPE_A] = PRIMARY_A_FLIP_DONE, 574 [PIPE_B] = PRIMARY_B_FLIP_DONE, 575 [PIPE_C] = PRIMARY_C_FLIP_DONE, 576 }; 577 578 write_vreg(vgpu, offset, p_data, bytes); 579 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 580 581 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 582 return 0; 583 } 584 585 #define SPRSURF_TO_PIPE(offset) \ 586 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 587 588 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 589 void *p_data, unsigned int bytes) 590 { 591 unsigned int index = SPRSURF_TO_PIPE(offset); 592 i915_reg_t surflive_reg = SPRSURFLIVE(index); 593 int flip_event[] = { 594 [PIPE_A] = SPRITE_A_FLIP_DONE, 595 [PIPE_B] = SPRITE_B_FLIP_DONE, 596 [PIPE_C] = SPRITE_C_FLIP_DONE, 597 }; 598 599 write_vreg(vgpu, offset, p_data, bytes); 600 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 601 602 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 603 return 0; 604 } 605 606 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 607 unsigned int reg) 608 { 609 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 610 enum intel_gvt_event_type event; 611 612 if (reg == _DPA_AUX_CH_CTL) 613 event = AUX_CHANNEL_A; 614 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 615 event = AUX_CHANNEL_B; 616 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 617 event = AUX_CHANNEL_C; 618 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 619 event = AUX_CHANNEL_D; 620 else { 621 WARN_ON(true); 622 return -EINVAL; 623 } 624 625 intel_vgpu_trigger_virtual_event(vgpu, event); 626 return 0; 627 } 628 629 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 630 unsigned int reg, int len, bool data_valid) 631 { 632 /* mark transaction done */ 633 value |= DP_AUX_CH_CTL_DONE; 634 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 635 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 636 637 if (data_valid) 638 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 639 else 640 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 641 642 /* message size */ 643 value &= ~(0xf << 20); 644 value |= (len << 20); 645 vgpu_vreg(vgpu, reg) = value; 646 647 if (value & DP_AUX_CH_CTL_INTERRUPT) 648 return trigger_aux_channel_interrupt(vgpu, reg); 649 return 0; 650 } 651 652 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 653 uint8_t t) 654 { 655 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 656 /* training pattern 1 for CR */ 657 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 658 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 659 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 660 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 661 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 662 DPCD_TRAINING_PATTERN_2) { 663 /* training pattern 2 for EQ */ 664 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 665 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 666 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 667 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 668 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 669 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 670 /* set INTERLANE_ALIGN_DONE */ 671 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 672 DPCD_INTERLANE_ALIGN_DONE; 673 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 674 DPCD_LINK_TRAINING_DISABLED) { 675 /* finish link training */ 676 /* set sink status as synchronized */ 677 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 678 } 679 } 680 681 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 682 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 683 684 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 685 686 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 687 688 #define dpy_is_valid_port(port) \ 689 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 690 691 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 692 unsigned int offset, void *p_data, unsigned int bytes) 693 { 694 struct intel_vgpu_display *display = &vgpu->display; 695 int msg, addr, ctrl, op, len; 696 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 697 struct intel_vgpu_dpcd_data *dpcd = NULL; 698 struct intel_vgpu_port *port = NULL; 699 u32 data; 700 701 if (!dpy_is_valid_port(port_index)) { 702 gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id); 703 return 0; 704 } 705 706 write_vreg(vgpu, offset, p_data, bytes); 707 data = vgpu_vreg(vgpu, offset); 708 709 if (IS_SKYLAKE(vgpu->gvt->dev_priv) && 710 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 711 /* SKL DPB/C/D aux ctl register changed */ 712 return 0; 713 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 714 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 715 /* write to the data registers */ 716 return 0; 717 } 718 719 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 720 /* just want to clear the sticky bits */ 721 vgpu_vreg(vgpu, offset) = 0; 722 return 0; 723 } 724 725 port = &display->ports[port_index]; 726 dpcd = port->dpcd; 727 728 /* read out message from DATA1 register */ 729 msg = vgpu_vreg(vgpu, offset + 4); 730 addr = (msg >> 8) & 0xffff; 731 ctrl = (msg >> 24) & 0xff; 732 len = msg & 0xff; 733 op = ctrl >> 4; 734 735 if (op == GVT_AUX_NATIVE_WRITE) { 736 int t; 737 uint8_t buf[16]; 738 739 if ((addr + len + 1) >= DPCD_SIZE) { 740 /* 741 * Write request exceeds what we supported, 742 * DCPD spec: When a Source Device is writing a DPCD 743 * address not supported by the Sink Device, the Sink 744 * Device shall reply with AUX NACK and “M” equal to 745 * zero. 746 */ 747 748 /* NAK the write */ 749 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 750 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 751 return 0; 752 } 753 754 /* 755 * Write request format: (command + address) occupies 756 * 3 bytes, followed by (len + 1) bytes of data. 757 */ 758 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 759 return -EINVAL; 760 761 /* unpack data from vreg to buf */ 762 for (t = 0; t < 4; t++) { 763 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 764 765 buf[t * 4] = (r >> 24) & 0xff; 766 buf[t * 4 + 1] = (r >> 16) & 0xff; 767 buf[t * 4 + 2] = (r >> 8) & 0xff; 768 buf[t * 4 + 3] = r & 0xff; 769 } 770 771 /* write to virtual DPCD */ 772 if (dpcd && dpcd->data_valid) { 773 for (t = 0; t <= len; t++) { 774 int p = addr + t; 775 776 dpcd->data[p] = buf[t]; 777 /* check for link training */ 778 if (p == DPCD_TRAINING_PATTERN_SET) 779 dp_aux_ch_ctl_link_training(dpcd, 780 buf[t]); 781 } 782 } 783 784 /* ACK the write */ 785 vgpu_vreg(vgpu, offset + 4) = 0; 786 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 787 dpcd && dpcd->data_valid); 788 return 0; 789 } 790 791 if (op == GVT_AUX_NATIVE_READ) { 792 int idx, i, ret = 0; 793 794 if ((addr + len + 1) >= DPCD_SIZE) { 795 /* 796 * read request exceeds what we supported 797 * DPCD spec: A Sink Device receiving a Native AUX CH 798 * read request for an unsupported DPCD address must 799 * reply with an AUX ACK and read data set equal to 800 * zero instead of replying with AUX NACK. 801 */ 802 803 /* ACK the READ*/ 804 vgpu_vreg(vgpu, offset + 4) = 0; 805 vgpu_vreg(vgpu, offset + 8) = 0; 806 vgpu_vreg(vgpu, offset + 12) = 0; 807 vgpu_vreg(vgpu, offset + 16) = 0; 808 vgpu_vreg(vgpu, offset + 20) = 0; 809 810 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 811 true); 812 return 0; 813 } 814 815 for (idx = 1; idx <= 5; idx++) { 816 /* clear the data registers */ 817 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 818 } 819 820 /* 821 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 822 */ 823 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 824 return -EINVAL; 825 826 /* read from virtual DPCD to vreg */ 827 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 828 if (dpcd && dpcd->data_valid) { 829 for (i = 1; i <= (len + 1); i++) { 830 int t; 831 832 t = dpcd->data[addr + i - 1]; 833 t <<= (24 - 8 * (i % 4)); 834 ret |= t; 835 836 if ((i % 4 == 3) || (i == (len + 1))) { 837 vgpu_vreg(vgpu, offset + 838 (i / 4 + 1) * 4) = ret; 839 ret = 0; 840 } 841 } 842 } 843 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 844 dpcd && dpcd->data_valid); 845 return 0; 846 } 847 848 /* i2c transaction starts */ 849 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 850 851 if (data & DP_AUX_CH_CTL_INTERRUPT) 852 trigger_aux_channel_interrupt(vgpu, offset); 853 return 0; 854 } 855 856 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 857 void *p_data, unsigned int bytes) 858 { 859 bool vga_disable; 860 861 write_vreg(vgpu, offset, p_data, bytes); 862 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 863 864 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 865 vga_disable ? "Disable" : "Enable"); 866 return 0; 867 } 868 869 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 870 unsigned int sbi_offset) 871 { 872 struct intel_vgpu_display *display = &vgpu->display; 873 int num = display->sbi.number; 874 int i; 875 876 for (i = 0; i < num; ++i) 877 if (display->sbi.registers[i].offset == sbi_offset) 878 break; 879 880 if (i == num) 881 return 0; 882 883 return display->sbi.registers[i].value; 884 } 885 886 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 887 unsigned int offset, u32 value) 888 { 889 struct intel_vgpu_display *display = &vgpu->display; 890 int num = display->sbi.number; 891 int i; 892 893 for (i = 0; i < num; ++i) { 894 if (display->sbi.registers[i].offset == offset) 895 break; 896 } 897 898 if (i == num) { 899 if (num == SBI_REG_MAX) { 900 gvt_err("vgpu%d: SBI caching meets maximum limits\n", 901 vgpu->id); 902 return; 903 } 904 display->sbi.number++; 905 } 906 907 display->sbi.registers[i].offset = offset; 908 display->sbi.registers[i].value = value; 909 } 910 911 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 912 void *p_data, unsigned int bytes) 913 { 914 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 915 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 916 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 917 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 918 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 919 sbi_offset); 920 } 921 read_vreg(vgpu, offset, p_data, bytes); 922 return 0; 923 } 924 925 static bool sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 926 void *p_data, unsigned int bytes) 927 { 928 u32 data; 929 930 write_vreg(vgpu, offset, p_data, bytes); 931 data = vgpu_vreg(vgpu, offset); 932 933 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 934 data |= SBI_READY; 935 936 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 937 data |= SBI_RESPONSE_SUCCESS; 938 939 vgpu_vreg(vgpu, offset) = data; 940 941 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 942 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 943 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 944 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 945 946 write_virtual_sbi_register(vgpu, sbi_offset, 947 vgpu_vreg(vgpu, SBI_DATA)); 948 } 949 return 0; 950 } 951 952 #define _vgtif_reg(x) \ 953 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 954 955 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 956 void *p_data, unsigned int bytes) 957 { 958 bool invalid_read = false; 959 960 read_vreg(vgpu, offset, p_data, bytes); 961 962 switch (offset) { 963 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 964 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 965 invalid_read = true; 966 break; 967 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 968 _vgtif_reg(avail_rs.fence_num): 969 if (offset + bytes > 970 _vgtif_reg(avail_rs.fence_num) + 4) 971 invalid_read = true; 972 break; 973 case 0x78010: /* vgt_caps */ 974 case 0x7881c: 975 break; 976 default: 977 invalid_read = true; 978 break; 979 } 980 if (invalid_read) 981 gvt_err("invalid pvinfo read: [%x:%x] = %x\n", 982 offset, bytes, *(u32 *)p_data); 983 return 0; 984 } 985 986 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 987 { 988 int ret = 0; 989 990 switch (notification) { 991 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 992 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); 993 break; 994 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 995 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); 996 break; 997 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 998 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); 999 break; 1000 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1001 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); 1002 break; 1003 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1004 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1005 case 1: /* Remove this in guest driver. */ 1006 break; 1007 default: 1008 gvt_err("Invalid PV notification %d\n", notification); 1009 } 1010 return ret; 1011 } 1012 1013 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1014 { 1015 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1016 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1017 char *env[3] = {NULL, NULL, NULL}; 1018 char vmid_str[20]; 1019 char display_ready_str[20]; 1020 1021 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready); 1022 env[0] = display_ready_str; 1023 1024 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1025 env[1] = vmid_str; 1026 1027 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1028 } 1029 1030 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1031 void *p_data, unsigned int bytes) 1032 { 1033 u32 data; 1034 int ret; 1035 1036 write_vreg(vgpu, offset, p_data, bytes); 1037 data = vgpu_vreg(vgpu, offset); 1038 1039 switch (offset) { 1040 case _vgtif_reg(display_ready): 1041 send_display_ready_uevent(vgpu, data ? 1 : 0); 1042 break; 1043 case _vgtif_reg(g2v_notify): 1044 ret = handle_g2v_notification(vgpu, data); 1045 break; 1046 /* add xhot and yhot to handled list to avoid error log */ 1047 case 0x78830: 1048 case 0x78834: 1049 case _vgtif_reg(pdp[0].lo): 1050 case _vgtif_reg(pdp[0].hi): 1051 case _vgtif_reg(pdp[1].lo): 1052 case _vgtif_reg(pdp[1].hi): 1053 case _vgtif_reg(pdp[2].lo): 1054 case _vgtif_reg(pdp[2].hi): 1055 case _vgtif_reg(pdp[3].lo): 1056 case _vgtif_reg(pdp[3].hi): 1057 case _vgtif_reg(execlist_context_descriptor_lo): 1058 case _vgtif_reg(execlist_context_descriptor_hi): 1059 break; 1060 default: 1061 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n", 1062 offset, bytes, data); 1063 break; 1064 } 1065 return 0; 1066 } 1067 1068 static int pf_write(struct intel_vgpu *vgpu, 1069 unsigned int offset, void *p_data, unsigned int bytes) 1070 { 1071 u32 val = *(u32 *)p_data; 1072 1073 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1074 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1075 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1076 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1077 vgpu->id); 1078 return 0; 1079 } 1080 1081 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1082 } 1083 1084 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1085 unsigned int offset, void *p_data, unsigned int bytes) 1086 { 1087 write_vreg(vgpu, offset, p_data, bytes); 1088 1089 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) 1090 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; 1091 else 1092 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; 1093 return 0; 1094 } 1095 1096 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1097 unsigned int offset, void *p_data, unsigned int bytes) 1098 { 1099 write_vreg(vgpu, offset, p_data, bytes); 1100 1101 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1102 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1103 return 0; 1104 } 1105 1106 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1107 void *p_data, unsigned int bytes) 1108 { 1109 u32 mode = *(u32 *)p_data; 1110 1111 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1112 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n", 1113 vgpu->id); 1114 return 0; 1115 } 1116 1117 return 0; 1118 } 1119 1120 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1121 void *p_data, unsigned int bytes) 1122 { 1123 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1124 u32 trtte = *(u32 *)p_data; 1125 1126 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1127 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1128 vgpu->id); 1129 return -EINVAL; 1130 } 1131 write_vreg(vgpu, offset, p_data, bytes); 1132 /* TRTTE is not per-context */ 1133 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1134 1135 return 0; 1136 } 1137 1138 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1139 void *p_data, unsigned int bytes) 1140 { 1141 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1142 u32 val = *(u32 *)p_data; 1143 1144 if (val & 1) { 1145 /* unblock hw logic */ 1146 I915_WRITE(_MMIO(offset), val); 1147 } 1148 write_vreg(vgpu, offset, p_data, bytes); 1149 return 0; 1150 } 1151 1152 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1153 void *p_data, unsigned int bytes) 1154 { 1155 u32 v = 0; 1156 1157 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1158 v |= (1 << 0); 1159 1160 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1161 v |= (1 << 8); 1162 1163 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1164 v |= (1 << 16); 1165 1166 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1167 v |= (1 << 24); 1168 1169 vgpu_vreg(vgpu, offset) = v; 1170 1171 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1172 } 1173 1174 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1175 void *p_data, unsigned int bytes) 1176 { 1177 u32 value = *(u32 *)p_data; 1178 u32 cmd = value & 0xff; 1179 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); 1180 1181 switch (cmd) { 1182 case 0x6: 1183 /** 1184 * "Read memory latency" command on gen9. 1185 * Below memory latency values are read 1186 * from skylake platform. 1187 */ 1188 if (!*data0) 1189 *data0 = 0x1e1a1100; 1190 else 1191 *data0 = 0x61514b3d; 1192 break; 1193 case 0x5: 1194 *data0 |= 0x1; 1195 break; 1196 } 1197 1198 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1199 vgpu->id, value, *data0); 1200 1201 value &= ~(1 << 31); 1202 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1203 } 1204 1205 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1206 unsigned int offset, void *p_data, unsigned int bytes) 1207 { 1208 u32 v = *(u32 *)p_data; 1209 1210 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1211 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1212 v |= (v >> 1); 1213 1214 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1215 } 1216 1217 static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1218 void *p_data, unsigned int bytes) 1219 { 1220 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1221 i915_reg_t reg = {.reg = offset}; 1222 1223 switch (offset) { 1224 case 0x4ddc: 1225 vgpu_vreg(vgpu, offset) = 0x8000003c; 1226 break; 1227 case 0x42080: 1228 vgpu_vreg(vgpu, offset) = 0x8000; 1229 break; 1230 default: 1231 return -EINVAL; 1232 } 1233 1234 /** 1235 * TODO: need detect stepping info after gvt contain such information 1236 * 0x4ddc enabled after C0, 0x42080 enabled after E0. 1237 */ 1238 I915_WRITE(reg, vgpu_vreg(vgpu, offset)); 1239 return 0; 1240 } 1241 1242 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1243 void *p_data, unsigned int bytes) 1244 { 1245 u32 v = *(u32 *)p_data; 1246 1247 /* other bits are MBZ. */ 1248 v &= (1 << 31) | (1 << 30); 1249 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1250 1251 vgpu_vreg(vgpu, offset) = v; 1252 1253 return 0; 1254 } 1255 1256 static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu, 1257 unsigned int offset, void *p_data, unsigned int bytes) 1258 { 1259 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1260 1261 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1262 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1263 } 1264 1265 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1266 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 1267 f, s, am, rm, d, r, w); \ 1268 if (ret) \ 1269 return ret; \ 1270 } while (0) 1271 1272 #define MMIO_D(reg, d) \ 1273 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1274 1275 #define MMIO_DH(reg, d, r, w) \ 1276 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1277 1278 #define MMIO_DFH(reg, d, f, r, w) \ 1279 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1280 1281 #define MMIO_GM(reg, d, r, w) \ 1282 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1283 1284 #define MMIO_RO(reg, d, f, rm, r, w) \ 1285 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1286 1287 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1288 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1289 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1290 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1291 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1292 } while (0) 1293 1294 #define MMIO_RING_D(prefix, d) \ 1295 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1296 1297 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1298 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1299 1300 #define MMIO_RING_GM(prefix, d, r, w) \ 1301 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1302 1303 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1304 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1305 1306 static int init_generic_mmio_info(struct intel_gvt *gvt) 1307 { 1308 struct drm_i915_private *dev_priv = gvt->dev_priv; 1309 int ret; 1310 1311 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1312 1313 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1314 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1315 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1316 MMIO_D(SDEISR, D_ALL); 1317 1318 MMIO_RING_D(RING_HWSTAM, D_ALL); 1319 1320 MMIO_GM(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1321 MMIO_GM(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1322 MMIO_GM(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1323 MMIO_GM(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1324 1325 #define RING_REG(base) (base + 0x28) 1326 MMIO_RING_D(RING_REG, D_ALL); 1327 #undef RING_REG 1328 1329 #define RING_REG(base) (base + 0x134) 1330 MMIO_RING_D(RING_REG, D_ALL); 1331 #undef RING_REG 1332 1333 MMIO_GM(0x2148, D_ALL, NULL, NULL); 1334 MMIO_GM(CCID, D_ALL, NULL, NULL); 1335 MMIO_GM(0x12198, D_ALL, NULL, NULL); 1336 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1337 1338 MMIO_RING_D(RING_TAIL, D_ALL); 1339 MMIO_RING_D(RING_HEAD, D_ALL); 1340 MMIO_RING_D(RING_CTL, D_ALL); 1341 MMIO_RING_D(RING_ACTHD, D_ALL); 1342 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 1343 1344 /* RING MODE */ 1345 #define RING_REG(base) (base + 0x29c) 1346 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK, NULL, NULL); 1347 #undef RING_REG 1348 1349 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1350 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL); 1351 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1352 ring_timestamp_mmio_read, NULL); 1353 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1354 ring_timestamp_mmio_read, NULL); 1355 1356 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1357 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL); 1358 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK, NULL, NULL); 1359 1360 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL); 1361 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL); 1362 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK, NULL, NULL); 1363 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK, NULL, NULL); 1364 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK, NULL, NULL); 1365 MMIO_D(GAM_ECOCHK, D_ALL); 1366 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK, NULL, NULL); 1367 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK, NULL, NULL); 1368 MMIO_D(0x9030, D_ALL); 1369 MMIO_D(0x20a0, D_ALL); 1370 MMIO_D(0x2420, D_ALL); 1371 MMIO_D(0x2430, D_ALL); 1372 MMIO_D(0x2434, D_ALL); 1373 MMIO_D(0x2438, D_ALL); 1374 MMIO_D(0x243c, D_ALL); 1375 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK, NULL, NULL); 1376 MMIO_DFH(0xe184, D_ALL, F_MODE_MASK, NULL, NULL); 1377 MMIO_DFH(0xe100, D_ALL, F_MODE_MASK, NULL, NULL); 1378 1379 /* display */ 1380 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1381 MMIO_D(0x602a0, D_ALL); 1382 1383 MMIO_D(0x65050, D_ALL); 1384 MMIO_D(0x650b4, D_ALL); 1385 1386 MMIO_D(0xc4040, D_ALL); 1387 MMIO_D(DERRMR, D_ALL); 1388 1389 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1390 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1391 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1392 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1393 1394 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1395 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1396 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1397 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1398 1399 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1400 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1401 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1402 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1403 1404 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1405 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1406 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1407 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1408 1409 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1410 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1411 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1412 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1413 1414 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1415 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1416 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1417 1418 MMIO_D(CURPOS(PIPE_A), D_ALL); 1419 MMIO_D(CURPOS(PIPE_B), D_ALL); 1420 MMIO_D(CURPOS(PIPE_C), D_ALL); 1421 1422 MMIO_D(CURBASE(PIPE_A), D_ALL); 1423 MMIO_D(CURBASE(PIPE_B), D_ALL); 1424 MMIO_D(CURBASE(PIPE_C), D_ALL); 1425 1426 MMIO_D(0x700ac, D_ALL); 1427 MMIO_D(0x710ac, D_ALL); 1428 MMIO_D(0x720ac, D_ALL); 1429 1430 MMIO_D(0x70090, D_ALL); 1431 MMIO_D(0x70094, D_ALL); 1432 MMIO_D(0x70098, D_ALL); 1433 MMIO_D(0x7009c, D_ALL); 1434 1435 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1436 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1437 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1438 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1439 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1440 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1441 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1442 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1443 1444 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1445 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1446 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1447 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1448 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1449 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1450 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1451 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1452 1453 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1454 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1455 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1456 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1457 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1458 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1459 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1460 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1461 1462 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1463 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1464 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1465 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1466 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1467 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1468 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1469 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1470 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1471 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1472 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1473 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1474 1475 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1476 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1477 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1478 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1479 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1480 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1481 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1482 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1483 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1484 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1485 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1486 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1487 1488 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1489 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1490 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1491 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1492 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1493 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1494 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1495 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1496 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1497 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1498 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1499 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1500 1501 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1502 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1503 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1504 1505 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1506 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1507 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1508 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1509 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1510 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1511 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1512 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1513 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1514 1515 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1516 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1517 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1518 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1519 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1520 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1521 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1522 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1523 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1524 1525 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1526 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1527 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1528 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1529 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1530 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1531 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1532 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1533 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1534 1535 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1536 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1537 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1538 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1539 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1540 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1541 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1542 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1543 1544 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1545 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1546 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1547 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1548 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1549 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1550 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1551 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1552 1553 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1554 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1555 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1556 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1557 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1558 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1559 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1560 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1561 1562 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1563 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1564 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1565 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1566 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1567 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1568 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1569 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1570 1571 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1572 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1573 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1574 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1575 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1576 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1577 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1578 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1579 1580 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1581 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1582 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1583 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1584 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1585 1586 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1587 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1588 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1589 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1590 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1591 1592 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1593 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1594 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1595 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1596 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1597 1598 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1599 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1600 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1601 MMIO_D(WM1_LP_ILK, D_ALL); 1602 MMIO_D(WM2_LP_ILK, D_ALL); 1603 MMIO_D(WM3_LP_ILK, D_ALL); 1604 MMIO_D(WM1S_LP_ILK, D_ALL); 1605 MMIO_D(WM2S_LP_IVB, D_ALL); 1606 MMIO_D(WM3S_LP_IVB, D_ALL); 1607 1608 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1609 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1610 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1611 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1612 1613 MMIO_D(0x48268, D_ALL); 1614 1615 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1616 gmbus_mmio_write); 1617 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1618 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1619 1620 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1621 dp_aux_ch_ctl_mmio_write); 1622 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1623 dp_aux_ch_ctl_mmio_write); 1624 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1625 dp_aux_ch_ctl_mmio_write); 1626 1627 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write); 1628 1629 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); 1630 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); 1631 1632 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1633 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1634 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1635 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1636 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1637 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1638 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1639 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1640 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1641 1642 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 1643 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 1644 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 1645 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 1646 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 1647 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 1648 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 1649 1650 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 1651 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 1652 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 1653 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 1654 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 1655 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 1656 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 1657 1658 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 1659 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 1660 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 1661 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 1662 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 1663 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 1664 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 1665 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 1666 1667 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 1668 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 1669 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 1670 1671 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 1672 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 1673 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 1674 1675 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 1676 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 1677 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 1678 1679 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 1680 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 1681 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 1682 1683 MMIO_D(_FDI_RXA_MISC, D_ALL); 1684 MMIO_D(_FDI_RXB_MISC, D_ALL); 1685 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 1686 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 1687 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 1688 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 1689 1690 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 1691 MMIO_D(PCH_PP_DIVISOR, D_ALL); 1692 MMIO_D(PCH_PP_STATUS, D_ALL); 1693 MMIO_D(PCH_LVDS, D_ALL); 1694 MMIO_D(_PCH_DPLL_A, D_ALL); 1695 MMIO_D(_PCH_DPLL_B, D_ALL); 1696 MMIO_D(_PCH_FPA0, D_ALL); 1697 MMIO_D(_PCH_FPA1, D_ALL); 1698 MMIO_D(_PCH_FPB0, D_ALL); 1699 MMIO_D(_PCH_FPB1, D_ALL); 1700 MMIO_D(PCH_DREF_CONTROL, D_ALL); 1701 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 1702 MMIO_D(PCH_DPLL_SEL, D_ALL); 1703 1704 MMIO_D(0x61208, D_ALL); 1705 MMIO_D(0x6120c, D_ALL); 1706 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 1707 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 1708 1709 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); 1710 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); 1711 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); 1712 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); 1713 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL); 1714 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL); 1715 1716 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 1717 PORTA_HOTPLUG_STATUS_MASK 1718 | PORTB_HOTPLUG_STATUS_MASK 1719 | PORTC_HOTPLUG_STATUS_MASK 1720 | PORTD_HOTPLUG_STATUS_MASK, 1721 NULL, NULL); 1722 1723 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 1724 MMIO_D(FUSE_STRAP, D_ALL); 1725 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 1726 1727 MMIO_D(DISP_ARB_CTL, D_ALL); 1728 MMIO_D(DISP_ARB_CTL2, D_ALL); 1729 1730 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 1731 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 1732 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 1733 1734 MMIO_D(SOUTH_CHICKEN1, D_ALL); 1735 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 1736 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 1737 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 1738 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 1739 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 1740 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 1741 1742 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 1743 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 1744 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 1745 MMIO_D(ILK_DPFC_STATUS, D_ALL); 1746 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 1747 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 1748 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 1749 1750 MMIO_D(IPS_CTL, D_ALL); 1751 1752 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 1753 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 1754 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 1755 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 1756 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 1757 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 1758 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 1759 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 1760 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 1761 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 1762 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 1763 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 1764 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 1765 1766 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 1767 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 1768 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 1769 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 1770 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 1771 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 1772 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 1773 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 1774 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 1775 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 1776 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 1777 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 1778 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 1779 1780 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 1781 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 1782 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 1783 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 1784 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 1785 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 1786 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 1787 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 1788 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 1789 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 1790 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 1791 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 1792 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 1793 1794 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 1795 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 1796 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1797 1798 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 1799 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 1800 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1801 1802 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 1803 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 1804 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1805 1806 MMIO_D(0x60110, D_ALL); 1807 MMIO_D(0x61110, D_ALL); 1808 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1809 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1810 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1811 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1812 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1813 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1814 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1815 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1816 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1817 1818 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 1819 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 1820 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 1821 MMIO_D(SPLL_CTL, D_ALL); 1822 MMIO_D(_WRPLL_CTL1, D_ALL); 1823 MMIO_D(_WRPLL_CTL2, D_ALL); 1824 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 1825 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 1826 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 1827 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 1828 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 1829 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 1830 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 1831 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 1832 1833 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 1834 MMIO_D(0x46508, D_ALL); 1835 1836 MMIO_D(0x49080, D_ALL); 1837 MMIO_D(0x49180, D_ALL); 1838 MMIO_D(0x49280, D_ALL); 1839 1840 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1841 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1842 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1843 1844 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 1845 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 1846 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 1847 1848 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 1849 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 1850 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 1851 1852 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 1853 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 1854 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 1855 1856 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 1857 MMIO_D(SBI_ADDR, D_ALL); 1858 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 1859 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 1860 MMIO_D(PIXCLK_GATE, D_ALL); 1861 1862 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, 1863 dp_aux_ch_ctl_mmio_write); 1864 1865 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1866 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1867 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1868 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1869 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1870 1871 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 1872 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 1873 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 1874 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 1875 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 1876 1877 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 1878 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 1879 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 1880 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 1881 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 1882 1883 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1884 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1885 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1886 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1887 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 1888 1889 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 1890 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 1891 1892 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 1893 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 1894 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 1895 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 1896 1897 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 1898 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 1899 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 1900 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 1901 1902 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 1903 MMIO_D(FORCEWAKE_ACK, D_ALL); 1904 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 1905 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 1906 MMIO_D(GTFIFODBG, D_ALL); 1907 MMIO_D(GTFIFOCTL, D_ALL); 1908 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 1909 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL); 1910 MMIO_D(ECOBUS, D_ALL); 1911 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 1912 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 1913 MMIO_D(GEN6_RPNSWREQ, D_ALL); 1914 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 1915 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 1916 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 1917 MMIO_D(GEN6_RPSTAT1, D_ALL); 1918 MMIO_D(GEN6_RP_CONTROL, D_ALL); 1919 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 1920 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 1921 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 1922 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 1923 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 1924 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 1925 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 1926 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 1927 MMIO_D(GEN6_RP_UP_EI, D_ALL); 1928 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 1929 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 1930 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 1931 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 1932 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 1933 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 1934 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 1935 MMIO_D(GEN6_RC_SLEEP, D_ALL); 1936 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 1937 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 1938 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 1939 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 1940 MMIO_D(GEN6_PMINTRMSK, D_ALL); 1941 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1942 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1943 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1944 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1945 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1946 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 1947 1948 MMIO_D(RSTDBYCTL, D_ALL); 1949 1950 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 1951 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 1952 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write); 1953 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 1954 1955 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL); 1956 1957 MMIO_D(TILECTL, D_ALL); 1958 1959 MMIO_D(GEN6_UCGCTL1, D_ALL); 1960 MMIO_D(GEN6_UCGCTL2, D_ALL); 1961 1962 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 1963 1964 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_SKL); 1965 MMIO_D(GEN6_PCODE_DATA, D_ALL); 1966 MMIO_D(0x13812c, D_ALL); 1967 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 1968 MMIO_D(HSW_EDRAM_CAP, D_ALL); 1969 MMIO_D(HSW_IDICR, D_ALL); 1970 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 1971 1972 MMIO_D(0x3c, D_ALL); 1973 MMIO_D(0x860, D_ALL); 1974 MMIO_D(ECOSKPD, D_ALL); 1975 MMIO_D(0x121d0, D_ALL); 1976 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 1977 MMIO_D(0x41d0, D_ALL); 1978 MMIO_D(GAC_ECO_BITS, D_ALL); 1979 MMIO_D(0x6200, D_ALL); 1980 MMIO_D(0x6204, D_ALL); 1981 MMIO_D(0x6208, D_ALL); 1982 MMIO_D(0x7118, D_ALL); 1983 MMIO_D(0x7180, D_ALL); 1984 MMIO_D(0x7408, D_ALL); 1985 MMIO_D(0x7c00, D_ALL); 1986 MMIO_D(GEN6_MBCTL, D_ALL); 1987 MMIO_D(0x911c, D_ALL); 1988 MMIO_D(0x9120, D_ALL); 1989 1990 MMIO_D(GAB_CTL, D_ALL); 1991 MMIO_D(0x48800, D_ALL); 1992 MMIO_D(0xce044, D_ALL); 1993 MMIO_D(0xe6500, D_ALL); 1994 MMIO_D(0xe6504, D_ALL); 1995 MMIO_D(0xe6600, D_ALL); 1996 MMIO_D(0xe6604, D_ALL); 1997 MMIO_D(0xe6700, D_ALL); 1998 MMIO_D(0xe6704, D_ALL); 1999 MMIO_D(0xe6800, D_ALL); 2000 MMIO_D(0xe6804, D_ALL); 2001 MMIO_D(PCH_GMBUS4, D_ALL); 2002 MMIO_D(PCH_GMBUS5, D_ALL); 2003 2004 MMIO_D(0x902c, D_ALL); 2005 MMIO_D(0xec008, D_ALL); 2006 MMIO_D(0xec00c, D_ALL); 2007 MMIO_D(0xec008 + 0x18, D_ALL); 2008 MMIO_D(0xec00c + 0x18, D_ALL); 2009 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 2010 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 2011 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 2012 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 2013 MMIO_D(0xec408, D_ALL); 2014 MMIO_D(0xec40c, D_ALL); 2015 MMIO_D(0xec408 + 0x18, D_ALL); 2016 MMIO_D(0xec40c + 0x18, D_ALL); 2017 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 2018 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 2019 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 2020 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 2021 MMIO_D(0xfc810, D_ALL); 2022 MMIO_D(0xfc81c, D_ALL); 2023 MMIO_D(0xfc828, D_ALL); 2024 MMIO_D(0xfc834, D_ALL); 2025 MMIO_D(0xfcc00, D_ALL); 2026 MMIO_D(0xfcc0c, D_ALL); 2027 MMIO_D(0xfcc18, D_ALL); 2028 MMIO_D(0xfcc24, D_ALL); 2029 MMIO_D(0xfd000, D_ALL); 2030 MMIO_D(0xfd00c, D_ALL); 2031 MMIO_D(0xfd018, D_ALL); 2032 MMIO_D(0xfd024, D_ALL); 2033 MMIO_D(0xfd034, D_ALL); 2034 2035 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2036 MMIO_D(0x2054, D_ALL); 2037 MMIO_D(0x12054, D_ALL); 2038 MMIO_D(0x22054, D_ALL); 2039 MMIO_D(0x1a054, D_ALL); 2040 2041 MMIO_D(0x44070, D_ALL); 2042 2043 MMIO_D(0x215c, D_HSW_PLUS); 2044 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2045 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2046 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2047 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2048 2049 MMIO_F(0x2290, 8, 0, 0, 0, D_HSW_PLUS, NULL, NULL); 2050 MMIO_D(OACONTROL, D_HSW); 2051 MMIO_D(0x2b00, D_BDW_PLUS); 2052 MMIO_D(0x2360, D_BDW_PLUS); 2053 MMIO_F(0x5200, 32, 0, 0, 0, D_ALL, NULL, NULL); 2054 MMIO_F(0x5240, 32, 0, 0, 0, D_ALL, NULL, NULL); 2055 MMIO_F(0x5280, 16, 0, 0, 0, D_ALL, NULL, NULL); 2056 2057 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2058 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2059 MMIO_D(BCS_SWCTRL, D_ALL); 2060 2061 MMIO_F(HS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2062 MMIO_F(DS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2063 MMIO_F(IA_VERTICES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2064 MMIO_F(IA_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2065 MMIO_F(VS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2066 MMIO_F(GS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2067 MMIO_F(GS_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2068 MMIO_F(CL_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2069 MMIO_F(CL_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2070 MMIO_F(PS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2071 MMIO_F(PS_DEPTH_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2072 MMIO_DH(0x4260, D_BDW_PLUS, NULL, NULL); 2073 MMIO_DH(0x4264, D_BDW_PLUS, NULL, NULL); 2074 MMIO_DH(0x4268, D_BDW_PLUS, NULL, NULL); 2075 MMIO_DH(0x426c, D_BDW_PLUS, NULL, NULL); 2076 MMIO_DH(0x4270, D_BDW_PLUS, NULL, NULL); 2077 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2078 2079 return 0; 2080 } 2081 2082 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2083 { 2084 struct drm_i915_private *dev_priv = gvt->dev_priv; 2085 int ret; 2086 2087 MMIO_DH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, 2088 intel_vgpu_reg_imr_handler); 2089 2090 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2091 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2092 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2093 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2094 2095 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2096 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2097 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2098 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2099 2100 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2101 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2102 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2103 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2104 2105 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2106 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2107 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2108 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2109 2110 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2111 intel_vgpu_reg_imr_handler); 2112 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2113 intel_vgpu_reg_ier_handler); 2114 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2115 intel_vgpu_reg_iir_handler); 2116 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2117 2118 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2119 intel_vgpu_reg_imr_handler); 2120 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2121 intel_vgpu_reg_ier_handler); 2122 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2123 intel_vgpu_reg_iir_handler); 2124 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2125 2126 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2127 intel_vgpu_reg_imr_handler); 2128 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2129 intel_vgpu_reg_ier_handler); 2130 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2131 intel_vgpu_reg_iir_handler); 2132 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2133 2134 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2135 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2136 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2137 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2138 2139 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2140 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2141 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2142 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2143 2144 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2145 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2146 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2147 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2148 2149 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2150 intel_vgpu_reg_master_irq_handler); 2151 2152 MMIO_D(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2153 MMIO_D(0x1c134, D_BDW_PLUS); 2154 2155 MMIO_D(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2156 MMIO_D(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2157 MMIO_GM(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2158 MMIO_D(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2159 MMIO_D(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2160 MMIO_D(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2161 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2162 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2163 NULL, NULL); 2164 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2165 NULL, NULL); 2166 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2167 ring_timestamp_mmio_read, NULL); 2168 2169 MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS); 2170 2171 #define RING_REG(base) (base + 0x230) 2172 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, NULL); 2173 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2174 #undef RING_REG 2175 2176 #define RING_REG(base) (base + 0x234) 2177 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2178 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, ~0LL, D_BDW_PLUS, NULL, NULL); 2179 #undef RING_REG 2180 2181 #define RING_REG(base) (base + 0x244) 2182 MMIO_RING_D(RING_REG, D_BDW_PLUS); 2183 MMIO_D(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2184 #undef RING_REG 2185 2186 #define RING_REG(base) (base + 0x370) 2187 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2188 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS, 2189 NULL, NULL); 2190 #undef RING_REG 2191 2192 #define RING_REG(base) (base + 0x3a0) 2193 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2194 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2195 #undef RING_REG 2196 2197 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2198 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2199 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2200 MMIO_D(0x1c1d0, D_BDW_PLUS); 2201 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2202 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2203 MMIO_D(0x1c054, D_BDW_PLUS); 2204 2205 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2206 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2207 2208 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2209 2210 #define RING_REG(base) (base + 0x270) 2211 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2212 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2213 #undef RING_REG 2214 2215 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); 2216 MMIO_GM(0x1c080, D_BDW_PLUS, NULL, NULL); 2217 2218 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2219 2220 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW); 2221 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW); 2222 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW); 2223 2224 MMIO_D(WM_MISC, D_BDW); 2225 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 2226 2227 MMIO_D(0x66c00, D_BDW_PLUS); 2228 MMIO_D(0x66c04, D_BDW_PLUS); 2229 2230 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2231 2232 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2233 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2234 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2235 2236 MMIO_D(0xfdc, D_BDW); 2237 MMIO_D(GEN8_ROW_CHICKEN, D_BDW_PLUS); 2238 MMIO_D(GEN7_ROW_CHICKEN2, D_BDW_PLUS); 2239 MMIO_D(GEN8_UCGCTL6, D_BDW_PLUS); 2240 2241 MMIO_D(0xb1f0, D_BDW); 2242 MMIO_D(0xb1c0, D_BDW); 2243 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2244 MMIO_D(0xb100, D_BDW); 2245 MMIO_D(0xb10c, D_BDW); 2246 MMIO_D(0xb110, D_BDW); 2247 2248 MMIO_DH(0x24d0, D_BDW_PLUS, NULL, NULL); 2249 MMIO_DH(0x24d4, D_BDW_PLUS, NULL, NULL); 2250 MMIO_DH(0x24d8, D_BDW_PLUS, NULL, NULL); 2251 MMIO_DH(0x24dc, D_BDW_PLUS, NULL, NULL); 2252 2253 MMIO_D(0x83a4, D_BDW); 2254 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2255 2256 MMIO_D(0x8430, D_BDW); 2257 2258 MMIO_D(0x110000, D_BDW_PLUS); 2259 2260 MMIO_D(0x48400, D_BDW_PLUS); 2261 2262 MMIO_D(0x6e570, D_BDW_PLUS); 2263 MMIO_D(0x65f10, D_BDW_PLUS); 2264 2265 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2266 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2267 MMIO_DFH(0xe180, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2268 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2269 2270 MMIO_D(0x2248, D_BDW); 2271 2272 return 0; 2273 } 2274 2275 static int init_skl_mmio_info(struct intel_gvt *gvt) 2276 { 2277 struct drm_i915_private *dev_priv = gvt->dev_priv; 2278 int ret; 2279 2280 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2281 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2282 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2283 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2284 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2285 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2286 2287 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2288 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2289 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2290 2291 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL); 2292 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write); 2293 2294 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, mailbox_write); 2295 MMIO_D(0xa210, D_SKL_PLUS); 2296 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2297 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2298 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write); 2299 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write); 2300 MMIO_D(0x45504, D_SKL); 2301 MMIO_D(0x45520, D_SKL); 2302 MMIO_D(0x46000, D_SKL); 2303 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write); 2304 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write); 2305 MMIO_D(0x6C040, D_SKL); 2306 MMIO_D(0x6C048, D_SKL); 2307 MMIO_D(0x6C050, D_SKL); 2308 MMIO_D(0x6C044, D_SKL); 2309 MMIO_D(0x6C04C, D_SKL); 2310 MMIO_D(0x6C054, D_SKL); 2311 MMIO_D(0x6c058, D_SKL); 2312 MMIO_D(0x6c05c, D_SKL); 2313 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL); 2314 2315 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write); 2316 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write); 2317 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write); 2318 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write); 2319 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write); 2320 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write); 2321 2322 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write); 2323 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write); 2324 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write); 2325 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write); 2326 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write); 2327 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write); 2328 2329 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write); 2330 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write); 2331 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write); 2332 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write); 2333 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write); 2334 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write); 2335 2336 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2337 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2338 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2339 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2340 2341 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2342 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2343 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2344 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2345 2346 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2347 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2348 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2349 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2350 2351 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL); 2352 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL); 2353 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL); 2354 2355 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2356 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2357 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2358 2359 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2360 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2361 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2362 2363 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2364 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2365 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2366 2367 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2368 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2369 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2370 2371 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL); 2372 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL); 2373 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL); 2374 2375 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL); 2376 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL); 2377 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL); 2378 2379 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL); 2380 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL); 2381 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL); 2382 2383 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL); 2384 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL); 2385 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL); 2386 2387 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2388 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2389 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2390 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2391 2392 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2393 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2394 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2395 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2396 2397 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2398 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2399 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2400 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2401 2402 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL); 2403 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL); 2404 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL); 2405 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL); 2406 2407 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL); 2408 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL); 2409 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL); 2410 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL); 2411 2412 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL); 2413 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL); 2414 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL); 2415 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL); 2416 2417 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL); 2418 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL); 2419 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL); 2420 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL); 2421 2422 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL); 2423 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL); 2424 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL); 2425 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL); 2426 2427 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL); 2428 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL); 2429 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL); 2430 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL); 2431 2432 MMIO_D(0x70380, D_SKL); 2433 MMIO_D(0x71380, D_SKL); 2434 MMIO_D(0x72380, D_SKL); 2435 MMIO_D(0x7039c, D_SKL); 2436 2437 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL); 2438 MMIO_D(0x8f074, D_SKL); 2439 MMIO_D(0x8f004, D_SKL); 2440 MMIO_D(0x8f034, D_SKL); 2441 2442 MMIO_D(0xb11c, D_SKL); 2443 2444 MMIO_D(0x51000, D_SKL); 2445 MMIO_D(0x6c00c, D_SKL); 2446 2447 MMIO_F(0xc800, 0x7f8, 0, 0, 0, D_SKL, NULL, NULL); 2448 MMIO_F(0xb020, 0x80, 0, 0, 0, D_SKL, NULL, NULL); 2449 2450 MMIO_D(0xd08, D_SKL); 2451 MMIO_D(0x20e0, D_SKL); 2452 MMIO_D(0x20ec, D_SKL); 2453 2454 /* TRTT */ 2455 MMIO_D(0x4de0, D_SKL); 2456 MMIO_D(0x4de4, D_SKL); 2457 MMIO_D(0x4de8, D_SKL); 2458 MMIO_D(0x4dec, D_SKL); 2459 MMIO_D(0x4df0, D_SKL); 2460 MMIO_DH(0x4df4, D_SKL, NULL, gen9_trtte_write); 2461 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write); 2462 2463 MMIO_D(0x45008, D_SKL); 2464 2465 MMIO_D(0x46430, D_SKL); 2466 2467 MMIO_D(0x46520, D_SKL); 2468 2469 MMIO_D(0xc403c, D_SKL); 2470 MMIO_D(0xb004, D_SKL); 2471 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2472 2473 MMIO_D(0x65900, D_SKL); 2474 MMIO_D(0x1082c0, D_SKL); 2475 MMIO_D(0x4068, D_SKL); 2476 MMIO_D(0x67054, D_SKL); 2477 MMIO_D(0x6e560, D_SKL); 2478 MMIO_D(0x6e554, D_SKL); 2479 MMIO_D(0x2b20, D_SKL); 2480 MMIO_D(0x65f00, D_SKL); 2481 MMIO_D(0x65f08, D_SKL); 2482 MMIO_D(0x320f0, D_SKL); 2483 2484 MMIO_D(_REG_VCS2_EXCC, D_SKL); 2485 MMIO_D(0x70034, D_SKL); 2486 MMIO_D(0x71034, D_SKL); 2487 MMIO_D(0x72034, D_SKL); 2488 2489 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL); 2490 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL); 2491 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL); 2492 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL); 2493 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL); 2494 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL); 2495 2496 MMIO_D(0x44500, D_SKL); 2497 return 0; 2498 } 2499 2500 /** 2501 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset 2502 * @gvt: GVT device 2503 * @offset: register offset 2504 * 2505 * This function is used to find the MMIO information entry from hash table 2506 * 2507 * Returns: 2508 * pointer to MMIO information entry, NULL if not exists 2509 */ 2510 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 2511 unsigned int offset) 2512 { 2513 struct intel_gvt_mmio_info *e; 2514 2515 WARN_ON(!IS_ALIGNED(offset, 4)); 2516 2517 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 2518 if (e->offset == offset) 2519 return e; 2520 } 2521 return NULL; 2522 } 2523 2524 /** 2525 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2526 * @gvt: GVT device 2527 * 2528 * This function is called at the driver unloading stage, to clean up the MMIO 2529 * information table of GVT device 2530 * 2531 */ 2532 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2533 { 2534 struct hlist_node *tmp; 2535 struct intel_gvt_mmio_info *e; 2536 int i; 2537 2538 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2539 kfree(e); 2540 2541 vfree(gvt->mmio.mmio_attribute); 2542 gvt->mmio.mmio_attribute = NULL; 2543 } 2544 2545 /** 2546 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2547 * @gvt: GVT device 2548 * 2549 * This function is called at the initialization stage, to setup the MMIO 2550 * information table for GVT device 2551 * 2552 * Returns: 2553 * zero on success, negative if failed. 2554 */ 2555 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2556 { 2557 struct intel_gvt_device_info *info = &gvt->device_info; 2558 struct drm_i915_private *dev_priv = gvt->dev_priv; 2559 int ret; 2560 2561 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size); 2562 if (!gvt->mmio.mmio_attribute) 2563 return -ENOMEM; 2564 2565 ret = init_generic_mmio_info(gvt); 2566 if (ret) 2567 goto err; 2568 2569 if (IS_BROADWELL(dev_priv)) { 2570 ret = init_broadwell_mmio_info(gvt); 2571 if (ret) 2572 goto err; 2573 } else if (IS_SKYLAKE(dev_priv)) { 2574 ret = init_broadwell_mmio_info(gvt); 2575 if (ret) 2576 goto err; 2577 ret = init_skl_mmio_info(gvt); 2578 if (ret) 2579 goto err; 2580 } 2581 return 0; 2582 err: 2583 intel_gvt_clean_mmio_info(gvt); 2584 return ret; 2585 } 2586 2587 /** 2588 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 2589 * @gvt: a GVT device 2590 * @offset: register offset 2591 * 2592 */ 2593 void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset) 2594 { 2595 gvt->mmio.mmio_attribute[offset >> 2] |= 2596 F_ACCESSED; 2597 } 2598 2599 /** 2600 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 2601 * @gvt: a GVT device 2602 * @offset: register offset 2603 * 2604 */ 2605 bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt, 2606 unsigned int offset) 2607 { 2608 return gvt->mmio.mmio_attribute[offset >> 2] & 2609 F_CMD_ACCESS; 2610 } 2611 2612 /** 2613 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 2614 * @gvt: a GVT device 2615 * @offset: register offset 2616 * 2617 */ 2618 bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, 2619 unsigned int offset) 2620 { 2621 return gvt->mmio.mmio_attribute[offset >> 2] & 2622 F_UNALIGN; 2623 } 2624 2625 /** 2626 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 2627 * @gvt: a GVT device 2628 * @offset: register offset 2629 * 2630 */ 2631 void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt, 2632 unsigned int offset) 2633 { 2634 gvt->mmio.mmio_attribute[offset >> 2] |= 2635 F_CMD_ACCESSED; 2636 } 2637 2638 /** 2639 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 2640 * @gvt: a GVT device 2641 * @offset: register offset 2642 * 2643 * Returns: 2644 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 2645 * 2646 */ 2647 bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset) 2648 { 2649 return gvt->mmio.mmio_attribute[offset >> 2] & 2650 F_MODE_MASK; 2651 } 2652 2653 /** 2654 * intel_vgpu_default_mmio_read - default MMIO read handler 2655 * @vgpu: a vGPU 2656 * @offset: access offset 2657 * @p_data: data return buffer 2658 * @bytes: access data length 2659 * 2660 * Returns: 2661 * Zero on success, negative error code if failed. 2662 */ 2663 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 2664 void *p_data, unsigned int bytes) 2665 { 2666 read_vreg(vgpu, offset, p_data, bytes); 2667 return 0; 2668 } 2669 2670 /** 2671 * intel_t_default_mmio_write - default MMIO write handler 2672 * @vgpu: a vGPU 2673 * @offset: access offset 2674 * @p_data: write data buffer 2675 * @bytes: access data length 2676 * 2677 * Returns: 2678 * Zero on success, negative error code if failed. 2679 */ 2680 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2681 void *p_data, unsigned int bytes) 2682 { 2683 write_vreg(vgpu, offset, p_data, bytes); 2684 return 0; 2685 } 2686