1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "i915_reg.h" 41 #include "gvt.h" 42 #include "i915_pvinfo.h" 43 #include "intel_mchbar_regs.h" 44 #include "display/bxt_dpio_phy_regs.h" 45 #include "display/intel_display_types.h" 46 #include "display/intel_dmc_regs.h" 47 #include "display/intel_dp_aux_regs.h" 48 #include "display/intel_dpio_phy.h" 49 #include "display/intel_fbc.h" 50 #include "display/intel_fdi_regs.h" 51 #include "display/intel_pps_regs.h" 52 #include "display/intel_psr_regs.h" 53 #include "display/intel_sprite_regs.h" 54 #include "display/skl_watermark_regs.h" 55 #include "display/vlv_dsi_pll_regs.h" 56 #include "gt/intel_gt_regs.h" 57 #include <linux/vmalloc.h> 58 59 /* XXX FIXME i915 has changed PP_XXX definition */ 60 #define PCH_PP_STATUS _MMIO(0xc7200) 61 #define PCH_PP_CONTROL _MMIO(0xc7204) 62 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 63 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 64 #define PCH_PP_DIVISOR _MMIO(0xc7210) 65 66 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 67 { 68 struct drm_i915_private *i915 = gvt->gt->i915; 69 70 if (IS_BROADWELL(i915)) 71 return D_BDW; 72 else if (IS_SKYLAKE(i915)) 73 return D_SKL; 74 else if (IS_KABYLAKE(i915)) 75 return D_KBL; 76 else if (IS_BROXTON(i915)) 77 return D_BXT; 78 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 79 return D_CFL; 80 81 return 0; 82 } 83 84 static bool intel_gvt_match_device(struct intel_gvt *gvt, 85 unsigned long device) 86 { 87 return intel_gvt_get_device_type(gvt) & device; 88 } 89 90 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 91 void *p_data, unsigned int bytes) 92 { 93 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 94 } 95 96 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 97 void *p_data, unsigned int bytes) 98 { 99 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 100 } 101 102 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 103 unsigned int offset) 104 { 105 struct intel_gvt_mmio_info *e; 106 107 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 108 if (e->offset == offset) 109 return e; 110 } 111 return NULL; 112 } 113 114 static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size, 115 u16 flags, u32 addr_mask, u32 ro_mask, u32 device, 116 gvt_mmio_func read, gvt_mmio_func write) 117 { 118 struct intel_gvt_mmio_info *p; 119 u32 start, end, i; 120 121 if (!intel_gvt_match_device(gvt, device)) 122 return 0; 123 124 if (WARN_ON(!IS_ALIGNED(offset, 4))) 125 return -EINVAL; 126 127 start = offset; 128 end = offset + size; 129 130 for (i = start; i < end; i += 4) { 131 p = intel_gvt_find_mmio_info(gvt, i); 132 if (!p) { 133 WARN(1, "assign a handler to a non-tracked mmio %x\n", 134 i); 135 return -ENODEV; 136 } 137 p->ro_mask = ro_mask; 138 gvt->mmio.mmio_attribute[i / 4] = flags; 139 if (read) 140 p->read = read; 141 if (write) 142 p->write = write; 143 } 144 return 0; 145 } 146 147 /** 148 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine 149 * @gvt: a GVT device 150 * @offset: register offset 151 * 152 * Returns: 153 * The engine containing the offset within its mmio page. 154 */ 155 const struct intel_engine_cs * 156 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset) 157 { 158 struct intel_engine_cs *engine; 159 enum intel_engine_id id; 160 161 offset &= ~GENMASK(11, 0); 162 for_each_engine(engine, gvt->gt, id) 163 if (engine->mmio_base == offset) 164 return engine; 165 166 return NULL; 167 } 168 169 #define offset_to_fence_num(offset) \ 170 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 171 172 #define fence_num_to_offset(num) \ 173 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 174 175 176 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 177 { 178 switch (reason) { 179 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 180 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 181 break; 182 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 183 pr_err("Graphics resource is not enough for the guest\n"); 184 break; 185 case GVT_FAILSAFE_GUEST_ERR: 186 pr_err("GVT Internal error for the guest\n"); 187 break; 188 default: 189 break; 190 } 191 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 192 vgpu->failsafe = true; 193 } 194 195 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 196 unsigned int fence_num, void *p_data, unsigned int bytes) 197 { 198 unsigned int max_fence = vgpu_fence_sz(vgpu); 199 200 if (fence_num >= max_fence) { 201 gvt_vgpu_err("access oob fence reg %d/%d\n", 202 fence_num, max_fence); 203 204 /* When guest access oob fence regs without access 205 * pv_info first, we treat guest not supporting GVT, 206 * and we will let vgpu enter failsafe mode. 207 */ 208 if (!vgpu->pv_notified) 209 enter_failsafe_mode(vgpu, 210 GVT_FAILSAFE_UNSUPPORTED_GUEST); 211 212 memset(p_data, 0, bytes); 213 return -EINVAL; 214 } 215 return 0; 216 } 217 218 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 219 unsigned int offset, void *p_data, unsigned int bytes) 220 { 221 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; 222 223 if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) { 224 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) 225 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); 226 else if (!ips) 227 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); 228 else { 229 /* All engines must be enabled together for vGPU, 230 * since we don't know which engine the ppgtt will 231 * bind to when shadowing. 232 */ 233 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", 234 ips); 235 return -EINVAL; 236 } 237 } 238 239 write_vreg(vgpu, offset, p_data, bytes); 240 return 0; 241 } 242 243 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 244 void *p_data, unsigned int bytes) 245 { 246 int ret; 247 248 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 249 p_data, bytes); 250 if (ret) 251 return ret; 252 read_vreg(vgpu, off, p_data, bytes); 253 return 0; 254 } 255 256 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 257 void *p_data, unsigned int bytes) 258 { 259 struct intel_gvt *gvt = vgpu->gvt; 260 unsigned int fence_num = offset_to_fence_num(off); 261 int ret; 262 263 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 264 if (ret) 265 return ret; 266 write_vreg(vgpu, off, p_data, bytes); 267 268 mmio_hw_access_pre(gvt->gt); 269 intel_vgpu_write_fence(vgpu, fence_num, 270 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 271 mmio_hw_access_post(gvt->gt); 272 return 0; 273 } 274 275 #define CALC_MODE_MASK_REG(old, new) \ 276 (((new) & GENMASK(31, 16)) \ 277 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 278 | ((new) & ((new) >> 16)))) 279 280 static int mul_force_wake_write(struct intel_vgpu *vgpu, 281 unsigned int offset, void *p_data, unsigned int bytes) 282 { 283 u32 old, new; 284 u32 ack_reg_offset; 285 286 old = vgpu_vreg(vgpu, offset); 287 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 288 289 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) { 290 switch (offset) { 291 case FORCEWAKE_RENDER_GEN9_REG: 292 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 293 break; 294 case FORCEWAKE_GT_GEN9_REG: 295 ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG; 296 break; 297 case FORCEWAKE_MEDIA_GEN9_REG: 298 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 299 break; 300 default: 301 /*should not hit here*/ 302 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 303 return -EINVAL; 304 } 305 } else { 306 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 307 } 308 309 vgpu_vreg(vgpu, offset) = new; 310 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 311 return 0; 312 } 313 314 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 315 void *p_data, unsigned int bytes) 316 { 317 intel_engine_mask_t engine_mask = 0; 318 u32 data; 319 320 write_vreg(vgpu, offset, p_data, bytes); 321 data = vgpu_vreg(vgpu, offset); 322 323 if (data & GEN6_GRDOM_FULL) { 324 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 325 engine_mask = ALL_ENGINES; 326 } else { 327 if (data & GEN6_GRDOM_RENDER) { 328 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 329 engine_mask |= BIT(RCS0); 330 } 331 if (data & GEN6_GRDOM_MEDIA) { 332 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 333 engine_mask |= BIT(VCS0); 334 } 335 if (data & GEN6_GRDOM_BLT) { 336 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 337 engine_mask |= BIT(BCS0); 338 } 339 if (data & GEN6_GRDOM_VECS) { 340 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 341 engine_mask |= BIT(VECS0); 342 } 343 if (data & GEN8_GRDOM_MEDIA2) { 344 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 345 engine_mask |= BIT(VCS1); 346 } 347 if (data & GEN9_GRDOM_GUC) { 348 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); 349 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; 350 } 351 engine_mask &= vgpu->gvt->gt->info.engine_mask; 352 } 353 354 /* vgpu_lock already hold by emulate mmio r/w */ 355 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 356 357 /* sw will wait for the device to ack the reset request */ 358 vgpu_vreg(vgpu, offset) = 0; 359 360 return 0; 361 } 362 363 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 364 void *p_data, unsigned int bytes) 365 { 366 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 367 } 368 369 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 370 void *p_data, unsigned int bytes) 371 { 372 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 373 } 374 375 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 376 unsigned int offset, void *p_data, unsigned int bytes) 377 { 378 write_vreg(vgpu, offset, p_data, bytes); 379 380 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 381 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 382 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 383 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 384 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 385 386 } else 387 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 388 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 389 | PP_CYCLE_DELAY_ACTIVE); 390 return 0; 391 } 392 393 static int transconf_mmio_write(struct intel_vgpu *vgpu, 394 unsigned int offset, void *p_data, unsigned int bytes) 395 { 396 write_vreg(vgpu, offset, p_data, bytes); 397 398 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 399 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 400 else 401 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 402 return 0; 403 } 404 405 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 406 void *p_data, unsigned int bytes) 407 { 408 write_vreg(vgpu, offset, p_data, bytes); 409 410 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 411 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 412 else 413 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 414 415 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 416 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 417 else 418 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 419 420 return 0; 421 } 422 423 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 424 void *p_data, unsigned int bytes) 425 { 426 switch (offset) { 427 case 0xe651c: 428 case 0xe661c: 429 case 0xe671c: 430 case 0xe681c: 431 vgpu_vreg(vgpu, offset) = 1 << 17; 432 break; 433 case 0xe6c04: 434 vgpu_vreg(vgpu, offset) = 0x3; 435 break; 436 case 0xe6e1c: 437 vgpu_vreg(vgpu, offset) = 0x2f << 16; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 read_vreg(vgpu, offset, p_data, bytes); 444 return 0; 445 } 446 447 /* 448 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to 449 * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on 450 * setup_virtual_dp_monitor(). 451 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled 452 * DPLL. Later guest driver may setup a different DPLLx when setting mode. 453 * So the correct sequence to find DP stream clock is: 454 * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x. 455 * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate. 456 * Then Refresh rate then can be calculated based on follow equations: 457 * Pixel clock = h_total * v_total * refresh_rate 458 * stream clock = Pixel clock 459 * ls_clk = DP bitrate 460 * Link M/N = strm_clk / ls_clk 461 */ 462 463 static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 464 { 465 u32 dp_br = 0; 466 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); 467 468 switch (ddi_pll_sel) { 469 case PORT_CLK_SEL_LCPLL_2700: 470 dp_br = 270000 * 2; 471 break; 472 case PORT_CLK_SEL_LCPLL_1350: 473 dp_br = 135000 * 2; 474 break; 475 case PORT_CLK_SEL_LCPLL_810: 476 dp_br = 81000 * 2; 477 break; 478 case PORT_CLK_SEL_SPLL: 479 { 480 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { 481 case SPLL_FREQ_810MHz: 482 dp_br = 81000 * 2; 483 break; 484 case SPLL_FREQ_1350MHz: 485 dp_br = 135000 * 2; 486 break; 487 case SPLL_FREQ_2700MHz: 488 dp_br = 270000 * 2; 489 break; 490 default: 491 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n", 492 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); 493 break; 494 } 495 break; 496 } 497 case PORT_CLK_SEL_WRPLL1: 498 case PORT_CLK_SEL_WRPLL2: 499 { 500 u32 wrpll_ctl; 501 int refclk, n, p, r; 502 503 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1) 504 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); 505 else 506 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2)); 507 508 switch (wrpll_ctl & WRPLL_REF_MASK) { 509 case WRPLL_REF_PCH_SSC: 510 refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc; 511 break; 512 case WRPLL_REF_LCPLL: 513 refclk = 2700000; 514 break; 515 default: 516 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n", 517 vgpu->id, port_name(port), wrpll_ctl); 518 goto out; 519 } 520 521 r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK; 522 p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 523 n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 524 525 dp_br = (refclk * n / 10) / (p * r) * 2; 526 break; 527 } 528 default: 529 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", 530 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port))); 531 break; 532 } 533 534 out: 535 return dp_br; 536 } 537 538 static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 539 { 540 u32 dp_br = 0; 541 int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc; 542 enum dpio_phy phy = DPIO_PHY0; 543 enum dpio_channel ch = DPIO_CH0; 544 struct dpll clock = {}; 545 u32 temp; 546 547 /* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */ 548 switch (port) { 549 case PORT_A: 550 phy = DPIO_PHY1; 551 ch = DPIO_CH0; 552 break; 553 case PORT_B: 554 phy = DPIO_PHY0; 555 ch = DPIO_CH0; 556 break; 557 case PORT_C: 558 phy = DPIO_PHY0; 559 ch = DPIO_CH1; 560 break; 561 default: 562 gvt_dbg_dpy("vgpu-%d no PHY for PORT_%c\n", vgpu->id, port_name(port)); 563 goto out; 564 } 565 566 temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)); 567 if (!(temp & PORT_PLL_ENABLE) || !(temp & PORT_PLL_LOCK)) { 568 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n", 569 vgpu->id, port_name(port), temp); 570 goto out; 571 } 572 573 clock.m1 = 2; 574 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, 575 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22; 576 if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE) 577 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, 578 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2))); 579 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, 580 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1))); 581 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, 582 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); 583 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, 584 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); 585 clock.m = clock.m1 * clock.m2; 586 clock.p = clock.p1 * clock.p2 * 5; 587 588 if (clock.n == 0 || clock.p == 0) { 589 gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port)); 590 goto out; 591 } 592 593 clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22); 594 clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p); 595 596 dp_br = clock.dot; 597 598 out: 599 return dp_br; 600 } 601 602 static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 603 { 604 u32 dp_br = 0; 605 enum intel_dpll_id dpll_id = DPLL_ID_SKL_DPLL0; 606 607 /* Find the enabled DPLL for the DDI/PORT */ 608 if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) && 609 (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) { 610 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) & 611 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 612 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 613 } else { 614 gvt_dbg_dpy("vgpu-%d DPLL for PORT_%c isn't turned on\n", 615 vgpu->id, port_name(port)); 616 return dp_br; 617 } 618 619 /* Find PLL output frequency from correct DPLL, and get bir rate */ 620 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) & 621 DPLL_CTRL1_LINK_RATE_MASK(dpll_id)) >> 622 DPLL_CTRL1_LINK_RATE_SHIFT(dpll_id)) { 623 case DPLL_CTRL1_LINK_RATE_810: 624 dp_br = 81000 * 2; 625 break; 626 case DPLL_CTRL1_LINK_RATE_1080: 627 dp_br = 108000 * 2; 628 break; 629 case DPLL_CTRL1_LINK_RATE_1350: 630 dp_br = 135000 * 2; 631 break; 632 case DPLL_CTRL1_LINK_RATE_1620: 633 dp_br = 162000 * 2; 634 break; 635 case DPLL_CTRL1_LINK_RATE_2160: 636 dp_br = 216000 * 2; 637 break; 638 case DPLL_CTRL1_LINK_RATE_2700: 639 dp_br = 270000 * 2; 640 break; 641 default: 642 dp_br = 0; 643 gvt_dbg_dpy("vgpu-%d PORT_%c fail to get DPLL-%d freq\n", 644 vgpu->id, port_name(port), dpll_id); 645 } 646 647 return dp_br; 648 } 649 650 static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) 651 { 652 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 653 enum port port; 654 u32 dp_br, link_m, link_n, htotal, vtotal; 655 656 /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */ 657 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) & 658 TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 659 if (port != PORT_B && port != PORT_D) { 660 gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port)); 661 return; 662 } 663 664 /* Calculate DP bitrate from PLL */ 665 if (IS_BROADWELL(dev_priv)) 666 dp_br = bdw_vgpu_get_dp_bitrate(vgpu, port); 667 else if (IS_BROXTON(dev_priv)) 668 dp_br = bxt_vgpu_get_dp_bitrate(vgpu, port); 669 else 670 dp_br = skl_vgpu_get_dp_bitrate(vgpu, port); 671 672 /* Get DP link symbol clock M/N */ 673 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)); 674 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)); 675 676 /* Get H/V total from transcoder timing */ 677 htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); 678 vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); 679 680 if (dp_br && link_n && htotal && vtotal) { 681 u64 pixel_clk = 0; 682 u32 new_rate = 0; 683 u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k); 684 685 /* Calcuate pixel clock by (ls_clk * M / N) */ 686 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); 687 pixel_clk *= MSEC_PER_SEC; 688 689 /* Calcuate refresh rate by (pixel_clk / (h_total * v_total)) */ 690 new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1)); 691 692 if (*old_rate != new_rate) 693 *old_rate = new_rate; 694 695 gvt_dbg_dpy("vgpu-%d PIPE_%c refresh rate updated to %d\n", 696 vgpu->id, pipe_name(PIPE_A), new_rate); 697 } 698 } 699 700 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 701 void *p_data, unsigned int bytes) 702 { 703 u32 data; 704 705 write_vreg(vgpu, offset, p_data, bytes); 706 data = vgpu_vreg(vgpu, offset); 707 708 if (data & TRANSCONF_ENABLE) { 709 vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE; 710 vgpu_update_refresh_rate(vgpu); 711 vgpu_update_vblank_emulation(vgpu, true); 712 } else { 713 vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE; 714 vgpu_update_vblank_emulation(vgpu, false); 715 } 716 return 0; 717 } 718 719 /* sorted in ascending order */ 720 static i915_reg_t force_nonpriv_white_list[] = { 721 _MMIO(0xd80), 722 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 723 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 724 CL_PRIMITIVES_COUNT, //_MMIO(0x2340) 725 PS_INVOCATION_COUNT, //_MMIO(0x2348) 726 PS_DEPTH_COUNT, //_MMIO(0x2350) 727 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 728 _MMIO(0x2690), 729 _MMIO(0x2694), 730 _MMIO(0x2698), 731 _MMIO(0x2754), 732 _MMIO(0x28a0), 733 _MMIO(0x4de0), 734 _MMIO(0x4de4), 735 _MMIO(0x4dfc), 736 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 737 _MMIO(0x7014), 738 HDC_CHICKEN0,//_MMIO(0x7300) 739 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 740 _MMIO(0x7700), 741 _MMIO(0x7704), 742 _MMIO(0x7708), 743 _MMIO(0x770c), 744 _MMIO(0x83a8), 745 _MMIO(0xb110), 746 _MMIO(0xb118), 747 _MMIO(0xe100), 748 _MMIO(0xe18c), 749 _MMIO(0xe48c), 750 _MMIO(0xe5f4), 751 _MMIO(0x64844), 752 }; 753 754 /* a simple bsearch */ 755 static inline bool in_whitelist(u32 reg) 756 { 757 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 758 i915_reg_t *array = force_nonpriv_white_list; 759 760 while (left < right) { 761 int mid = (left + right)/2; 762 763 if (reg > array[mid].reg) 764 left = mid + 1; 765 else if (reg < array[mid].reg) 766 right = mid; 767 else 768 return true; 769 } 770 return false; 771 } 772 773 static int force_nonpriv_write(struct intel_vgpu *vgpu, 774 unsigned int offset, void *p_data, unsigned int bytes) 775 { 776 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2); 777 const struct intel_engine_cs *engine = 778 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 779 780 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) { 781 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 782 vgpu->id, offset, bytes); 783 return -EINVAL; 784 } 785 786 if (!in_whitelist(reg_nonpriv) && 787 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) { 788 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 789 vgpu->id, reg_nonpriv, offset); 790 } else 791 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 792 793 return 0; 794 } 795 796 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 797 void *p_data, unsigned int bytes) 798 { 799 write_vreg(vgpu, offset, p_data, bytes); 800 801 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 802 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 803 } else { 804 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 805 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 806 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 807 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 808 } 809 return 0; 810 } 811 812 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 813 unsigned int offset, void *p_data, unsigned int bytes) 814 { 815 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 816 return 0; 817 } 818 819 #define FDI_LINK_TRAIN_PATTERN1 0 820 #define FDI_LINK_TRAIN_PATTERN2 1 821 822 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 823 { 824 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 825 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 826 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 827 828 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 829 (rx_ctl & FDI_RX_ENABLE) && 830 (rx_ctl & FDI_AUTO_TRAINING) && 831 (tx_ctl & DP_TP_CTL_ENABLE) && 832 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 833 return 1; 834 else 835 return 0; 836 } 837 838 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 839 enum pipe pipe, unsigned int train_pattern) 840 { 841 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 842 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 843 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 844 unsigned int fdi_iir_check_bits; 845 846 fdi_rx_imr = FDI_RX_IMR(pipe); 847 fdi_tx_ctl = FDI_TX_CTL(pipe); 848 fdi_rx_ctl = FDI_RX_CTL(pipe); 849 850 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 851 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 852 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 853 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 854 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 855 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 856 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 857 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 858 } else { 859 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 860 return -EINVAL; 861 } 862 863 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 864 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 865 866 /* If imr bit has been masked */ 867 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 868 return 0; 869 870 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 871 == fdi_tx_check_bits) 872 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 873 == fdi_rx_check_bits)) 874 return 1; 875 else 876 return 0; 877 } 878 879 #define INVALID_INDEX (~0U) 880 881 static unsigned int calc_index(unsigned int offset, unsigned int start, 882 unsigned int next, unsigned int end, i915_reg_t i915_end) 883 { 884 unsigned int range = next - start; 885 886 if (!end) 887 end = i915_mmio_reg_offset(i915_end); 888 if (offset < start || offset > end) 889 return INVALID_INDEX; 890 offset -= start; 891 return offset / range; 892 } 893 894 #define FDI_RX_CTL_TO_PIPE(offset) \ 895 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 896 897 #define FDI_TX_CTL_TO_PIPE(offset) \ 898 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 899 900 #define FDI_RX_IMR_TO_PIPE(offset) \ 901 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 902 903 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 904 unsigned int offset, void *p_data, unsigned int bytes) 905 { 906 i915_reg_t fdi_rx_iir; 907 unsigned int index; 908 int ret; 909 910 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 911 index = FDI_RX_CTL_TO_PIPE(offset); 912 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 913 index = FDI_TX_CTL_TO_PIPE(offset); 914 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 915 index = FDI_RX_IMR_TO_PIPE(offset); 916 else { 917 gvt_vgpu_err("Unsupported registers %x\n", offset); 918 return -EINVAL; 919 } 920 921 write_vreg(vgpu, offset, p_data, bytes); 922 923 fdi_rx_iir = FDI_RX_IIR(index); 924 925 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 926 if (ret < 0) 927 return ret; 928 if (ret) 929 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 930 931 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 932 if (ret < 0) 933 return ret; 934 if (ret) 935 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 936 937 if (offset == _FDI_RXA_CTL) 938 if (fdi_auto_training_started(vgpu)) 939 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 940 DP_TP_STATUS_AUTOTRAIN_DONE; 941 return 0; 942 } 943 944 #define DP_TP_CTL_TO_PORT(offset) \ 945 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 946 947 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 948 void *p_data, unsigned int bytes) 949 { 950 i915_reg_t status_reg; 951 unsigned int index; 952 u32 data; 953 954 write_vreg(vgpu, offset, p_data, bytes); 955 956 index = DP_TP_CTL_TO_PORT(offset); 957 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 958 if (data == 0x2) { 959 status_reg = DP_TP_STATUS(index); 960 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 961 } 962 return 0; 963 } 964 965 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 966 unsigned int offset, void *p_data, unsigned int bytes) 967 { 968 u32 reg_val; 969 u32 sticky_mask; 970 971 reg_val = *((u32 *)p_data); 972 sticky_mask = GENMASK(27, 26) | (1 << 24); 973 974 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 975 (vgpu_vreg(vgpu, offset) & sticky_mask); 976 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 977 return 0; 978 } 979 980 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 981 unsigned int offset, void *p_data, unsigned int bytes) 982 { 983 u32 data; 984 985 write_vreg(vgpu, offset, p_data, bytes); 986 data = vgpu_vreg(vgpu, offset); 987 988 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 989 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 990 return 0; 991 } 992 993 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 994 unsigned int offset, void *p_data, unsigned int bytes) 995 { 996 u32 data; 997 998 write_vreg(vgpu, offset, p_data, bytes); 999 data = vgpu_vreg(vgpu, offset); 1000 1001 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 1002 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 1003 else 1004 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 1005 return 0; 1006 } 1007 1008 #define DSPSURF_TO_PIPE(offset) \ 1009 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 1010 1011 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1012 void *p_data, unsigned int bytes) 1013 { 1014 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1015 u32 pipe = DSPSURF_TO_PIPE(offset); 1016 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); 1017 1018 write_vreg(vgpu, offset, p_data, bytes); 1019 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1020 1021 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 1022 1023 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) 1024 intel_vgpu_trigger_virtual_event(vgpu, event); 1025 else 1026 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1027 1028 return 0; 1029 } 1030 1031 #define SPRSURF_TO_PIPE(offset) \ 1032 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 1033 1034 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1035 void *p_data, unsigned int bytes) 1036 { 1037 u32 pipe = SPRSURF_TO_PIPE(offset); 1038 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0); 1039 1040 write_vreg(vgpu, offset, p_data, bytes); 1041 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1042 1043 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) 1044 intel_vgpu_trigger_virtual_event(vgpu, event); 1045 else 1046 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1047 1048 return 0; 1049 } 1050 1051 static int reg50080_mmio_write(struct intel_vgpu *vgpu, 1052 unsigned int offset, void *p_data, 1053 unsigned int bytes) 1054 { 1055 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1056 enum pipe pipe = REG_50080_TO_PIPE(offset); 1057 enum plane_id plane = REG_50080_TO_PLANE(offset); 1058 int event = SKL_FLIP_EVENT(pipe, plane); 1059 1060 write_vreg(vgpu, offset, p_data, bytes); 1061 if (plane == PLANE_PRIMARY) { 1062 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1063 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 1064 } else { 1065 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1066 } 1067 1068 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) 1069 intel_vgpu_trigger_virtual_event(vgpu, event); 1070 else 1071 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1072 1073 return 0; 1074 } 1075 1076 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 1077 unsigned int reg) 1078 { 1079 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1080 enum intel_gvt_event_type event; 1081 1082 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) 1083 event = AUX_CHANNEL_A; 1084 else if (reg == _PCH_DPB_AUX_CH_CTL || 1085 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) 1086 event = AUX_CHANNEL_B; 1087 else if (reg == _PCH_DPC_AUX_CH_CTL || 1088 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) 1089 event = AUX_CHANNEL_C; 1090 else if (reg == _PCH_DPD_AUX_CH_CTL || 1091 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) 1092 event = AUX_CHANNEL_D; 1093 else { 1094 drm_WARN_ON(&dev_priv->drm, true); 1095 return -EINVAL; 1096 } 1097 1098 intel_vgpu_trigger_virtual_event(vgpu, event); 1099 return 0; 1100 } 1101 1102 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 1103 unsigned int reg, int len, bool data_valid) 1104 { 1105 /* mark transaction done */ 1106 value |= DP_AUX_CH_CTL_DONE; 1107 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 1108 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 1109 1110 if (data_valid) 1111 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 1112 else 1113 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 1114 1115 /* message size */ 1116 value &= ~(0xf << 20); 1117 value |= (len << 20); 1118 vgpu_vreg(vgpu, reg) = value; 1119 1120 if (value & DP_AUX_CH_CTL_INTERRUPT) 1121 return trigger_aux_channel_interrupt(vgpu, reg); 1122 return 0; 1123 } 1124 1125 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 1126 u8 t) 1127 { 1128 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 1129 /* training pattern 1 for CR */ 1130 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 1131 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 1132 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 1133 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 1134 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 1135 DPCD_TRAINING_PATTERN_2) { 1136 /* training pattern 2 for EQ */ 1137 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 1138 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 1139 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 1140 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 1141 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 1142 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 1143 /* set INTERLANE_ALIGN_DONE */ 1144 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 1145 DPCD_INTERLANE_ALIGN_DONE; 1146 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 1147 DPCD_LINK_TRAINING_DISABLED) { 1148 /* finish link training */ 1149 /* set sink status as synchronized */ 1150 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 1151 } 1152 } 1153 1154 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 1155 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 1156 1157 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 1158 1159 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 1160 1161 #define dpy_is_valid_port(port) \ 1162 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 1163 1164 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 1165 unsigned int offset, void *p_data, unsigned int bytes) 1166 { 1167 struct intel_vgpu_display *display = &vgpu->display; 1168 int msg, addr, ctrl, op, len; 1169 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 1170 struct intel_vgpu_dpcd_data *dpcd = NULL; 1171 struct intel_vgpu_port *port = NULL; 1172 u32 data; 1173 1174 if (!dpy_is_valid_port(port_index)) { 1175 gvt_vgpu_err("Unsupported DP port access!\n"); 1176 return 0; 1177 } 1178 1179 write_vreg(vgpu, offset, p_data, bytes); 1180 data = vgpu_vreg(vgpu, offset); 1181 1182 if ((GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) 1183 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 1184 /* SKL DPB/C/D aux ctl register changed */ 1185 return 0; 1186 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) && 1187 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 1188 /* write to the data registers */ 1189 return 0; 1190 } 1191 1192 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 1193 /* just want to clear the sticky bits */ 1194 vgpu_vreg(vgpu, offset) = 0; 1195 return 0; 1196 } 1197 1198 port = &display->ports[port_index]; 1199 dpcd = port->dpcd; 1200 1201 /* read out message from DATA1 register */ 1202 msg = vgpu_vreg(vgpu, offset + 4); 1203 addr = (msg >> 8) & 0xffff; 1204 ctrl = (msg >> 24) & 0xff; 1205 len = msg & 0xff; 1206 op = ctrl >> 4; 1207 1208 if (op == GVT_AUX_NATIVE_WRITE) { 1209 int t; 1210 u8 buf[16]; 1211 1212 if ((addr + len + 1) >= DPCD_SIZE) { 1213 /* 1214 * Write request exceeds what we supported, 1215 * DCPD spec: When a Source Device is writing a DPCD 1216 * address not supported by the Sink Device, the Sink 1217 * Device shall reply with AUX NACK and “M” equal to 1218 * zero. 1219 */ 1220 1221 /* NAK the write */ 1222 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 1223 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 1224 return 0; 1225 } 1226 1227 /* 1228 * Write request format: Headr (command + address + size) occupies 1229 * 4 bytes, followed by (len + 1) bytes of data. See details at 1230 * intel_dp_aux_transfer(). 1231 */ 1232 if ((len + 1 + 4) > AUX_BURST_SIZE) { 1233 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1234 return -EINVAL; 1235 } 1236 1237 /* unpack data from vreg to buf */ 1238 for (t = 0; t < 4; t++) { 1239 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 1240 1241 buf[t * 4] = (r >> 24) & 0xff; 1242 buf[t * 4 + 1] = (r >> 16) & 0xff; 1243 buf[t * 4 + 2] = (r >> 8) & 0xff; 1244 buf[t * 4 + 3] = r & 0xff; 1245 } 1246 1247 /* write to virtual DPCD */ 1248 if (dpcd && dpcd->data_valid) { 1249 for (t = 0; t <= len; t++) { 1250 int p = addr + t; 1251 1252 dpcd->data[p] = buf[t]; 1253 /* check for link training */ 1254 if (p == DPCD_TRAINING_PATTERN_SET) 1255 dp_aux_ch_ctl_link_training(dpcd, 1256 buf[t]); 1257 } 1258 } 1259 1260 /* ACK the write */ 1261 vgpu_vreg(vgpu, offset + 4) = 0; 1262 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 1263 dpcd && dpcd->data_valid); 1264 return 0; 1265 } 1266 1267 if (op == GVT_AUX_NATIVE_READ) { 1268 int idx, i, ret = 0; 1269 1270 if ((addr + len + 1) >= DPCD_SIZE) { 1271 /* 1272 * read request exceeds what we supported 1273 * DPCD spec: A Sink Device receiving a Native AUX CH 1274 * read request for an unsupported DPCD address must 1275 * reply with an AUX ACK and read data set equal to 1276 * zero instead of replying with AUX NACK. 1277 */ 1278 1279 /* ACK the READ*/ 1280 vgpu_vreg(vgpu, offset + 4) = 0; 1281 vgpu_vreg(vgpu, offset + 8) = 0; 1282 vgpu_vreg(vgpu, offset + 12) = 0; 1283 vgpu_vreg(vgpu, offset + 16) = 0; 1284 vgpu_vreg(vgpu, offset + 20) = 0; 1285 1286 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1287 true); 1288 return 0; 1289 } 1290 1291 for (idx = 1; idx <= 5; idx++) { 1292 /* clear the data registers */ 1293 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 1294 } 1295 1296 /* 1297 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1298 */ 1299 if ((len + 2) > AUX_BURST_SIZE) { 1300 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1301 return -EINVAL; 1302 } 1303 1304 /* read from virtual DPCD to vreg */ 1305 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1306 if (dpcd && dpcd->data_valid) { 1307 for (i = 1; i <= (len + 1); i++) { 1308 int t; 1309 1310 t = dpcd->data[addr + i - 1]; 1311 t <<= (24 - 8 * (i % 4)); 1312 ret |= t; 1313 1314 if ((i % 4 == 3) || (i == (len + 1))) { 1315 vgpu_vreg(vgpu, offset + 1316 (i / 4 + 1) * 4) = ret; 1317 ret = 0; 1318 } 1319 } 1320 } 1321 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1322 dpcd && dpcd->data_valid); 1323 return 0; 1324 } 1325 1326 /* i2c transaction starts */ 1327 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1328 1329 if (data & DP_AUX_CH_CTL_INTERRUPT) 1330 trigger_aux_channel_interrupt(vgpu, offset); 1331 return 0; 1332 } 1333 1334 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1335 void *p_data, unsigned int bytes) 1336 { 1337 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1338 write_vreg(vgpu, offset, p_data, bytes); 1339 return 0; 1340 } 1341 1342 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1343 void *p_data, unsigned int bytes) 1344 { 1345 bool vga_disable; 1346 1347 write_vreg(vgpu, offset, p_data, bytes); 1348 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1349 1350 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1351 vga_disable ? "Disable" : "Enable"); 1352 return 0; 1353 } 1354 1355 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1356 unsigned int sbi_offset) 1357 { 1358 struct intel_vgpu_display *display = &vgpu->display; 1359 int num = display->sbi.number; 1360 int i; 1361 1362 for (i = 0; i < num; ++i) 1363 if (display->sbi.registers[i].offset == sbi_offset) 1364 break; 1365 1366 if (i == num) 1367 return 0; 1368 1369 return display->sbi.registers[i].value; 1370 } 1371 1372 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1373 unsigned int offset, u32 value) 1374 { 1375 struct intel_vgpu_display *display = &vgpu->display; 1376 int num = display->sbi.number; 1377 int i; 1378 1379 for (i = 0; i < num; ++i) { 1380 if (display->sbi.registers[i].offset == offset) 1381 break; 1382 } 1383 1384 if (i == num) { 1385 if (num == SBI_REG_MAX) { 1386 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1387 return; 1388 } 1389 display->sbi.number++; 1390 } 1391 1392 display->sbi.registers[i].offset = offset; 1393 display->sbi.registers[i].value = value; 1394 } 1395 1396 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1397 void *p_data, unsigned int bytes) 1398 { 1399 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1400 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1401 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1402 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1403 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1404 sbi_offset); 1405 } 1406 read_vreg(vgpu, offset, p_data, bytes); 1407 return 0; 1408 } 1409 1410 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1411 void *p_data, unsigned int bytes) 1412 { 1413 u32 data; 1414 1415 write_vreg(vgpu, offset, p_data, bytes); 1416 data = vgpu_vreg(vgpu, offset); 1417 1418 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1419 data |= SBI_READY; 1420 1421 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1422 data |= SBI_RESPONSE_SUCCESS; 1423 1424 vgpu_vreg(vgpu, offset) = data; 1425 1426 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1427 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1428 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1429 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1430 1431 write_virtual_sbi_register(vgpu, sbi_offset, 1432 vgpu_vreg_t(vgpu, SBI_DATA)); 1433 } 1434 return 0; 1435 } 1436 1437 #define _vgtif_reg(x) \ 1438 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1439 1440 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1441 void *p_data, unsigned int bytes) 1442 { 1443 bool invalid_read = false; 1444 1445 read_vreg(vgpu, offset, p_data, bytes); 1446 1447 switch (offset) { 1448 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1449 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1450 invalid_read = true; 1451 break; 1452 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1453 _vgtif_reg(avail_rs.fence_num): 1454 if (offset + bytes > 1455 _vgtif_reg(avail_rs.fence_num) + 4) 1456 invalid_read = true; 1457 break; 1458 case 0x78010: /* vgt_caps */ 1459 case 0x7881c: 1460 break; 1461 default: 1462 invalid_read = true; 1463 break; 1464 } 1465 if (invalid_read) 1466 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1467 offset, bytes, *(u32 *)p_data); 1468 vgpu->pv_notified = true; 1469 return 0; 1470 } 1471 1472 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1473 { 1474 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1475 struct intel_vgpu_mm *mm; 1476 u64 *pdps; 1477 1478 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1479 1480 switch (notification) { 1481 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1482 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1483 fallthrough; 1484 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1485 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1486 return PTR_ERR_OR_ZERO(mm); 1487 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1488 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1489 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1490 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1491 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1492 case 1: /* Remove this in guest driver. */ 1493 break; 1494 default: 1495 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1496 } 1497 return 0; 1498 } 1499 1500 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1501 { 1502 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj; 1503 char *env[3] = {NULL, NULL, NULL}; 1504 char vmid_str[20]; 1505 char display_ready_str[20]; 1506 1507 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1508 env[0] = display_ready_str; 1509 1510 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1511 env[1] = vmid_str; 1512 1513 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1514 } 1515 1516 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1517 void *p_data, unsigned int bytes) 1518 { 1519 u32 data = *(u32 *)p_data; 1520 bool invalid_write = false; 1521 1522 switch (offset) { 1523 case _vgtif_reg(display_ready): 1524 send_display_ready_uevent(vgpu, data ? 1 : 0); 1525 break; 1526 case _vgtif_reg(g2v_notify): 1527 handle_g2v_notification(vgpu, data); 1528 break; 1529 /* add xhot and yhot to handled list to avoid error log */ 1530 case _vgtif_reg(cursor_x_hot): 1531 case _vgtif_reg(cursor_y_hot): 1532 case _vgtif_reg(pdp[0].lo): 1533 case _vgtif_reg(pdp[0].hi): 1534 case _vgtif_reg(pdp[1].lo): 1535 case _vgtif_reg(pdp[1].hi): 1536 case _vgtif_reg(pdp[2].lo): 1537 case _vgtif_reg(pdp[2].hi): 1538 case _vgtif_reg(pdp[3].lo): 1539 case _vgtif_reg(pdp[3].hi): 1540 case _vgtif_reg(execlist_context_descriptor_lo): 1541 case _vgtif_reg(execlist_context_descriptor_hi): 1542 break; 1543 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1544 invalid_write = true; 1545 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1546 break; 1547 default: 1548 invalid_write = true; 1549 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1550 offset, bytes, data); 1551 break; 1552 } 1553 1554 if (!invalid_write) 1555 write_vreg(vgpu, offset, p_data, bytes); 1556 1557 return 0; 1558 } 1559 1560 static int pf_write(struct intel_vgpu *vgpu, 1561 unsigned int offset, void *p_data, unsigned int bytes) 1562 { 1563 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1564 u32 val = *(u32 *)p_data; 1565 1566 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1567 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1568 offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) { 1569 drm_WARN_ONCE(&i915->drm, true, 1570 "VM(%d): guest is trying to scaling a plane\n", 1571 vgpu->id); 1572 return 0; 1573 } 1574 1575 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1576 } 1577 1578 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1579 unsigned int offset, void *p_data, unsigned int bytes) 1580 { 1581 write_vreg(vgpu, offset, p_data, bytes); 1582 1583 if (vgpu_vreg(vgpu, offset) & 1584 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL)) 1585 vgpu_vreg(vgpu, offset) |= 1586 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1587 else 1588 vgpu_vreg(vgpu, offset) &= 1589 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1590 return 0; 1591 } 1592 1593 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1594 unsigned int offset, void *p_data, unsigned int bytes) 1595 { 1596 write_vreg(vgpu, offset, p_data, bytes); 1597 1598 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1599 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1600 else 1601 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1602 1603 return 0; 1604 } 1605 1606 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1607 unsigned int offset, void *p_data, unsigned int bytes) 1608 { 1609 write_vreg(vgpu, offset, p_data, bytes); 1610 1611 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1612 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1613 return 0; 1614 } 1615 1616 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1617 void *p_data, unsigned int bytes) 1618 { 1619 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1620 u32 mode; 1621 1622 write_vreg(vgpu, offset, p_data, bytes); 1623 mode = vgpu_vreg(vgpu, offset); 1624 1625 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1626 drm_WARN_ONCE(&i915->drm, 1, 1627 "VM(%d): iGVT-g doesn't support GuC\n", 1628 vgpu->id); 1629 return 0; 1630 } 1631 1632 return 0; 1633 } 1634 1635 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1636 void *p_data, unsigned int bytes) 1637 { 1638 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1639 u32 trtte = *(u32 *)p_data; 1640 1641 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1642 drm_WARN(&i915->drm, 1, 1643 "VM(%d): Use physical address for TRTT!\n", 1644 vgpu->id); 1645 return -EINVAL; 1646 } 1647 write_vreg(vgpu, offset, p_data, bytes); 1648 1649 return 0; 1650 } 1651 1652 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1653 void *p_data, unsigned int bytes) 1654 { 1655 write_vreg(vgpu, offset, p_data, bytes); 1656 return 0; 1657 } 1658 1659 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1660 void *p_data, unsigned int bytes) 1661 { 1662 u32 v = 0; 1663 1664 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1665 v |= (1 << 0); 1666 1667 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1668 v |= (1 << 8); 1669 1670 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1671 v |= (1 << 16); 1672 1673 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1674 v |= (1 << 24); 1675 1676 vgpu_vreg(vgpu, offset) = v; 1677 1678 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1679 } 1680 1681 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1682 void *p_data, unsigned int bytes) 1683 { 1684 u32 value = *(u32 *)p_data; 1685 u32 cmd = value & 0xff; 1686 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1687 1688 switch (cmd) { 1689 case GEN9_PCODE_READ_MEM_LATENCY: 1690 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1691 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1692 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1693 IS_COMETLAKE(vgpu->gvt->gt->i915)) { 1694 /** 1695 * "Read memory latency" command on gen9. 1696 * Below memory latency values are read 1697 * from skylake platform. 1698 */ 1699 if (!*data0) 1700 *data0 = 0x1e1a1100; 1701 else 1702 *data0 = 0x61514b3d; 1703 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) { 1704 /** 1705 * "Read memory latency" command on gen9. 1706 * Below memory latency values are read 1707 * from Broxton MRB. 1708 */ 1709 if (!*data0) 1710 *data0 = 0x16080707; 1711 else 1712 *data0 = 0x16161616; 1713 } 1714 break; 1715 case SKL_PCODE_CDCLK_CONTROL: 1716 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1717 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1718 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1719 IS_COMETLAKE(vgpu->gvt->gt->i915)) 1720 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1721 break; 1722 case GEN6_PCODE_READ_RC6VIDS: 1723 *data0 |= 0x1; 1724 break; 1725 } 1726 1727 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1728 vgpu->id, value, *data0); 1729 /** 1730 * PCODE_READY clear means ready for pcode read/write, 1731 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1732 * always emulate as pcode read/write success and ready for access 1733 * anytime, since we don't touch real physical registers here. 1734 */ 1735 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1736 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1737 } 1738 1739 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1740 void *p_data, unsigned int bytes) 1741 { 1742 u32 value = *(u32 *)p_data; 1743 const struct intel_engine_cs *engine = 1744 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1745 1746 if (value != 0 && 1747 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1748 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1749 offset, value); 1750 return -EINVAL; 1751 } 1752 1753 /* 1754 * Need to emulate all the HWSP register write to ensure host can 1755 * update the VM CSB status correctly. Here listed registers can 1756 * support BDW, SKL or other platforms with same HWSP registers. 1757 */ 1758 if (unlikely(!engine)) { 1759 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1760 offset); 1761 return -EINVAL; 1762 } 1763 vgpu->hws_pga[engine->id] = value; 1764 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1765 vgpu->id, value, offset); 1766 1767 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1768 } 1769 1770 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1771 unsigned int offset, void *p_data, unsigned int bytes) 1772 { 1773 u32 v = *(u32 *)p_data; 1774 1775 if (IS_BROXTON(vgpu->gvt->gt->i915)) 1776 v &= (1 << 31) | (1 << 29); 1777 else 1778 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1779 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1780 v |= (v >> 1); 1781 1782 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1783 } 1784 1785 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1786 void *p_data, unsigned int bytes) 1787 { 1788 u32 v = *(u32 *)p_data; 1789 1790 /* other bits are MBZ. */ 1791 v &= (1 << 31) | (1 << 30); 1792 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1793 1794 vgpu_vreg(vgpu, offset) = v; 1795 1796 return 0; 1797 } 1798 1799 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1800 unsigned int offset, void *p_data, unsigned int bytes) 1801 { 1802 u32 v = *(u32 *)p_data; 1803 1804 if (v & BXT_DE_PLL_PLL_ENABLE) 1805 v |= BXT_DE_PLL_LOCK; 1806 1807 vgpu_vreg(vgpu, offset) = v; 1808 1809 return 0; 1810 } 1811 1812 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1813 unsigned int offset, void *p_data, unsigned int bytes) 1814 { 1815 u32 v = *(u32 *)p_data; 1816 1817 if (v & PORT_PLL_ENABLE) 1818 v |= PORT_PLL_LOCK; 1819 1820 vgpu_vreg(vgpu, offset) = v; 1821 1822 return 0; 1823 } 1824 1825 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1826 unsigned int offset, void *p_data, unsigned int bytes) 1827 { 1828 u32 v = *(u32 *)p_data; 1829 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1830 1831 switch (offset) { 1832 case _PHY_CTL_FAMILY_EDP: 1833 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1834 break; 1835 case _PHY_CTL_FAMILY_DDI: 1836 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1837 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1838 break; 1839 } 1840 1841 vgpu_vreg(vgpu, offset) = v; 1842 1843 return 0; 1844 } 1845 1846 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1847 unsigned int offset, void *p_data, unsigned int bytes) 1848 { 1849 u32 v = vgpu_vreg(vgpu, offset); 1850 1851 v &= ~UNIQUE_TRANGE_EN_METHOD; 1852 1853 vgpu_vreg(vgpu, offset) = v; 1854 1855 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1856 } 1857 1858 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1859 unsigned int offset, void *p_data, unsigned int bytes) 1860 { 1861 u32 v = *(u32 *)p_data; 1862 1863 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1864 vgpu_vreg(vgpu, offset - 0x600) = v; 1865 vgpu_vreg(vgpu, offset - 0x800) = v; 1866 } else { 1867 vgpu_vreg(vgpu, offset - 0x400) = v; 1868 vgpu_vreg(vgpu, offset - 0x600) = v; 1869 } 1870 1871 vgpu_vreg(vgpu, offset) = v; 1872 1873 return 0; 1874 } 1875 1876 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1877 unsigned int offset, void *p_data, unsigned int bytes) 1878 { 1879 u32 v = *(u32 *)p_data; 1880 1881 if (v & BIT(0)) { 1882 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1883 ~PHY_RESERVED; 1884 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1885 PHY_POWER_GOOD; 1886 } 1887 1888 if (v & BIT(1)) { 1889 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1890 ~PHY_RESERVED; 1891 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1892 PHY_POWER_GOOD; 1893 } 1894 1895 1896 vgpu_vreg(vgpu, offset) = v; 1897 1898 return 0; 1899 } 1900 1901 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1902 unsigned int offset, void *p_data, unsigned int bytes) 1903 { 1904 vgpu_vreg(vgpu, offset) = 0; 1905 return 0; 1906 } 1907 1908 /* 1909 * FixMe: 1910 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did: 1911 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.) 1912 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing 1913 * these MI_BATCH_BUFFER. 1914 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT 1915 * PML4 PTE: PAT(0) PCD(1) PWT(1). 1916 * The performance is still expected to be low, will need further improvement. 1917 */ 1918 static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset, 1919 void *p_data, unsigned int bytes) 1920 { 1921 u64 pat = 1922 GEN8_PPAT(0, CHV_PPAT_SNOOP) | 1923 GEN8_PPAT(1, 0) | 1924 GEN8_PPAT(2, 0) | 1925 GEN8_PPAT(3, CHV_PPAT_SNOOP) | 1926 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 1927 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 1928 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 1929 GEN8_PPAT(7, CHV_PPAT_SNOOP); 1930 1931 vgpu_vreg(vgpu, offset) = lower_32_bits(pat); 1932 1933 return 0; 1934 } 1935 1936 static int guc_status_read(struct intel_vgpu *vgpu, 1937 unsigned int offset, void *p_data, 1938 unsigned int bytes) 1939 { 1940 /* keep MIA_IN_RESET before clearing */ 1941 read_vreg(vgpu, offset, p_data, bytes); 1942 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET; 1943 return 0; 1944 } 1945 1946 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1947 unsigned int offset, void *p_data, unsigned int bytes) 1948 { 1949 struct intel_gvt *gvt = vgpu->gvt; 1950 const struct intel_engine_cs *engine = 1951 intel_gvt_render_mmio_to_engine(gvt, offset); 1952 1953 /** 1954 * Read HW reg in following case 1955 * a. the offset isn't a ring mmio 1956 * b. the offset's ring is running on hw. 1957 * c. the offset is ring time stamp mmio 1958 */ 1959 1960 if (!engine || 1961 vgpu == gvt->scheduler.engine_owner[engine->id] || 1962 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) || 1963 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) { 1964 mmio_hw_access_pre(gvt->gt); 1965 vgpu_vreg(vgpu, offset) = 1966 intel_uncore_read(gvt->gt->uncore, _MMIO(offset)); 1967 mmio_hw_access_post(gvt->gt); 1968 } 1969 1970 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1971 } 1972 1973 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1974 void *p_data, unsigned int bytes) 1975 { 1976 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1977 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1978 struct intel_vgpu_execlist *execlist; 1979 u32 data = *(u32 *)p_data; 1980 int ret = 0; 1981 1982 if (drm_WARN_ON(&i915->drm, !engine)) 1983 return -EINVAL; 1984 1985 /* 1986 * Due to d3_entered is used to indicate skipping PPGTT invalidation on 1987 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after 1988 * vGPU reset if in resuming. 1989 * In S0ix exit, the device power state also transite from D3 to D0 as 1990 * S3 resume, but no vGPU reset (triggered by QEMU devic model). After 1991 * S0ix exit, all engines continue to work. However the d3_entered 1992 * remains set which will break next vGPU reset logic (miss the expected 1993 * PPGTT invalidation). 1994 * Engines can only work in D0. Thus the 1st elsp write gives GVT a 1995 * chance to clear d3_entered. 1996 */ 1997 if (vgpu->d3_entered) 1998 vgpu->d3_entered = false; 1999 2000 execlist = &vgpu->submission.execlist[engine->id]; 2001 2002 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 2003 if (execlist->elsp_dwords.index == 3) { 2004 ret = intel_vgpu_submit_execlist(vgpu, engine); 2005 if(ret) 2006 gvt_vgpu_err("fail submit workload on ring %s\n", 2007 engine->name); 2008 } 2009 2010 ++execlist->elsp_dwords.index; 2011 execlist->elsp_dwords.index &= 0x3; 2012 return ret; 2013 } 2014 2015 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2016 void *p_data, unsigned int bytes) 2017 { 2018 u32 data = *(u32 *)p_data; 2019 const struct intel_engine_cs *engine = 2020 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 2021 bool enable_execlist; 2022 int ret; 2023 2024 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); 2025 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2026 IS_COMETLAKE(vgpu->gvt->gt->i915)) 2027 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); 2028 write_vreg(vgpu, offset, p_data, bytes); 2029 2030 if (IS_MASKED_BITS_ENABLED(data, 1)) { 2031 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2032 return 0; 2033 } 2034 2035 if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2036 IS_COMETLAKE(vgpu->gvt->gt->i915)) && 2037 IS_MASKED_BITS_ENABLED(data, 2)) { 2038 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2039 return 0; 2040 } 2041 2042 /* when PPGTT mode enabled, we will check if guest has called 2043 * pvinfo, if not, we will treat this guest as non-gvtg-aware 2044 * guest, and stop emulating its cfg space, mmio, gtt, etc. 2045 */ 2046 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) || 2047 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) && 2048 !vgpu->pv_notified) { 2049 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2050 return 0; 2051 } 2052 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) || 2053 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) { 2054 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 2055 2056 gvt_dbg_core("EXECLIST %s on ring %s\n", 2057 (enable_execlist ? "enabling" : "disabling"), 2058 engine->name); 2059 2060 if (!enable_execlist) 2061 return 0; 2062 2063 ret = intel_vgpu_select_submission_ops(vgpu, 2064 engine->mask, 2065 INTEL_VGPU_EXECLIST_SUBMISSION); 2066 if (ret) 2067 return ret; 2068 2069 intel_vgpu_start_schedule(vgpu); 2070 } 2071 return 0; 2072 } 2073 2074 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 2075 unsigned int offset, void *p_data, unsigned int bytes) 2076 { 2077 unsigned int id = 0; 2078 2079 write_vreg(vgpu, offset, p_data, bytes); 2080 vgpu_vreg(vgpu, offset) = 0; 2081 2082 switch (offset) { 2083 case 0x4260: 2084 id = RCS0; 2085 break; 2086 case 0x4264: 2087 id = VCS0; 2088 break; 2089 case 0x4268: 2090 id = VCS1; 2091 break; 2092 case 0x426c: 2093 id = BCS0; 2094 break; 2095 case 0x4270: 2096 id = VECS0; 2097 break; 2098 default: 2099 return -EINVAL; 2100 } 2101 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 2102 2103 return 0; 2104 } 2105 2106 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 2107 unsigned int offset, void *p_data, unsigned int bytes) 2108 { 2109 u32 data; 2110 2111 write_vreg(vgpu, offset, p_data, bytes); 2112 data = vgpu_vreg(vgpu, offset); 2113 2114 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET)) 2115 data |= RESET_CTL_READY_TO_RESET; 2116 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 2117 data &= ~RESET_CTL_READY_TO_RESET; 2118 2119 vgpu_vreg(vgpu, offset) = data; 2120 return 0; 2121 } 2122 2123 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, 2124 unsigned int offset, void *p_data, 2125 unsigned int bytes) 2126 { 2127 u32 data = *(u32 *)p_data; 2128 2129 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); 2130 write_vreg(vgpu, offset, p_data, bytes); 2131 2132 if (IS_MASKED_BITS_ENABLED(data, 0x10) || 2133 IS_MASKED_BITS_ENABLED(data, 0x8)) 2134 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2135 2136 return 0; 2137 } 2138 2139 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 2140 ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 2141 s, f, am, rm, d, r, w); \ 2142 if (ret) \ 2143 return ret; \ 2144 } while (0) 2145 2146 #define MMIO_DH(reg, d, r, w) \ 2147 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 2148 2149 #define MMIO_DFH(reg, d, f, r, w) \ 2150 MMIO_F(reg, 4, f, 0, 0, d, r, w) 2151 2152 #define MMIO_GM(reg, d, r, w) \ 2153 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 2154 2155 #define MMIO_GM_RDR(reg, d, r, w) \ 2156 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 2157 2158 #define MMIO_RO(reg, d, f, rm, r, w) \ 2159 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 2160 2161 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 2162 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 2163 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 2164 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 2165 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 2166 if (HAS_ENGINE(gvt->gt, VCS1)) \ 2167 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 2168 } while (0) 2169 2170 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 2171 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 2172 2173 #define MMIO_RING_GM(prefix, d, r, w) \ 2174 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 2175 2176 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 2177 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 2178 2179 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 2180 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 2181 2182 static int init_generic_mmio_info(struct intel_gvt *gvt) 2183 { 2184 struct drm_i915_private *dev_priv = gvt->gt->i915; 2185 int ret; 2186 2187 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, 2188 intel_vgpu_reg_imr_handler); 2189 2190 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 2191 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 2192 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 2193 2194 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL); 2195 2196 2197 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, 2198 gamw_echo_dev_rw_ia_write); 2199 2200 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2201 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2202 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2203 2204 #define RING_REG(base) _MMIO((base) + 0x28) 2205 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2206 #undef RING_REG 2207 2208 #define RING_REG(base) _MMIO((base) + 0x134) 2209 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2210 #undef RING_REG 2211 2212 #define RING_REG(base) _MMIO((base) + 0x6c) 2213 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 2214 #undef RING_REG 2215 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 2216 2217 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 2218 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); 2219 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 2220 2221 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL); 2222 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL); 2223 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL); 2224 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL); 2225 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 2226 2227 /* RING MODE */ 2228 #define RING_REG(base) _MMIO((base) + 0x29c) 2229 MMIO_RING_DFH(RING_REG, D_ALL, 2230 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL, 2231 ring_mode_mmio_write); 2232 #undef RING_REG 2233 2234 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2235 NULL, NULL); 2236 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2237 NULL, NULL); 2238 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 2239 mmio_read_from_hw, NULL); 2240 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 2241 mmio_read_from_hw, NULL); 2242 2243 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2244 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2245 NULL, NULL); 2246 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2247 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2248 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2249 2250 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2251 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2252 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2253 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL, 2254 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2255 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2256 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 2257 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2258 NULL, NULL); 2259 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2260 NULL, NULL); 2261 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 2262 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 2263 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 2264 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 2265 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 2266 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 2267 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2268 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2269 MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2270 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2271 2272 /* display */ 2273 MMIO_DH(TRANSCONF(TRANSCODER_A), D_ALL, NULL, pipeconf_mmio_write); 2274 MMIO_DH(TRANSCONF(TRANSCODER_B), D_ALL, NULL, pipeconf_mmio_write); 2275 MMIO_DH(TRANSCONF(TRANSCODER_C), D_ALL, NULL, pipeconf_mmio_write); 2276 MMIO_DH(TRANSCONF(TRANSCODER_EDP), D_ALL, NULL, pipeconf_mmio_write); 2277 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2278 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, 2279 reg50080_mmio_write); 2280 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2281 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, 2282 reg50080_mmio_write); 2283 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2284 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, 2285 reg50080_mmio_write); 2286 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 2287 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, 2288 reg50080_mmio_write); 2289 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 2290 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, 2291 reg50080_mmio_write); 2292 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 2293 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, 2294 reg50080_mmio_write); 2295 2296 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2297 gmbus_mmio_write); 2298 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2299 2300 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2301 dp_aux_ch_ctl_mmio_write); 2302 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2303 dp_aux_ch_ctl_mmio_write); 2304 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2305 dp_aux_ch_ctl_mmio_write); 2306 2307 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2308 2309 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2310 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2311 2312 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2313 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2314 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2315 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2316 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2317 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2318 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2319 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2320 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2321 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2322 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2323 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2324 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2325 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2326 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2327 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2328 2329 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2330 PORTA_HOTPLUG_STATUS_MASK 2331 | PORTB_HOTPLUG_STATUS_MASK 2332 | PORTC_HOTPLUG_STATUS_MASK 2333 | PORTD_HOTPLUG_STATUS_MASK, 2334 NULL, NULL); 2335 2336 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2337 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2338 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2339 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2340 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2341 2342 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2343 dp_aux_ch_ctl_mmio_write); 2344 2345 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2346 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2347 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2348 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2349 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2350 2351 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2352 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2353 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2354 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2355 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2356 2357 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2358 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2359 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2360 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2361 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2362 2363 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2364 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2365 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2366 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2367 2368 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2369 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2370 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2371 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2372 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2373 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2374 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2375 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); 2376 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); 2377 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); 2378 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); 2379 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2380 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2381 2382 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2383 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2384 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2385 2386 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2387 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2388 2389 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2390 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2391 2392 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2393 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2394 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2395 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2396 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2397 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2398 2399 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2400 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2401 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2402 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2403 2404 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2405 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2406 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2407 2408 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2409 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2410 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2411 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2412 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2413 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2414 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2415 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2416 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2417 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2418 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2419 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2420 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2421 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2422 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2423 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2424 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2425 2426 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2427 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL); 2428 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2429 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2430 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2431 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2432 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2433 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2434 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2435 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2436 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2437 2438 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2439 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2440 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL); 2441 2442 return 0; 2443 } 2444 2445 static int init_bdw_mmio_info(struct intel_gvt *gvt) 2446 { 2447 int ret; 2448 2449 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2450 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2451 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2452 2453 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2454 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2455 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2456 2457 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2458 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2459 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2460 2461 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2462 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2463 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2464 2465 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2466 intel_vgpu_reg_imr_handler); 2467 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2468 intel_vgpu_reg_ier_handler); 2469 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2470 intel_vgpu_reg_iir_handler); 2471 2472 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2473 intel_vgpu_reg_imr_handler); 2474 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2475 intel_vgpu_reg_ier_handler); 2476 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2477 intel_vgpu_reg_iir_handler); 2478 2479 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2480 intel_vgpu_reg_imr_handler); 2481 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2482 intel_vgpu_reg_ier_handler); 2483 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2484 intel_vgpu_reg_iir_handler); 2485 2486 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2487 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2488 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2489 2490 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2491 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2492 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2493 2494 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2495 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2496 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2497 2498 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2499 intel_vgpu_reg_master_irq_handler); 2500 2501 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0, 2502 mmio_read_from_hw, NULL); 2503 2504 #define RING_REG(base) _MMIO((base) + 0xd0) 2505 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2506 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2507 ring_reset_ctl_write); 2508 #undef RING_REG 2509 2510 #define RING_REG(base) _MMIO((base) + 0x230) 2511 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2512 #undef RING_REG 2513 2514 #define RING_REG(base) _MMIO((base) + 0x234) 2515 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, 2516 NULL, NULL); 2517 #undef RING_REG 2518 2519 #define RING_REG(base) _MMIO((base) + 0x244) 2520 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2521 #undef RING_REG 2522 2523 #define RING_REG(base) _MMIO((base) + 0x370) 2524 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2525 #undef RING_REG 2526 2527 #define RING_REG(base) _MMIO((base) + 0x3a0) 2528 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2529 #undef RING_REG 2530 2531 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2532 2533 #define RING_REG(base) _MMIO((base) + 0x270) 2534 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2535 #undef RING_REG 2536 2537 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2538 2539 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2540 2541 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2542 NULL, NULL); 2543 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2544 NULL, NULL); 2545 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2546 2547 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2548 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2549 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2550 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2551 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2552 2553 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0, 2554 D_BDW_PLUS, NULL, force_nonpriv_write); 2555 2556 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2557 2558 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2559 2560 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2561 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2562 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2563 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2564 2565 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2566 2567 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2568 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2569 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2570 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2571 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2572 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2573 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2574 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2575 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2576 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2577 return 0; 2578 } 2579 2580 static int init_skl_mmio_info(struct intel_gvt *gvt) 2581 { 2582 int ret; 2583 2584 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2585 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2586 MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2587 MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL); 2588 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2589 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2590 2591 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2592 dp_aux_ch_ctl_mmio_write); 2593 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2594 dp_aux_ch_ctl_mmio_write); 2595 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2596 dp_aux_ch_ctl_mmio_write); 2597 2598 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); 2599 2600 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 2601 2602 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2603 MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2604 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL); 2605 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2606 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2607 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL); 2608 2609 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2610 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2611 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2612 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2613 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2614 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2615 2616 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2617 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2618 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2619 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2620 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2621 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2622 2623 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2624 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2625 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2626 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2627 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2628 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2629 2630 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2631 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2632 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2633 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2634 2635 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2636 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2637 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2638 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2639 2640 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2641 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2642 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2643 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2644 2645 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2646 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2647 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2648 2649 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2650 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2651 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2652 2653 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2654 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2655 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2656 2657 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2658 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2659 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2660 2661 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2662 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2663 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2664 2665 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2666 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2667 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2668 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2669 2670 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2671 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2672 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2673 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2674 2675 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2676 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2677 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2678 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2679 2680 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2681 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2682 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2683 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2684 2685 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2686 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2687 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2688 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2689 2690 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2691 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2692 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2693 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2694 2695 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2696 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2697 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2698 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2699 2700 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2701 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2702 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2703 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2704 2705 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2706 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2707 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2708 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2709 2710 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2711 2712 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2713 NULL, NULL); 2714 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2715 NULL, NULL); 2716 2717 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, 2718 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2719 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2720 NULL, NULL); 2721 2722 /* TRTT */ 2723 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2724 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2725 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2726 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2727 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2728 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE, 2729 NULL, gen9_trtte_write); 2730 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE, 2731 NULL, gen9_trtt_chicken_write); 2732 2733 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2734 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2735 2736 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) 2737 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2738 NULL, csfe_chicken1_mmio_write); 2739 #undef CSFE_CHICKEN1_REG 2740 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2741 NULL, NULL); 2742 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2743 NULL, NULL); 2744 2745 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL); 2746 MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2747 2748 return 0; 2749 } 2750 2751 static int init_bxt_mmio_info(struct intel_gvt *gvt) 2752 { 2753 int ret; 2754 2755 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 2756 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 2757 NULL, bxt_phy_ctl_family_write); 2758 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 2759 NULL, bxt_phy_ctl_family_write); 2760 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 2761 NULL, bxt_port_pll_enable_write); 2762 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 2763 NULL, bxt_port_pll_enable_write); 2764 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 2765 bxt_port_pll_enable_write); 2766 2767 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 2768 NULL, bxt_pcs_dw12_grp_write); 2769 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT, 2770 bxt_port_tx_dw3_read, NULL); 2771 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 2772 NULL, bxt_pcs_dw12_grp_write); 2773 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT, 2774 bxt_port_tx_dw3_read, NULL); 2775 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 2776 NULL, bxt_pcs_dw12_grp_write); 2777 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT, 2778 bxt_port_tx_dw3_read, NULL); 2779 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 2780 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); 2781 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL); 2782 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL); 2783 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2784 0, 0, D_BXT, NULL, NULL); 2785 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2786 0, 0, D_BXT, NULL, NULL); 2787 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2788 0, 0, D_BXT, NULL, NULL); 2789 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2790 0, 0, D_BXT, NULL, NULL); 2791 2792 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 2793 2794 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write); 2795 2796 return 0; 2797 } 2798 2799 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 2800 unsigned int offset) 2801 { 2802 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2803 int num = gvt->mmio.num_mmio_block; 2804 int i; 2805 2806 for (i = 0; i < num; i++, block++) { 2807 if (offset >= i915_mmio_reg_offset(block->offset) && 2808 offset < i915_mmio_reg_offset(block->offset) + block->size) 2809 return block; 2810 } 2811 return NULL; 2812 } 2813 2814 /** 2815 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2816 * @gvt: GVT device 2817 * 2818 * This function is called at the driver unloading stage, to clean up the MMIO 2819 * information table of GVT device 2820 * 2821 */ 2822 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2823 { 2824 struct hlist_node *tmp; 2825 struct intel_gvt_mmio_info *e; 2826 int i; 2827 2828 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2829 kfree(e); 2830 2831 kfree(gvt->mmio.mmio_block); 2832 gvt->mmio.mmio_block = NULL; 2833 gvt->mmio.num_mmio_block = 0; 2834 2835 vfree(gvt->mmio.mmio_attribute); 2836 gvt->mmio.mmio_attribute = NULL; 2837 } 2838 2839 static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset, 2840 u32 size) 2841 { 2842 struct intel_gvt *gvt = iter->data; 2843 struct intel_gvt_mmio_info *info, *p; 2844 u32 start, end, i; 2845 2846 if (WARN_ON(!IS_ALIGNED(offset, 4))) 2847 return -EINVAL; 2848 2849 start = offset; 2850 end = offset + size; 2851 2852 for (i = start; i < end; i += 4) { 2853 p = intel_gvt_find_mmio_info(gvt, i); 2854 if (p) { 2855 WARN(1, "dup mmio definition offset %x\n", i); 2856 2857 /* We return -EEXIST here to make GVT-g load fail. 2858 * So duplicated MMIO can be found as soon as 2859 * possible. 2860 */ 2861 return -EEXIST; 2862 } 2863 2864 info = kzalloc(sizeof(*info), GFP_KERNEL); 2865 if (!info) 2866 return -ENOMEM; 2867 2868 info->offset = i; 2869 info->read = intel_vgpu_default_mmio_read; 2870 info->write = intel_vgpu_default_mmio_write; 2871 INIT_HLIST_NODE(&info->node); 2872 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 2873 gvt->mmio.num_tracked_mmio++; 2874 } 2875 return 0; 2876 } 2877 2878 static int handle_mmio_block(struct intel_gvt_mmio_table_iter *iter, 2879 u32 offset, u32 size) 2880 { 2881 struct intel_gvt *gvt = iter->data; 2882 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2883 void *ret; 2884 2885 ret = krealloc(block, 2886 (gvt->mmio.num_mmio_block + 1) * sizeof(*block), 2887 GFP_KERNEL); 2888 if (!ret) 2889 return -ENOMEM; 2890 2891 gvt->mmio.mmio_block = block = ret; 2892 2893 block += gvt->mmio.num_mmio_block; 2894 2895 memset(block, 0, sizeof(*block)); 2896 2897 block->offset = _MMIO(offset); 2898 block->size = size; 2899 2900 gvt->mmio.num_mmio_block++; 2901 2902 return 0; 2903 } 2904 2905 static int handle_mmio_cb(struct intel_gvt_mmio_table_iter *iter, u32 offset, 2906 u32 size) 2907 { 2908 if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0))) 2909 return handle_mmio(iter, offset, size); 2910 else 2911 return handle_mmio_block(iter, offset, size); 2912 } 2913 2914 static int init_mmio_info(struct intel_gvt *gvt) 2915 { 2916 struct intel_gvt_mmio_table_iter iter = { 2917 .i915 = gvt->gt->i915, 2918 .data = gvt, 2919 .handle_mmio_cb = handle_mmio_cb, 2920 }; 2921 2922 return intel_gvt_iterate_mmio_table(&iter); 2923 } 2924 2925 static int init_mmio_block_handlers(struct intel_gvt *gvt) 2926 { 2927 struct gvt_mmio_block *block; 2928 2929 block = find_mmio_block(gvt, VGT_PVINFO_PAGE); 2930 if (!block) { 2931 WARN(1, "fail to assign handlers to mmio block %x\n", 2932 i915_mmio_reg_offset(gvt->mmio.mmio_block->offset)); 2933 return -ENODEV; 2934 } 2935 2936 block->read = pvinfo_mmio_read; 2937 block->write = pvinfo_mmio_write; 2938 2939 return 0; 2940 } 2941 2942 /** 2943 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2944 * @gvt: GVT device 2945 * 2946 * This function is called at the initialization stage, to setup the MMIO 2947 * information table for GVT device 2948 * 2949 * Returns: 2950 * zero on success, negative if failed. 2951 */ 2952 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2953 { 2954 struct intel_gvt_device_info *info = &gvt->device_info; 2955 struct drm_i915_private *i915 = gvt->gt->i915; 2956 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 2957 int ret; 2958 2959 gvt->mmio.mmio_attribute = vzalloc(size); 2960 if (!gvt->mmio.mmio_attribute) 2961 return -ENOMEM; 2962 2963 ret = init_mmio_info(gvt); 2964 if (ret) 2965 goto err; 2966 2967 ret = init_mmio_block_handlers(gvt); 2968 if (ret) 2969 goto err; 2970 2971 ret = init_generic_mmio_info(gvt); 2972 if (ret) 2973 goto err; 2974 2975 if (IS_BROADWELL(i915)) { 2976 ret = init_bdw_mmio_info(gvt); 2977 if (ret) 2978 goto err; 2979 } else if (IS_SKYLAKE(i915) || 2980 IS_KABYLAKE(i915) || 2981 IS_COFFEELAKE(i915) || 2982 IS_COMETLAKE(i915)) { 2983 ret = init_bdw_mmio_info(gvt); 2984 if (ret) 2985 goto err; 2986 ret = init_skl_mmio_info(gvt); 2987 if (ret) 2988 goto err; 2989 } else if (IS_BROXTON(i915)) { 2990 ret = init_bdw_mmio_info(gvt); 2991 if (ret) 2992 goto err; 2993 ret = init_skl_mmio_info(gvt); 2994 if (ret) 2995 goto err; 2996 ret = init_bxt_mmio_info(gvt); 2997 if (ret) 2998 goto err; 2999 } 3000 3001 return 0; 3002 err: 3003 intel_gvt_clean_mmio_info(gvt); 3004 return ret; 3005 } 3006 3007 /** 3008 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 3009 * @gvt: a GVT device 3010 * @handler: the handler 3011 * @data: private data given to handler 3012 * 3013 * Returns: 3014 * Zero on success, negative error code if failed. 3015 */ 3016 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3017 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3018 void *data) 3019 { 3020 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3021 struct intel_gvt_mmio_info *e; 3022 int i, j, ret; 3023 3024 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3025 ret = handler(gvt, e->offset, data); 3026 if (ret) 3027 return ret; 3028 } 3029 3030 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3031 /* pvinfo data doesn't come from hw mmio */ 3032 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE) 3033 continue; 3034 3035 for (j = 0; j < block->size; j += 4) { 3036 ret = handler(gvt, i915_mmio_reg_offset(block->offset) + j, data); 3037 if (ret) 3038 return ret; 3039 } 3040 } 3041 return 0; 3042 } 3043 3044 /** 3045 * intel_vgpu_default_mmio_read - default MMIO read handler 3046 * @vgpu: a vGPU 3047 * @offset: access offset 3048 * @p_data: data return buffer 3049 * @bytes: access data length 3050 * 3051 * Returns: 3052 * Zero on success, negative error code if failed. 3053 */ 3054 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3055 void *p_data, unsigned int bytes) 3056 { 3057 read_vreg(vgpu, offset, p_data, bytes); 3058 return 0; 3059 } 3060 3061 /** 3062 * intel_vgpu_default_mmio_write() - default MMIO write handler 3063 * @vgpu: a vGPU 3064 * @offset: access offset 3065 * @p_data: write data buffer 3066 * @bytes: access data length 3067 * 3068 * Returns: 3069 * Zero on success, negative error code if failed. 3070 */ 3071 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3072 void *p_data, unsigned int bytes) 3073 { 3074 write_vreg(vgpu, offset, p_data, bytes); 3075 return 0; 3076 } 3077 3078 /** 3079 * intel_vgpu_mask_mmio_write - write mask register 3080 * @vgpu: a vGPU 3081 * @offset: access offset 3082 * @p_data: write data buffer 3083 * @bytes: access data length 3084 * 3085 * Returns: 3086 * Zero on success, negative error code if failed. 3087 */ 3088 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3089 void *p_data, unsigned int bytes) 3090 { 3091 u32 mask, old_vreg; 3092 3093 old_vreg = vgpu_vreg(vgpu, offset); 3094 write_vreg(vgpu, offset, p_data, bytes); 3095 mask = vgpu_vreg(vgpu, offset) >> 16; 3096 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | 3097 (vgpu_vreg(vgpu, offset) & mask); 3098 3099 return 0; 3100 } 3101 3102 /** 3103 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3104 * force-nopriv register 3105 * 3106 * @gvt: a GVT device 3107 * @offset: register offset 3108 * 3109 * Returns: 3110 * True if the register is in force-nonpriv whitelist; 3111 * False if outside; 3112 */ 3113 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3114 unsigned int offset) 3115 { 3116 return in_whitelist(offset); 3117 } 3118 3119 /** 3120 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3121 * @vgpu: a vGPU 3122 * @offset: register offset 3123 * @pdata: data buffer 3124 * @bytes: data length 3125 * @is_read: read or write 3126 * 3127 * Returns: 3128 * Zero on success, negative error code if failed. 3129 */ 3130 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3131 void *pdata, unsigned int bytes, bool is_read) 3132 { 3133 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 3134 struct intel_gvt *gvt = vgpu->gvt; 3135 struct intel_gvt_mmio_info *mmio_info; 3136 struct gvt_mmio_block *mmio_block; 3137 gvt_mmio_func func; 3138 int ret; 3139 3140 if (drm_WARN_ON(&i915->drm, bytes > 8)) 3141 return -EINVAL; 3142 3143 /* 3144 * Handle special MMIO blocks. 3145 */ 3146 mmio_block = find_mmio_block(gvt, offset); 3147 if (mmio_block) { 3148 func = is_read ? mmio_block->read : mmio_block->write; 3149 if (func) 3150 return func(vgpu, offset, pdata, bytes); 3151 goto default_rw; 3152 } 3153 3154 /* 3155 * Normal tracked MMIOs. 3156 */ 3157 mmio_info = intel_gvt_find_mmio_info(gvt, offset); 3158 if (!mmio_info) { 3159 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3160 goto default_rw; 3161 } 3162 3163 if (is_read) 3164 return mmio_info->read(vgpu, offset, pdata, bytes); 3165 else { 3166 u64 ro_mask = mmio_info->ro_mask; 3167 u32 old_vreg = 0; 3168 u64 data = 0; 3169 3170 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3171 old_vreg = vgpu_vreg(vgpu, offset); 3172 } 3173 3174 if (likely(!ro_mask)) 3175 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3176 else if (!~ro_mask) { 3177 gvt_vgpu_err("try to write RO reg %x\n", offset); 3178 return 0; 3179 } else { 3180 /* keep the RO bits in the virtual register */ 3181 memcpy(&data, pdata, bytes); 3182 data &= ~ro_mask; 3183 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3184 ret = mmio_info->write(vgpu, offset, &data, bytes); 3185 } 3186 3187 /* higher 16bits of mode ctl regs are mask bits for change */ 3188 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3189 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3190 3191 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3192 | (vgpu_vreg(vgpu, offset) & mask); 3193 } 3194 } 3195 3196 return ret; 3197 3198 default_rw: 3199 return is_read ? 3200 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3201 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3202 } 3203 3204 void intel_gvt_restore_fence(struct intel_gvt *gvt) 3205 { 3206 struct intel_vgpu *vgpu; 3207 int i, id; 3208 3209 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3210 mmio_hw_access_pre(gvt->gt); 3211 for (i = 0; i < vgpu_fence_sz(vgpu); i++) 3212 intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i))); 3213 mmio_hw_access_post(gvt->gt); 3214 } 3215 } 3216 3217 static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data) 3218 { 3219 struct intel_vgpu *vgpu = data; 3220 struct drm_i915_private *dev_priv = gvt->gt->i915; 3221 3222 if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE) 3223 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset)); 3224 3225 return 0; 3226 } 3227 3228 void intel_gvt_restore_mmio(struct intel_gvt *gvt) 3229 { 3230 struct intel_vgpu *vgpu; 3231 int id; 3232 3233 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3234 mmio_hw_access_pre(gvt->gt); 3235 intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu); 3236 mmio_hw_access_post(gvt->gt); 3237 } 3238 } 3239