1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <linux/debugfs.h> 7 8 #include <drm/drm_blend.h> 9 10 #include "soc/intel_dram.h" 11 12 #include "i915_drv.h" 13 #include "i915_reg.h" 14 #include "i9xx_wm.h" 15 #include "intel_atomic.h" 16 #include "intel_atomic_plane.h" 17 #include "intel_bw.h" 18 #include "intel_cdclk.h" 19 #include "intel_crtc.h" 20 #include "intel_cursor_regs.h" 21 #include "intel_de.h" 22 #include "intel_display.h" 23 #include "intel_display_power.h" 24 #include "intel_display_regs.h" 25 #include "intel_display_rpm.h" 26 #include "intel_display_types.h" 27 #include "intel_fb.h" 28 #include "intel_fixed.h" 29 #include "intel_pcode.h" 30 #include "intel_wm.h" 31 #include "skl_universal_plane_regs.h" 32 #include "skl_watermark.h" 33 #include "skl_watermark_regs.h" 34 35 /*It is expected that DSB can do posted writes to every register in 36 * the pipe and planes within 100us. For flip queue use case, the 37 * recommended DSB execution time is 100us + one SAGV block time. 38 */ 39 #define DSB_EXE_TIME 100 40 41 static void skl_sagv_disable(struct intel_display *display); 42 43 /* Stores plane specific WM parameters */ 44 struct skl_wm_params { 45 bool x_tiled, y_tiled; 46 bool rc_surface; 47 bool is_planar; 48 u32 width; 49 u8 cpp; 50 u32 plane_pixel_rate; 51 u32 y_min_scanlines; 52 u32 plane_bytes_per_line; 53 uint_fixed_16_16_t plane_blocks_per_line; 54 uint_fixed_16_16_t y_tile_minimum; 55 u32 linetime_us; 56 u32 dbuf_block_size; 57 }; 58 59 u8 intel_enabled_dbuf_slices_mask(struct intel_display *display) 60 { 61 u8 enabled_slices = 0; 62 enum dbuf_slice slice; 63 64 for_each_dbuf_slice(display, slice) { 65 if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE) 66 enabled_slices |= BIT(slice); 67 } 68 69 return enabled_slices; 70 } 71 72 /* 73 * FIXME: We still don't have the proper code detect if we need to apply the WA, 74 * so assume we'll always need it in order to avoid underruns. 75 */ 76 static bool skl_needs_memory_bw_wa(struct intel_display *display) 77 { 78 return DISPLAY_VER(display) == 9; 79 } 80 81 bool 82 intel_has_sagv(struct intel_display *display) 83 { 84 return HAS_SAGV(display) && display->sagv.status != I915_SAGV_NOT_CONTROLLED; 85 } 86 87 static u32 88 intel_sagv_block_time(struct intel_display *display) 89 { 90 struct drm_i915_private *i915 = to_i915(display->drm); 91 92 if (DISPLAY_VER(display) >= 14) { 93 u32 val; 94 95 val = intel_de_read(display, MTL_LATENCY_SAGV); 96 97 return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); 98 } else if (DISPLAY_VER(display) >= 12) { 99 u32 val = 0; 100 int ret; 101 102 ret = snb_pcode_read(&i915->uncore, 103 GEN12_PCODE_READ_SAGV_BLOCK_TIME_US, 104 &val, NULL); 105 if (ret) { 106 drm_dbg_kms(display->drm, "Couldn't read SAGV block time!\n"); 107 return 0; 108 } 109 110 return val; 111 } else if (DISPLAY_VER(display) == 11) { 112 return 10; 113 } else if (HAS_SAGV(display)) { 114 return 30; 115 } else { 116 return 0; 117 } 118 } 119 120 static void intel_sagv_init(struct intel_display *display) 121 { 122 if (!HAS_SAGV(display)) 123 display->sagv.status = I915_SAGV_NOT_CONTROLLED; 124 125 /* 126 * Probe to see if we have working SAGV control. 127 * For icl+ this was already determined by intel_bw_init_hw(). 128 */ 129 if (DISPLAY_VER(display) < 11) 130 skl_sagv_disable(display); 131 132 drm_WARN_ON(display->drm, display->sagv.status == I915_SAGV_UNKNOWN); 133 134 display->sagv.block_time_us = intel_sagv_block_time(display); 135 136 drm_dbg_kms(display->drm, "SAGV supported: %s, original SAGV block time: %u us\n", 137 str_yes_no(intel_has_sagv(display)), display->sagv.block_time_us); 138 139 /* avoid overflow when adding with wm0 latency/etc. */ 140 if (drm_WARN(display->drm, display->sagv.block_time_us > U16_MAX, 141 "Excessive SAGV block time %u, ignoring\n", 142 display->sagv.block_time_us)) 143 display->sagv.block_time_us = 0; 144 145 if (!intel_has_sagv(display)) 146 display->sagv.block_time_us = 0; 147 } 148 149 /* 150 * SAGV dynamically adjusts the system agent voltage and clock frequencies 151 * depending on power and performance requirements. The display engine access 152 * to system memory is blocked during the adjustment time. Because of the 153 * blocking time, having this enabled can cause full system hangs and/or pipe 154 * underruns if we don't meet all of the following requirements: 155 * 156 * - <= 1 pipe enabled 157 * - All planes can enable watermarks for latencies >= SAGV engine block time 158 * - We're not using an interlaced display configuration 159 */ 160 static void skl_sagv_enable(struct intel_display *display) 161 { 162 struct drm_i915_private *i915 = to_i915(display->drm); 163 int ret; 164 165 if (!intel_has_sagv(display)) 166 return; 167 168 if (display->sagv.status == I915_SAGV_ENABLED) 169 return; 170 171 drm_dbg_kms(display->drm, "Enabling SAGV\n"); 172 ret = snb_pcode_write(&i915->uncore, GEN9_PCODE_SAGV_CONTROL, 173 GEN9_SAGV_ENABLE); 174 175 /* We don't need to wait for SAGV when enabling */ 176 177 /* 178 * Some skl systems, pre-release machines in particular, 179 * don't actually have SAGV. 180 */ 181 if (display->platform.skylake && ret == -ENXIO) { 182 drm_dbg(display->drm, "No SAGV found on system, ignoring\n"); 183 display->sagv.status = I915_SAGV_NOT_CONTROLLED; 184 return; 185 } else if (ret < 0) { 186 drm_err(display->drm, "Failed to enable SAGV\n"); 187 return; 188 } 189 190 display->sagv.status = I915_SAGV_ENABLED; 191 } 192 193 static void skl_sagv_disable(struct intel_display *display) 194 { 195 struct drm_i915_private *i915 = to_i915(display->drm); 196 int ret; 197 198 if (!intel_has_sagv(display)) 199 return; 200 201 if (display->sagv.status == I915_SAGV_DISABLED) 202 return; 203 204 drm_dbg_kms(display->drm, "Disabling SAGV\n"); 205 /* bspec says to keep retrying for at least 1 ms */ 206 ret = skl_pcode_request(&i915->uncore, GEN9_PCODE_SAGV_CONTROL, 207 GEN9_SAGV_DISABLE, 208 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 209 1); 210 /* 211 * Some skl systems, pre-release machines in particular, 212 * don't actually have SAGV. 213 */ 214 if (display->platform.skylake && ret == -ENXIO) { 215 drm_dbg(display->drm, "No SAGV found on system, ignoring\n"); 216 display->sagv.status = I915_SAGV_NOT_CONTROLLED; 217 return; 218 } else if (ret < 0) { 219 drm_err(display->drm, "Failed to disable SAGV (%d)\n", ret); 220 return; 221 } 222 223 display->sagv.status = I915_SAGV_DISABLED; 224 } 225 226 static void skl_sagv_pre_plane_update(struct intel_atomic_state *state) 227 { 228 struct intel_display *display = to_intel_display(state); 229 const struct intel_bw_state *new_bw_state = 230 intel_atomic_get_new_bw_state(state); 231 232 if (!new_bw_state) 233 return; 234 235 if (!intel_can_enable_sagv(display, new_bw_state)) 236 skl_sagv_disable(display); 237 } 238 239 static void skl_sagv_post_plane_update(struct intel_atomic_state *state) 240 { 241 struct intel_display *display = to_intel_display(state); 242 const struct intel_bw_state *new_bw_state = 243 intel_atomic_get_new_bw_state(state); 244 245 if (!new_bw_state) 246 return; 247 248 if (intel_can_enable_sagv(display, new_bw_state)) 249 skl_sagv_enable(display); 250 } 251 252 static void icl_sagv_pre_plane_update(struct intel_atomic_state *state) 253 { 254 struct intel_display *display = to_intel_display(state); 255 const struct intel_bw_state *old_bw_state = 256 intel_atomic_get_old_bw_state(state); 257 const struct intel_bw_state *new_bw_state = 258 intel_atomic_get_new_bw_state(state); 259 u16 old_mask, new_mask; 260 261 if (!new_bw_state) 262 return; 263 264 old_mask = old_bw_state->qgv_points_mask; 265 new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask; 266 267 if (old_mask == new_mask) 268 return; 269 270 WARN_ON(!new_bw_state->base.changed); 271 272 drm_dbg_kms(display->drm, "Restricting QGV points: 0x%x -> 0x%x\n", 273 old_mask, new_mask); 274 275 /* 276 * Restrict required qgv points before updating the configuration. 277 * According to BSpec we can't mask and unmask qgv points at the same 278 * time. Also masking should be done before updating the configuration 279 * and unmasking afterwards. 280 */ 281 icl_pcode_restrict_qgv_points(display, new_mask); 282 } 283 284 static void icl_sagv_post_plane_update(struct intel_atomic_state *state) 285 { 286 struct intel_display *display = to_intel_display(state); 287 const struct intel_bw_state *old_bw_state = 288 intel_atomic_get_old_bw_state(state); 289 const struct intel_bw_state *new_bw_state = 290 intel_atomic_get_new_bw_state(state); 291 u16 old_mask, new_mask; 292 293 if (!new_bw_state) 294 return; 295 296 old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask; 297 new_mask = new_bw_state->qgv_points_mask; 298 299 if (old_mask == new_mask) 300 return; 301 302 WARN_ON(!new_bw_state->base.changed); 303 304 drm_dbg_kms(display->drm, "Relaxing QGV points: 0x%x -> 0x%x\n", 305 old_mask, new_mask); 306 307 /* 308 * Allow required qgv points after updating the configuration. 309 * According to BSpec we can't mask and unmask qgv points at the same 310 * time. Also masking should be done before updating the configuration 311 * and unmasking afterwards. 312 */ 313 icl_pcode_restrict_qgv_points(display, new_mask); 314 } 315 316 void intel_sagv_pre_plane_update(struct intel_atomic_state *state) 317 { 318 struct intel_display *display = to_intel_display(state); 319 320 /* 321 * Just return if we can't control SAGV or don't have it. 322 * This is different from situation when we have SAGV but just can't 323 * afford it due to DBuf limitation - in case if SAGV is completely 324 * disabled in a BIOS, we are not even allowed to send a PCode request, 325 * as it will throw an error. So have to check it here. 326 */ 327 if (!intel_has_sagv(display)) 328 return; 329 330 if (DISPLAY_VER(display) >= 11) 331 icl_sagv_pre_plane_update(state); 332 else 333 skl_sagv_pre_plane_update(state); 334 } 335 336 void intel_sagv_post_plane_update(struct intel_atomic_state *state) 337 { 338 struct intel_display *display = to_intel_display(state); 339 340 /* 341 * Just return if we can't control SAGV or don't have it. 342 * This is different from situation when we have SAGV but just can't 343 * afford it due to DBuf limitation - in case if SAGV is completely 344 * disabled in a BIOS, we are not even allowed to send a PCode request, 345 * as it will throw an error. So have to check it here. 346 */ 347 if (!intel_has_sagv(display)) 348 return; 349 350 if (DISPLAY_VER(display) >= 11) 351 icl_sagv_post_plane_update(state); 352 else 353 skl_sagv_post_plane_update(state); 354 } 355 356 static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) 357 { 358 struct intel_display *display = to_intel_display(crtc_state); 359 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 360 enum plane_id plane_id; 361 int max_level = INT_MAX; 362 363 if (!intel_has_sagv(display)) 364 return false; 365 366 if (!crtc_state->hw.active) 367 return true; 368 369 if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE) 370 return false; 371 372 for_each_plane_id_on_crtc(crtc, plane_id) { 373 const struct skl_plane_wm *wm = 374 &crtc_state->wm.skl.optimal.planes[plane_id]; 375 int level; 376 377 /* Skip this plane if it's not enabled */ 378 if (!wm->wm[0].enable) 379 continue; 380 381 /* Find the highest enabled wm level for this plane */ 382 for (level = display->wm.num_levels - 1; 383 !wm->wm[level].enable; --level) 384 { } 385 386 /* Highest common enabled wm level for all planes */ 387 max_level = min(level, max_level); 388 } 389 390 /* No enabled planes? */ 391 if (max_level == INT_MAX) 392 return true; 393 394 for_each_plane_id_on_crtc(crtc, plane_id) { 395 const struct skl_plane_wm *wm = 396 &crtc_state->wm.skl.optimal.planes[plane_id]; 397 398 /* 399 * All enabled planes must have enabled a common wm level that 400 * can tolerate memory latencies higher than sagv_block_time_us 401 */ 402 if (wm->wm[0].enable && !wm->wm[max_level].can_sagv) 403 return false; 404 } 405 406 return true; 407 } 408 409 static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) 410 { 411 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 412 enum plane_id plane_id; 413 414 if (!crtc_state->hw.active) 415 return true; 416 417 for_each_plane_id_on_crtc(crtc, plane_id) { 418 const struct skl_plane_wm *wm = 419 &crtc_state->wm.skl.optimal.planes[plane_id]; 420 421 if (wm->wm[0].enable && !wm->sagv.wm0.enable) 422 return false; 423 } 424 425 return true; 426 } 427 428 bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) 429 { 430 struct intel_display *display = to_intel_display(crtc_state); 431 432 if (!display->params.enable_sagv) 433 return false; 434 435 /* 436 * SAGV is initially forced off because its current 437 * state can't be queried from pcode. Allow SAGV to 438 * be enabled upon the first real commit. 439 */ 440 if (crtc_state->inherited) 441 return false; 442 443 if (DISPLAY_VER(display) >= 12) 444 return tgl_crtc_can_enable_sagv(crtc_state); 445 else 446 return skl_crtc_can_enable_sagv(crtc_state); 447 } 448 449 bool intel_can_enable_sagv(struct intel_display *display, 450 const struct intel_bw_state *bw_state) 451 { 452 if (DISPLAY_VER(display) < 11 && 453 bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes)) 454 return false; 455 456 return bw_state->pipe_sagv_reject == 0; 457 } 458 459 static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry, 460 u16 start, u16 end) 461 { 462 entry->start = start; 463 entry->end = end; 464 465 return end; 466 } 467 468 static int intel_dbuf_slice_size(struct intel_display *display) 469 { 470 return DISPLAY_INFO(display)->dbuf.size / 471 hweight8(DISPLAY_INFO(display)->dbuf.slice_mask); 472 } 473 474 static void 475 skl_ddb_entry_for_slices(struct intel_display *display, u8 slice_mask, 476 struct skl_ddb_entry *ddb) 477 { 478 int slice_size = intel_dbuf_slice_size(display); 479 480 if (!slice_mask) { 481 ddb->start = 0; 482 ddb->end = 0; 483 return; 484 } 485 486 ddb->start = (ffs(slice_mask) - 1) * slice_size; 487 ddb->end = fls(slice_mask) * slice_size; 488 489 WARN_ON(ddb->start >= ddb->end); 490 WARN_ON(ddb->end > DISPLAY_INFO(display)->dbuf.size); 491 } 492 493 static unsigned int mbus_ddb_offset(struct intel_display *display, u8 slice_mask) 494 { 495 struct skl_ddb_entry ddb; 496 497 if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2))) 498 slice_mask = BIT(DBUF_S1); 499 else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4))) 500 slice_mask = BIT(DBUF_S3); 501 502 skl_ddb_entry_for_slices(display, slice_mask, &ddb); 503 504 return ddb.start; 505 } 506 507 u32 skl_ddb_dbuf_slice_mask(struct intel_display *display, 508 const struct skl_ddb_entry *entry) 509 { 510 int slice_size = intel_dbuf_slice_size(display); 511 enum dbuf_slice start_slice, end_slice; 512 u8 slice_mask = 0; 513 514 if (!skl_ddb_entry_size(entry)) 515 return 0; 516 517 start_slice = entry->start / slice_size; 518 end_slice = (entry->end - 1) / slice_size; 519 520 /* 521 * Per plane DDB entry can in a really worst case be on multiple slices 522 * but single entry is anyway contiguous. 523 */ 524 while (start_slice <= end_slice) { 525 slice_mask |= BIT(start_slice); 526 start_slice++; 527 } 528 529 return slice_mask; 530 } 531 532 static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_state) 533 { 534 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 535 int hdisplay, vdisplay; 536 537 if (!crtc_state->hw.active) 538 return 0; 539 540 /* 541 * Watermark/ddb requirement highly depends upon width of the 542 * framebuffer, So instead of allocating DDB equally among pipes 543 * distribute DDB based on resolution/width of the display. 544 */ 545 drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay); 546 547 return hdisplay; 548 } 549 550 static void intel_crtc_dbuf_weights(const struct intel_dbuf_state *dbuf_state, 551 enum pipe for_pipe, 552 unsigned int *weight_start, 553 unsigned int *weight_end, 554 unsigned int *weight_total) 555 { 556 struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev); 557 enum pipe pipe; 558 559 *weight_start = 0; 560 *weight_end = 0; 561 *weight_total = 0; 562 563 for_each_pipe(display, pipe) { 564 int weight = dbuf_state->weight[pipe]; 565 566 /* 567 * Do not account pipes using other slice sets 568 * luckily as of current BSpec slice sets do not partially 569 * intersect(pipes share either same one slice or same slice set 570 * i.e no partial intersection), so it is enough to check for 571 * equality for now. 572 */ 573 if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe]) 574 continue; 575 576 *weight_total += weight; 577 if (pipe < for_pipe) { 578 *weight_start += weight; 579 *weight_end += weight; 580 } else if (pipe == for_pipe) { 581 *weight_end += weight; 582 } 583 } 584 } 585 586 static int 587 skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc) 588 { 589 struct intel_display *display = to_intel_display(crtc); 590 unsigned int weight_total, weight_start, weight_end; 591 const struct intel_dbuf_state *old_dbuf_state = 592 intel_atomic_get_old_dbuf_state(state); 593 struct intel_dbuf_state *new_dbuf_state = 594 intel_atomic_get_new_dbuf_state(state); 595 struct intel_crtc_state *crtc_state; 596 struct skl_ddb_entry ddb_slices; 597 enum pipe pipe = crtc->pipe; 598 unsigned int mbus_offset = 0; 599 u32 ddb_range_size; 600 u32 dbuf_slice_mask; 601 u32 start, end; 602 int ret; 603 604 if (new_dbuf_state->weight[pipe] == 0) { 605 skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 0, 0); 606 goto out; 607 } 608 609 dbuf_slice_mask = new_dbuf_state->slices[pipe]; 610 611 skl_ddb_entry_for_slices(display, dbuf_slice_mask, &ddb_slices); 612 mbus_offset = mbus_ddb_offset(display, dbuf_slice_mask); 613 ddb_range_size = skl_ddb_entry_size(&ddb_slices); 614 615 intel_crtc_dbuf_weights(new_dbuf_state, pipe, 616 &weight_start, &weight_end, &weight_total); 617 618 start = ddb_range_size * weight_start / weight_total; 619 end = ddb_range_size * weight_end / weight_total; 620 621 skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 622 ddb_slices.start - mbus_offset + start, 623 ddb_slices.start - mbus_offset + end); 624 625 out: 626 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] && 627 skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe], 628 &new_dbuf_state->ddb[pipe])) 629 return 0; 630 631 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 632 if (ret) 633 return ret; 634 635 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 636 if (IS_ERR(crtc_state)) 637 return PTR_ERR(crtc_state); 638 639 /* 640 * Used for checking overlaps, so we need absolute 641 * offsets instead of MBUS relative offsets. 642 */ 643 crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start; 644 crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end; 645 646 drm_dbg_kms(display->drm, 647 "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n", 648 crtc->base.base.id, crtc->base.name, 649 old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe], 650 old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end, 651 new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end, 652 old_dbuf_state->active_pipes, new_dbuf_state->active_pipes); 653 654 return 0; 655 } 656 657 static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state, 658 int width, const struct drm_format_info *format, 659 u64 modifier, unsigned int rotation, 660 u32 plane_pixel_rate, struct skl_wm_params *wp, 661 int color_plane, unsigned int pan_x); 662 663 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, 664 struct intel_plane *plane, 665 int level, 666 unsigned int latency, 667 const struct skl_wm_params *wp, 668 const struct skl_wm_level *result_prev, 669 struct skl_wm_level *result /* out */); 670 671 static unsigned int skl_wm_latency(struct intel_display *display, int level, 672 const struct skl_wm_params *wp) 673 { 674 unsigned int latency = display->wm.skl_latency[level]; 675 676 if (latency == 0) 677 return 0; 678 679 /* 680 * WaIncreaseLatencyIPCEnabled: kbl,cfl 681 * Display WA #1141: kbl,cfl 682 */ 683 if ((display->platform.kabylake || display->platform.coffeelake || 684 display->platform.cometlake) && skl_watermark_ipc_enabled(display)) 685 latency += 4; 686 687 if (skl_needs_memory_bw_wa(display) && wp && wp->x_tiled) 688 latency += 15; 689 690 return latency; 691 } 692 693 static unsigned int 694 skl_cursor_allocation(const struct intel_crtc_state *crtc_state, 695 int num_active) 696 { 697 struct intel_display *display = to_intel_display(crtc_state); 698 struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor); 699 struct skl_wm_level wm = {}; 700 int ret, min_ddb_alloc = 0; 701 struct skl_wm_params wp; 702 int level; 703 704 ret = skl_compute_wm_params(crtc_state, 256, 705 drm_format_info(DRM_FORMAT_ARGB8888), 706 DRM_FORMAT_MOD_LINEAR, 707 DRM_MODE_ROTATE_0, 708 crtc_state->pixel_rate, &wp, 0, 0); 709 drm_WARN_ON(display->drm, ret); 710 711 for (level = 0; level < display->wm.num_levels; level++) { 712 unsigned int latency = skl_wm_latency(display, level, &wp); 713 714 skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm); 715 if (wm.min_ddb_alloc == U16_MAX) 716 break; 717 718 min_ddb_alloc = wm.min_ddb_alloc; 719 } 720 721 return max(num_active == 1 ? 32 : 8, min_ddb_alloc); 722 } 723 724 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) 725 { 726 skl_ddb_entry_init(entry, 727 REG_FIELD_GET(PLANE_BUF_START_MASK, reg), 728 REG_FIELD_GET(PLANE_BUF_END_MASK, reg)); 729 if (entry->end) 730 entry->end++; 731 } 732 733 static void 734 skl_ddb_get_hw_plane_state(struct intel_display *display, 735 const enum pipe pipe, 736 const enum plane_id plane_id, 737 struct skl_ddb_entry *ddb, 738 struct skl_ddb_entry *ddb_y, 739 u16 *min_ddb, u16 *interim_ddb) 740 { 741 u32 val; 742 743 /* Cursor doesn't support NV12/planar, so no extra calculation needed */ 744 if (plane_id == PLANE_CURSOR) { 745 val = intel_de_read(display, CUR_BUF_CFG(pipe)); 746 skl_ddb_entry_init_from_hw(ddb, val); 747 return; 748 } 749 750 val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id)); 751 skl_ddb_entry_init_from_hw(ddb, val); 752 753 if (DISPLAY_VER(display) >= 30) { 754 val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id)); 755 756 *min_ddb = REG_FIELD_GET(PLANE_MIN_DBUF_BLOCKS_MASK, val); 757 *interim_ddb = REG_FIELD_GET(PLANE_INTERIM_DBUF_BLOCKS_MASK, val); 758 } 759 760 if (DISPLAY_VER(display) >= 11) 761 return; 762 763 val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id)); 764 skl_ddb_entry_init_from_hw(ddb_y, val); 765 } 766 767 static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, 768 struct skl_ddb_entry *ddb, 769 struct skl_ddb_entry *ddb_y, 770 u16 *min_ddb, u16 *interim_ddb) 771 { 772 struct intel_display *display = to_intel_display(crtc); 773 enum intel_display_power_domain power_domain; 774 enum pipe pipe = crtc->pipe; 775 intel_wakeref_t wakeref; 776 enum plane_id plane_id; 777 778 power_domain = POWER_DOMAIN_PIPE(pipe); 779 wakeref = intel_display_power_get_if_enabled(display, power_domain); 780 if (!wakeref) 781 return; 782 783 for_each_plane_id_on_crtc(crtc, plane_id) 784 skl_ddb_get_hw_plane_state(display, pipe, 785 plane_id, 786 &ddb[plane_id], 787 &ddb_y[plane_id], 788 &min_ddb[plane_id], 789 &interim_ddb[plane_id]); 790 791 intel_display_power_put(display, power_domain, wakeref); 792 } 793 794 struct dbuf_slice_conf_entry { 795 u8 active_pipes; 796 u8 dbuf_mask[I915_MAX_PIPES]; 797 bool join_mbus; 798 }; 799 800 /* 801 * Table taken from Bspec 12716 802 * Pipes do have some preferred DBuf slice affinity, 803 * plus there are some hardcoded requirements on how 804 * those should be distributed for multipipe scenarios. 805 * For more DBuf slices algorithm can get even more messy 806 * and less readable, so decided to use a table almost 807 * as is from BSpec itself - that way it is at least easier 808 * to compare, change and check. 809 */ 810 static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] = 811 /* Autogenerated with igt/tools/intel_dbuf_map tool: */ 812 { 813 { 814 .active_pipes = BIT(PIPE_A), 815 .dbuf_mask = { 816 [PIPE_A] = BIT(DBUF_S1), 817 }, 818 }, 819 { 820 .active_pipes = BIT(PIPE_B), 821 .dbuf_mask = { 822 [PIPE_B] = BIT(DBUF_S1), 823 }, 824 }, 825 { 826 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 827 .dbuf_mask = { 828 [PIPE_A] = BIT(DBUF_S1), 829 [PIPE_B] = BIT(DBUF_S2), 830 }, 831 }, 832 { 833 .active_pipes = BIT(PIPE_C), 834 .dbuf_mask = { 835 [PIPE_C] = BIT(DBUF_S2), 836 }, 837 }, 838 { 839 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 840 .dbuf_mask = { 841 [PIPE_A] = BIT(DBUF_S1), 842 [PIPE_C] = BIT(DBUF_S2), 843 }, 844 }, 845 { 846 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 847 .dbuf_mask = { 848 [PIPE_B] = BIT(DBUF_S1), 849 [PIPE_C] = BIT(DBUF_S2), 850 }, 851 }, 852 { 853 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 854 .dbuf_mask = { 855 [PIPE_A] = BIT(DBUF_S1), 856 [PIPE_B] = BIT(DBUF_S1), 857 [PIPE_C] = BIT(DBUF_S2), 858 }, 859 }, 860 {} 861 }; 862 863 /* 864 * Table taken from Bspec 49255 865 * Pipes do have some preferred DBuf slice affinity, 866 * plus there are some hardcoded requirements on how 867 * those should be distributed for multipipe scenarios. 868 * For more DBuf slices algorithm can get even more messy 869 * and less readable, so decided to use a table almost 870 * as is from BSpec itself - that way it is at least easier 871 * to compare, change and check. 872 */ 873 static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = 874 /* Autogenerated with igt/tools/intel_dbuf_map tool: */ 875 { 876 { 877 .active_pipes = BIT(PIPE_A), 878 .dbuf_mask = { 879 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 880 }, 881 }, 882 { 883 .active_pipes = BIT(PIPE_B), 884 .dbuf_mask = { 885 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 886 }, 887 }, 888 { 889 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 890 .dbuf_mask = { 891 [PIPE_A] = BIT(DBUF_S2), 892 [PIPE_B] = BIT(DBUF_S1), 893 }, 894 }, 895 { 896 .active_pipes = BIT(PIPE_C), 897 .dbuf_mask = { 898 [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1), 899 }, 900 }, 901 { 902 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 903 .dbuf_mask = { 904 [PIPE_A] = BIT(DBUF_S1), 905 [PIPE_C] = BIT(DBUF_S2), 906 }, 907 }, 908 { 909 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 910 .dbuf_mask = { 911 [PIPE_B] = BIT(DBUF_S1), 912 [PIPE_C] = BIT(DBUF_S2), 913 }, 914 }, 915 { 916 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 917 .dbuf_mask = { 918 [PIPE_A] = BIT(DBUF_S1), 919 [PIPE_B] = BIT(DBUF_S1), 920 [PIPE_C] = BIT(DBUF_S2), 921 }, 922 }, 923 { 924 .active_pipes = BIT(PIPE_D), 925 .dbuf_mask = { 926 [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1), 927 }, 928 }, 929 { 930 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), 931 .dbuf_mask = { 932 [PIPE_A] = BIT(DBUF_S1), 933 [PIPE_D] = BIT(DBUF_S2), 934 }, 935 }, 936 { 937 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), 938 .dbuf_mask = { 939 [PIPE_B] = BIT(DBUF_S1), 940 [PIPE_D] = BIT(DBUF_S2), 941 }, 942 }, 943 { 944 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), 945 .dbuf_mask = { 946 [PIPE_A] = BIT(DBUF_S1), 947 [PIPE_B] = BIT(DBUF_S1), 948 [PIPE_D] = BIT(DBUF_S2), 949 }, 950 }, 951 { 952 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), 953 .dbuf_mask = { 954 [PIPE_C] = BIT(DBUF_S1), 955 [PIPE_D] = BIT(DBUF_S2), 956 }, 957 }, 958 { 959 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), 960 .dbuf_mask = { 961 [PIPE_A] = BIT(DBUF_S1), 962 [PIPE_C] = BIT(DBUF_S2), 963 [PIPE_D] = BIT(DBUF_S2), 964 }, 965 }, 966 { 967 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 968 .dbuf_mask = { 969 [PIPE_B] = BIT(DBUF_S1), 970 [PIPE_C] = BIT(DBUF_S2), 971 [PIPE_D] = BIT(DBUF_S2), 972 }, 973 }, 974 { 975 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 976 .dbuf_mask = { 977 [PIPE_A] = BIT(DBUF_S1), 978 [PIPE_B] = BIT(DBUF_S1), 979 [PIPE_C] = BIT(DBUF_S2), 980 [PIPE_D] = BIT(DBUF_S2), 981 }, 982 }, 983 {} 984 }; 985 986 static const struct dbuf_slice_conf_entry dg2_allowed_dbufs[] = { 987 { 988 .active_pipes = BIT(PIPE_A), 989 .dbuf_mask = { 990 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 991 }, 992 }, 993 { 994 .active_pipes = BIT(PIPE_B), 995 .dbuf_mask = { 996 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 997 }, 998 }, 999 { 1000 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 1001 .dbuf_mask = { 1002 [PIPE_A] = BIT(DBUF_S1), 1003 [PIPE_B] = BIT(DBUF_S2), 1004 }, 1005 }, 1006 { 1007 .active_pipes = BIT(PIPE_C), 1008 .dbuf_mask = { 1009 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1010 }, 1011 }, 1012 { 1013 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 1014 .dbuf_mask = { 1015 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1016 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1017 }, 1018 }, 1019 { 1020 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 1021 .dbuf_mask = { 1022 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 1023 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1024 }, 1025 }, 1026 { 1027 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 1028 .dbuf_mask = { 1029 [PIPE_A] = BIT(DBUF_S1), 1030 [PIPE_B] = BIT(DBUF_S2), 1031 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1032 }, 1033 }, 1034 { 1035 .active_pipes = BIT(PIPE_D), 1036 .dbuf_mask = { 1037 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 1038 }, 1039 }, 1040 { 1041 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), 1042 .dbuf_mask = { 1043 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1044 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 1045 }, 1046 }, 1047 { 1048 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), 1049 .dbuf_mask = { 1050 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 1051 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 1052 }, 1053 }, 1054 { 1055 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), 1056 .dbuf_mask = { 1057 [PIPE_A] = BIT(DBUF_S1), 1058 [PIPE_B] = BIT(DBUF_S2), 1059 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 1060 }, 1061 }, 1062 { 1063 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), 1064 .dbuf_mask = { 1065 [PIPE_C] = BIT(DBUF_S3), 1066 [PIPE_D] = BIT(DBUF_S4), 1067 }, 1068 }, 1069 { 1070 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), 1071 .dbuf_mask = { 1072 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1073 [PIPE_C] = BIT(DBUF_S3), 1074 [PIPE_D] = BIT(DBUF_S4), 1075 }, 1076 }, 1077 { 1078 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1079 .dbuf_mask = { 1080 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 1081 [PIPE_C] = BIT(DBUF_S3), 1082 [PIPE_D] = BIT(DBUF_S4), 1083 }, 1084 }, 1085 { 1086 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1087 .dbuf_mask = { 1088 [PIPE_A] = BIT(DBUF_S1), 1089 [PIPE_B] = BIT(DBUF_S2), 1090 [PIPE_C] = BIT(DBUF_S3), 1091 [PIPE_D] = BIT(DBUF_S4), 1092 }, 1093 }, 1094 {} 1095 }; 1096 1097 static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = { 1098 /* 1099 * Keep the join_mbus cases first so check_mbus_joined() 1100 * will prefer them over the !join_mbus cases. 1101 */ 1102 { 1103 .active_pipes = BIT(PIPE_A), 1104 .dbuf_mask = { 1105 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4), 1106 }, 1107 .join_mbus = true, 1108 }, 1109 { 1110 .active_pipes = BIT(PIPE_B), 1111 .dbuf_mask = { 1112 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4), 1113 }, 1114 .join_mbus = true, 1115 }, 1116 { 1117 .active_pipes = BIT(PIPE_A), 1118 .dbuf_mask = { 1119 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1120 }, 1121 .join_mbus = false, 1122 }, 1123 { 1124 .active_pipes = BIT(PIPE_B), 1125 .dbuf_mask = { 1126 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1127 }, 1128 .join_mbus = false, 1129 }, 1130 { 1131 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 1132 .dbuf_mask = { 1133 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1134 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1135 }, 1136 }, 1137 { 1138 .active_pipes = BIT(PIPE_C), 1139 .dbuf_mask = { 1140 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1141 }, 1142 }, 1143 { 1144 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 1145 .dbuf_mask = { 1146 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1147 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1148 }, 1149 }, 1150 { 1151 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 1152 .dbuf_mask = { 1153 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1154 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1155 }, 1156 }, 1157 { 1158 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 1159 .dbuf_mask = { 1160 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1161 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1162 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1163 }, 1164 }, 1165 { 1166 .active_pipes = BIT(PIPE_D), 1167 .dbuf_mask = { 1168 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1169 }, 1170 }, 1171 { 1172 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), 1173 .dbuf_mask = { 1174 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1175 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1176 }, 1177 }, 1178 { 1179 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), 1180 .dbuf_mask = { 1181 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1182 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1183 }, 1184 }, 1185 { 1186 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), 1187 .dbuf_mask = { 1188 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1189 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1190 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1191 }, 1192 }, 1193 { 1194 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), 1195 .dbuf_mask = { 1196 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1197 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1198 }, 1199 }, 1200 { 1201 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), 1202 .dbuf_mask = { 1203 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1204 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1205 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1206 }, 1207 }, 1208 { 1209 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1210 .dbuf_mask = { 1211 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1212 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1213 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1214 }, 1215 }, 1216 { 1217 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1218 .dbuf_mask = { 1219 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1220 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1221 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1222 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1223 }, 1224 }, 1225 {} 1226 1227 }; 1228 1229 static bool check_mbus_joined(u8 active_pipes, 1230 const struct dbuf_slice_conf_entry *dbuf_slices) 1231 { 1232 int i; 1233 1234 for (i = 0; dbuf_slices[i].active_pipes != 0; i++) { 1235 if (dbuf_slices[i].active_pipes == active_pipes) 1236 return dbuf_slices[i].join_mbus; 1237 } 1238 return false; 1239 } 1240 1241 static bool adlp_check_mbus_joined(u8 active_pipes) 1242 { 1243 return check_mbus_joined(active_pipes, adlp_allowed_dbufs); 1244 } 1245 1246 static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus, 1247 const struct dbuf_slice_conf_entry *dbuf_slices) 1248 { 1249 int i; 1250 1251 for (i = 0; dbuf_slices[i].active_pipes != 0; i++) { 1252 if (dbuf_slices[i].active_pipes == active_pipes && 1253 dbuf_slices[i].join_mbus == join_mbus) 1254 return dbuf_slices[i].dbuf_mask[pipe]; 1255 } 1256 return 0; 1257 } 1258 1259 /* 1260 * This function finds an entry with same enabled pipe configuration and 1261 * returns correspondent DBuf slice mask as stated in BSpec for particular 1262 * platform. 1263 */ 1264 static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1265 { 1266 /* 1267 * FIXME: For ICL this is still a bit unclear as prev BSpec revision 1268 * required calculating "pipe ratio" in order to determine 1269 * if one or two slices can be used for single pipe configurations 1270 * as additional constraint to the existing table. 1271 * However based on recent info, it should be not "pipe ratio" 1272 * but rather ratio between pixel_rate and cdclk with additional 1273 * constants, so for now we are using only table until this is 1274 * clarified. Also this is the reason why crtc_state param is 1275 * still here - we will need it once those additional constraints 1276 * pop up. 1277 */ 1278 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1279 icl_allowed_dbufs); 1280 } 1281 1282 static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1283 { 1284 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1285 tgl_allowed_dbufs); 1286 } 1287 1288 static u8 adlp_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1289 { 1290 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1291 adlp_allowed_dbufs); 1292 } 1293 1294 static u8 dg2_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1295 { 1296 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1297 dg2_allowed_dbufs); 1298 } 1299 1300 static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool join_mbus) 1301 { 1302 struct intel_display *display = to_intel_display(crtc); 1303 enum pipe pipe = crtc->pipe; 1304 1305 if (display->platform.dg2) 1306 return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1307 else if (DISPLAY_VER(display) >= 13) 1308 return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1309 else if (DISPLAY_VER(display) == 12) 1310 return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1311 else if (DISPLAY_VER(display) == 11) 1312 return icl_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1313 /* 1314 * For anything else just return one slice yet. 1315 * Should be extended for other platforms. 1316 */ 1317 return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0; 1318 } 1319 1320 static bool 1321 use_minimal_wm0_only(const struct intel_crtc_state *crtc_state, 1322 struct intel_plane *plane) 1323 { 1324 struct intel_display *display = to_intel_display(plane); 1325 1326 /* Xe3+ are auto minimum DDB capble. So don't force minimal wm0 */ 1327 return IS_DISPLAY_VER(display, 13, 20) && 1328 crtc_state->uapi.async_flip && 1329 plane->async_flip; 1330 } 1331 1332 unsigned int 1333 skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, 1334 struct intel_plane *plane, int width, int height, 1335 int cpp) 1336 { 1337 /* 1338 * We calculate extra ddb based on ratio plane rate/total data rate 1339 * in case, in some cases we should not allocate extra ddb for the plane, 1340 * so do not count its data rate, if this is the case. 1341 */ 1342 if (use_minimal_wm0_only(crtc_state, plane)) 1343 return 0; 1344 1345 return width * height * cpp; 1346 } 1347 1348 static u64 1349 skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state) 1350 { 1351 struct intel_display *display = to_intel_display(crtc_state); 1352 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1353 enum plane_id plane_id; 1354 u64 data_rate = 0; 1355 1356 for_each_plane_id_on_crtc(crtc, plane_id) { 1357 if (plane_id == PLANE_CURSOR) 1358 continue; 1359 1360 data_rate += crtc_state->rel_data_rate[plane_id]; 1361 1362 if (DISPLAY_VER(display) < 11) 1363 data_rate += crtc_state->rel_data_rate_y[plane_id]; 1364 } 1365 1366 return data_rate; 1367 } 1368 1369 const struct skl_wm_level * 1370 skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, 1371 enum plane_id plane_id, 1372 int level) 1373 { 1374 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 1375 1376 if (level == 0 && pipe_wm->use_sagv_wm) 1377 return &wm->sagv.wm0; 1378 1379 return &wm->wm[level]; 1380 } 1381 1382 const struct skl_wm_level * 1383 skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm, 1384 enum plane_id plane_id) 1385 { 1386 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 1387 1388 if (pipe_wm->use_sagv_wm) 1389 return &wm->sagv.trans_wm; 1390 1391 return &wm->trans_wm; 1392 } 1393 1394 /* 1395 * We only disable the watermarks for each plane if 1396 * they exceed the ddb allocation of said plane. This 1397 * is done so that we don't end up touching cursor 1398 * watermarks needlessly when some other plane reduces 1399 * our max possible watermark level. 1400 * 1401 * Bspec has this to say about the PLANE_WM enable bit: 1402 * "All the watermarks at this level for all enabled 1403 * planes must be enabled before the level will be used." 1404 * So this is actually safe to do. 1405 */ 1406 static void 1407 skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb) 1408 { 1409 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) 1410 memset(wm, 0, sizeof(*wm)); 1411 } 1412 1413 static void 1414 skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm, 1415 const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb) 1416 { 1417 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) || 1418 uv_wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) { 1419 memset(wm, 0, sizeof(*wm)); 1420 memset(uv_wm, 0, sizeof(*uv_wm)); 1421 } 1422 } 1423 1424 static bool skl_need_wm_copy_wa(struct intel_display *display, int level, 1425 const struct skl_plane_wm *wm) 1426 { 1427 /* 1428 * Wa_1408961008:icl, ehl 1429 * Wa_14012656716:tgl, adl 1430 * Wa_14017887344:icl 1431 * Wa_14017868169:adl, tgl 1432 * Due to some power saving optimizations, different subsystems 1433 * like PSR, might still use even disabled wm level registers, 1434 * for "reference", so lets keep at least the values sane. 1435 * Considering amount of WA requiring us to do similar things, was 1436 * decided to simply do it for all of the platforms, as those wm 1437 * levels are disabled, this isn't going to do harm anyway. 1438 */ 1439 return level > 0 && !wm->wm[level].enable; 1440 } 1441 1442 struct skl_plane_ddb_iter { 1443 u64 data_rate; 1444 u16 start, size; 1445 }; 1446 1447 static void 1448 skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter, 1449 struct skl_ddb_entry *ddb, 1450 const struct skl_wm_level *wm, 1451 u64 data_rate) 1452 { 1453 u16 size, extra = 0; 1454 1455 if (data_rate) { 1456 extra = min_t(u16, iter->size, 1457 DIV64_U64_ROUND_UP(iter->size * data_rate, 1458 iter->data_rate)); 1459 iter->size -= extra; 1460 iter->data_rate -= data_rate; 1461 } 1462 1463 /* 1464 * Keep ddb entry of all disabled planes explicitly zeroed 1465 * to avoid skl_ddb_add_affected_planes() adding them to 1466 * the state when other planes change their allocations. 1467 */ 1468 size = wm->min_ddb_alloc + extra; 1469 if (size) 1470 iter->start = skl_ddb_entry_init(ddb, iter->start, 1471 iter->start + size); 1472 } 1473 1474 static int 1475 skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, 1476 struct intel_crtc *crtc) 1477 { 1478 struct intel_crtc_state *crtc_state = 1479 intel_atomic_get_new_crtc_state(state, crtc); 1480 const struct intel_dbuf_state *dbuf_state = 1481 intel_atomic_get_new_dbuf_state(state); 1482 const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe]; 1483 struct intel_display *display = to_intel_display(state); 1484 int num_active = hweight8(dbuf_state->active_pipes); 1485 struct skl_plane_ddb_iter iter; 1486 enum plane_id plane_id; 1487 u16 cursor_size; 1488 u32 blocks; 1489 int level; 1490 1491 /* Clear the partitioning for disabled planes. */ 1492 memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb)); 1493 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); 1494 memset(crtc_state->wm.skl.plane_min_ddb, 0, 1495 sizeof(crtc_state->wm.skl.plane_min_ddb)); 1496 memset(crtc_state->wm.skl.plane_interim_ddb, 0, 1497 sizeof(crtc_state->wm.skl.plane_interim_ddb)); 1498 1499 if (!crtc_state->hw.active) 1500 return 0; 1501 1502 iter.start = alloc->start; 1503 iter.size = skl_ddb_entry_size(alloc); 1504 if (iter.size == 0) 1505 return 0; 1506 1507 /* Allocate fixed number of blocks for cursor. */ 1508 cursor_size = skl_cursor_allocation(crtc_state, num_active); 1509 iter.size -= cursor_size; 1510 skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR], 1511 alloc->end - cursor_size, alloc->end); 1512 1513 iter.data_rate = skl_total_relative_data_rate(crtc_state); 1514 1515 /* 1516 * Find the highest watermark level for which we can satisfy the block 1517 * requirement of active planes. 1518 */ 1519 for (level = display->wm.num_levels - 1; level >= 0; level--) { 1520 blocks = 0; 1521 for_each_plane_id_on_crtc(crtc, plane_id) { 1522 const struct skl_plane_wm *wm = 1523 &crtc_state->wm.skl.optimal.planes[plane_id]; 1524 1525 if (plane_id == PLANE_CURSOR) { 1526 const struct skl_ddb_entry *ddb = 1527 &crtc_state->wm.skl.plane_ddb[plane_id]; 1528 1529 if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) { 1530 drm_WARN_ON(display->drm, 1531 wm->wm[level].min_ddb_alloc != U16_MAX); 1532 blocks = U32_MAX; 1533 break; 1534 } 1535 continue; 1536 } 1537 1538 blocks += wm->wm[level].min_ddb_alloc; 1539 blocks += wm->uv_wm[level].min_ddb_alloc; 1540 } 1541 1542 if (blocks <= iter.size) { 1543 iter.size -= blocks; 1544 break; 1545 } 1546 } 1547 1548 if (level < 0) { 1549 drm_dbg_kms(display->drm, 1550 "Requested display configuration exceeds system DDB limitations"); 1551 drm_dbg_kms(display->drm, "minimum required %d/%d\n", 1552 blocks, iter.size); 1553 return -EINVAL; 1554 } 1555 1556 /* avoid the WARN later when we don't allocate any extra DDB */ 1557 if (iter.data_rate == 0) 1558 iter.size = 0; 1559 1560 /* 1561 * Grant each plane the blocks it requires at the highest achievable 1562 * watermark level, plus an extra share of the leftover blocks 1563 * proportional to its relative data rate. 1564 */ 1565 for_each_plane_id_on_crtc(crtc, plane_id) { 1566 struct skl_ddb_entry *ddb = 1567 &crtc_state->wm.skl.plane_ddb[plane_id]; 1568 struct skl_ddb_entry *ddb_y = 1569 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 1570 u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id]; 1571 u16 *interim_ddb = 1572 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; 1573 const struct skl_plane_wm *wm = 1574 &crtc_state->wm.skl.optimal.planes[plane_id]; 1575 1576 if (plane_id == PLANE_CURSOR) 1577 continue; 1578 1579 if (DISPLAY_VER(display) < 11 && 1580 crtc_state->nv12_planes & BIT(plane_id)) { 1581 skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level], 1582 crtc_state->rel_data_rate_y[plane_id]); 1583 skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level], 1584 crtc_state->rel_data_rate[plane_id]); 1585 } else { 1586 skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level], 1587 crtc_state->rel_data_rate[plane_id]); 1588 } 1589 1590 if (DISPLAY_VER(display) >= 30) { 1591 *min_ddb = wm->wm[0].min_ddb_alloc; 1592 *interim_ddb = wm->sagv.wm0.min_ddb_alloc; 1593 } 1594 } 1595 drm_WARN_ON(display->drm, iter.size != 0 || iter.data_rate != 0); 1596 1597 /* 1598 * When we calculated watermark values we didn't know how high 1599 * of a level we'd actually be able to hit, so we just marked 1600 * all levels as "enabled." Go back now and disable the ones 1601 * that aren't actually possible. 1602 */ 1603 for (level++; level < display->wm.num_levels; level++) { 1604 for_each_plane_id_on_crtc(crtc, plane_id) { 1605 const struct skl_ddb_entry *ddb = 1606 &crtc_state->wm.skl.plane_ddb[plane_id]; 1607 const struct skl_ddb_entry *ddb_y = 1608 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 1609 struct skl_plane_wm *wm = 1610 &crtc_state->wm.skl.optimal.planes[plane_id]; 1611 1612 if (DISPLAY_VER(display) < 11 && 1613 crtc_state->nv12_planes & BIT(plane_id)) 1614 skl_check_nv12_wm_level(&wm->wm[level], 1615 &wm->uv_wm[level], 1616 ddb_y, ddb); 1617 else 1618 skl_check_wm_level(&wm->wm[level], ddb); 1619 1620 if (skl_need_wm_copy_wa(display, level, wm)) { 1621 wm->wm[level].blocks = wm->wm[level - 1].blocks; 1622 wm->wm[level].lines = wm->wm[level - 1].lines; 1623 wm->wm[level].ignore_lines = wm->wm[level - 1].ignore_lines; 1624 } 1625 } 1626 } 1627 1628 /* 1629 * Go back and disable the transition and SAGV watermarks 1630 * if it turns out we don't have enough DDB blocks for them. 1631 */ 1632 for_each_plane_id_on_crtc(crtc, plane_id) { 1633 const struct skl_ddb_entry *ddb = 1634 &crtc_state->wm.skl.plane_ddb[plane_id]; 1635 const struct skl_ddb_entry *ddb_y = 1636 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 1637 u16 *interim_ddb = 1638 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; 1639 struct skl_plane_wm *wm = 1640 &crtc_state->wm.skl.optimal.planes[plane_id]; 1641 1642 if (DISPLAY_VER(display) < 11 && 1643 crtc_state->nv12_planes & BIT(plane_id)) { 1644 skl_check_wm_level(&wm->trans_wm, ddb_y); 1645 } else { 1646 WARN_ON(skl_ddb_entry_size(ddb_y)); 1647 1648 skl_check_wm_level(&wm->trans_wm, ddb); 1649 } 1650 1651 skl_check_wm_level(&wm->sagv.wm0, ddb); 1652 if (DISPLAY_VER(display) >= 30) 1653 *interim_ddb = wm->sagv.wm0.min_ddb_alloc; 1654 1655 skl_check_wm_level(&wm->sagv.trans_wm, ddb); 1656 } 1657 1658 return 0; 1659 } 1660 1661 /* 1662 * The max latency should be 257 (max the punit can code is 255 and we add 2us 1663 * for the read latency) and cpp should always be <= 8, so that 1664 * should allow pixel_rate up to ~2 GHz which seems sufficient since max 1665 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. 1666 */ 1667 static uint_fixed_16_16_t 1668 skl_wm_method1(struct intel_display *display, u32 pixel_rate, 1669 u8 cpp, u32 latency, u32 dbuf_block_size) 1670 { 1671 u32 wm_intermediate_val; 1672 uint_fixed_16_16_t ret; 1673 1674 if (latency == 0) 1675 return FP_16_16_MAX; 1676 1677 wm_intermediate_val = latency * pixel_rate * cpp; 1678 ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size); 1679 1680 if (DISPLAY_VER(display) >= 10) 1681 ret = add_fixed16_u32(ret, 1); 1682 1683 return ret; 1684 } 1685 1686 static uint_fixed_16_16_t 1687 skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency, 1688 uint_fixed_16_16_t plane_blocks_per_line) 1689 { 1690 u32 wm_intermediate_val; 1691 uint_fixed_16_16_t ret; 1692 1693 if (latency == 0) 1694 return FP_16_16_MAX; 1695 1696 wm_intermediate_val = latency * pixel_rate; 1697 wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val, 1698 pipe_htotal * 1000); 1699 ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line); 1700 return ret; 1701 } 1702 1703 static uint_fixed_16_16_t 1704 intel_get_linetime_us(const struct intel_crtc_state *crtc_state) 1705 { 1706 struct intel_display *display = to_intel_display(crtc_state); 1707 u32 pixel_rate; 1708 u32 crtc_htotal; 1709 uint_fixed_16_16_t linetime_us; 1710 1711 if (!crtc_state->hw.active) 1712 return u32_to_fixed16(0); 1713 1714 pixel_rate = crtc_state->pixel_rate; 1715 1716 if (drm_WARN_ON(display->drm, pixel_rate == 0)) 1717 return u32_to_fixed16(0); 1718 1719 crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal; 1720 linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate); 1721 1722 return linetime_us; 1723 } 1724 1725 static int 1726 skl_compute_wm_params(const struct intel_crtc_state *crtc_state, 1727 int width, const struct drm_format_info *format, 1728 u64 modifier, unsigned int rotation, 1729 u32 plane_pixel_rate, struct skl_wm_params *wp, 1730 int color_plane, unsigned int pan_x) 1731 { 1732 struct intel_display *display = to_intel_display(crtc_state); 1733 u32 interm_pbpl; 1734 1735 /* only planar format has two planes */ 1736 if (color_plane == 1 && 1737 !intel_format_info_is_yuv_semiplanar(format, modifier)) { 1738 drm_dbg_kms(display->drm, 1739 "Non planar format have single plane\n"); 1740 return -EINVAL; 1741 } 1742 1743 wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; 1744 wp->y_tiled = modifier != I915_FORMAT_MOD_X_TILED && 1745 intel_fb_is_tiled_modifier(modifier); 1746 wp->rc_surface = intel_fb_is_ccs_modifier(modifier); 1747 wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); 1748 1749 wp->width = width; 1750 if (color_plane == 1 && wp->is_planar) 1751 wp->width /= 2; 1752 1753 wp->cpp = format->cpp[color_plane]; 1754 wp->plane_pixel_rate = plane_pixel_rate; 1755 1756 if (DISPLAY_VER(display) >= 11 && 1757 modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1) 1758 wp->dbuf_block_size = 256; 1759 else 1760 wp->dbuf_block_size = 512; 1761 1762 if (drm_rotation_90_or_270(rotation)) { 1763 switch (wp->cpp) { 1764 case 1: 1765 wp->y_min_scanlines = 16; 1766 break; 1767 case 2: 1768 wp->y_min_scanlines = 8; 1769 break; 1770 case 4: 1771 wp->y_min_scanlines = 4; 1772 break; 1773 default: 1774 MISSING_CASE(wp->cpp); 1775 return -EINVAL; 1776 } 1777 } else { 1778 wp->y_min_scanlines = 4; 1779 } 1780 1781 if (skl_needs_memory_bw_wa(display)) 1782 wp->y_min_scanlines *= 2; 1783 1784 wp->plane_bytes_per_line = wp->width * wp->cpp; 1785 if (wp->y_tiled) { 1786 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line * 1787 wp->y_min_scanlines, 1788 wp->dbuf_block_size); 1789 1790 if (DISPLAY_VER(display) >= 30) 1791 interm_pbpl += (pan_x != 0); 1792 else if (DISPLAY_VER(display) >= 10) 1793 interm_pbpl++; 1794 1795 wp->plane_blocks_per_line = div_fixed16(interm_pbpl, 1796 wp->y_min_scanlines); 1797 } else { 1798 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 1799 wp->dbuf_block_size); 1800 1801 if (!wp->x_tiled || DISPLAY_VER(display) >= 10) 1802 interm_pbpl++; 1803 1804 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl); 1805 } 1806 1807 wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines, 1808 wp->plane_blocks_per_line); 1809 1810 wp->linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(crtc_state)); 1811 1812 return 0; 1813 } 1814 1815 static int 1816 skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state, 1817 const struct intel_plane_state *plane_state, 1818 struct skl_wm_params *wp, int color_plane) 1819 { 1820 const struct drm_framebuffer *fb = plane_state->hw.fb; 1821 int width; 1822 1823 /* 1824 * Src coordinates are already rotated by 270 degrees for 1825 * the 90/270 degree plane rotation cases (to match the 1826 * GTT mapping), hence no need to account for rotation here. 1827 */ 1828 width = drm_rect_width(&plane_state->uapi.src) >> 16; 1829 1830 return skl_compute_wm_params(crtc_state, width, 1831 fb->format, fb->modifier, 1832 plane_state->hw.rotation, 1833 intel_plane_pixel_rate(crtc_state, plane_state), 1834 wp, color_plane, 1835 plane_state->uapi.src.x1); 1836 } 1837 1838 static bool skl_wm_has_lines(struct intel_display *display, int level) 1839 { 1840 if (DISPLAY_VER(display) >= 10) 1841 return true; 1842 1843 /* The number of lines are ignored for the level 0 watermark. */ 1844 return level > 0; 1845 } 1846 1847 static int skl_wm_max_lines(struct intel_display *display) 1848 { 1849 if (DISPLAY_VER(display) >= 13) 1850 return 255; 1851 else 1852 return 31; 1853 } 1854 1855 static bool xe3_auto_min_alloc_capable(struct intel_plane *plane, int level) 1856 { 1857 struct intel_display *display = to_intel_display(plane); 1858 1859 return DISPLAY_VER(display) >= 30 && level == 0 && plane->id != PLANE_CURSOR; 1860 } 1861 1862 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, 1863 struct intel_plane *plane, 1864 int level, 1865 unsigned int latency, 1866 const struct skl_wm_params *wp, 1867 const struct skl_wm_level *result_prev, 1868 struct skl_wm_level *result /* out */) 1869 { 1870 struct intel_display *display = to_intel_display(crtc_state); 1871 uint_fixed_16_16_t method1, method2; 1872 uint_fixed_16_16_t selected_result; 1873 u32 blocks, lines, min_ddb_alloc = 0; 1874 1875 if (latency == 0 || 1876 (use_minimal_wm0_only(crtc_state, plane) && level > 0)) { 1877 /* reject it */ 1878 result->min_ddb_alloc = U16_MAX; 1879 return; 1880 } 1881 1882 method1 = skl_wm_method1(display, wp->plane_pixel_rate, 1883 wp->cpp, latency, wp->dbuf_block_size); 1884 method2 = skl_wm_method2(wp->plane_pixel_rate, 1885 crtc_state->hw.pipe_mode.crtc_htotal, 1886 latency, 1887 wp->plane_blocks_per_line); 1888 1889 if (wp->y_tiled) { 1890 selected_result = max_fixed16(method2, wp->y_tile_minimum); 1891 } else { 1892 if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal / 1893 wp->dbuf_block_size < 1) && 1894 (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) { 1895 selected_result = method2; 1896 } else if (latency >= wp->linetime_us) { 1897 if (DISPLAY_VER(display) == 9) 1898 selected_result = min_fixed16(method1, method2); 1899 else 1900 selected_result = method2; 1901 } else { 1902 selected_result = method1; 1903 } 1904 } 1905 1906 blocks = fixed16_to_u32_round_up(selected_result); 1907 if (DISPLAY_VER(display) < 30) 1908 blocks++; 1909 1910 /* 1911 * Lets have blocks at minimum equivalent to plane_blocks_per_line 1912 * as there will be at minimum one line for lines configuration. This 1913 * is a work around for FIFO underruns observed with resolutions like 1914 * 4k 60 Hz in single channel DRAM configurations. 1915 * 1916 * As per the Bspec 49325, if the ddb allocation can hold at least 1917 * one plane_blocks_per_line, we should have selected method2 in 1918 * the above logic. Assuming that modern versions have enough dbuf 1919 * and method2 guarantees blocks equivalent to at least 1 line, 1920 * select the blocks as plane_blocks_per_line. 1921 * 1922 * TODO: Revisit the logic when we have better understanding on DRAM 1923 * channels' impact on the level 0 memory latency and the relevant 1924 * wm calculations. 1925 */ 1926 if (skl_wm_has_lines(display, level)) 1927 blocks = max(blocks, 1928 fixed16_to_u32_round_up(wp->plane_blocks_per_line)); 1929 lines = div_round_up_fixed16(selected_result, 1930 wp->plane_blocks_per_line); 1931 1932 if (DISPLAY_VER(display) == 9) { 1933 /* Display WA #1125: skl,bxt,kbl */ 1934 if (level == 0 && wp->rc_surface) 1935 blocks += fixed16_to_u32_round_up(wp->y_tile_minimum); 1936 1937 /* Display WA #1126: skl,bxt,kbl */ 1938 if (level >= 1 && level <= 7) { 1939 if (wp->y_tiled) { 1940 blocks += fixed16_to_u32_round_up(wp->y_tile_minimum); 1941 lines += wp->y_min_scanlines; 1942 } else { 1943 blocks++; 1944 } 1945 1946 /* 1947 * Make sure result blocks for higher latency levels are 1948 * at least as high as level below the current level. 1949 * Assumption in DDB algorithm optimization for special 1950 * cases. Also covers Display WA #1125 for RC. 1951 */ 1952 if (result_prev->blocks > blocks) 1953 blocks = result_prev->blocks; 1954 } 1955 } 1956 1957 if (DISPLAY_VER(display) >= 11) { 1958 if (wp->y_tiled) { 1959 int extra_lines; 1960 1961 if (lines % wp->y_min_scanlines == 0) 1962 extra_lines = wp->y_min_scanlines; 1963 else 1964 extra_lines = wp->y_min_scanlines * 2 - 1965 lines % wp->y_min_scanlines; 1966 1967 min_ddb_alloc = mul_round_up_u32_fixed16(lines + extra_lines, 1968 wp->plane_blocks_per_line); 1969 } else { 1970 min_ddb_alloc = blocks + DIV_ROUND_UP(blocks, 10); 1971 } 1972 } 1973 1974 if (!skl_wm_has_lines(display, level)) 1975 lines = 0; 1976 1977 if (lines > skl_wm_max_lines(display)) { 1978 /* reject it */ 1979 result->min_ddb_alloc = U16_MAX; 1980 return; 1981 } 1982 1983 /* 1984 * If lines is valid, assume we can use this watermark level 1985 * for now. We'll come back and disable it after we calculate the 1986 * DDB allocation if it turns out we don't actually have enough 1987 * blocks to satisfy it. 1988 */ 1989 result->blocks = blocks; 1990 result->lines = lines; 1991 /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */ 1992 result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1; 1993 result->enable = true; 1994 result->auto_min_alloc_wm_enable = xe3_auto_min_alloc_capable(plane, level); 1995 1996 if (DISPLAY_VER(display) < 12 && display->sagv.block_time_us) 1997 result->can_sagv = latency >= display->sagv.block_time_us; 1998 } 1999 2000 static void 2001 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state, 2002 struct intel_plane *plane, 2003 const struct skl_wm_params *wm_params, 2004 struct skl_wm_level *levels) 2005 { 2006 struct intel_display *display = to_intel_display(crtc_state); 2007 struct skl_wm_level *result_prev = &levels[0]; 2008 int level; 2009 2010 for (level = 0; level < display->wm.num_levels; level++) { 2011 struct skl_wm_level *result = &levels[level]; 2012 unsigned int latency = skl_wm_latency(display, level, wm_params); 2013 2014 skl_compute_plane_wm(crtc_state, plane, level, latency, 2015 wm_params, result_prev, result); 2016 2017 result_prev = result; 2018 } 2019 } 2020 2021 static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state, 2022 struct intel_plane *plane, 2023 const struct skl_wm_params *wm_params, 2024 struct skl_plane_wm *plane_wm) 2025 { 2026 struct intel_display *display = to_intel_display(crtc_state); 2027 struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0; 2028 struct skl_wm_level *levels = plane_wm->wm; 2029 unsigned int latency = 0; 2030 2031 if (display->sagv.block_time_us) 2032 latency = display->sagv.block_time_us + 2033 skl_wm_latency(display, 0, wm_params); 2034 2035 skl_compute_plane_wm(crtc_state, plane, 0, latency, 2036 wm_params, &levels[0], 2037 sagv_wm); 2038 } 2039 2040 static void skl_compute_transition_wm(struct intel_display *display, 2041 struct skl_wm_level *trans_wm, 2042 const struct skl_wm_level *wm0, 2043 const struct skl_wm_params *wp) 2044 { 2045 u16 trans_min, trans_amount, trans_y_tile_min; 2046 u16 wm0_blocks, trans_offset, blocks; 2047 2048 /* Transition WM don't make any sense if ipc is disabled */ 2049 if (!skl_watermark_ipc_enabled(display)) 2050 return; 2051 2052 /* 2053 * WaDisableTWM:skl,kbl,cfl,bxt 2054 * Transition WM are not recommended by HW team for GEN9 2055 */ 2056 if (DISPLAY_VER(display) == 9) 2057 return; 2058 2059 if (DISPLAY_VER(display) >= 11) 2060 trans_min = 4; 2061 else 2062 trans_min = 14; 2063 2064 /* Display WA #1140: glk,cnl */ 2065 if (DISPLAY_VER(display) == 10) 2066 trans_amount = 0; 2067 else 2068 trans_amount = 10; /* This is configurable amount */ 2069 2070 trans_offset = trans_min + trans_amount; 2071 2072 /* 2073 * The spec asks for Selected Result Blocks for wm0 (the real value), 2074 * not Result Blocks (the integer value). Pay attention to the capital 2075 * letters. The value wm_l0->blocks is actually Result Blocks, but 2076 * since Result Blocks is the ceiling of Selected Result Blocks plus 1, 2077 * and since we later will have to get the ceiling of the sum in the 2078 * transition watermarks calculation, we can just pretend Selected 2079 * Result Blocks is Result Blocks minus 1 and it should work for the 2080 * current platforms. 2081 */ 2082 wm0_blocks = wm0->blocks - 1; 2083 2084 if (wp->y_tiled) { 2085 trans_y_tile_min = 2086 (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum); 2087 blocks = max(wm0_blocks, trans_y_tile_min) + trans_offset; 2088 } else { 2089 blocks = wm0_blocks + trans_offset; 2090 } 2091 blocks++; 2092 2093 /* 2094 * Just assume we can enable the transition watermark. After 2095 * computing the DDB we'll come back and disable it if that 2096 * assumption turns out to be false. 2097 */ 2098 trans_wm->blocks = blocks; 2099 trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1); 2100 trans_wm->enable = true; 2101 } 2102 2103 static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state, 2104 const struct intel_plane_state *plane_state, 2105 struct intel_plane *plane, int color_plane) 2106 { 2107 struct intel_display *display = to_intel_display(crtc_state); 2108 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id]; 2109 struct skl_wm_params wm_params; 2110 int ret; 2111 2112 ret = skl_compute_plane_wm_params(crtc_state, plane_state, 2113 &wm_params, color_plane); 2114 if (ret) 2115 return ret; 2116 2117 skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm); 2118 2119 skl_compute_transition_wm(display, &wm->trans_wm, 2120 &wm->wm[0], &wm_params); 2121 2122 if (DISPLAY_VER(display) >= 12) { 2123 tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm); 2124 2125 skl_compute_transition_wm(display, &wm->sagv.trans_wm, 2126 &wm->sagv.wm0, &wm_params); 2127 } 2128 2129 return 0; 2130 } 2131 2132 static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state, 2133 const struct intel_plane_state *plane_state, 2134 struct intel_plane *plane) 2135 { 2136 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id]; 2137 struct skl_wm_params wm_params; 2138 int ret; 2139 2140 wm->is_planar = true; 2141 2142 /* uv plane watermarks must also be validated for NV12/Planar */ 2143 ret = skl_compute_plane_wm_params(crtc_state, plane_state, 2144 &wm_params, 1); 2145 if (ret) 2146 return ret; 2147 2148 skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm); 2149 2150 return 0; 2151 } 2152 2153 static int skl_build_plane_wm(struct intel_crtc_state *crtc_state, 2154 const struct intel_plane_state *plane_state) 2155 { 2156 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2157 enum plane_id plane_id = plane->id; 2158 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; 2159 const struct drm_framebuffer *fb = plane_state->hw.fb; 2160 int ret; 2161 2162 memset(wm, 0, sizeof(*wm)); 2163 2164 if (!intel_wm_plane_visible(crtc_state, plane_state)) 2165 return 0; 2166 2167 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2168 plane, 0); 2169 if (ret) 2170 return ret; 2171 2172 if (fb->format->is_yuv && fb->format->num_planes > 1) { 2173 ret = skl_build_plane_wm_uv(crtc_state, plane_state, 2174 plane); 2175 if (ret) 2176 return ret; 2177 } 2178 2179 return 0; 2180 } 2181 2182 static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, 2183 const struct intel_plane_state *plane_state) 2184 { 2185 struct intel_display *display = to_intel_display(plane_state); 2186 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2187 enum plane_id plane_id = plane->id; 2188 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; 2189 int ret; 2190 2191 /* Watermarks calculated on UV plane */ 2192 if (plane_state->is_y_plane) 2193 return 0; 2194 2195 memset(wm, 0, sizeof(*wm)); 2196 2197 if (plane_state->planar_linked_plane) { 2198 const struct drm_framebuffer *fb = plane_state->hw.fb; 2199 2200 drm_WARN_ON(display->drm, 2201 !intel_wm_plane_visible(crtc_state, plane_state)); 2202 drm_WARN_ON(display->drm, !fb->format->is_yuv || 2203 fb->format->num_planes == 1); 2204 2205 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2206 plane_state->planar_linked_plane, 0); 2207 if (ret) 2208 return ret; 2209 2210 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2211 plane, 1); 2212 if (ret) 2213 return ret; 2214 } else if (intel_wm_plane_visible(crtc_state, plane_state)) { 2215 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2216 plane, 0); 2217 if (ret) 2218 return ret; 2219 } 2220 2221 return 0; 2222 } 2223 2224 static int 2225 cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) 2226 { 2227 struct intel_display *display = to_intel_display(crtc_state); 2228 struct intel_atomic_state *state = 2229 to_intel_atomic_state(crtc_state->uapi.state); 2230 const struct intel_cdclk_state *cdclk_state; 2231 2232 cdclk_state = intel_atomic_get_cdclk_state(state); 2233 if (IS_ERR(cdclk_state)) { 2234 drm_WARN_ON(display->drm, PTR_ERR(cdclk_state)); 2235 return 1; 2236 } 2237 2238 return min(1, DIV_ROUND_UP(crtc_state->pixel_rate, 2239 2 * cdclk_state->logical.cdclk)); 2240 } 2241 2242 static int 2243 dsc_prefill_latency(const struct intel_crtc_state *crtc_state) 2244 { 2245 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2246 const struct intel_crtc_scaler_state *scaler_state = 2247 &crtc_state->scaler_state; 2248 int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, 2249 crtc_state->hw.adjusted_mode.clock); 2250 int num_scaler_users = hweight32(scaler_state->scaler_users); 2251 int chroma_downscaling_factor = 2252 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; 2253 u32 dsc_prefill_latency = 0; 2254 2255 if (!crtc_state->dsc.compression_enable || 2256 !num_scaler_users || 2257 num_scaler_users > crtc->num_scalers) 2258 return dsc_prefill_latency; 2259 2260 dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10); 2261 2262 for (int i = 0; i < num_scaler_users; i++) { 2263 u64 hscale_k, vscale_k; 2264 2265 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16); 2266 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16); 2267 dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k, 2268 1000000); 2269 } 2270 2271 dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state); 2272 2273 return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency); 2274 } 2275 2276 static int 2277 scaler_prefill_latency(const struct intel_crtc_state *crtc_state) 2278 { 2279 const struct intel_crtc_scaler_state *scaler_state = 2280 &crtc_state->scaler_state; 2281 int num_scaler_users = hweight32(scaler_state->scaler_users); 2282 int scaler_prefill_latency = 0; 2283 int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, 2284 crtc_state->hw.adjusted_mode.clock); 2285 2286 if (!num_scaler_users) 2287 return scaler_prefill_latency; 2288 2289 scaler_prefill_latency = 4 * linetime; 2290 2291 if (num_scaler_users > 1) { 2292 u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16); 2293 u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16); 2294 int chroma_downscaling_factor = 2295 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; 2296 int latency; 2297 2298 latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k * 2299 chroma_downscaling_factor), 1000000); 2300 scaler_prefill_latency += latency; 2301 } 2302 2303 scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state); 2304 2305 return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency); 2306 } 2307 2308 static bool 2309 skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, 2310 int wm0_lines, int latency) 2311 { 2312 const struct drm_display_mode *adjusted_mode = 2313 &crtc_state->hw.adjusted_mode; 2314 2315 return crtc_state->framestart_delay + 2316 intel_usecs_to_scanlines(adjusted_mode, latency) + 2317 scaler_prefill_latency(crtc_state) + 2318 dsc_prefill_latency(crtc_state) + 2319 wm0_lines > 2320 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start; 2321 } 2322 2323 static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state) 2324 { 2325 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2326 enum plane_id plane_id; 2327 int wm0_lines = 0; 2328 2329 for_each_plane_id_on_crtc(crtc, plane_id) { 2330 const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; 2331 2332 /* FIXME what about !skl_wm_has_lines() platforms? */ 2333 wm0_lines = max_t(int, wm0_lines, wm->wm[0].lines); 2334 } 2335 2336 return wm0_lines; 2337 } 2338 2339 static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state, 2340 int wm0_lines) 2341 { 2342 struct intel_display *display = to_intel_display(crtc_state); 2343 int level; 2344 2345 for (level = display->wm.num_levels - 1; level >= 0; level--) { 2346 int latency; 2347 2348 /* FIXME should we care about the latency w/a's? */ 2349 latency = skl_wm_latency(display, level, NULL); 2350 if (latency == 0) 2351 continue; 2352 2353 /* FIXME is it correct to use 0 latency for wm0 here? */ 2354 if (level == 0) 2355 latency = 0; 2356 2357 if (!skl_is_vblank_too_short(crtc_state, wm0_lines, latency)) 2358 return level; 2359 } 2360 2361 return -EINVAL; 2362 } 2363 2364 static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state) 2365 { 2366 struct intel_display *display = to_intel_display(crtc_state); 2367 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2368 int wm0_lines, level; 2369 2370 if (!crtc_state->hw.active) 2371 return 0; 2372 2373 wm0_lines = skl_max_wm0_lines(crtc_state); 2374 2375 level = skl_max_wm_level_for_vblank(crtc_state, wm0_lines); 2376 if (level < 0) 2377 return level; 2378 2379 /* 2380 * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_* 2381 * based on whether we're limited by the vblank duration. 2382 */ 2383 crtc_state->wm_level_disabled = level < display->wm.num_levels - 1; 2384 2385 for (level++; level < display->wm.num_levels; level++) { 2386 enum plane_id plane_id; 2387 2388 for_each_plane_id_on_crtc(crtc, plane_id) { 2389 struct skl_plane_wm *wm = 2390 &crtc_state->wm.skl.optimal.planes[plane_id]; 2391 2392 /* 2393 * FIXME just clear enable or flag the entire 2394 * thing as bad via min_ddb_alloc=U16_MAX? 2395 */ 2396 wm->wm[level].enable = false; 2397 wm->uv_wm[level].enable = false; 2398 } 2399 } 2400 2401 if (DISPLAY_VER(display) >= 12 && 2402 display->sagv.block_time_us && 2403 skl_is_vblank_too_short(crtc_state, wm0_lines, 2404 display->sagv.block_time_us)) { 2405 enum plane_id plane_id; 2406 2407 for_each_plane_id_on_crtc(crtc, plane_id) { 2408 struct skl_plane_wm *wm = 2409 &crtc_state->wm.skl.optimal.planes[plane_id]; 2410 2411 wm->sagv.wm0.enable = false; 2412 wm->sagv.trans_wm.enable = false; 2413 } 2414 } 2415 2416 return 0; 2417 } 2418 2419 static int skl_build_pipe_wm(struct intel_atomic_state *state, 2420 struct intel_crtc *crtc) 2421 { 2422 struct intel_display *display = to_intel_display(crtc); 2423 struct intel_crtc_state *crtc_state = 2424 intel_atomic_get_new_crtc_state(state, crtc); 2425 const struct intel_plane_state *plane_state; 2426 struct intel_plane *plane; 2427 int ret, i; 2428 2429 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 2430 /* 2431 * FIXME should perhaps check {old,new}_plane_crtc->hw.crtc 2432 * instead but we don't populate that correctly for NV12 Y 2433 * planes so for now hack this. 2434 */ 2435 if (plane->pipe != crtc->pipe) 2436 continue; 2437 2438 if (DISPLAY_VER(display) >= 11) 2439 ret = icl_build_plane_wm(crtc_state, plane_state); 2440 else 2441 ret = skl_build_plane_wm(crtc_state, plane_state); 2442 if (ret) 2443 return ret; 2444 } 2445 2446 crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw; 2447 2448 return skl_wm_check_vblank(crtc_state); 2449 } 2450 2451 static bool skl_wm_level_equals(const struct skl_wm_level *l1, 2452 const struct skl_wm_level *l2) 2453 { 2454 return l1->enable == l2->enable && 2455 l1->ignore_lines == l2->ignore_lines && 2456 l1->lines == l2->lines && 2457 l1->blocks == l2->blocks && 2458 l1->auto_min_alloc_wm_enable == l2->auto_min_alloc_wm_enable; 2459 } 2460 2461 static bool skl_plane_wm_equals(struct intel_display *display, 2462 const struct skl_plane_wm *wm1, 2463 const struct skl_plane_wm *wm2) 2464 { 2465 int level; 2466 2467 for (level = 0; level < display->wm.num_levels; level++) { 2468 /* 2469 * We don't check uv_wm as the hardware doesn't actually 2470 * use it. It only gets used for calculating the required 2471 * ddb allocation. 2472 */ 2473 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level])) 2474 return false; 2475 } 2476 2477 return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) && 2478 skl_wm_level_equals(&wm1->sagv.wm0, &wm2->sagv.wm0) && 2479 skl_wm_level_equals(&wm1->sagv.trans_wm, &wm2->sagv.trans_wm); 2480 } 2481 2482 static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, 2483 const struct skl_ddb_entry *b) 2484 { 2485 return a->start < b->end && b->start < a->end; 2486 } 2487 2488 static void skl_ddb_entry_union(struct skl_ddb_entry *a, 2489 const struct skl_ddb_entry *b) 2490 { 2491 if (a->end && b->end) { 2492 a->start = min(a->start, b->start); 2493 a->end = max(a->end, b->end); 2494 } else if (b->end) { 2495 a->start = b->start; 2496 a->end = b->end; 2497 } 2498 } 2499 2500 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, 2501 const struct skl_ddb_entry *entries, 2502 int num_entries, int ignore_idx) 2503 { 2504 int i; 2505 2506 for (i = 0; i < num_entries; i++) { 2507 if (i != ignore_idx && 2508 skl_ddb_entries_overlap(ddb, &entries[i])) 2509 return true; 2510 } 2511 2512 return false; 2513 } 2514 2515 static int 2516 skl_ddb_add_affected_planes(struct intel_atomic_state *state, 2517 struct intel_crtc *crtc) 2518 { 2519 struct intel_display *display = to_intel_display(state); 2520 const struct intel_crtc_state *old_crtc_state = 2521 intel_atomic_get_old_crtc_state(state, crtc); 2522 struct intel_crtc_state *new_crtc_state = 2523 intel_atomic_get_new_crtc_state(state, crtc); 2524 struct intel_plane *plane; 2525 2526 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 2527 struct intel_plane_state *plane_state; 2528 enum plane_id plane_id = plane->id; 2529 2530 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id], 2531 &new_crtc_state->wm.skl.plane_ddb[plane_id]) && 2532 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id], 2533 &new_crtc_state->wm.skl.plane_ddb_y[plane_id])) 2534 continue; 2535 2536 if (new_crtc_state->do_async_flip) { 2537 drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change DDB during async flip\n", 2538 plane->base.base.id, plane->base.name); 2539 return -EINVAL; 2540 } 2541 2542 plane_state = intel_atomic_get_plane_state(state, plane); 2543 if (IS_ERR(plane_state)) 2544 return PTR_ERR(plane_state); 2545 2546 new_crtc_state->update_planes |= BIT(plane_id); 2547 new_crtc_state->async_flip_planes = 0; 2548 new_crtc_state->do_async_flip = false; 2549 } 2550 2551 return 0; 2552 } 2553 2554 static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state) 2555 { 2556 struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev); 2557 u8 enabled_slices; 2558 enum pipe pipe; 2559 2560 /* 2561 * FIXME: For now we always enable slice S1 as per 2562 * the Bspec display initialization sequence. 2563 */ 2564 enabled_slices = BIT(DBUF_S1); 2565 2566 for_each_pipe(display, pipe) 2567 enabled_slices |= dbuf_state->slices[pipe]; 2568 2569 return enabled_slices; 2570 } 2571 2572 static int 2573 skl_compute_ddb(struct intel_atomic_state *state) 2574 { 2575 struct intel_display *display = to_intel_display(state); 2576 const struct intel_dbuf_state *old_dbuf_state; 2577 struct intel_dbuf_state *new_dbuf_state = NULL; 2578 struct intel_crtc_state *new_crtc_state; 2579 struct intel_crtc *crtc; 2580 int ret, i; 2581 2582 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2583 new_dbuf_state = intel_atomic_get_dbuf_state(state); 2584 if (IS_ERR(new_dbuf_state)) 2585 return PTR_ERR(new_dbuf_state); 2586 2587 old_dbuf_state = intel_atomic_get_old_dbuf_state(state); 2588 break; 2589 } 2590 2591 if (!new_dbuf_state) 2592 return 0; 2593 2594 new_dbuf_state->active_pipes = 2595 intel_calc_active_pipes(state, old_dbuf_state->active_pipes); 2596 2597 if (old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) { 2598 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 2599 if (ret) 2600 return ret; 2601 } 2602 2603 if (HAS_MBUS_JOINING(display)) { 2604 new_dbuf_state->joined_mbus = 2605 adlp_check_mbus_joined(new_dbuf_state->active_pipes); 2606 2607 if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) { 2608 ret = intel_cdclk_state_set_joined_mbus(state, new_dbuf_state->joined_mbus); 2609 if (ret) 2610 return ret; 2611 } 2612 } 2613 2614 for_each_intel_crtc(display->drm, crtc) { 2615 enum pipe pipe = crtc->pipe; 2616 2617 new_dbuf_state->slices[pipe] = 2618 skl_compute_dbuf_slices(crtc, new_dbuf_state->active_pipes, 2619 new_dbuf_state->joined_mbus); 2620 2621 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe]) 2622 continue; 2623 2624 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 2625 if (ret) 2626 return ret; 2627 } 2628 2629 new_dbuf_state->enabled_slices = intel_dbuf_enabled_slices(new_dbuf_state); 2630 2631 if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices || 2632 old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) { 2633 ret = intel_atomic_serialize_global_state(&new_dbuf_state->base); 2634 if (ret) 2635 return ret; 2636 2637 drm_dbg_kms(display->drm, 2638 "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n", 2639 old_dbuf_state->enabled_slices, 2640 new_dbuf_state->enabled_slices, 2641 DISPLAY_INFO(display)->dbuf.slice_mask, 2642 str_yes_no(old_dbuf_state->joined_mbus), 2643 str_yes_no(new_dbuf_state->joined_mbus)); 2644 } 2645 2646 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2647 enum pipe pipe = crtc->pipe; 2648 2649 new_dbuf_state->weight[pipe] = intel_crtc_ddb_weight(new_crtc_state); 2650 2651 if (old_dbuf_state->weight[pipe] == new_dbuf_state->weight[pipe]) 2652 continue; 2653 2654 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 2655 if (ret) 2656 return ret; 2657 } 2658 2659 for_each_intel_crtc(display->drm, crtc) { 2660 ret = skl_crtc_allocate_ddb(state, crtc); 2661 if (ret) 2662 return ret; 2663 } 2664 2665 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2666 ret = skl_crtc_allocate_plane_ddb(state, crtc); 2667 if (ret) 2668 return ret; 2669 2670 ret = skl_ddb_add_affected_planes(state, crtc); 2671 if (ret) 2672 return ret; 2673 } 2674 2675 return 0; 2676 } 2677 2678 static char enast(bool enable) 2679 { 2680 return enable ? '*' : ' '; 2681 } 2682 2683 static void 2684 skl_print_wm_changes(struct intel_atomic_state *state) 2685 { 2686 struct intel_display *display = to_intel_display(state); 2687 const struct intel_crtc_state *old_crtc_state; 2688 const struct intel_crtc_state *new_crtc_state; 2689 struct intel_plane *plane; 2690 struct intel_crtc *crtc; 2691 int i; 2692 2693 if (!drm_debug_enabled(DRM_UT_KMS)) 2694 return; 2695 2696 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 2697 new_crtc_state, i) { 2698 const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm; 2699 2700 old_pipe_wm = &old_crtc_state->wm.skl.optimal; 2701 new_pipe_wm = &new_crtc_state->wm.skl.optimal; 2702 2703 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 2704 enum plane_id plane_id = plane->id; 2705 const struct skl_ddb_entry *old, *new; 2706 2707 old = &old_crtc_state->wm.skl.plane_ddb[plane_id]; 2708 new = &new_crtc_state->wm.skl.plane_ddb[plane_id]; 2709 2710 if (skl_ddb_entry_equal(old, new)) 2711 continue; 2712 2713 drm_dbg_kms(display->drm, 2714 "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n", 2715 plane->base.base.id, plane->base.name, 2716 old->start, old->end, new->start, new->end, 2717 skl_ddb_entry_size(old), skl_ddb_entry_size(new)); 2718 } 2719 2720 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 2721 enum plane_id plane_id = plane->id; 2722 const struct skl_plane_wm *old_wm, *new_wm; 2723 2724 old_wm = &old_pipe_wm->planes[plane_id]; 2725 new_wm = &new_pipe_wm->planes[plane_id]; 2726 2727 if (skl_plane_wm_equals(display, old_wm, new_wm)) 2728 continue; 2729 2730 drm_dbg_kms(display->drm, 2731 "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm" 2732 " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n", 2733 plane->base.base.id, plane->base.name, 2734 enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable), 2735 enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable), 2736 enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable), 2737 enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable), 2738 enast(old_wm->trans_wm.enable), 2739 enast(old_wm->sagv.wm0.enable), 2740 enast(old_wm->sagv.trans_wm.enable), 2741 enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable), 2742 enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable), 2743 enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable), 2744 enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable), 2745 enast(new_wm->trans_wm.enable), 2746 enast(new_wm->sagv.wm0.enable), 2747 enast(new_wm->sagv.trans_wm.enable)); 2748 2749 drm_dbg_kms(display->drm, 2750 "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d" 2751 " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n", 2752 plane->base.base.id, plane->base.name, 2753 enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines, 2754 enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines, 2755 enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines, 2756 enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines, 2757 enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines, 2758 enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines, 2759 enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines, 2760 enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines, 2761 enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines, 2762 enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines, 2763 enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines, 2764 enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines, 2765 enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines, 2766 enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines, 2767 enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines, 2768 enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines, 2769 enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines, 2770 enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines, 2771 enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines, 2772 enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines, 2773 enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines, 2774 enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines); 2775 2776 drm_dbg_kms(display->drm, 2777 "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" 2778 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", 2779 plane->base.base.id, plane->base.name, 2780 old_wm->wm[0].blocks, old_wm->wm[1].blocks, 2781 old_wm->wm[2].blocks, old_wm->wm[3].blocks, 2782 old_wm->wm[4].blocks, old_wm->wm[5].blocks, 2783 old_wm->wm[6].blocks, old_wm->wm[7].blocks, 2784 old_wm->trans_wm.blocks, 2785 old_wm->sagv.wm0.blocks, 2786 old_wm->sagv.trans_wm.blocks, 2787 new_wm->wm[0].blocks, new_wm->wm[1].blocks, 2788 new_wm->wm[2].blocks, new_wm->wm[3].blocks, 2789 new_wm->wm[4].blocks, new_wm->wm[5].blocks, 2790 new_wm->wm[6].blocks, new_wm->wm[7].blocks, 2791 new_wm->trans_wm.blocks, 2792 new_wm->sagv.wm0.blocks, 2793 new_wm->sagv.trans_wm.blocks); 2794 2795 drm_dbg_kms(display->drm, 2796 "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" 2797 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", 2798 plane->base.base.id, plane->base.name, 2799 old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc, 2800 old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc, 2801 old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc, 2802 old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc, 2803 old_wm->trans_wm.min_ddb_alloc, 2804 old_wm->sagv.wm0.min_ddb_alloc, 2805 old_wm->sagv.trans_wm.min_ddb_alloc, 2806 new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc, 2807 new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc, 2808 new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc, 2809 new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc, 2810 new_wm->trans_wm.min_ddb_alloc, 2811 new_wm->sagv.wm0.min_ddb_alloc, 2812 new_wm->sagv.trans_wm.min_ddb_alloc); 2813 } 2814 } 2815 } 2816 2817 static bool skl_plane_selected_wm_equals(struct intel_plane *plane, 2818 const struct skl_pipe_wm *old_pipe_wm, 2819 const struct skl_pipe_wm *new_pipe_wm) 2820 { 2821 struct intel_display *display = to_intel_display(plane); 2822 int level; 2823 2824 for (level = 0; level < display->wm.num_levels; level++) { 2825 /* 2826 * We don't check uv_wm as the hardware doesn't actually 2827 * use it. It only gets used for calculating the required 2828 * ddb allocation. 2829 */ 2830 if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level), 2831 skl_plane_wm_level(new_pipe_wm, plane->id, level))) 2832 return false; 2833 } 2834 2835 if (HAS_HW_SAGV_WM(display)) { 2836 const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id]; 2837 const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id]; 2838 2839 if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) || 2840 !skl_wm_level_equals(&old_wm->sagv.trans_wm, &new_wm->sagv.trans_wm)) 2841 return false; 2842 } 2843 2844 return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id), 2845 skl_plane_trans_wm(new_pipe_wm, plane->id)); 2846 } 2847 2848 /* 2849 * To make sure the cursor watermark registers are always consistent 2850 * with our computed state the following scenario needs special 2851 * treatment: 2852 * 2853 * 1. enable cursor 2854 * 2. move cursor entirely offscreen 2855 * 3. disable cursor 2856 * 2857 * Step 2. does call .disable_plane() but does not zero the watermarks 2858 * (since we consider an offscreen cursor still active for the purposes 2859 * of watermarks). Step 3. would not normally call .disable_plane() 2860 * because the actual plane visibility isn't changing, and we don't 2861 * deallocate the cursor ddb until the pipe gets disabled. So we must 2862 * force step 3. to call .disable_plane() to update the watermark 2863 * registers properly. 2864 * 2865 * Other planes do not suffer from this issues as their watermarks are 2866 * calculated based on the actual plane visibility. The only time this 2867 * can trigger for the other planes is during the initial readout as the 2868 * default value of the watermarks registers is not zero. 2869 */ 2870 static int skl_wm_add_affected_planes(struct intel_atomic_state *state, 2871 struct intel_crtc *crtc) 2872 { 2873 struct intel_display *display = to_intel_display(state); 2874 const struct intel_crtc_state *old_crtc_state = 2875 intel_atomic_get_old_crtc_state(state, crtc); 2876 struct intel_crtc_state *new_crtc_state = 2877 intel_atomic_get_new_crtc_state(state, crtc); 2878 struct intel_plane *plane; 2879 2880 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 2881 struct intel_plane_state *plane_state; 2882 enum plane_id plane_id = plane->id; 2883 2884 /* 2885 * Force a full wm update for every plane on modeset. 2886 * Required because the reset value of the wm registers 2887 * is non-zero, whereas we want all disabled planes to 2888 * have zero watermarks. So if we turn off the relevant 2889 * power well the hardware state will go out of sync 2890 * with the software state. 2891 */ 2892 if (!intel_crtc_needs_modeset(new_crtc_state) && 2893 skl_plane_selected_wm_equals(plane, 2894 &old_crtc_state->wm.skl.optimal, 2895 &new_crtc_state->wm.skl.optimal)) 2896 continue; 2897 2898 if (new_crtc_state->do_async_flip) { 2899 drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change watermarks during async flip\n", 2900 plane->base.base.id, plane->base.name); 2901 return -EINVAL; 2902 } 2903 2904 plane_state = intel_atomic_get_plane_state(state, plane); 2905 if (IS_ERR(plane_state)) 2906 return PTR_ERR(plane_state); 2907 2908 new_crtc_state->update_planes |= BIT(plane_id); 2909 new_crtc_state->async_flip_planes = 0; 2910 new_crtc_state->do_async_flip = false; 2911 } 2912 2913 return 0; 2914 } 2915 2916 /* 2917 * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline: 2918 * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from 2919 * watermark level1 and up and above. If watermark level 1 is 2920 * invalid program it with all 1's. 2921 * Program PKG_C_LATENCY Added Wake Time = DSB execution time 2922 * If Variable Refresh Rate where Vmin != Vmax != Flipline: 2923 * Program DEEP PKG_C_LATENCY Pkg C with all 1's. 2924 * Program PKG_C_LATENCY Added Wake Time = 0 2925 */ 2926 void 2927 intel_program_dpkgc_latency(struct intel_atomic_state *state) 2928 { 2929 struct intel_display *display = to_intel_display(state); 2930 struct intel_crtc *crtc; 2931 struct intel_crtc_state *new_crtc_state; 2932 u32 latency = LNL_PKG_C_LATENCY_MASK; 2933 u32 added_wake_time = 0; 2934 u32 max_linetime = 0; 2935 u32 clear, val; 2936 bool fixed_refresh_rate = false; 2937 int i; 2938 2939 if (DISPLAY_VER(display) < 20) 2940 return; 2941 2942 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2943 if (!new_crtc_state->vrr.enable || 2944 (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax && 2945 new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline)) 2946 fixed_refresh_rate = true; 2947 2948 max_linetime = max(new_crtc_state->linetime, max_linetime); 2949 } 2950 2951 if (fixed_refresh_rate) { 2952 added_wake_time = DSB_EXE_TIME + 2953 display->sagv.block_time_us; 2954 2955 latency = skl_watermark_max_latency(display, 1); 2956 2957 /* Wa_22020432604 */ 2958 if ((DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30) && !latency) { 2959 latency += added_wake_time; 2960 added_wake_time = 0; 2961 } 2962 2963 /* Wa_22020299601 */ 2964 if ((latency && max_linetime) && 2965 (DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30)) { 2966 latency = max_linetime * DIV_ROUND_UP(latency, max_linetime); 2967 } else if (!latency) { 2968 latency = LNL_PKG_C_LATENCY_MASK; 2969 } 2970 } 2971 2972 clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; 2973 val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, latency) | 2974 REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time); 2975 2976 intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val); 2977 } 2978 2979 static int 2980 skl_compute_wm(struct intel_atomic_state *state) 2981 { 2982 struct intel_display *display = to_intel_display(state); 2983 struct intel_crtc *crtc; 2984 struct intel_crtc_state __maybe_unused *new_crtc_state; 2985 int ret, i; 2986 2987 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2988 ret = skl_build_pipe_wm(state, crtc); 2989 if (ret) 2990 return ret; 2991 } 2992 2993 ret = skl_compute_ddb(state); 2994 if (ret) 2995 return ret; 2996 2997 /* 2998 * skl_compute_ddb() will have adjusted the final watermarks 2999 * based on how much ddb is available. Now we can actually 3000 * check if the final watermarks changed. 3001 */ 3002 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 3003 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal; 3004 3005 /* 3006 * We store use_sagv_wm in the crtc state rather than relying on 3007 * that bw state since we have no convenient way to get at the 3008 * latter from the plane commit hooks (especially in the legacy 3009 * cursor case). 3010 * 3011 * drm_atomic_check_only() gets upset if we pull more crtcs 3012 * into the state, so we have to calculate this based on the 3013 * individual intel_crtc_can_enable_sagv() rather than 3014 * the overall intel_can_enable_sagv(). Otherwise the 3015 * crtcs not included in the commit would not switch to the 3016 * SAGV watermarks when we are about to enable SAGV, and that 3017 * would lead to underruns. This does mean extra power draw 3018 * when only a subset of the crtcs are blocking SAGV as the 3019 * other crtcs can't be allowed to use the more optimal 3020 * normal (ie. non-SAGV) watermarks. 3021 */ 3022 pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(display) && 3023 DISPLAY_VER(display) >= 12 && 3024 intel_crtc_can_enable_sagv(new_crtc_state); 3025 3026 ret = skl_wm_add_affected_planes(state, crtc); 3027 if (ret) 3028 return ret; 3029 } 3030 3031 skl_print_wm_changes(state); 3032 3033 return 0; 3034 } 3035 3036 static void skl_wm_level_from_reg_val(struct intel_display *display, 3037 u32 val, struct skl_wm_level *level) 3038 { 3039 level->enable = val & PLANE_WM_EN; 3040 level->ignore_lines = val & PLANE_WM_IGNORE_LINES; 3041 level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val); 3042 level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); 3043 level->auto_min_alloc_wm_enable = DISPLAY_VER(display) >= 30 ? 3044 val & PLANE_WM_AUTO_MIN_ALLOC_EN : 0; 3045 } 3046 3047 static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, 3048 struct skl_pipe_wm *out) 3049 { 3050 struct intel_display *display = to_intel_display(crtc); 3051 enum pipe pipe = crtc->pipe; 3052 enum plane_id plane_id; 3053 int level; 3054 u32 val; 3055 3056 for_each_plane_id_on_crtc(crtc, plane_id) { 3057 struct skl_plane_wm *wm = &out->planes[plane_id]; 3058 3059 for (level = 0; level < display->wm.num_levels; level++) { 3060 if (plane_id != PLANE_CURSOR) 3061 val = intel_de_read(display, PLANE_WM(pipe, plane_id, level)); 3062 else 3063 val = intel_de_read(display, CUR_WM(pipe, level)); 3064 3065 skl_wm_level_from_reg_val(display, val, &wm->wm[level]); 3066 } 3067 3068 if (plane_id != PLANE_CURSOR) 3069 val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id)); 3070 else 3071 val = intel_de_read(display, CUR_WM_TRANS(pipe)); 3072 3073 skl_wm_level_from_reg_val(display, val, &wm->trans_wm); 3074 3075 if (HAS_HW_SAGV_WM(display)) { 3076 if (plane_id != PLANE_CURSOR) 3077 val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id)); 3078 else 3079 val = intel_de_read(display, CUR_WM_SAGV(pipe)); 3080 3081 skl_wm_level_from_reg_val(display, val, &wm->sagv.wm0); 3082 3083 if (plane_id != PLANE_CURSOR) 3084 val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id)); 3085 else 3086 val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe)); 3087 3088 skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm); 3089 } else if (DISPLAY_VER(display) >= 12) { 3090 wm->sagv.wm0 = wm->wm[0]; 3091 wm->sagv.trans_wm = wm->trans_wm; 3092 } 3093 } 3094 } 3095 3096 static void skl_wm_get_hw_state(struct intel_display *display) 3097 { 3098 struct intel_dbuf_state *dbuf_state = 3099 to_intel_dbuf_state(display->dbuf.obj.state); 3100 struct intel_crtc *crtc; 3101 3102 if (HAS_MBUS_JOINING(display)) 3103 dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 3104 3105 dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw); 3106 dbuf_state->active_pipes = 0; 3107 3108 for_each_intel_crtc(display->drm, crtc) { 3109 struct intel_crtc_state *crtc_state = 3110 to_intel_crtc_state(crtc->base.state); 3111 enum pipe pipe = crtc->pipe; 3112 unsigned int mbus_offset; 3113 enum plane_id plane_id; 3114 u8 slices; 3115 3116 memset(&crtc_state->wm.skl.optimal, 0, 3117 sizeof(crtc_state->wm.skl.optimal)); 3118 if (crtc_state->hw.active) { 3119 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); 3120 dbuf_state->active_pipes |= BIT(pipe); 3121 } 3122 crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal; 3123 3124 memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe])); 3125 3126 for_each_plane_id_on_crtc(crtc, plane_id) { 3127 struct skl_ddb_entry *ddb = 3128 &crtc_state->wm.skl.plane_ddb[plane_id]; 3129 struct skl_ddb_entry *ddb_y = 3130 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 3131 u16 *min_ddb = 3132 &crtc_state->wm.skl.plane_min_ddb[plane_id]; 3133 u16 *interim_ddb = 3134 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; 3135 3136 if (!crtc_state->hw.active) 3137 continue; 3138 3139 skl_ddb_get_hw_plane_state(display, crtc->pipe, 3140 plane_id, ddb, ddb_y, 3141 min_ddb, interim_ddb); 3142 3143 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb); 3144 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y); 3145 } 3146 3147 dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state); 3148 3149 /* 3150 * Used for checking overlaps, so we need absolute 3151 * offsets instead of MBUS relative offsets. 3152 */ 3153 slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, 3154 dbuf_state->joined_mbus); 3155 mbus_offset = mbus_ddb_offset(display, slices); 3156 crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start; 3157 crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end; 3158 3159 /* The slices actually used by the planes on the pipe */ 3160 dbuf_state->slices[pipe] = 3161 skl_ddb_dbuf_slice_mask(display, &crtc_state->wm.skl.ddb); 3162 3163 drm_dbg_kms(display->drm, 3164 "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n", 3165 crtc->base.base.id, crtc->base.name, 3166 dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start, 3167 dbuf_state->ddb[pipe].end, dbuf_state->active_pipes, 3168 str_yes_no(dbuf_state->joined_mbus)); 3169 } 3170 3171 dbuf_state->enabled_slices = display->dbuf.enabled_slices; 3172 } 3173 3174 bool skl_watermark_ipc_enabled(struct intel_display *display) 3175 { 3176 return display->wm.ipc_enabled; 3177 } 3178 3179 void skl_watermark_ipc_update(struct intel_display *display) 3180 { 3181 if (!HAS_IPC(display)) 3182 return; 3183 3184 intel_de_rmw(display, DISP_ARB_CTL2, DISP_IPC_ENABLE, 3185 skl_watermark_ipc_enabled(display) ? DISP_IPC_ENABLE : 0); 3186 } 3187 3188 static bool skl_watermark_ipc_can_enable(struct intel_display *display) 3189 { 3190 /* Display WA #0477 WaDisableIPC: skl */ 3191 if (display->platform.skylake) 3192 return false; 3193 3194 /* Display WA #1141: SKL:all KBL:all CFL */ 3195 if (display->platform.kabylake || 3196 display->platform.coffeelake || 3197 display->platform.cometlake) { 3198 const struct dram_info *dram_info = intel_dram_info(display->drm); 3199 3200 return dram_info->symmetric_memory; 3201 } 3202 3203 return true; 3204 } 3205 3206 void skl_watermark_ipc_init(struct intel_display *display) 3207 { 3208 if (!HAS_IPC(display)) 3209 return; 3210 3211 display->wm.ipc_enabled = skl_watermark_ipc_can_enable(display); 3212 3213 skl_watermark_ipc_update(display); 3214 } 3215 3216 static void 3217 adjust_wm_latency(struct intel_display *display, 3218 u16 wm[], int num_levels, int read_latency) 3219 { 3220 const struct dram_info *dram_info = intel_dram_info(display->drm); 3221 int i, level; 3222 3223 /* 3224 * If a level n (n > 1) has a 0us latency, all levels m (m >= n) 3225 * need to be disabled. We make sure to sanitize the values out 3226 * of the punit to satisfy this requirement. 3227 */ 3228 for (level = 1; level < num_levels; level++) { 3229 if (wm[level] == 0) { 3230 for (i = level + 1; i < num_levels; i++) 3231 wm[i] = 0; 3232 3233 num_levels = level; 3234 break; 3235 } 3236 } 3237 3238 /* 3239 * WaWmMemoryReadLatency 3240 * 3241 * punit doesn't take into account the read latency so we need 3242 * to add proper adjustment to each valid level we retrieve 3243 * from the punit when level 0 response data is 0us. 3244 */ 3245 if (wm[0] == 0) { 3246 for (level = 0; level < num_levels; level++) 3247 wm[level] += read_latency; 3248 } 3249 3250 /* 3251 * WA Level-0 adjustment for 16GB DIMMs: SKL+ 3252 * If we could not get dimm info enable this WA to prevent from 3253 * any underrun. If not able to get Dimm info assume 16GB dimm 3254 * to avoid any underrun. 3255 */ 3256 if (!display->platform.dg2 && dram_info->wm_lv_0_adjust_needed) 3257 wm[0] += 1; 3258 } 3259 3260 static void mtl_read_wm_latency(struct intel_display *display, u16 wm[]) 3261 { 3262 int num_levels = display->wm.num_levels; 3263 u32 val; 3264 3265 val = intel_de_read(display, MTL_LATENCY_LP0_LP1); 3266 wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); 3267 wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); 3268 3269 val = intel_de_read(display, MTL_LATENCY_LP2_LP3); 3270 wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); 3271 wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); 3272 3273 val = intel_de_read(display, MTL_LATENCY_LP4_LP5); 3274 wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); 3275 wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); 3276 3277 adjust_wm_latency(display, wm, num_levels, 6); 3278 } 3279 3280 static void skl_read_wm_latency(struct intel_display *display, u16 wm[]) 3281 { 3282 struct drm_i915_private *i915 = to_i915(display->drm); 3283 int num_levels = display->wm.num_levels; 3284 int read_latency = DISPLAY_VER(display) >= 12 ? 3 : 2; 3285 int mult = display->platform.dg2 ? 2 : 1; 3286 u32 val; 3287 int ret; 3288 3289 /* read the first set of memory latencies[0:3] */ 3290 val = 0; /* data0 to be programmed to 0 for first set */ 3291 ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL); 3292 if (ret) { 3293 drm_err(display->drm, "SKL Mailbox read error = %d\n", ret); 3294 return; 3295 } 3296 3297 wm[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; 3298 wm[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; 3299 wm[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; 3300 wm[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; 3301 3302 /* read the second set of memory latencies[4:7] */ 3303 val = 1; /* data0 to be programmed to 1 for second set */ 3304 ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL); 3305 if (ret) { 3306 drm_err(display->drm, "SKL Mailbox read error = %d\n", ret); 3307 return; 3308 } 3309 3310 wm[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; 3311 wm[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; 3312 wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; 3313 wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; 3314 3315 adjust_wm_latency(display, wm, num_levels, read_latency); 3316 } 3317 3318 static void skl_setup_wm_latency(struct intel_display *display) 3319 { 3320 if (HAS_HW_SAGV_WM(display)) 3321 display->wm.num_levels = 6; 3322 else 3323 display->wm.num_levels = 8; 3324 3325 if (DISPLAY_VER(display) >= 14) 3326 mtl_read_wm_latency(display, display->wm.skl_latency); 3327 else 3328 skl_read_wm_latency(display, display->wm.skl_latency); 3329 3330 intel_print_wm_latency(display, "Gen9 Plane", display->wm.skl_latency); 3331 } 3332 3333 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj) 3334 { 3335 struct intel_dbuf_state *dbuf_state; 3336 3337 dbuf_state = kmemdup(obj->state, sizeof(*dbuf_state), GFP_KERNEL); 3338 if (!dbuf_state) 3339 return NULL; 3340 3341 return &dbuf_state->base; 3342 } 3343 3344 static void intel_dbuf_destroy_state(struct intel_global_obj *obj, 3345 struct intel_global_state *state) 3346 { 3347 kfree(state); 3348 } 3349 3350 static const struct intel_global_state_funcs intel_dbuf_funcs = { 3351 .atomic_duplicate_state = intel_dbuf_duplicate_state, 3352 .atomic_destroy_state = intel_dbuf_destroy_state, 3353 }; 3354 3355 struct intel_dbuf_state * 3356 intel_atomic_get_dbuf_state(struct intel_atomic_state *state) 3357 { 3358 struct intel_display *display = to_intel_display(state); 3359 struct intel_global_state *dbuf_state; 3360 3361 dbuf_state = intel_atomic_get_global_obj_state(state, &display->dbuf.obj); 3362 if (IS_ERR(dbuf_state)) 3363 return ERR_CAST(dbuf_state); 3364 3365 return to_intel_dbuf_state(dbuf_state); 3366 } 3367 3368 int intel_dbuf_init(struct intel_display *display) 3369 { 3370 struct intel_dbuf_state *dbuf_state; 3371 3372 dbuf_state = kzalloc(sizeof(*dbuf_state), GFP_KERNEL); 3373 if (!dbuf_state) 3374 return -ENOMEM; 3375 3376 intel_atomic_global_obj_init(display, &display->dbuf.obj, 3377 &dbuf_state->base, &intel_dbuf_funcs); 3378 3379 return 0; 3380 } 3381 3382 static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes) 3383 { 3384 switch (pipe) { 3385 case PIPE_A: 3386 case PIPE_D: 3387 active_pipes &= BIT(PIPE_A) | BIT(PIPE_D); 3388 break; 3389 case PIPE_B: 3390 case PIPE_C: 3391 active_pipes &= BIT(PIPE_B) | BIT(PIPE_C); 3392 break; 3393 default: /* to suppress compiler warning */ 3394 MISSING_CASE(pipe); 3395 return false; 3396 } 3397 3398 return is_power_of_2(active_pipes); 3399 } 3400 3401 static u32 pipe_mbus_dbox_ctl(const struct intel_crtc *crtc, 3402 const struct intel_dbuf_state *dbuf_state) 3403 { 3404 struct intel_display *display = to_intel_display(crtc); 3405 u32 val = 0; 3406 3407 if (DISPLAY_VER(display) >= 14) 3408 val |= MBUS_DBOX_I_CREDIT(2); 3409 3410 if (DISPLAY_VER(display) >= 12) { 3411 val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16); 3412 val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1); 3413 val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN; 3414 } 3415 3416 if (DISPLAY_VER(display) >= 14) 3417 val |= dbuf_state->joined_mbus ? 3418 MBUS_DBOX_A_CREDIT(12) : MBUS_DBOX_A_CREDIT(8); 3419 else if (display->platform.alderlake_p) 3420 /* Wa_22010947358:adl-p */ 3421 val |= dbuf_state->joined_mbus ? 3422 MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); 3423 else 3424 val |= MBUS_DBOX_A_CREDIT(2); 3425 3426 if (DISPLAY_VER(display) >= 14) { 3427 val |= MBUS_DBOX_B_CREDIT(0xA); 3428 } else if (display->platform.alderlake_p) { 3429 val |= MBUS_DBOX_BW_CREDIT(2); 3430 val |= MBUS_DBOX_B_CREDIT(8); 3431 } else if (DISPLAY_VER(display) >= 12) { 3432 val |= MBUS_DBOX_BW_CREDIT(2); 3433 val |= MBUS_DBOX_B_CREDIT(12); 3434 } else { 3435 val |= MBUS_DBOX_BW_CREDIT(1); 3436 val |= MBUS_DBOX_B_CREDIT(8); 3437 } 3438 3439 if (DISPLAY_VERx100(display) == 1400) { 3440 if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, dbuf_state->active_pipes)) 3441 val |= MBUS_DBOX_BW_8CREDITS_MTL; 3442 else 3443 val |= MBUS_DBOX_BW_4CREDITS_MTL; 3444 } 3445 3446 return val; 3447 } 3448 3449 static void pipe_mbus_dbox_ctl_update(struct intel_display *display, 3450 const struct intel_dbuf_state *dbuf_state) 3451 { 3452 struct intel_crtc *crtc; 3453 3454 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, dbuf_state->active_pipes) 3455 intel_de_write(display, PIPE_MBUS_DBOX_CTL(crtc->pipe), 3456 pipe_mbus_dbox_ctl(crtc, dbuf_state)); 3457 } 3458 3459 static void intel_mbus_dbox_update(struct intel_atomic_state *state) 3460 { 3461 struct intel_display *display = to_intel_display(state); 3462 const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; 3463 3464 if (DISPLAY_VER(display) < 11) 3465 return; 3466 3467 new_dbuf_state = intel_atomic_get_new_dbuf_state(state); 3468 old_dbuf_state = intel_atomic_get_old_dbuf_state(state); 3469 if (!new_dbuf_state || 3470 (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus && 3471 new_dbuf_state->active_pipes == old_dbuf_state->active_pipes)) 3472 return; 3473 3474 pipe_mbus_dbox_ctl_update(display, new_dbuf_state); 3475 } 3476 3477 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, 3478 int ratio) 3479 { 3480 struct intel_dbuf_state *dbuf_state; 3481 3482 dbuf_state = intel_atomic_get_dbuf_state(state); 3483 if (IS_ERR(dbuf_state)) 3484 return PTR_ERR(dbuf_state); 3485 3486 dbuf_state->mdclk_cdclk_ratio = ratio; 3487 3488 return intel_atomic_lock_global_state(&dbuf_state->base); 3489 } 3490 3491 void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display, 3492 int ratio, bool joined_mbus) 3493 { 3494 enum dbuf_slice slice; 3495 3496 if (!HAS_MBUS_JOINING(display)) 3497 return; 3498 3499 if (DISPLAY_VER(display) >= 20) 3500 intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK, 3501 MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1)); 3502 3503 if (joined_mbus) 3504 ratio *= 2; 3505 3506 drm_dbg_kms(display->drm, "Updating dbuf ratio to %d (mbus joined: %s)\n", 3507 ratio, str_yes_no(joined_mbus)); 3508 3509 for_each_dbuf_slice(display, slice) 3510 intel_de_rmw(display, DBUF_CTL_S(slice), 3511 DBUF_MIN_TRACKER_STATE_SERVICE_MASK, 3512 DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1)); 3513 } 3514 3515 static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state) 3516 { 3517 struct intel_display *display = to_intel_display(state); 3518 const struct intel_dbuf_state *old_dbuf_state = 3519 intel_atomic_get_old_dbuf_state(state); 3520 const struct intel_dbuf_state *new_dbuf_state = 3521 intel_atomic_get_new_dbuf_state(state); 3522 int mdclk_cdclk_ratio; 3523 3524 if (intel_cdclk_is_decreasing_later(state)) { 3525 /* cdclk/mdclk will be changed later by intel_set_cdclk_post_plane_update() */ 3526 mdclk_cdclk_ratio = old_dbuf_state->mdclk_cdclk_ratio; 3527 } else { 3528 /* cdclk/mdclk already changed by intel_set_cdclk_pre_plane_update() */ 3529 mdclk_cdclk_ratio = new_dbuf_state->mdclk_cdclk_ratio; 3530 } 3531 3532 intel_dbuf_mdclk_cdclk_ratio_update(display, mdclk_cdclk_ratio, 3533 new_dbuf_state->joined_mbus); 3534 } 3535 3536 static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state, 3537 const struct intel_dbuf_state *dbuf_state) 3538 { 3539 struct intel_display *display = to_intel_display(state); 3540 enum pipe pipe = ffs(dbuf_state->active_pipes) - 1; 3541 const struct intel_crtc_state *new_crtc_state; 3542 struct intel_crtc *crtc; 3543 3544 drm_WARN_ON(display->drm, !dbuf_state->joined_mbus); 3545 drm_WARN_ON(display->drm, !is_power_of_2(dbuf_state->active_pipes)); 3546 3547 crtc = intel_crtc_for_pipe(display, pipe); 3548 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 3549 3550 if (new_crtc_state && !intel_crtc_needs_modeset(new_crtc_state)) 3551 return pipe; 3552 else 3553 return INVALID_PIPE; 3554 } 3555 3556 static void mbus_ctl_join_update(struct intel_display *display, 3557 const struct intel_dbuf_state *dbuf_state, 3558 enum pipe pipe) 3559 { 3560 u32 mbus_ctl; 3561 3562 if (dbuf_state->joined_mbus) 3563 mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN; 3564 else 3565 mbus_ctl = MBUS_HASHING_MODE_2x2; 3566 3567 if (pipe != INVALID_PIPE) 3568 mbus_ctl |= MBUS_JOIN_PIPE_SELECT(pipe); 3569 else 3570 mbus_ctl |= MBUS_JOIN_PIPE_SELECT_NONE; 3571 3572 intel_de_rmw(display, MBUS_CTL, 3573 MBUS_HASHING_MODE_MASK | MBUS_JOIN | 3574 MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl); 3575 } 3576 3577 static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state, 3578 enum pipe pipe) 3579 { 3580 struct intel_display *display = to_intel_display(state); 3581 const struct intel_dbuf_state *old_dbuf_state = 3582 intel_atomic_get_old_dbuf_state(state); 3583 const struct intel_dbuf_state *new_dbuf_state = 3584 intel_atomic_get_new_dbuf_state(state); 3585 3586 drm_dbg_kms(display->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n", 3587 str_yes_no(old_dbuf_state->joined_mbus), 3588 str_yes_no(new_dbuf_state->joined_mbus), 3589 pipe != INVALID_PIPE ? pipe_name(pipe) : '*'); 3590 3591 mbus_ctl_join_update(display, new_dbuf_state, pipe); 3592 } 3593 3594 void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state) 3595 { 3596 const struct intel_dbuf_state *new_dbuf_state = 3597 intel_atomic_get_new_dbuf_state(state); 3598 const struct intel_dbuf_state *old_dbuf_state = 3599 intel_atomic_get_old_dbuf_state(state); 3600 3601 if (!new_dbuf_state) 3602 return; 3603 3604 if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) { 3605 enum pipe pipe = intel_mbus_joined_pipe(state, new_dbuf_state); 3606 3607 WARN_ON(!new_dbuf_state->base.changed); 3608 3609 intel_dbuf_mbus_join_update(state, pipe); 3610 intel_mbus_dbox_update(state); 3611 intel_dbuf_mdclk_min_tracker_update(state); 3612 } 3613 } 3614 3615 void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state) 3616 { 3617 struct intel_display *display = to_intel_display(state); 3618 const struct intel_dbuf_state *new_dbuf_state = 3619 intel_atomic_get_new_dbuf_state(state); 3620 const struct intel_dbuf_state *old_dbuf_state = 3621 intel_atomic_get_old_dbuf_state(state); 3622 3623 if (!new_dbuf_state) 3624 return; 3625 3626 if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) { 3627 enum pipe pipe = intel_mbus_joined_pipe(state, old_dbuf_state); 3628 3629 WARN_ON(!new_dbuf_state->base.changed); 3630 3631 intel_dbuf_mdclk_min_tracker_update(state); 3632 intel_mbus_dbox_update(state); 3633 intel_dbuf_mbus_join_update(state, pipe); 3634 3635 if (pipe != INVALID_PIPE) { 3636 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 3637 3638 intel_crtc_wait_for_next_vblank(crtc); 3639 } 3640 } else if (old_dbuf_state->joined_mbus == new_dbuf_state->joined_mbus && 3641 old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) { 3642 WARN_ON(!new_dbuf_state->base.changed); 3643 3644 intel_dbuf_mdclk_min_tracker_update(state); 3645 intel_mbus_dbox_update(state); 3646 } 3647 3648 } 3649 3650 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) 3651 { 3652 struct intel_display *display = to_intel_display(state); 3653 const struct intel_dbuf_state *new_dbuf_state = 3654 intel_atomic_get_new_dbuf_state(state); 3655 const struct intel_dbuf_state *old_dbuf_state = 3656 intel_atomic_get_old_dbuf_state(state); 3657 u8 old_slices, new_slices; 3658 3659 if (!new_dbuf_state) 3660 return; 3661 3662 old_slices = old_dbuf_state->enabled_slices; 3663 new_slices = old_dbuf_state->enabled_slices | new_dbuf_state->enabled_slices; 3664 3665 if (old_slices == new_slices) 3666 return; 3667 3668 WARN_ON(!new_dbuf_state->base.changed); 3669 3670 gen9_dbuf_slices_update(display, new_slices); 3671 } 3672 3673 void intel_dbuf_post_plane_update(struct intel_atomic_state *state) 3674 { 3675 struct intel_display *display = to_intel_display(state); 3676 const struct intel_dbuf_state *new_dbuf_state = 3677 intel_atomic_get_new_dbuf_state(state); 3678 const struct intel_dbuf_state *old_dbuf_state = 3679 intel_atomic_get_old_dbuf_state(state); 3680 u8 old_slices, new_slices; 3681 3682 if (!new_dbuf_state) 3683 return; 3684 3685 old_slices = old_dbuf_state->enabled_slices | new_dbuf_state->enabled_slices; 3686 new_slices = new_dbuf_state->enabled_slices; 3687 3688 if (old_slices == new_slices) 3689 return; 3690 3691 WARN_ON(!new_dbuf_state->base.changed); 3692 3693 gen9_dbuf_slices_update(display, new_slices); 3694 } 3695 3696 static void skl_mbus_sanitize(struct intel_display *display) 3697 { 3698 struct intel_dbuf_state *dbuf_state = 3699 to_intel_dbuf_state(display->dbuf.obj.state); 3700 3701 if (!HAS_MBUS_JOINING(display)) 3702 return; 3703 3704 if (!dbuf_state->joined_mbus || 3705 adlp_check_mbus_joined(dbuf_state->active_pipes)) 3706 return; 3707 3708 drm_dbg_kms(display->drm, "Disabling redundant MBUS joining (active pipes 0x%x)\n", 3709 dbuf_state->active_pipes); 3710 3711 dbuf_state->joined_mbus = false; 3712 intel_dbuf_mdclk_cdclk_ratio_update(display, 3713 dbuf_state->mdclk_cdclk_ratio, 3714 dbuf_state->joined_mbus); 3715 pipe_mbus_dbox_ctl_update(display, dbuf_state); 3716 mbus_ctl_join_update(display, dbuf_state, INVALID_PIPE); 3717 } 3718 3719 static bool skl_dbuf_is_misconfigured(struct intel_display *display) 3720 { 3721 const struct intel_dbuf_state *dbuf_state = 3722 to_intel_dbuf_state(display->dbuf.obj.state); 3723 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 3724 struct intel_crtc *crtc; 3725 3726 for_each_intel_crtc(display->drm, crtc) { 3727 const struct intel_crtc_state *crtc_state = 3728 to_intel_crtc_state(crtc->base.state); 3729 3730 entries[crtc->pipe] = crtc_state->wm.skl.ddb; 3731 } 3732 3733 for_each_intel_crtc(display->drm, crtc) { 3734 const struct intel_crtc_state *crtc_state = 3735 to_intel_crtc_state(crtc->base.state); 3736 u8 slices; 3737 3738 slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, 3739 dbuf_state->joined_mbus); 3740 if (dbuf_state->slices[crtc->pipe] & ~slices) 3741 return true; 3742 3743 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries, 3744 I915_MAX_PIPES, crtc->pipe)) 3745 return true; 3746 } 3747 3748 return false; 3749 } 3750 3751 static void skl_dbuf_sanitize(struct intel_display *display) 3752 { 3753 struct intel_crtc *crtc; 3754 3755 /* 3756 * On TGL/RKL (at least) the BIOS likes to assign the planes 3757 * to the wrong DBUF slices. This will cause an infinite loop 3758 * in skl_commit_modeset_enables() as it can't find a way to 3759 * transition between the old bogus DBUF layout to the new 3760 * proper DBUF layout without DBUF allocation overlaps between 3761 * the planes (which cannot be allowed or else the hardware 3762 * may hang). If we detect a bogus DBUF layout just turn off 3763 * all the planes so that skl_commit_modeset_enables() can 3764 * simply ignore them. 3765 */ 3766 if (!skl_dbuf_is_misconfigured(display)) 3767 return; 3768 3769 drm_dbg_kms(display->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n"); 3770 3771 for_each_intel_crtc(display->drm, crtc) { 3772 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3773 const struct intel_plane_state *plane_state = 3774 to_intel_plane_state(plane->base.state); 3775 struct intel_crtc_state *crtc_state = 3776 to_intel_crtc_state(crtc->base.state); 3777 3778 if (plane_state->uapi.visible) 3779 intel_plane_disable_noatomic(crtc, plane); 3780 3781 drm_WARN_ON(display->drm, crtc_state->active_planes != 0); 3782 3783 memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); 3784 } 3785 } 3786 3787 static void skl_wm_sanitize(struct intel_display *display) 3788 { 3789 skl_mbus_sanitize(display); 3790 skl_dbuf_sanitize(display); 3791 } 3792 3793 void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc) 3794 { 3795 struct intel_display *display = to_intel_display(crtc); 3796 struct intel_crtc_state *crtc_state = 3797 to_intel_crtc_state(crtc->base.state); 3798 struct intel_dbuf_state *dbuf_state = 3799 to_intel_dbuf_state(display->dbuf.obj.state); 3800 enum pipe pipe = crtc->pipe; 3801 3802 if (DISPLAY_VER(display) < 9) 3803 return; 3804 3805 dbuf_state->active_pipes &= ~BIT(pipe); 3806 3807 dbuf_state->weight[pipe] = 0; 3808 dbuf_state->slices[pipe] = 0; 3809 3810 memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe])); 3811 3812 memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); 3813 } 3814 3815 void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc, 3816 struct intel_plane *plane) 3817 { 3818 struct intel_display *display = to_intel_display(crtc); 3819 struct intel_crtc_state *crtc_state = 3820 to_intel_crtc_state(crtc->base.state); 3821 3822 if (DISPLAY_VER(display) < 9) 3823 return; 3824 3825 skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0); 3826 skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0); 3827 3828 crtc_state->wm.skl.plane_min_ddb[plane->id] = 0; 3829 crtc_state->wm.skl.plane_interim_ddb[plane->id] = 0; 3830 3831 memset(&crtc_state->wm.skl.raw.planes[plane->id], 0, 3832 sizeof(crtc_state->wm.skl.raw.planes[plane->id])); 3833 memset(&crtc_state->wm.skl.optimal.planes[plane->id], 0, 3834 sizeof(crtc_state->wm.skl.optimal.planes[plane->id])); 3835 } 3836 3837 void intel_wm_state_verify(struct intel_atomic_state *state, 3838 struct intel_crtc *crtc) 3839 { 3840 struct intel_display *display = to_intel_display(state); 3841 const struct intel_crtc_state *new_crtc_state = 3842 intel_atomic_get_new_crtc_state(state, crtc); 3843 struct skl_hw_state { 3844 struct skl_ddb_entry ddb[I915_MAX_PLANES]; 3845 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 3846 u16 min_ddb[I915_MAX_PLANES]; 3847 u16 interim_ddb[I915_MAX_PLANES]; 3848 struct skl_pipe_wm wm; 3849 } *hw; 3850 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 3851 struct intel_plane *plane; 3852 u8 hw_enabled_slices; 3853 int level; 3854 3855 if (DISPLAY_VER(display) < 9 || !new_crtc_state->hw.active) 3856 return; 3857 3858 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 3859 if (!hw) 3860 return; 3861 3862 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 3863 3864 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y, hw->min_ddb, hw->interim_ddb); 3865 3866 hw_enabled_slices = intel_enabled_dbuf_slices_mask(display); 3867 3868 if (DISPLAY_VER(display) >= 11 && 3869 hw_enabled_slices != display->dbuf.enabled_slices) 3870 drm_err(display->drm, 3871 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 3872 display->dbuf.enabled_slices, 3873 hw_enabled_slices); 3874 3875 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 3876 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 3877 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 3878 3879 /* Watermarks */ 3880 for (level = 0; level < display->wm.num_levels; level++) { 3881 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 3882 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 3883 3884 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 3885 continue; 3886 3887 drm_err(display->drm, 3888 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3889 plane->base.base.id, plane->base.name, level, 3890 sw_wm_level->enable, 3891 sw_wm_level->blocks, 3892 sw_wm_level->lines, 3893 hw_wm_level->enable, 3894 hw_wm_level->blocks, 3895 hw_wm_level->lines); 3896 } 3897 3898 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 3899 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 3900 3901 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3902 drm_err(display->drm, 3903 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3904 plane->base.base.id, plane->base.name, 3905 sw_wm_level->enable, 3906 sw_wm_level->blocks, 3907 sw_wm_level->lines, 3908 hw_wm_level->enable, 3909 hw_wm_level->blocks, 3910 hw_wm_level->lines); 3911 } 3912 3913 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 3914 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 3915 3916 if (HAS_HW_SAGV_WM(display) && 3917 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3918 drm_err(display->drm, 3919 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3920 plane->base.base.id, plane->base.name, 3921 sw_wm_level->enable, 3922 sw_wm_level->blocks, 3923 sw_wm_level->lines, 3924 hw_wm_level->enable, 3925 hw_wm_level->blocks, 3926 hw_wm_level->lines); 3927 } 3928 3929 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 3930 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 3931 3932 if (HAS_HW_SAGV_WM(display) && 3933 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3934 drm_err(display->drm, 3935 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3936 plane->base.base.id, plane->base.name, 3937 sw_wm_level->enable, 3938 sw_wm_level->blocks, 3939 sw_wm_level->lines, 3940 hw_wm_level->enable, 3941 hw_wm_level->blocks, 3942 hw_wm_level->lines); 3943 } 3944 3945 /* DDB */ 3946 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 3947 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 3948 3949 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 3950 drm_err(display->drm, 3951 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 3952 plane->base.base.id, plane->base.name, 3953 sw_ddb_entry->start, sw_ddb_entry->end, 3954 hw_ddb_entry->start, hw_ddb_entry->end); 3955 } 3956 } 3957 3958 kfree(hw); 3959 } 3960 3961 static const struct intel_wm_funcs skl_wm_funcs = { 3962 .compute_global_watermarks = skl_compute_wm, 3963 .get_hw_state = skl_wm_get_hw_state, 3964 .sanitize = skl_wm_sanitize, 3965 }; 3966 3967 void skl_wm_init(struct intel_display *display) 3968 { 3969 intel_sagv_init(display); 3970 3971 skl_setup_wm_latency(display); 3972 3973 display->funcs.wm = &skl_wm_funcs; 3974 } 3975 3976 static int skl_watermark_ipc_status_show(struct seq_file *m, void *data) 3977 { 3978 struct intel_display *display = m->private; 3979 3980 seq_printf(m, "Isochronous Priority Control: %s\n", 3981 str_yes_no(skl_watermark_ipc_enabled(display))); 3982 return 0; 3983 } 3984 3985 static int skl_watermark_ipc_status_open(struct inode *inode, struct file *file) 3986 { 3987 struct intel_display *display = inode->i_private; 3988 3989 return single_open(file, skl_watermark_ipc_status_show, display); 3990 } 3991 3992 static ssize_t skl_watermark_ipc_status_write(struct file *file, 3993 const char __user *ubuf, 3994 size_t len, loff_t *offp) 3995 { 3996 struct seq_file *m = file->private_data; 3997 struct intel_display *display = m->private; 3998 bool enable; 3999 int ret; 4000 4001 ret = kstrtobool_from_user(ubuf, len, &enable); 4002 if (ret < 0) 4003 return ret; 4004 4005 with_intel_display_rpm(display) { 4006 if (!skl_watermark_ipc_enabled(display) && enable) 4007 drm_info(display->drm, 4008 "Enabling IPC: WM will be proper only after next commit\n"); 4009 display->wm.ipc_enabled = enable; 4010 skl_watermark_ipc_update(display); 4011 } 4012 4013 return len; 4014 } 4015 4016 static const struct file_operations skl_watermark_ipc_status_fops = { 4017 .owner = THIS_MODULE, 4018 .open = skl_watermark_ipc_status_open, 4019 .read = seq_read, 4020 .llseek = seq_lseek, 4021 .release = single_release, 4022 .write = skl_watermark_ipc_status_write 4023 }; 4024 4025 static int intel_sagv_status_show(struct seq_file *m, void *unused) 4026 { 4027 struct intel_display *display = m->private; 4028 static const char * const sagv_status[] = { 4029 [I915_SAGV_UNKNOWN] = "unknown", 4030 [I915_SAGV_DISABLED] = "disabled", 4031 [I915_SAGV_ENABLED] = "enabled", 4032 [I915_SAGV_NOT_CONTROLLED] = "not controlled", 4033 }; 4034 4035 seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(display))); 4036 seq_printf(m, "SAGV modparam: %s\n", 4037 str_enabled_disabled(display->params.enable_sagv)); 4038 seq_printf(m, "SAGV status: %s\n", sagv_status[display->sagv.status]); 4039 seq_printf(m, "SAGV block time: %d usec\n", display->sagv.block_time_us); 4040 4041 return 0; 4042 } 4043 4044 DEFINE_SHOW_ATTRIBUTE(intel_sagv_status); 4045 4046 void skl_watermark_debugfs_register(struct intel_display *display) 4047 { 4048 struct drm_minor *minor = display->drm->primary; 4049 4050 if (HAS_IPC(display)) 4051 debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, 4052 display, &skl_watermark_ipc_status_fops); 4053 4054 if (HAS_SAGV(display)) 4055 debugfs_create_file("i915_sagv_status", 0444, minor->debugfs_root, 4056 display, &intel_sagv_status_fops); 4057 } 4058 4059 unsigned int skl_watermark_max_latency(struct intel_display *display, int initial_wm_level) 4060 { 4061 int level; 4062 4063 for (level = display->wm.num_levels - 1; level >= initial_wm_level; level--) { 4064 unsigned int latency = skl_wm_latency(display, level, NULL); 4065 4066 if (latency) 4067 return latency; 4068 } 4069 4070 return 0; 4071 } 4072