1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <linux/debugfs.h> 7 8 #include <drm/drm_blend.h> 9 10 #include "i915_drv.h" 11 #include "i915_reg.h" 12 #include "i9xx_wm.h" 13 #include "intel_atomic.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_bw.h" 16 #include "intel_cdclk.h" 17 #include "intel_crtc.h" 18 #include "intel_cursor_regs.h" 19 #include "intel_de.h" 20 #include "intel_display.h" 21 #include "intel_display_power.h" 22 #include "intel_display_rpm.h" 23 #include "intel_display_types.h" 24 #include "intel_fb.h" 25 #include "intel_fixed.h" 26 #include "intel_pcode.h" 27 #include "intel_wm.h" 28 #include "skl_universal_plane_regs.h" 29 #include "skl_watermark.h" 30 #include "skl_watermark_regs.h" 31 32 /*It is expected that DSB can do posted writes to every register in 33 * the pipe and planes within 100us. For flip queue use case, the 34 * recommended DSB execution time is 100us + one SAGV block time. 35 */ 36 #define DSB_EXE_TIME 100 37 38 static void skl_sagv_disable(struct intel_display *display); 39 40 /* Stores plane specific WM parameters */ 41 struct skl_wm_params { 42 bool x_tiled, y_tiled; 43 bool rc_surface; 44 bool is_planar; 45 u32 width; 46 u8 cpp; 47 u32 plane_pixel_rate; 48 u32 y_min_scanlines; 49 u32 plane_bytes_per_line; 50 uint_fixed_16_16_t plane_blocks_per_line; 51 uint_fixed_16_16_t y_tile_minimum; 52 u32 linetime_us; 53 u32 dbuf_block_size; 54 }; 55 56 u8 intel_enabled_dbuf_slices_mask(struct intel_display *display) 57 { 58 u8 enabled_slices = 0; 59 enum dbuf_slice slice; 60 61 for_each_dbuf_slice(display, slice) { 62 if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE) 63 enabled_slices |= BIT(slice); 64 } 65 66 return enabled_slices; 67 } 68 69 /* 70 * FIXME: We still don't have the proper code detect if we need to apply the WA, 71 * so assume we'll always need it in order to avoid underruns. 72 */ 73 static bool skl_needs_memory_bw_wa(struct intel_display *display) 74 { 75 return DISPLAY_VER(display) == 9; 76 } 77 78 bool 79 intel_has_sagv(struct intel_display *display) 80 { 81 return HAS_SAGV(display) && display->sagv.status != I915_SAGV_NOT_CONTROLLED; 82 } 83 84 static u32 85 intel_sagv_block_time(struct intel_display *display) 86 { 87 struct drm_i915_private *i915 = to_i915(display->drm); 88 89 if (DISPLAY_VER(display) >= 14) { 90 u32 val; 91 92 val = intel_de_read(display, MTL_LATENCY_SAGV); 93 94 return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); 95 } else if (DISPLAY_VER(display) >= 12) { 96 u32 val = 0; 97 int ret; 98 99 ret = snb_pcode_read(&i915->uncore, 100 GEN12_PCODE_READ_SAGV_BLOCK_TIME_US, 101 &val, NULL); 102 if (ret) { 103 drm_dbg_kms(display->drm, "Couldn't read SAGV block time!\n"); 104 return 0; 105 } 106 107 return val; 108 } else if (DISPLAY_VER(display) == 11) { 109 return 10; 110 } else if (HAS_SAGV(display)) { 111 return 30; 112 } else { 113 return 0; 114 } 115 } 116 117 static void intel_sagv_init(struct intel_display *display) 118 { 119 if (!HAS_SAGV(display)) 120 display->sagv.status = I915_SAGV_NOT_CONTROLLED; 121 122 /* 123 * Probe to see if we have working SAGV control. 124 * For icl+ this was already determined by intel_bw_init_hw(). 125 */ 126 if (DISPLAY_VER(display) < 11) 127 skl_sagv_disable(display); 128 129 drm_WARN_ON(display->drm, display->sagv.status == I915_SAGV_UNKNOWN); 130 131 display->sagv.block_time_us = intel_sagv_block_time(display); 132 133 drm_dbg_kms(display->drm, "SAGV supported: %s, original SAGV block time: %u us\n", 134 str_yes_no(intel_has_sagv(display)), display->sagv.block_time_us); 135 136 /* avoid overflow when adding with wm0 latency/etc. */ 137 if (drm_WARN(display->drm, display->sagv.block_time_us > U16_MAX, 138 "Excessive SAGV block time %u, ignoring\n", 139 display->sagv.block_time_us)) 140 display->sagv.block_time_us = 0; 141 142 if (!intel_has_sagv(display)) 143 display->sagv.block_time_us = 0; 144 } 145 146 /* 147 * SAGV dynamically adjusts the system agent voltage and clock frequencies 148 * depending on power and performance requirements. The display engine access 149 * to system memory is blocked during the adjustment time. Because of the 150 * blocking time, having this enabled can cause full system hangs and/or pipe 151 * underruns if we don't meet all of the following requirements: 152 * 153 * - <= 1 pipe enabled 154 * - All planes can enable watermarks for latencies >= SAGV engine block time 155 * - We're not using an interlaced display configuration 156 */ 157 static void skl_sagv_enable(struct intel_display *display) 158 { 159 struct drm_i915_private *i915 = to_i915(display->drm); 160 int ret; 161 162 if (!intel_has_sagv(display)) 163 return; 164 165 if (display->sagv.status == I915_SAGV_ENABLED) 166 return; 167 168 drm_dbg_kms(display->drm, "Enabling SAGV\n"); 169 ret = snb_pcode_write(&i915->uncore, GEN9_PCODE_SAGV_CONTROL, 170 GEN9_SAGV_ENABLE); 171 172 /* We don't need to wait for SAGV when enabling */ 173 174 /* 175 * Some skl systems, pre-release machines in particular, 176 * don't actually have SAGV. 177 */ 178 if (display->platform.skylake && ret == -ENXIO) { 179 drm_dbg(display->drm, "No SAGV found on system, ignoring\n"); 180 display->sagv.status = I915_SAGV_NOT_CONTROLLED; 181 return; 182 } else if (ret < 0) { 183 drm_err(display->drm, "Failed to enable SAGV\n"); 184 return; 185 } 186 187 display->sagv.status = I915_SAGV_ENABLED; 188 } 189 190 static void skl_sagv_disable(struct intel_display *display) 191 { 192 struct drm_i915_private *i915 = to_i915(display->drm); 193 int ret; 194 195 if (!intel_has_sagv(display)) 196 return; 197 198 if (display->sagv.status == I915_SAGV_DISABLED) 199 return; 200 201 drm_dbg_kms(display->drm, "Disabling SAGV\n"); 202 /* bspec says to keep retrying for at least 1 ms */ 203 ret = skl_pcode_request(&i915->uncore, GEN9_PCODE_SAGV_CONTROL, 204 GEN9_SAGV_DISABLE, 205 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 206 1); 207 /* 208 * Some skl systems, pre-release machines in particular, 209 * don't actually have SAGV. 210 */ 211 if (display->platform.skylake && ret == -ENXIO) { 212 drm_dbg(display->drm, "No SAGV found on system, ignoring\n"); 213 display->sagv.status = I915_SAGV_NOT_CONTROLLED; 214 return; 215 } else if (ret < 0) { 216 drm_err(display->drm, "Failed to disable SAGV (%d)\n", ret); 217 return; 218 } 219 220 display->sagv.status = I915_SAGV_DISABLED; 221 } 222 223 static void skl_sagv_pre_plane_update(struct intel_atomic_state *state) 224 { 225 struct intel_display *display = to_intel_display(state); 226 const struct intel_bw_state *new_bw_state = 227 intel_atomic_get_new_bw_state(state); 228 229 if (!new_bw_state) 230 return; 231 232 if (!intel_can_enable_sagv(display, new_bw_state)) 233 skl_sagv_disable(display); 234 } 235 236 static void skl_sagv_post_plane_update(struct intel_atomic_state *state) 237 { 238 struct intel_display *display = to_intel_display(state); 239 const struct intel_bw_state *new_bw_state = 240 intel_atomic_get_new_bw_state(state); 241 242 if (!new_bw_state) 243 return; 244 245 if (intel_can_enable_sagv(display, new_bw_state)) 246 skl_sagv_enable(display); 247 } 248 249 static void icl_sagv_pre_plane_update(struct intel_atomic_state *state) 250 { 251 struct intel_display *display = to_intel_display(state); 252 const struct intel_bw_state *old_bw_state = 253 intel_atomic_get_old_bw_state(state); 254 const struct intel_bw_state *new_bw_state = 255 intel_atomic_get_new_bw_state(state); 256 u16 old_mask, new_mask; 257 258 if (!new_bw_state) 259 return; 260 261 old_mask = old_bw_state->qgv_points_mask; 262 new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask; 263 264 if (old_mask == new_mask) 265 return; 266 267 WARN_ON(!new_bw_state->base.changed); 268 269 drm_dbg_kms(display->drm, "Restricting QGV points: 0x%x -> 0x%x\n", 270 old_mask, new_mask); 271 272 /* 273 * Restrict required qgv points before updating the configuration. 274 * According to BSpec we can't mask and unmask qgv points at the same 275 * time. Also masking should be done before updating the configuration 276 * and unmasking afterwards. 277 */ 278 icl_pcode_restrict_qgv_points(display, new_mask); 279 } 280 281 static void icl_sagv_post_plane_update(struct intel_atomic_state *state) 282 { 283 struct intel_display *display = to_intel_display(state); 284 const struct intel_bw_state *old_bw_state = 285 intel_atomic_get_old_bw_state(state); 286 const struct intel_bw_state *new_bw_state = 287 intel_atomic_get_new_bw_state(state); 288 u16 old_mask, new_mask; 289 290 if (!new_bw_state) 291 return; 292 293 old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask; 294 new_mask = new_bw_state->qgv_points_mask; 295 296 if (old_mask == new_mask) 297 return; 298 299 WARN_ON(!new_bw_state->base.changed); 300 301 drm_dbg_kms(display->drm, "Relaxing QGV points: 0x%x -> 0x%x\n", 302 old_mask, new_mask); 303 304 /* 305 * Allow required qgv points after updating the configuration. 306 * According to BSpec we can't mask and unmask qgv points at the same 307 * time. Also masking should be done before updating the configuration 308 * and unmasking afterwards. 309 */ 310 icl_pcode_restrict_qgv_points(display, new_mask); 311 } 312 313 void intel_sagv_pre_plane_update(struct intel_atomic_state *state) 314 { 315 struct intel_display *display = to_intel_display(state); 316 317 /* 318 * Just return if we can't control SAGV or don't have it. 319 * This is different from situation when we have SAGV but just can't 320 * afford it due to DBuf limitation - in case if SAGV is completely 321 * disabled in a BIOS, we are not even allowed to send a PCode request, 322 * as it will throw an error. So have to check it here. 323 */ 324 if (!intel_has_sagv(display)) 325 return; 326 327 if (DISPLAY_VER(display) >= 11) 328 icl_sagv_pre_plane_update(state); 329 else 330 skl_sagv_pre_plane_update(state); 331 } 332 333 void intel_sagv_post_plane_update(struct intel_atomic_state *state) 334 { 335 struct intel_display *display = to_intel_display(state); 336 337 /* 338 * Just return if we can't control SAGV or don't have it. 339 * This is different from situation when we have SAGV but just can't 340 * afford it due to DBuf limitation - in case if SAGV is completely 341 * disabled in a BIOS, we are not even allowed to send a PCode request, 342 * as it will throw an error. So have to check it here. 343 */ 344 if (!intel_has_sagv(display)) 345 return; 346 347 if (DISPLAY_VER(display) >= 11) 348 icl_sagv_post_plane_update(state); 349 else 350 skl_sagv_post_plane_update(state); 351 } 352 353 static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) 354 { 355 struct intel_display *display = to_intel_display(crtc_state); 356 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 357 enum plane_id plane_id; 358 int max_level = INT_MAX; 359 360 if (!intel_has_sagv(display)) 361 return false; 362 363 if (!crtc_state->hw.active) 364 return true; 365 366 if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE) 367 return false; 368 369 for_each_plane_id_on_crtc(crtc, plane_id) { 370 const struct skl_plane_wm *wm = 371 &crtc_state->wm.skl.optimal.planes[plane_id]; 372 int level; 373 374 /* Skip this plane if it's not enabled */ 375 if (!wm->wm[0].enable) 376 continue; 377 378 /* Find the highest enabled wm level for this plane */ 379 for (level = display->wm.num_levels - 1; 380 !wm->wm[level].enable; --level) 381 { } 382 383 /* Highest common enabled wm level for all planes */ 384 max_level = min(level, max_level); 385 } 386 387 /* No enabled planes? */ 388 if (max_level == INT_MAX) 389 return true; 390 391 for_each_plane_id_on_crtc(crtc, plane_id) { 392 const struct skl_plane_wm *wm = 393 &crtc_state->wm.skl.optimal.planes[plane_id]; 394 395 /* 396 * All enabled planes must have enabled a common wm level that 397 * can tolerate memory latencies higher than sagv_block_time_us 398 */ 399 if (wm->wm[0].enable && !wm->wm[max_level].can_sagv) 400 return false; 401 } 402 403 return true; 404 } 405 406 static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) 407 { 408 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 409 enum plane_id plane_id; 410 411 if (!crtc_state->hw.active) 412 return true; 413 414 for_each_plane_id_on_crtc(crtc, plane_id) { 415 const struct skl_plane_wm *wm = 416 &crtc_state->wm.skl.optimal.planes[plane_id]; 417 418 if (wm->wm[0].enable && !wm->sagv.wm0.enable) 419 return false; 420 } 421 422 return true; 423 } 424 425 bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) 426 { 427 struct intel_display *display = to_intel_display(crtc_state); 428 429 if (!display->params.enable_sagv) 430 return false; 431 432 /* 433 * SAGV is initially forced off because its current 434 * state can't be queried from pcode. Allow SAGV to 435 * be enabled upon the first real commit. 436 */ 437 if (crtc_state->inherited) 438 return false; 439 440 if (DISPLAY_VER(display) >= 12) 441 return tgl_crtc_can_enable_sagv(crtc_state); 442 else 443 return skl_crtc_can_enable_sagv(crtc_state); 444 } 445 446 bool intel_can_enable_sagv(struct intel_display *display, 447 const struct intel_bw_state *bw_state) 448 { 449 if (DISPLAY_VER(display) < 11 && 450 bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes)) 451 return false; 452 453 return bw_state->pipe_sagv_reject == 0; 454 } 455 456 static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry, 457 u16 start, u16 end) 458 { 459 entry->start = start; 460 entry->end = end; 461 462 return end; 463 } 464 465 static int intel_dbuf_slice_size(struct intel_display *display) 466 { 467 return DISPLAY_INFO(display)->dbuf.size / 468 hweight8(DISPLAY_INFO(display)->dbuf.slice_mask); 469 } 470 471 static void 472 skl_ddb_entry_for_slices(struct intel_display *display, u8 slice_mask, 473 struct skl_ddb_entry *ddb) 474 { 475 int slice_size = intel_dbuf_slice_size(display); 476 477 if (!slice_mask) { 478 ddb->start = 0; 479 ddb->end = 0; 480 return; 481 } 482 483 ddb->start = (ffs(slice_mask) - 1) * slice_size; 484 ddb->end = fls(slice_mask) * slice_size; 485 486 WARN_ON(ddb->start >= ddb->end); 487 WARN_ON(ddb->end > DISPLAY_INFO(display)->dbuf.size); 488 } 489 490 static unsigned int mbus_ddb_offset(struct intel_display *display, u8 slice_mask) 491 { 492 struct skl_ddb_entry ddb; 493 494 if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2))) 495 slice_mask = BIT(DBUF_S1); 496 else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4))) 497 slice_mask = BIT(DBUF_S3); 498 499 skl_ddb_entry_for_slices(display, slice_mask, &ddb); 500 501 return ddb.start; 502 } 503 504 u32 skl_ddb_dbuf_slice_mask(struct intel_display *display, 505 const struct skl_ddb_entry *entry) 506 { 507 int slice_size = intel_dbuf_slice_size(display); 508 enum dbuf_slice start_slice, end_slice; 509 u8 slice_mask = 0; 510 511 if (!skl_ddb_entry_size(entry)) 512 return 0; 513 514 start_slice = entry->start / slice_size; 515 end_slice = (entry->end - 1) / slice_size; 516 517 /* 518 * Per plane DDB entry can in a really worst case be on multiple slices 519 * but single entry is anyway contiguous. 520 */ 521 while (start_slice <= end_slice) { 522 slice_mask |= BIT(start_slice); 523 start_slice++; 524 } 525 526 return slice_mask; 527 } 528 529 static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_state) 530 { 531 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 532 int hdisplay, vdisplay; 533 534 if (!crtc_state->hw.active) 535 return 0; 536 537 /* 538 * Watermark/ddb requirement highly depends upon width of the 539 * framebuffer, So instead of allocating DDB equally among pipes 540 * distribute DDB based on resolution/width of the display. 541 */ 542 drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay); 543 544 return hdisplay; 545 } 546 547 static void intel_crtc_dbuf_weights(const struct intel_dbuf_state *dbuf_state, 548 enum pipe for_pipe, 549 unsigned int *weight_start, 550 unsigned int *weight_end, 551 unsigned int *weight_total) 552 { 553 struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev); 554 enum pipe pipe; 555 556 *weight_start = 0; 557 *weight_end = 0; 558 *weight_total = 0; 559 560 for_each_pipe(display, pipe) { 561 int weight = dbuf_state->weight[pipe]; 562 563 /* 564 * Do not account pipes using other slice sets 565 * luckily as of current BSpec slice sets do not partially 566 * intersect(pipes share either same one slice or same slice set 567 * i.e no partial intersection), so it is enough to check for 568 * equality for now. 569 */ 570 if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe]) 571 continue; 572 573 *weight_total += weight; 574 if (pipe < for_pipe) { 575 *weight_start += weight; 576 *weight_end += weight; 577 } else if (pipe == for_pipe) { 578 *weight_end += weight; 579 } 580 } 581 } 582 583 static int 584 skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc) 585 { 586 struct intel_display *display = to_intel_display(crtc); 587 unsigned int weight_total, weight_start, weight_end; 588 const struct intel_dbuf_state *old_dbuf_state = 589 intel_atomic_get_old_dbuf_state(state); 590 struct intel_dbuf_state *new_dbuf_state = 591 intel_atomic_get_new_dbuf_state(state); 592 struct intel_crtc_state *crtc_state; 593 struct skl_ddb_entry ddb_slices; 594 enum pipe pipe = crtc->pipe; 595 unsigned int mbus_offset = 0; 596 u32 ddb_range_size; 597 u32 dbuf_slice_mask; 598 u32 start, end; 599 int ret; 600 601 if (new_dbuf_state->weight[pipe] == 0) { 602 skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 0, 0); 603 goto out; 604 } 605 606 dbuf_slice_mask = new_dbuf_state->slices[pipe]; 607 608 skl_ddb_entry_for_slices(display, dbuf_slice_mask, &ddb_slices); 609 mbus_offset = mbus_ddb_offset(display, dbuf_slice_mask); 610 ddb_range_size = skl_ddb_entry_size(&ddb_slices); 611 612 intel_crtc_dbuf_weights(new_dbuf_state, pipe, 613 &weight_start, &weight_end, &weight_total); 614 615 start = ddb_range_size * weight_start / weight_total; 616 end = ddb_range_size * weight_end / weight_total; 617 618 skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 619 ddb_slices.start - mbus_offset + start, 620 ddb_slices.start - mbus_offset + end); 621 622 out: 623 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] && 624 skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe], 625 &new_dbuf_state->ddb[pipe])) 626 return 0; 627 628 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 629 if (ret) 630 return ret; 631 632 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 633 if (IS_ERR(crtc_state)) 634 return PTR_ERR(crtc_state); 635 636 /* 637 * Used for checking overlaps, so we need absolute 638 * offsets instead of MBUS relative offsets. 639 */ 640 crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start; 641 crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end; 642 643 drm_dbg_kms(display->drm, 644 "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n", 645 crtc->base.base.id, crtc->base.name, 646 old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe], 647 old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end, 648 new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end, 649 old_dbuf_state->active_pipes, new_dbuf_state->active_pipes); 650 651 return 0; 652 } 653 654 static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state, 655 int width, const struct drm_format_info *format, 656 u64 modifier, unsigned int rotation, 657 u32 plane_pixel_rate, struct skl_wm_params *wp, 658 int color_plane, unsigned int pan_x); 659 660 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, 661 struct intel_plane *plane, 662 int level, 663 unsigned int latency, 664 const struct skl_wm_params *wp, 665 const struct skl_wm_level *result_prev, 666 struct skl_wm_level *result /* out */); 667 668 static unsigned int skl_wm_latency(struct intel_display *display, int level, 669 const struct skl_wm_params *wp) 670 { 671 unsigned int latency = display->wm.skl_latency[level]; 672 673 if (latency == 0) 674 return 0; 675 676 /* 677 * WaIncreaseLatencyIPCEnabled: kbl,cfl 678 * Display WA #1141: kbl,cfl 679 */ 680 if ((display->platform.kabylake || display->platform.coffeelake || 681 display->platform.cometlake) && skl_watermark_ipc_enabled(display)) 682 latency += 4; 683 684 if (skl_needs_memory_bw_wa(display) && wp && wp->x_tiled) 685 latency += 15; 686 687 return latency; 688 } 689 690 static unsigned int 691 skl_cursor_allocation(const struct intel_crtc_state *crtc_state, 692 int num_active) 693 { 694 struct intel_display *display = to_intel_display(crtc_state); 695 struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor); 696 struct skl_wm_level wm = {}; 697 int ret, min_ddb_alloc = 0; 698 struct skl_wm_params wp; 699 int level; 700 701 ret = skl_compute_wm_params(crtc_state, 256, 702 drm_format_info(DRM_FORMAT_ARGB8888), 703 DRM_FORMAT_MOD_LINEAR, 704 DRM_MODE_ROTATE_0, 705 crtc_state->pixel_rate, &wp, 0, 0); 706 drm_WARN_ON(display->drm, ret); 707 708 for (level = 0; level < display->wm.num_levels; level++) { 709 unsigned int latency = skl_wm_latency(display, level, &wp); 710 711 skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm); 712 if (wm.min_ddb_alloc == U16_MAX) 713 break; 714 715 min_ddb_alloc = wm.min_ddb_alloc; 716 } 717 718 return max(num_active == 1 ? 32 : 8, min_ddb_alloc); 719 } 720 721 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) 722 { 723 skl_ddb_entry_init(entry, 724 REG_FIELD_GET(PLANE_BUF_START_MASK, reg), 725 REG_FIELD_GET(PLANE_BUF_END_MASK, reg)); 726 if (entry->end) 727 entry->end++; 728 } 729 730 static void 731 skl_ddb_get_hw_plane_state(struct intel_display *display, 732 const enum pipe pipe, 733 const enum plane_id plane_id, 734 struct skl_ddb_entry *ddb, 735 struct skl_ddb_entry *ddb_y, 736 u16 *min_ddb, u16 *interim_ddb) 737 { 738 u32 val; 739 740 /* Cursor doesn't support NV12/planar, so no extra calculation needed */ 741 if (plane_id == PLANE_CURSOR) { 742 val = intel_de_read(display, CUR_BUF_CFG(pipe)); 743 skl_ddb_entry_init_from_hw(ddb, val); 744 return; 745 } 746 747 val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id)); 748 skl_ddb_entry_init_from_hw(ddb, val); 749 750 if (DISPLAY_VER(display) >= 30) { 751 val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id)); 752 753 *min_ddb = REG_FIELD_GET(PLANE_MIN_DBUF_BLOCKS_MASK, val); 754 *interim_ddb = REG_FIELD_GET(PLANE_INTERIM_DBUF_BLOCKS_MASK, val); 755 } 756 757 if (DISPLAY_VER(display) >= 11) 758 return; 759 760 val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id)); 761 skl_ddb_entry_init_from_hw(ddb_y, val); 762 } 763 764 static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, 765 struct skl_ddb_entry *ddb, 766 struct skl_ddb_entry *ddb_y, 767 u16 *min_ddb, u16 *interim_ddb) 768 { 769 struct intel_display *display = to_intel_display(crtc); 770 enum intel_display_power_domain power_domain; 771 enum pipe pipe = crtc->pipe; 772 intel_wakeref_t wakeref; 773 enum plane_id plane_id; 774 775 power_domain = POWER_DOMAIN_PIPE(pipe); 776 wakeref = intel_display_power_get_if_enabled(display, power_domain); 777 if (!wakeref) 778 return; 779 780 for_each_plane_id_on_crtc(crtc, plane_id) 781 skl_ddb_get_hw_plane_state(display, pipe, 782 plane_id, 783 &ddb[plane_id], 784 &ddb_y[plane_id], 785 &min_ddb[plane_id], 786 &interim_ddb[plane_id]); 787 788 intel_display_power_put(display, power_domain, wakeref); 789 } 790 791 struct dbuf_slice_conf_entry { 792 u8 active_pipes; 793 u8 dbuf_mask[I915_MAX_PIPES]; 794 bool join_mbus; 795 }; 796 797 /* 798 * Table taken from Bspec 12716 799 * Pipes do have some preferred DBuf slice affinity, 800 * plus there are some hardcoded requirements on how 801 * those should be distributed for multipipe scenarios. 802 * For more DBuf slices algorithm can get even more messy 803 * and less readable, so decided to use a table almost 804 * as is from BSpec itself - that way it is at least easier 805 * to compare, change and check. 806 */ 807 static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] = 808 /* Autogenerated with igt/tools/intel_dbuf_map tool: */ 809 { 810 { 811 .active_pipes = BIT(PIPE_A), 812 .dbuf_mask = { 813 [PIPE_A] = BIT(DBUF_S1), 814 }, 815 }, 816 { 817 .active_pipes = BIT(PIPE_B), 818 .dbuf_mask = { 819 [PIPE_B] = BIT(DBUF_S1), 820 }, 821 }, 822 { 823 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 824 .dbuf_mask = { 825 [PIPE_A] = BIT(DBUF_S1), 826 [PIPE_B] = BIT(DBUF_S2), 827 }, 828 }, 829 { 830 .active_pipes = BIT(PIPE_C), 831 .dbuf_mask = { 832 [PIPE_C] = BIT(DBUF_S2), 833 }, 834 }, 835 { 836 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 837 .dbuf_mask = { 838 [PIPE_A] = BIT(DBUF_S1), 839 [PIPE_C] = BIT(DBUF_S2), 840 }, 841 }, 842 { 843 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 844 .dbuf_mask = { 845 [PIPE_B] = BIT(DBUF_S1), 846 [PIPE_C] = BIT(DBUF_S2), 847 }, 848 }, 849 { 850 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 851 .dbuf_mask = { 852 [PIPE_A] = BIT(DBUF_S1), 853 [PIPE_B] = BIT(DBUF_S1), 854 [PIPE_C] = BIT(DBUF_S2), 855 }, 856 }, 857 {} 858 }; 859 860 /* 861 * Table taken from Bspec 49255 862 * Pipes do have some preferred DBuf slice affinity, 863 * plus there are some hardcoded requirements on how 864 * those should be distributed for multipipe scenarios. 865 * For more DBuf slices algorithm can get even more messy 866 * and less readable, so decided to use a table almost 867 * as is from BSpec itself - that way it is at least easier 868 * to compare, change and check. 869 */ 870 static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = 871 /* Autogenerated with igt/tools/intel_dbuf_map tool: */ 872 { 873 { 874 .active_pipes = BIT(PIPE_A), 875 .dbuf_mask = { 876 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 877 }, 878 }, 879 { 880 .active_pipes = BIT(PIPE_B), 881 .dbuf_mask = { 882 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 883 }, 884 }, 885 { 886 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 887 .dbuf_mask = { 888 [PIPE_A] = BIT(DBUF_S2), 889 [PIPE_B] = BIT(DBUF_S1), 890 }, 891 }, 892 { 893 .active_pipes = BIT(PIPE_C), 894 .dbuf_mask = { 895 [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1), 896 }, 897 }, 898 { 899 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 900 .dbuf_mask = { 901 [PIPE_A] = BIT(DBUF_S1), 902 [PIPE_C] = BIT(DBUF_S2), 903 }, 904 }, 905 { 906 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 907 .dbuf_mask = { 908 [PIPE_B] = BIT(DBUF_S1), 909 [PIPE_C] = BIT(DBUF_S2), 910 }, 911 }, 912 { 913 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 914 .dbuf_mask = { 915 [PIPE_A] = BIT(DBUF_S1), 916 [PIPE_B] = BIT(DBUF_S1), 917 [PIPE_C] = BIT(DBUF_S2), 918 }, 919 }, 920 { 921 .active_pipes = BIT(PIPE_D), 922 .dbuf_mask = { 923 [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1), 924 }, 925 }, 926 { 927 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), 928 .dbuf_mask = { 929 [PIPE_A] = BIT(DBUF_S1), 930 [PIPE_D] = BIT(DBUF_S2), 931 }, 932 }, 933 { 934 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), 935 .dbuf_mask = { 936 [PIPE_B] = BIT(DBUF_S1), 937 [PIPE_D] = BIT(DBUF_S2), 938 }, 939 }, 940 { 941 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), 942 .dbuf_mask = { 943 [PIPE_A] = BIT(DBUF_S1), 944 [PIPE_B] = BIT(DBUF_S1), 945 [PIPE_D] = BIT(DBUF_S2), 946 }, 947 }, 948 { 949 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), 950 .dbuf_mask = { 951 [PIPE_C] = BIT(DBUF_S1), 952 [PIPE_D] = BIT(DBUF_S2), 953 }, 954 }, 955 { 956 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), 957 .dbuf_mask = { 958 [PIPE_A] = BIT(DBUF_S1), 959 [PIPE_C] = BIT(DBUF_S2), 960 [PIPE_D] = BIT(DBUF_S2), 961 }, 962 }, 963 { 964 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 965 .dbuf_mask = { 966 [PIPE_B] = BIT(DBUF_S1), 967 [PIPE_C] = BIT(DBUF_S2), 968 [PIPE_D] = BIT(DBUF_S2), 969 }, 970 }, 971 { 972 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 973 .dbuf_mask = { 974 [PIPE_A] = BIT(DBUF_S1), 975 [PIPE_B] = BIT(DBUF_S1), 976 [PIPE_C] = BIT(DBUF_S2), 977 [PIPE_D] = BIT(DBUF_S2), 978 }, 979 }, 980 {} 981 }; 982 983 static const struct dbuf_slice_conf_entry dg2_allowed_dbufs[] = { 984 { 985 .active_pipes = BIT(PIPE_A), 986 .dbuf_mask = { 987 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 988 }, 989 }, 990 { 991 .active_pipes = BIT(PIPE_B), 992 .dbuf_mask = { 993 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 994 }, 995 }, 996 { 997 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 998 .dbuf_mask = { 999 [PIPE_A] = BIT(DBUF_S1), 1000 [PIPE_B] = BIT(DBUF_S2), 1001 }, 1002 }, 1003 { 1004 .active_pipes = BIT(PIPE_C), 1005 .dbuf_mask = { 1006 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1007 }, 1008 }, 1009 { 1010 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 1011 .dbuf_mask = { 1012 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1013 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1014 }, 1015 }, 1016 { 1017 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 1018 .dbuf_mask = { 1019 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 1020 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1021 }, 1022 }, 1023 { 1024 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 1025 .dbuf_mask = { 1026 [PIPE_A] = BIT(DBUF_S1), 1027 [PIPE_B] = BIT(DBUF_S2), 1028 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1029 }, 1030 }, 1031 { 1032 .active_pipes = BIT(PIPE_D), 1033 .dbuf_mask = { 1034 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 1035 }, 1036 }, 1037 { 1038 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), 1039 .dbuf_mask = { 1040 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1041 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 1042 }, 1043 }, 1044 { 1045 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), 1046 .dbuf_mask = { 1047 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 1048 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 1049 }, 1050 }, 1051 { 1052 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), 1053 .dbuf_mask = { 1054 [PIPE_A] = BIT(DBUF_S1), 1055 [PIPE_B] = BIT(DBUF_S2), 1056 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 1057 }, 1058 }, 1059 { 1060 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), 1061 .dbuf_mask = { 1062 [PIPE_C] = BIT(DBUF_S3), 1063 [PIPE_D] = BIT(DBUF_S4), 1064 }, 1065 }, 1066 { 1067 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), 1068 .dbuf_mask = { 1069 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1070 [PIPE_C] = BIT(DBUF_S3), 1071 [PIPE_D] = BIT(DBUF_S4), 1072 }, 1073 }, 1074 { 1075 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1076 .dbuf_mask = { 1077 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 1078 [PIPE_C] = BIT(DBUF_S3), 1079 [PIPE_D] = BIT(DBUF_S4), 1080 }, 1081 }, 1082 { 1083 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1084 .dbuf_mask = { 1085 [PIPE_A] = BIT(DBUF_S1), 1086 [PIPE_B] = BIT(DBUF_S2), 1087 [PIPE_C] = BIT(DBUF_S3), 1088 [PIPE_D] = BIT(DBUF_S4), 1089 }, 1090 }, 1091 {} 1092 }; 1093 1094 static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = { 1095 /* 1096 * Keep the join_mbus cases first so check_mbus_joined() 1097 * will prefer them over the !join_mbus cases. 1098 */ 1099 { 1100 .active_pipes = BIT(PIPE_A), 1101 .dbuf_mask = { 1102 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4), 1103 }, 1104 .join_mbus = true, 1105 }, 1106 { 1107 .active_pipes = BIT(PIPE_B), 1108 .dbuf_mask = { 1109 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4), 1110 }, 1111 .join_mbus = true, 1112 }, 1113 { 1114 .active_pipes = BIT(PIPE_A), 1115 .dbuf_mask = { 1116 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1117 }, 1118 .join_mbus = false, 1119 }, 1120 { 1121 .active_pipes = BIT(PIPE_B), 1122 .dbuf_mask = { 1123 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1124 }, 1125 .join_mbus = false, 1126 }, 1127 { 1128 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 1129 .dbuf_mask = { 1130 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1131 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1132 }, 1133 }, 1134 { 1135 .active_pipes = BIT(PIPE_C), 1136 .dbuf_mask = { 1137 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1138 }, 1139 }, 1140 { 1141 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 1142 .dbuf_mask = { 1143 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1144 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1145 }, 1146 }, 1147 { 1148 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 1149 .dbuf_mask = { 1150 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1151 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1152 }, 1153 }, 1154 { 1155 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 1156 .dbuf_mask = { 1157 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1158 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1159 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1160 }, 1161 }, 1162 { 1163 .active_pipes = BIT(PIPE_D), 1164 .dbuf_mask = { 1165 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1166 }, 1167 }, 1168 { 1169 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), 1170 .dbuf_mask = { 1171 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1172 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1173 }, 1174 }, 1175 { 1176 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), 1177 .dbuf_mask = { 1178 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1179 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1180 }, 1181 }, 1182 { 1183 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), 1184 .dbuf_mask = { 1185 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1186 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1187 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1188 }, 1189 }, 1190 { 1191 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), 1192 .dbuf_mask = { 1193 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1194 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1195 }, 1196 }, 1197 { 1198 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), 1199 .dbuf_mask = { 1200 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1201 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1202 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1203 }, 1204 }, 1205 { 1206 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1207 .dbuf_mask = { 1208 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1209 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1210 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1211 }, 1212 }, 1213 { 1214 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1215 .dbuf_mask = { 1216 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1217 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1218 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1219 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1220 }, 1221 }, 1222 {} 1223 1224 }; 1225 1226 static bool check_mbus_joined(u8 active_pipes, 1227 const struct dbuf_slice_conf_entry *dbuf_slices) 1228 { 1229 int i; 1230 1231 for (i = 0; dbuf_slices[i].active_pipes != 0; i++) { 1232 if (dbuf_slices[i].active_pipes == active_pipes) 1233 return dbuf_slices[i].join_mbus; 1234 } 1235 return false; 1236 } 1237 1238 static bool adlp_check_mbus_joined(u8 active_pipes) 1239 { 1240 return check_mbus_joined(active_pipes, adlp_allowed_dbufs); 1241 } 1242 1243 static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus, 1244 const struct dbuf_slice_conf_entry *dbuf_slices) 1245 { 1246 int i; 1247 1248 for (i = 0; dbuf_slices[i].active_pipes != 0; i++) { 1249 if (dbuf_slices[i].active_pipes == active_pipes && 1250 dbuf_slices[i].join_mbus == join_mbus) 1251 return dbuf_slices[i].dbuf_mask[pipe]; 1252 } 1253 return 0; 1254 } 1255 1256 /* 1257 * This function finds an entry with same enabled pipe configuration and 1258 * returns correspondent DBuf slice mask as stated in BSpec for particular 1259 * platform. 1260 */ 1261 static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1262 { 1263 /* 1264 * FIXME: For ICL this is still a bit unclear as prev BSpec revision 1265 * required calculating "pipe ratio" in order to determine 1266 * if one or two slices can be used for single pipe configurations 1267 * as additional constraint to the existing table. 1268 * However based on recent info, it should be not "pipe ratio" 1269 * but rather ratio between pixel_rate and cdclk with additional 1270 * constants, so for now we are using only table until this is 1271 * clarified. Also this is the reason why crtc_state param is 1272 * still here - we will need it once those additional constraints 1273 * pop up. 1274 */ 1275 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1276 icl_allowed_dbufs); 1277 } 1278 1279 static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1280 { 1281 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1282 tgl_allowed_dbufs); 1283 } 1284 1285 static u8 adlp_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1286 { 1287 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1288 adlp_allowed_dbufs); 1289 } 1290 1291 static u8 dg2_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1292 { 1293 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1294 dg2_allowed_dbufs); 1295 } 1296 1297 static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool join_mbus) 1298 { 1299 struct intel_display *display = to_intel_display(crtc); 1300 enum pipe pipe = crtc->pipe; 1301 1302 if (display->platform.dg2) 1303 return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1304 else if (DISPLAY_VER(display) >= 13) 1305 return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1306 else if (DISPLAY_VER(display) == 12) 1307 return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1308 else if (DISPLAY_VER(display) == 11) 1309 return icl_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1310 /* 1311 * For anything else just return one slice yet. 1312 * Should be extended for other platforms. 1313 */ 1314 return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0; 1315 } 1316 1317 static bool 1318 use_minimal_wm0_only(const struct intel_crtc_state *crtc_state, 1319 struct intel_plane *plane) 1320 { 1321 struct intel_display *display = to_intel_display(plane); 1322 1323 /* Xe3+ are auto minimum DDB capble. So don't force minimal wm0 */ 1324 return IS_DISPLAY_VER(display, 13, 20) && 1325 crtc_state->uapi.async_flip && 1326 plane->async_flip; 1327 } 1328 1329 unsigned int 1330 skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, 1331 struct intel_plane *plane, int width, int height, 1332 int cpp) 1333 { 1334 /* 1335 * We calculate extra ddb based on ratio plane rate/total data rate 1336 * in case, in some cases we should not allocate extra ddb for the plane, 1337 * so do not count its data rate, if this is the case. 1338 */ 1339 if (use_minimal_wm0_only(crtc_state, plane)) 1340 return 0; 1341 1342 return width * height * cpp; 1343 } 1344 1345 static u64 1346 skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state) 1347 { 1348 struct intel_display *display = to_intel_display(crtc_state); 1349 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1350 enum plane_id plane_id; 1351 u64 data_rate = 0; 1352 1353 for_each_plane_id_on_crtc(crtc, plane_id) { 1354 if (plane_id == PLANE_CURSOR) 1355 continue; 1356 1357 data_rate += crtc_state->rel_data_rate[plane_id]; 1358 1359 if (DISPLAY_VER(display) < 11) 1360 data_rate += crtc_state->rel_data_rate_y[plane_id]; 1361 } 1362 1363 return data_rate; 1364 } 1365 1366 const struct skl_wm_level * 1367 skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, 1368 enum plane_id plane_id, 1369 int level) 1370 { 1371 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 1372 1373 if (level == 0 && pipe_wm->use_sagv_wm) 1374 return &wm->sagv.wm0; 1375 1376 return &wm->wm[level]; 1377 } 1378 1379 const struct skl_wm_level * 1380 skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm, 1381 enum plane_id plane_id) 1382 { 1383 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 1384 1385 if (pipe_wm->use_sagv_wm) 1386 return &wm->sagv.trans_wm; 1387 1388 return &wm->trans_wm; 1389 } 1390 1391 /* 1392 * We only disable the watermarks for each plane if 1393 * they exceed the ddb allocation of said plane. This 1394 * is done so that we don't end up touching cursor 1395 * watermarks needlessly when some other plane reduces 1396 * our max possible watermark level. 1397 * 1398 * Bspec has this to say about the PLANE_WM enable bit: 1399 * "All the watermarks at this level for all enabled 1400 * planes must be enabled before the level will be used." 1401 * So this is actually safe to do. 1402 */ 1403 static void 1404 skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb) 1405 { 1406 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) 1407 memset(wm, 0, sizeof(*wm)); 1408 } 1409 1410 static void 1411 skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm, 1412 const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb) 1413 { 1414 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) || 1415 uv_wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) { 1416 memset(wm, 0, sizeof(*wm)); 1417 memset(uv_wm, 0, sizeof(*uv_wm)); 1418 } 1419 } 1420 1421 static bool skl_need_wm_copy_wa(struct intel_display *display, int level, 1422 const struct skl_plane_wm *wm) 1423 { 1424 /* 1425 * Wa_1408961008:icl, ehl 1426 * Wa_14012656716:tgl, adl 1427 * Wa_14017887344:icl 1428 * Wa_14017868169:adl, tgl 1429 * Due to some power saving optimizations, different subsystems 1430 * like PSR, might still use even disabled wm level registers, 1431 * for "reference", so lets keep at least the values sane. 1432 * Considering amount of WA requiring us to do similar things, was 1433 * decided to simply do it for all of the platforms, as those wm 1434 * levels are disabled, this isn't going to do harm anyway. 1435 */ 1436 return level > 0 && !wm->wm[level].enable; 1437 } 1438 1439 struct skl_plane_ddb_iter { 1440 u64 data_rate; 1441 u16 start, size; 1442 }; 1443 1444 static void 1445 skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter, 1446 struct skl_ddb_entry *ddb, 1447 const struct skl_wm_level *wm, 1448 u64 data_rate) 1449 { 1450 u16 size, extra = 0; 1451 1452 if (data_rate) { 1453 extra = min_t(u16, iter->size, 1454 DIV64_U64_ROUND_UP(iter->size * data_rate, 1455 iter->data_rate)); 1456 iter->size -= extra; 1457 iter->data_rate -= data_rate; 1458 } 1459 1460 /* 1461 * Keep ddb entry of all disabled planes explicitly zeroed 1462 * to avoid skl_ddb_add_affected_planes() adding them to 1463 * the state when other planes change their allocations. 1464 */ 1465 size = wm->min_ddb_alloc + extra; 1466 if (size) 1467 iter->start = skl_ddb_entry_init(ddb, iter->start, 1468 iter->start + size); 1469 } 1470 1471 static int 1472 skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, 1473 struct intel_crtc *crtc) 1474 { 1475 struct intel_crtc_state *crtc_state = 1476 intel_atomic_get_new_crtc_state(state, crtc); 1477 const struct intel_dbuf_state *dbuf_state = 1478 intel_atomic_get_new_dbuf_state(state); 1479 const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe]; 1480 struct intel_display *display = to_intel_display(state); 1481 int num_active = hweight8(dbuf_state->active_pipes); 1482 struct skl_plane_ddb_iter iter; 1483 enum plane_id plane_id; 1484 u16 cursor_size; 1485 u32 blocks; 1486 int level; 1487 1488 /* Clear the partitioning for disabled planes. */ 1489 memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb)); 1490 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); 1491 memset(crtc_state->wm.skl.plane_min_ddb, 0, 1492 sizeof(crtc_state->wm.skl.plane_min_ddb)); 1493 memset(crtc_state->wm.skl.plane_interim_ddb, 0, 1494 sizeof(crtc_state->wm.skl.plane_interim_ddb)); 1495 1496 if (!crtc_state->hw.active) 1497 return 0; 1498 1499 iter.start = alloc->start; 1500 iter.size = skl_ddb_entry_size(alloc); 1501 if (iter.size == 0) 1502 return 0; 1503 1504 /* Allocate fixed number of blocks for cursor. */ 1505 cursor_size = skl_cursor_allocation(crtc_state, num_active); 1506 iter.size -= cursor_size; 1507 skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR], 1508 alloc->end - cursor_size, alloc->end); 1509 1510 iter.data_rate = skl_total_relative_data_rate(crtc_state); 1511 1512 /* 1513 * Find the highest watermark level for which we can satisfy the block 1514 * requirement of active planes. 1515 */ 1516 for (level = display->wm.num_levels - 1; level >= 0; level--) { 1517 blocks = 0; 1518 for_each_plane_id_on_crtc(crtc, plane_id) { 1519 const struct skl_plane_wm *wm = 1520 &crtc_state->wm.skl.optimal.planes[plane_id]; 1521 1522 if (plane_id == PLANE_CURSOR) { 1523 const struct skl_ddb_entry *ddb = 1524 &crtc_state->wm.skl.plane_ddb[plane_id]; 1525 1526 if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) { 1527 drm_WARN_ON(display->drm, 1528 wm->wm[level].min_ddb_alloc != U16_MAX); 1529 blocks = U32_MAX; 1530 break; 1531 } 1532 continue; 1533 } 1534 1535 blocks += wm->wm[level].min_ddb_alloc; 1536 blocks += wm->uv_wm[level].min_ddb_alloc; 1537 } 1538 1539 if (blocks <= iter.size) { 1540 iter.size -= blocks; 1541 break; 1542 } 1543 } 1544 1545 if (level < 0) { 1546 drm_dbg_kms(display->drm, 1547 "Requested display configuration exceeds system DDB limitations"); 1548 drm_dbg_kms(display->drm, "minimum required %d/%d\n", 1549 blocks, iter.size); 1550 return -EINVAL; 1551 } 1552 1553 /* avoid the WARN later when we don't allocate any extra DDB */ 1554 if (iter.data_rate == 0) 1555 iter.size = 0; 1556 1557 /* 1558 * Grant each plane the blocks it requires at the highest achievable 1559 * watermark level, plus an extra share of the leftover blocks 1560 * proportional to its relative data rate. 1561 */ 1562 for_each_plane_id_on_crtc(crtc, plane_id) { 1563 struct skl_ddb_entry *ddb = 1564 &crtc_state->wm.skl.plane_ddb[plane_id]; 1565 struct skl_ddb_entry *ddb_y = 1566 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 1567 u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id]; 1568 u16 *interim_ddb = 1569 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; 1570 const struct skl_plane_wm *wm = 1571 &crtc_state->wm.skl.optimal.planes[plane_id]; 1572 1573 if (plane_id == PLANE_CURSOR) 1574 continue; 1575 1576 if (DISPLAY_VER(display) < 11 && 1577 crtc_state->nv12_planes & BIT(plane_id)) { 1578 skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level], 1579 crtc_state->rel_data_rate_y[plane_id]); 1580 skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level], 1581 crtc_state->rel_data_rate[plane_id]); 1582 } else { 1583 skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level], 1584 crtc_state->rel_data_rate[plane_id]); 1585 } 1586 1587 if (DISPLAY_VER(display) >= 30) { 1588 *min_ddb = wm->wm[0].min_ddb_alloc; 1589 *interim_ddb = wm->sagv.wm0.min_ddb_alloc; 1590 } 1591 } 1592 drm_WARN_ON(display->drm, iter.size != 0 || iter.data_rate != 0); 1593 1594 /* 1595 * When we calculated watermark values we didn't know how high 1596 * of a level we'd actually be able to hit, so we just marked 1597 * all levels as "enabled." Go back now and disable the ones 1598 * that aren't actually possible. 1599 */ 1600 for (level++; level < display->wm.num_levels; level++) { 1601 for_each_plane_id_on_crtc(crtc, plane_id) { 1602 const struct skl_ddb_entry *ddb = 1603 &crtc_state->wm.skl.plane_ddb[plane_id]; 1604 const struct skl_ddb_entry *ddb_y = 1605 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 1606 struct skl_plane_wm *wm = 1607 &crtc_state->wm.skl.optimal.planes[plane_id]; 1608 1609 if (DISPLAY_VER(display) < 11 && 1610 crtc_state->nv12_planes & BIT(plane_id)) 1611 skl_check_nv12_wm_level(&wm->wm[level], 1612 &wm->uv_wm[level], 1613 ddb_y, ddb); 1614 else 1615 skl_check_wm_level(&wm->wm[level], ddb); 1616 1617 if (skl_need_wm_copy_wa(display, level, wm)) { 1618 wm->wm[level].blocks = wm->wm[level - 1].blocks; 1619 wm->wm[level].lines = wm->wm[level - 1].lines; 1620 wm->wm[level].ignore_lines = wm->wm[level - 1].ignore_lines; 1621 } 1622 } 1623 } 1624 1625 /* 1626 * Go back and disable the transition and SAGV watermarks 1627 * if it turns out we don't have enough DDB blocks for them. 1628 */ 1629 for_each_plane_id_on_crtc(crtc, plane_id) { 1630 const struct skl_ddb_entry *ddb = 1631 &crtc_state->wm.skl.plane_ddb[plane_id]; 1632 const struct skl_ddb_entry *ddb_y = 1633 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 1634 u16 *interim_ddb = 1635 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; 1636 struct skl_plane_wm *wm = 1637 &crtc_state->wm.skl.optimal.planes[plane_id]; 1638 1639 if (DISPLAY_VER(display) < 11 && 1640 crtc_state->nv12_planes & BIT(plane_id)) { 1641 skl_check_wm_level(&wm->trans_wm, ddb_y); 1642 } else { 1643 WARN_ON(skl_ddb_entry_size(ddb_y)); 1644 1645 skl_check_wm_level(&wm->trans_wm, ddb); 1646 } 1647 1648 skl_check_wm_level(&wm->sagv.wm0, ddb); 1649 if (DISPLAY_VER(display) >= 30) 1650 *interim_ddb = wm->sagv.wm0.min_ddb_alloc; 1651 1652 skl_check_wm_level(&wm->sagv.trans_wm, ddb); 1653 } 1654 1655 return 0; 1656 } 1657 1658 /* 1659 * The max latency should be 257 (max the punit can code is 255 and we add 2us 1660 * for the read latency) and cpp should always be <= 8, so that 1661 * should allow pixel_rate up to ~2 GHz which seems sufficient since max 1662 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. 1663 */ 1664 static uint_fixed_16_16_t 1665 skl_wm_method1(struct intel_display *display, u32 pixel_rate, 1666 u8 cpp, u32 latency, u32 dbuf_block_size) 1667 { 1668 u32 wm_intermediate_val; 1669 uint_fixed_16_16_t ret; 1670 1671 if (latency == 0) 1672 return FP_16_16_MAX; 1673 1674 wm_intermediate_val = latency * pixel_rate * cpp; 1675 ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size); 1676 1677 if (DISPLAY_VER(display) >= 10) 1678 ret = add_fixed16_u32(ret, 1); 1679 1680 return ret; 1681 } 1682 1683 static uint_fixed_16_16_t 1684 skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency, 1685 uint_fixed_16_16_t plane_blocks_per_line) 1686 { 1687 u32 wm_intermediate_val; 1688 uint_fixed_16_16_t ret; 1689 1690 if (latency == 0) 1691 return FP_16_16_MAX; 1692 1693 wm_intermediate_val = latency * pixel_rate; 1694 wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val, 1695 pipe_htotal * 1000); 1696 ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line); 1697 return ret; 1698 } 1699 1700 static uint_fixed_16_16_t 1701 intel_get_linetime_us(const struct intel_crtc_state *crtc_state) 1702 { 1703 struct intel_display *display = to_intel_display(crtc_state); 1704 u32 pixel_rate; 1705 u32 crtc_htotal; 1706 uint_fixed_16_16_t linetime_us; 1707 1708 if (!crtc_state->hw.active) 1709 return u32_to_fixed16(0); 1710 1711 pixel_rate = crtc_state->pixel_rate; 1712 1713 if (drm_WARN_ON(display->drm, pixel_rate == 0)) 1714 return u32_to_fixed16(0); 1715 1716 crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal; 1717 linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate); 1718 1719 return linetime_us; 1720 } 1721 1722 static int 1723 skl_compute_wm_params(const struct intel_crtc_state *crtc_state, 1724 int width, const struct drm_format_info *format, 1725 u64 modifier, unsigned int rotation, 1726 u32 plane_pixel_rate, struct skl_wm_params *wp, 1727 int color_plane, unsigned int pan_x) 1728 { 1729 struct intel_display *display = to_intel_display(crtc_state); 1730 u32 interm_pbpl; 1731 1732 /* only planar format has two planes */ 1733 if (color_plane == 1 && 1734 !intel_format_info_is_yuv_semiplanar(format, modifier)) { 1735 drm_dbg_kms(display->drm, 1736 "Non planar format have single plane\n"); 1737 return -EINVAL; 1738 } 1739 1740 wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; 1741 wp->y_tiled = modifier != I915_FORMAT_MOD_X_TILED && 1742 intel_fb_is_tiled_modifier(modifier); 1743 wp->rc_surface = intel_fb_is_ccs_modifier(modifier); 1744 wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); 1745 1746 wp->width = width; 1747 if (color_plane == 1 && wp->is_planar) 1748 wp->width /= 2; 1749 1750 wp->cpp = format->cpp[color_plane]; 1751 wp->plane_pixel_rate = plane_pixel_rate; 1752 1753 if (DISPLAY_VER(display) >= 11 && 1754 modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1) 1755 wp->dbuf_block_size = 256; 1756 else 1757 wp->dbuf_block_size = 512; 1758 1759 if (drm_rotation_90_or_270(rotation)) { 1760 switch (wp->cpp) { 1761 case 1: 1762 wp->y_min_scanlines = 16; 1763 break; 1764 case 2: 1765 wp->y_min_scanlines = 8; 1766 break; 1767 case 4: 1768 wp->y_min_scanlines = 4; 1769 break; 1770 default: 1771 MISSING_CASE(wp->cpp); 1772 return -EINVAL; 1773 } 1774 } else { 1775 wp->y_min_scanlines = 4; 1776 } 1777 1778 if (skl_needs_memory_bw_wa(display)) 1779 wp->y_min_scanlines *= 2; 1780 1781 wp->plane_bytes_per_line = wp->width * wp->cpp; 1782 if (wp->y_tiled) { 1783 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line * 1784 wp->y_min_scanlines, 1785 wp->dbuf_block_size); 1786 1787 if (DISPLAY_VER(display) >= 30) 1788 interm_pbpl += (pan_x != 0); 1789 else if (DISPLAY_VER(display) >= 10) 1790 interm_pbpl++; 1791 1792 wp->plane_blocks_per_line = div_fixed16(interm_pbpl, 1793 wp->y_min_scanlines); 1794 } else { 1795 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 1796 wp->dbuf_block_size); 1797 1798 if (!wp->x_tiled || DISPLAY_VER(display) >= 10) 1799 interm_pbpl++; 1800 1801 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl); 1802 } 1803 1804 wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines, 1805 wp->plane_blocks_per_line); 1806 1807 wp->linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(crtc_state)); 1808 1809 return 0; 1810 } 1811 1812 static int 1813 skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state, 1814 const struct intel_plane_state *plane_state, 1815 struct skl_wm_params *wp, int color_plane) 1816 { 1817 const struct drm_framebuffer *fb = plane_state->hw.fb; 1818 int width; 1819 1820 /* 1821 * Src coordinates are already rotated by 270 degrees for 1822 * the 90/270 degree plane rotation cases (to match the 1823 * GTT mapping), hence no need to account for rotation here. 1824 */ 1825 width = drm_rect_width(&plane_state->uapi.src) >> 16; 1826 1827 return skl_compute_wm_params(crtc_state, width, 1828 fb->format, fb->modifier, 1829 plane_state->hw.rotation, 1830 intel_plane_pixel_rate(crtc_state, plane_state), 1831 wp, color_plane, 1832 plane_state->uapi.src.x1); 1833 } 1834 1835 static bool skl_wm_has_lines(struct intel_display *display, int level) 1836 { 1837 if (DISPLAY_VER(display) >= 10) 1838 return true; 1839 1840 /* The number of lines are ignored for the level 0 watermark. */ 1841 return level > 0; 1842 } 1843 1844 static int skl_wm_max_lines(struct intel_display *display) 1845 { 1846 if (DISPLAY_VER(display) >= 13) 1847 return 255; 1848 else 1849 return 31; 1850 } 1851 1852 static bool xe3_auto_min_alloc_capable(struct intel_plane *plane, int level) 1853 { 1854 struct intel_display *display = to_intel_display(plane); 1855 1856 return DISPLAY_VER(display) >= 30 && level == 0 && plane->id != PLANE_CURSOR; 1857 } 1858 1859 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, 1860 struct intel_plane *plane, 1861 int level, 1862 unsigned int latency, 1863 const struct skl_wm_params *wp, 1864 const struct skl_wm_level *result_prev, 1865 struct skl_wm_level *result /* out */) 1866 { 1867 struct intel_display *display = to_intel_display(crtc_state); 1868 uint_fixed_16_16_t method1, method2; 1869 uint_fixed_16_16_t selected_result; 1870 u32 blocks, lines, min_ddb_alloc = 0; 1871 1872 if (latency == 0 || 1873 (use_minimal_wm0_only(crtc_state, plane) && level > 0)) { 1874 /* reject it */ 1875 result->min_ddb_alloc = U16_MAX; 1876 return; 1877 } 1878 1879 method1 = skl_wm_method1(display, wp->plane_pixel_rate, 1880 wp->cpp, latency, wp->dbuf_block_size); 1881 method2 = skl_wm_method2(wp->plane_pixel_rate, 1882 crtc_state->hw.pipe_mode.crtc_htotal, 1883 latency, 1884 wp->plane_blocks_per_line); 1885 1886 if (wp->y_tiled) { 1887 selected_result = max_fixed16(method2, wp->y_tile_minimum); 1888 } else { 1889 if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal / 1890 wp->dbuf_block_size < 1) && 1891 (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) { 1892 selected_result = method2; 1893 } else if (latency >= wp->linetime_us) { 1894 if (DISPLAY_VER(display) == 9) 1895 selected_result = min_fixed16(method1, method2); 1896 else 1897 selected_result = method2; 1898 } else { 1899 selected_result = method1; 1900 } 1901 } 1902 1903 blocks = fixed16_to_u32_round_up(selected_result); 1904 if (DISPLAY_VER(display) < 30) 1905 blocks++; 1906 1907 /* 1908 * Lets have blocks at minimum equivalent to plane_blocks_per_line 1909 * as there will be at minimum one line for lines configuration. This 1910 * is a work around for FIFO underruns observed with resolutions like 1911 * 4k 60 Hz in single channel DRAM configurations. 1912 * 1913 * As per the Bspec 49325, if the ddb allocation can hold at least 1914 * one plane_blocks_per_line, we should have selected method2 in 1915 * the above logic. Assuming that modern versions have enough dbuf 1916 * and method2 guarantees blocks equivalent to at least 1 line, 1917 * select the blocks as plane_blocks_per_line. 1918 * 1919 * TODO: Revisit the logic when we have better understanding on DRAM 1920 * channels' impact on the level 0 memory latency and the relevant 1921 * wm calculations. 1922 */ 1923 if (skl_wm_has_lines(display, level)) 1924 blocks = max(blocks, 1925 fixed16_to_u32_round_up(wp->plane_blocks_per_line)); 1926 lines = div_round_up_fixed16(selected_result, 1927 wp->plane_blocks_per_line); 1928 1929 if (DISPLAY_VER(display) == 9) { 1930 /* Display WA #1125: skl,bxt,kbl */ 1931 if (level == 0 && wp->rc_surface) 1932 blocks += fixed16_to_u32_round_up(wp->y_tile_minimum); 1933 1934 /* Display WA #1126: skl,bxt,kbl */ 1935 if (level >= 1 && level <= 7) { 1936 if (wp->y_tiled) { 1937 blocks += fixed16_to_u32_round_up(wp->y_tile_minimum); 1938 lines += wp->y_min_scanlines; 1939 } else { 1940 blocks++; 1941 } 1942 1943 /* 1944 * Make sure result blocks for higher latency levels are 1945 * at least as high as level below the current level. 1946 * Assumption in DDB algorithm optimization for special 1947 * cases. Also covers Display WA #1125 for RC. 1948 */ 1949 if (result_prev->blocks > blocks) 1950 blocks = result_prev->blocks; 1951 } 1952 } 1953 1954 if (DISPLAY_VER(display) >= 11) { 1955 if (wp->y_tiled) { 1956 int extra_lines; 1957 1958 if (lines % wp->y_min_scanlines == 0) 1959 extra_lines = wp->y_min_scanlines; 1960 else 1961 extra_lines = wp->y_min_scanlines * 2 - 1962 lines % wp->y_min_scanlines; 1963 1964 min_ddb_alloc = mul_round_up_u32_fixed16(lines + extra_lines, 1965 wp->plane_blocks_per_line); 1966 } else { 1967 min_ddb_alloc = blocks + DIV_ROUND_UP(blocks, 10); 1968 } 1969 } 1970 1971 if (!skl_wm_has_lines(display, level)) 1972 lines = 0; 1973 1974 if (lines > skl_wm_max_lines(display)) { 1975 /* reject it */ 1976 result->min_ddb_alloc = U16_MAX; 1977 return; 1978 } 1979 1980 /* 1981 * If lines is valid, assume we can use this watermark level 1982 * for now. We'll come back and disable it after we calculate the 1983 * DDB allocation if it turns out we don't actually have enough 1984 * blocks to satisfy it. 1985 */ 1986 result->blocks = blocks; 1987 result->lines = lines; 1988 /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */ 1989 result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1; 1990 result->enable = true; 1991 result->auto_min_alloc_wm_enable = xe3_auto_min_alloc_capable(plane, level); 1992 1993 if (DISPLAY_VER(display) < 12 && display->sagv.block_time_us) 1994 result->can_sagv = latency >= display->sagv.block_time_us; 1995 } 1996 1997 static void 1998 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state, 1999 struct intel_plane *plane, 2000 const struct skl_wm_params *wm_params, 2001 struct skl_wm_level *levels) 2002 { 2003 struct intel_display *display = to_intel_display(crtc_state); 2004 struct skl_wm_level *result_prev = &levels[0]; 2005 int level; 2006 2007 for (level = 0; level < display->wm.num_levels; level++) { 2008 struct skl_wm_level *result = &levels[level]; 2009 unsigned int latency = skl_wm_latency(display, level, wm_params); 2010 2011 skl_compute_plane_wm(crtc_state, plane, level, latency, 2012 wm_params, result_prev, result); 2013 2014 result_prev = result; 2015 } 2016 } 2017 2018 static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state, 2019 struct intel_plane *plane, 2020 const struct skl_wm_params *wm_params, 2021 struct skl_plane_wm *plane_wm) 2022 { 2023 struct intel_display *display = to_intel_display(crtc_state); 2024 struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0; 2025 struct skl_wm_level *levels = plane_wm->wm; 2026 unsigned int latency = 0; 2027 2028 if (display->sagv.block_time_us) 2029 latency = display->sagv.block_time_us + 2030 skl_wm_latency(display, 0, wm_params); 2031 2032 skl_compute_plane_wm(crtc_state, plane, 0, latency, 2033 wm_params, &levels[0], 2034 sagv_wm); 2035 } 2036 2037 static void skl_compute_transition_wm(struct intel_display *display, 2038 struct skl_wm_level *trans_wm, 2039 const struct skl_wm_level *wm0, 2040 const struct skl_wm_params *wp) 2041 { 2042 u16 trans_min, trans_amount, trans_y_tile_min; 2043 u16 wm0_blocks, trans_offset, blocks; 2044 2045 /* Transition WM don't make any sense if ipc is disabled */ 2046 if (!skl_watermark_ipc_enabled(display)) 2047 return; 2048 2049 /* 2050 * WaDisableTWM:skl,kbl,cfl,bxt 2051 * Transition WM are not recommended by HW team for GEN9 2052 */ 2053 if (DISPLAY_VER(display) == 9) 2054 return; 2055 2056 if (DISPLAY_VER(display) >= 11) 2057 trans_min = 4; 2058 else 2059 trans_min = 14; 2060 2061 /* Display WA #1140: glk,cnl */ 2062 if (DISPLAY_VER(display) == 10) 2063 trans_amount = 0; 2064 else 2065 trans_amount = 10; /* This is configurable amount */ 2066 2067 trans_offset = trans_min + trans_amount; 2068 2069 /* 2070 * The spec asks for Selected Result Blocks for wm0 (the real value), 2071 * not Result Blocks (the integer value). Pay attention to the capital 2072 * letters. The value wm_l0->blocks is actually Result Blocks, but 2073 * since Result Blocks is the ceiling of Selected Result Blocks plus 1, 2074 * and since we later will have to get the ceiling of the sum in the 2075 * transition watermarks calculation, we can just pretend Selected 2076 * Result Blocks is Result Blocks minus 1 and it should work for the 2077 * current platforms. 2078 */ 2079 wm0_blocks = wm0->blocks - 1; 2080 2081 if (wp->y_tiled) { 2082 trans_y_tile_min = 2083 (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum); 2084 blocks = max(wm0_blocks, trans_y_tile_min) + trans_offset; 2085 } else { 2086 blocks = wm0_blocks + trans_offset; 2087 } 2088 blocks++; 2089 2090 /* 2091 * Just assume we can enable the transition watermark. After 2092 * computing the DDB we'll come back and disable it if that 2093 * assumption turns out to be false. 2094 */ 2095 trans_wm->blocks = blocks; 2096 trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1); 2097 trans_wm->enable = true; 2098 } 2099 2100 static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state, 2101 const struct intel_plane_state *plane_state, 2102 struct intel_plane *plane, int color_plane) 2103 { 2104 struct intel_display *display = to_intel_display(crtc_state); 2105 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id]; 2106 struct skl_wm_params wm_params; 2107 int ret; 2108 2109 ret = skl_compute_plane_wm_params(crtc_state, plane_state, 2110 &wm_params, color_plane); 2111 if (ret) 2112 return ret; 2113 2114 skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm); 2115 2116 skl_compute_transition_wm(display, &wm->trans_wm, 2117 &wm->wm[0], &wm_params); 2118 2119 if (DISPLAY_VER(display) >= 12) { 2120 tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm); 2121 2122 skl_compute_transition_wm(display, &wm->sagv.trans_wm, 2123 &wm->sagv.wm0, &wm_params); 2124 } 2125 2126 return 0; 2127 } 2128 2129 static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state, 2130 const struct intel_plane_state *plane_state, 2131 struct intel_plane *plane) 2132 { 2133 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id]; 2134 struct skl_wm_params wm_params; 2135 int ret; 2136 2137 wm->is_planar = true; 2138 2139 /* uv plane watermarks must also be validated for NV12/Planar */ 2140 ret = skl_compute_plane_wm_params(crtc_state, plane_state, 2141 &wm_params, 1); 2142 if (ret) 2143 return ret; 2144 2145 skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm); 2146 2147 return 0; 2148 } 2149 2150 static int skl_build_plane_wm(struct intel_crtc_state *crtc_state, 2151 const struct intel_plane_state *plane_state) 2152 { 2153 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2154 enum plane_id plane_id = plane->id; 2155 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; 2156 const struct drm_framebuffer *fb = plane_state->hw.fb; 2157 int ret; 2158 2159 memset(wm, 0, sizeof(*wm)); 2160 2161 if (!intel_wm_plane_visible(crtc_state, plane_state)) 2162 return 0; 2163 2164 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2165 plane, 0); 2166 if (ret) 2167 return ret; 2168 2169 if (fb->format->is_yuv && fb->format->num_planes > 1) { 2170 ret = skl_build_plane_wm_uv(crtc_state, plane_state, 2171 plane); 2172 if (ret) 2173 return ret; 2174 } 2175 2176 return 0; 2177 } 2178 2179 static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, 2180 const struct intel_plane_state *plane_state) 2181 { 2182 struct intel_display *display = to_intel_display(plane_state); 2183 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2184 enum plane_id plane_id = plane->id; 2185 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; 2186 int ret; 2187 2188 /* Watermarks calculated on UV plane */ 2189 if (plane_state->is_y_plane) 2190 return 0; 2191 2192 memset(wm, 0, sizeof(*wm)); 2193 2194 if (plane_state->planar_linked_plane) { 2195 const struct drm_framebuffer *fb = plane_state->hw.fb; 2196 2197 drm_WARN_ON(display->drm, 2198 !intel_wm_plane_visible(crtc_state, plane_state)); 2199 drm_WARN_ON(display->drm, !fb->format->is_yuv || 2200 fb->format->num_planes == 1); 2201 2202 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2203 plane_state->planar_linked_plane, 0); 2204 if (ret) 2205 return ret; 2206 2207 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2208 plane, 1); 2209 if (ret) 2210 return ret; 2211 } else if (intel_wm_plane_visible(crtc_state, plane_state)) { 2212 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2213 plane, 0); 2214 if (ret) 2215 return ret; 2216 } 2217 2218 return 0; 2219 } 2220 2221 static int 2222 cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) 2223 { 2224 struct intel_display *display = to_intel_display(crtc_state); 2225 struct intel_atomic_state *state = 2226 to_intel_atomic_state(crtc_state->uapi.state); 2227 const struct intel_cdclk_state *cdclk_state; 2228 2229 cdclk_state = intel_atomic_get_cdclk_state(state); 2230 if (IS_ERR(cdclk_state)) { 2231 drm_WARN_ON(display->drm, PTR_ERR(cdclk_state)); 2232 return 1; 2233 } 2234 2235 return min(1, DIV_ROUND_UP(crtc_state->pixel_rate, 2236 2 * cdclk_state->logical.cdclk)); 2237 } 2238 2239 static int 2240 dsc_prefill_latency(const struct intel_crtc_state *crtc_state) 2241 { 2242 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2243 const struct intel_crtc_scaler_state *scaler_state = 2244 &crtc_state->scaler_state; 2245 int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, 2246 crtc_state->hw.adjusted_mode.clock); 2247 int num_scaler_users = hweight32(scaler_state->scaler_users); 2248 int chroma_downscaling_factor = 2249 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; 2250 u32 dsc_prefill_latency = 0; 2251 2252 if (!crtc_state->dsc.compression_enable || 2253 !num_scaler_users || 2254 num_scaler_users > crtc->num_scalers) 2255 return dsc_prefill_latency; 2256 2257 dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10); 2258 2259 for (int i = 0; i < num_scaler_users; i++) { 2260 u64 hscale_k, vscale_k; 2261 2262 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16); 2263 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16); 2264 dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k, 2265 1000000); 2266 } 2267 2268 dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state); 2269 2270 return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency); 2271 } 2272 2273 static int 2274 scaler_prefill_latency(const struct intel_crtc_state *crtc_state) 2275 { 2276 const struct intel_crtc_scaler_state *scaler_state = 2277 &crtc_state->scaler_state; 2278 int num_scaler_users = hweight32(scaler_state->scaler_users); 2279 int scaler_prefill_latency = 0; 2280 int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, 2281 crtc_state->hw.adjusted_mode.clock); 2282 2283 if (!num_scaler_users) 2284 return scaler_prefill_latency; 2285 2286 scaler_prefill_latency = 4 * linetime; 2287 2288 if (num_scaler_users > 1) { 2289 u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16); 2290 u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16); 2291 int chroma_downscaling_factor = 2292 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; 2293 int latency; 2294 2295 latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k * 2296 chroma_downscaling_factor), 1000000); 2297 scaler_prefill_latency += latency; 2298 } 2299 2300 scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state); 2301 2302 return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency); 2303 } 2304 2305 static bool 2306 skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, 2307 int wm0_lines, int latency) 2308 { 2309 const struct drm_display_mode *adjusted_mode = 2310 &crtc_state->hw.adjusted_mode; 2311 2312 return crtc_state->framestart_delay + 2313 intel_usecs_to_scanlines(adjusted_mode, latency) + 2314 scaler_prefill_latency(crtc_state) + 2315 dsc_prefill_latency(crtc_state) + 2316 wm0_lines > 2317 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start; 2318 } 2319 2320 static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state) 2321 { 2322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2323 enum plane_id plane_id; 2324 int wm0_lines = 0; 2325 2326 for_each_plane_id_on_crtc(crtc, plane_id) { 2327 const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; 2328 2329 /* FIXME what about !skl_wm_has_lines() platforms? */ 2330 wm0_lines = max_t(int, wm0_lines, wm->wm[0].lines); 2331 } 2332 2333 return wm0_lines; 2334 } 2335 2336 static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state, 2337 int wm0_lines) 2338 { 2339 struct intel_display *display = to_intel_display(crtc_state); 2340 int level; 2341 2342 for (level = display->wm.num_levels - 1; level >= 0; level--) { 2343 int latency; 2344 2345 /* FIXME should we care about the latency w/a's? */ 2346 latency = skl_wm_latency(display, level, NULL); 2347 if (latency == 0) 2348 continue; 2349 2350 /* FIXME is it correct to use 0 latency for wm0 here? */ 2351 if (level == 0) 2352 latency = 0; 2353 2354 if (!skl_is_vblank_too_short(crtc_state, wm0_lines, latency)) 2355 return level; 2356 } 2357 2358 return -EINVAL; 2359 } 2360 2361 static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state) 2362 { 2363 struct intel_display *display = to_intel_display(crtc_state); 2364 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2365 int wm0_lines, level; 2366 2367 if (!crtc_state->hw.active) 2368 return 0; 2369 2370 wm0_lines = skl_max_wm0_lines(crtc_state); 2371 2372 level = skl_max_wm_level_for_vblank(crtc_state, wm0_lines); 2373 if (level < 0) 2374 return level; 2375 2376 /* 2377 * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_* 2378 * based on whether we're limited by the vblank duration. 2379 */ 2380 crtc_state->wm_level_disabled = level < display->wm.num_levels - 1; 2381 2382 for (level++; level < display->wm.num_levels; level++) { 2383 enum plane_id plane_id; 2384 2385 for_each_plane_id_on_crtc(crtc, plane_id) { 2386 struct skl_plane_wm *wm = 2387 &crtc_state->wm.skl.optimal.planes[plane_id]; 2388 2389 /* 2390 * FIXME just clear enable or flag the entire 2391 * thing as bad via min_ddb_alloc=U16_MAX? 2392 */ 2393 wm->wm[level].enable = false; 2394 wm->uv_wm[level].enable = false; 2395 } 2396 } 2397 2398 if (DISPLAY_VER(display) >= 12 && 2399 display->sagv.block_time_us && 2400 skl_is_vblank_too_short(crtc_state, wm0_lines, 2401 display->sagv.block_time_us)) { 2402 enum plane_id plane_id; 2403 2404 for_each_plane_id_on_crtc(crtc, plane_id) { 2405 struct skl_plane_wm *wm = 2406 &crtc_state->wm.skl.optimal.planes[plane_id]; 2407 2408 wm->sagv.wm0.enable = false; 2409 wm->sagv.trans_wm.enable = false; 2410 } 2411 } 2412 2413 return 0; 2414 } 2415 2416 static int skl_build_pipe_wm(struct intel_atomic_state *state, 2417 struct intel_crtc *crtc) 2418 { 2419 struct intel_display *display = to_intel_display(crtc); 2420 struct intel_crtc_state *crtc_state = 2421 intel_atomic_get_new_crtc_state(state, crtc); 2422 const struct intel_plane_state *plane_state; 2423 struct intel_plane *plane; 2424 int ret, i; 2425 2426 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 2427 /* 2428 * FIXME should perhaps check {old,new}_plane_crtc->hw.crtc 2429 * instead but we don't populate that correctly for NV12 Y 2430 * planes so for now hack this. 2431 */ 2432 if (plane->pipe != crtc->pipe) 2433 continue; 2434 2435 if (DISPLAY_VER(display) >= 11) 2436 ret = icl_build_plane_wm(crtc_state, plane_state); 2437 else 2438 ret = skl_build_plane_wm(crtc_state, plane_state); 2439 if (ret) 2440 return ret; 2441 } 2442 2443 crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw; 2444 2445 return skl_wm_check_vblank(crtc_state); 2446 } 2447 2448 static bool skl_wm_level_equals(const struct skl_wm_level *l1, 2449 const struct skl_wm_level *l2) 2450 { 2451 return l1->enable == l2->enable && 2452 l1->ignore_lines == l2->ignore_lines && 2453 l1->lines == l2->lines && 2454 l1->blocks == l2->blocks && 2455 l1->auto_min_alloc_wm_enable == l2->auto_min_alloc_wm_enable; 2456 } 2457 2458 static bool skl_plane_wm_equals(struct intel_display *display, 2459 const struct skl_plane_wm *wm1, 2460 const struct skl_plane_wm *wm2) 2461 { 2462 int level; 2463 2464 for (level = 0; level < display->wm.num_levels; level++) { 2465 /* 2466 * We don't check uv_wm as the hardware doesn't actually 2467 * use it. It only gets used for calculating the required 2468 * ddb allocation. 2469 */ 2470 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level])) 2471 return false; 2472 } 2473 2474 return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) && 2475 skl_wm_level_equals(&wm1->sagv.wm0, &wm2->sagv.wm0) && 2476 skl_wm_level_equals(&wm1->sagv.trans_wm, &wm2->sagv.trans_wm); 2477 } 2478 2479 static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, 2480 const struct skl_ddb_entry *b) 2481 { 2482 return a->start < b->end && b->start < a->end; 2483 } 2484 2485 static void skl_ddb_entry_union(struct skl_ddb_entry *a, 2486 const struct skl_ddb_entry *b) 2487 { 2488 if (a->end && b->end) { 2489 a->start = min(a->start, b->start); 2490 a->end = max(a->end, b->end); 2491 } else if (b->end) { 2492 a->start = b->start; 2493 a->end = b->end; 2494 } 2495 } 2496 2497 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, 2498 const struct skl_ddb_entry *entries, 2499 int num_entries, int ignore_idx) 2500 { 2501 int i; 2502 2503 for (i = 0; i < num_entries; i++) { 2504 if (i != ignore_idx && 2505 skl_ddb_entries_overlap(ddb, &entries[i])) 2506 return true; 2507 } 2508 2509 return false; 2510 } 2511 2512 static int 2513 skl_ddb_add_affected_planes(struct intel_atomic_state *state, 2514 struct intel_crtc *crtc) 2515 { 2516 struct intel_display *display = to_intel_display(state); 2517 const struct intel_crtc_state *old_crtc_state = 2518 intel_atomic_get_old_crtc_state(state, crtc); 2519 struct intel_crtc_state *new_crtc_state = 2520 intel_atomic_get_new_crtc_state(state, crtc); 2521 struct intel_plane *plane; 2522 2523 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 2524 struct intel_plane_state *plane_state; 2525 enum plane_id plane_id = plane->id; 2526 2527 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id], 2528 &new_crtc_state->wm.skl.plane_ddb[plane_id]) && 2529 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id], 2530 &new_crtc_state->wm.skl.plane_ddb_y[plane_id])) 2531 continue; 2532 2533 if (new_crtc_state->do_async_flip) { 2534 drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change DDB during async flip\n", 2535 plane->base.base.id, plane->base.name); 2536 return -EINVAL; 2537 } 2538 2539 plane_state = intel_atomic_get_plane_state(state, plane); 2540 if (IS_ERR(plane_state)) 2541 return PTR_ERR(plane_state); 2542 2543 new_crtc_state->update_planes |= BIT(plane_id); 2544 new_crtc_state->async_flip_planes = 0; 2545 new_crtc_state->do_async_flip = false; 2546 } 2547 2548 return 0; 2549 } 2550 2551 static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state) 2552 { 2553 struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev); 2554 u8 enabled_slices; 2555 enum pipe pipe; 2556 2557 /* 2558 * FIXME: For now we always enable slice S1 as per 2559 * the Bspec display initialization sequence. 2560 */ 2561 enabled_slices = BIT(DBUF_S1); 2562 2563 for_each_pipe(display, pipe) 2564 enabled_slices |= dbuf_state->slices[pipe]; 2565 2566 return enabled_slices; 2567 } 2568 2569 static int 2570 skl_compute_ddb(struct intel_atomic_state *state) 2571 { 2572 struct intel_display *display = to_intel_display(state); 2573 const struct intel_dbuf_state *old_dbuf_state; 2574 struct intel_dbuf_state *new_dbuf_state = NULL; 2575 struct intel_crtc_state *new_crtc_state; 2576 struct intel_crtc *crtc; 2577 int ret, i; 2578 2579 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2580 new_dbuf_state = intel_atomic_get_dbuf_state(state); 2581 if (IS_ERR(new_dbuf_state)) 2582 return PTR_ERR(new_dbuf_state); 2583 2584 old_dbuf_state = intel_atomic_get_old_dbuf_state(state); 2585 break; 2586 } 2587 2588 if (!new_dbuf_state) 2589 return 0; 2590 2591 new_dbuf_state->active_pipes = 2592 intel_calc_active_pipes(state, old_dbuf_state->active_pipes); 2593 2594 if (old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) { 2595 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 2596 if (ret) 2597 return ret; 2598 } 2599 2600 if (HAS_MBUS_JOINING(display)) { 2601 new_dbuf_state->joined_mbus = 2602 adlp_check_mbus_joined(new_dbuf_state->active_pipes); 2603 2604 if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) { 2605 ret = intel_cdclk_state_set_joined_mbus(state, new_dbuf_state->joined_mbus); 2606 if (ret) 2607 return ret; 2608 } 2609 } 2610 2611 for_each_intel_crtc(display->drm, crtc) { 2612 enum pipe pipe = crtc->pipe; 2613 2614 new_dbuf_state->slices[pipe] = 2615 skl_compute_dbuf_slices(crtc, new_dbuf_state->active_pipes, 2616 new_dbuf_state->joined_mbus); 2617 2618 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe]) 2619 continue; 2620 2621 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 2622 if (ret) 2623 return ret; 2624 } 2625 2626 new_dbuf_state->enabled_slices = intel_dbuf_enabled_slices(new_dbuf_state); 2627 2628 if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices || 2629 old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) { 2630 ret = intel_atomic_serialize_global_state(&new_dbuf_state->base); 2631 if (ret) 2632 return ret; 2633 2634 drm_dbg_kms(display->drm, 2635 "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n", 2636 old_dbuf_state->enabled_slices, 2637 new_dbuf_state->enabled_slices, 2638 DISPLAY_INFO(display)->dbuf.slice_mask, 2639 str_yes_no(old_dbuf_state->joined_mbus), 2640 str_yes_no(new_dbuf_state->joined_mbus)); 2641 } 2642 2643 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2644 enum pipe pipe = crtc->pipe; 2645 2646 new_dbuf_state->weight[pipe] = intel_crtc_ddb_weight(new_crtc_state); 2647 2648 if (old_dbuf_state->weight[pipe] == new_dbuf_state->weight[pipe]) 2649 continue; 2650 2651 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 2652 if (ret) 2653 return ret; 2654 } 2655 2656 for_each_intel_crtc(display->drm, crtc) { 2657 ret = skl_crtc_allocate_ddb(state, crtc); 2658 if (ret) 2659 return ret; 2660 } 2661 2662 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2663 ret = skl_crtc_allocate_plane_ddb(state, crtc); 2664 if (ret) 2665 return ret; 2666 2667 ret = skl_ddb_add_affected_planes(state, crtc); 2668 if (ret) 2669 return ret; 2670 } 2671 2672 return 0; 2673 } 2674 2675 static char enast(bool enable) 2676 { 2677 return enable ? '*' : ' '; 2678 } 2679 2680 static void 2681 skl_print_wm_changes(struct intel_atomic_state *state) 2682 { 2683 struct intel_display *display = to_intel_display(state); 2684 const struct intel_crtc_state *old_crtc_state; 2685 const struct intel_crtc_state *new_crtc_state; 2686 struct intel_plane *plane; 2687 struct intel_crtc *crtc; 2688 int i; 2689 2690 if (!drm_debug_enabled(DRM_UT_KMS)) 2691 return; 2692 2693 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 2694 new_crtc_state, i) { 2695 const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm; 2696 2697 old_pipe_wm = &old_crtc_state->wm.skl.optimal; 2698 new_pipe_wm = &new_crtc_state->wm.skl.optimal; 2699 2700 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 2701 enum plane_id plane_id = plane->id; 2702 const struct skl_ddb_entry *old, *new; 2703 2704 old = &old_crtc_state->wm.skl.plane_ddb[plane_id]; 2705 new = &new_crtc_state->wm.skl.plane_ddb[plane_id]; 2706 2707 if (skl_ddb_entry_equal(old, new)) 2708 continue; 2709 2710 drm_dbg_kms(display->drm, 2711 "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n", 2712 plane->base.base.id, plane->base.name, 2713 old->start, old->end, new->start, new->end, 2714 skl_ddb_entry_size(old), skl_ddb_entry_size(new)); 2715 } 2716 2717 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 2718 enum plane_id plane_id = plane->id; 2719 const struct skl_plane_wm *old_wm, *new_wm; 2720 2721 old_wm = &old_pipe_wm->planes[plane_id]; 2722 new_wm = &new_pipe_wm->planes[plane_id]; 2723 2724 if (skl_plane_wm_equals(display, old_wm, new_wm)) 2725 continue; 2726 2727 drm_dbg_kms(display->drm, 2728 "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm" 2729 " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n", 2730 plane->base.base.id, plane->base.name, 2731 enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable), 2732 enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable), 2733 enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable), 2734 enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable), 2735 enast(old_wm->trans_wm.enable), 2736 enast(old_wm->sagv.wm0.enable), 2737 enast(old_wm->sagv.trans_wm.enable), 2738 enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable), 2739 enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable), 2740 enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable), 2741 enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable), 2742 enast(new_wm->trans_wm.enable), 2743 enast(new_wm->sagv.wm0.enable), 2744 enast(new_wm->sagv.trans_wm.enable)); 2745 2746 drm_dbg_kms(display->drm, 2747 "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d" 2748 " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n", 2749 plane->base.base.id, plane->base.name, 2750 enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines, 2751 enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines, 2752 enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines, 2753 enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines, 2754 enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines, 2755 enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines, 2756 enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines, 2757 enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines, 2758 enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines, 2759 enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines, 2760 enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines, 2761 enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines, 2762 enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines, 2763 enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines, 2764 enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines, 2765 enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines, 2766 enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines, 2767 enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines, 2768 enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines, 2769 enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines, 2770 enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines, 2771 enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines); 2772 2773 drm_dbg_kms(display->drm, 2774 "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" 2775 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", 2776 plane->base.base.id, plane->base.name, 2777 old_wm->wm[0].blocks, old_wm->wm[1].blocks, 2778 old_wm->wm[2].blocks, old_wm->wm[3].blocks, 2779 old_wm->wm[4].blocks, old_wm->wm[5].blocks, 2780 old_wm->wm[6].blocks, old_wm->wm[7].blocks, 2781 old_wm->trans_wm.blocks, 2782 old_wm->sagv.wm0.blocks, 2783 old_wm->sagv.trans_wm.blocks, 2784 new_wm->wm[0].blocks, new_wm->wm[1].blocks, 2785 new_wm->wm[2].blocks, new_wm->wm[3].blocks, 2786 new_wm->wm[4].blocks, new_wm->wm[5].blocks, 2787 new_wm->wm[6].blocks, new_wm->wm[7].blocks, 2788 new_wm->trans_wm.blocks, 2789 new_wm->sagv.wm0.blocks, 2790 new_wm->sagv.trans_wm.blocks); 2791 2792 drm_dbg_kms(display->drm, 2793 "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" 2794 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", 2795 plane->base.base.id, plane->base.name, 2796 old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc, 2797 old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc, 2798 old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc, 2799 old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc, 2800 old_wm->trans_wm.min_ddb_alloc, 2801 old_wm->sagv.wm0.min_ddb_alloc, 2802 old_wm->sagv.trans_wm.min_ddb_alloc, 2803 new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc, 2804 new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc, 2805 new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc, 2806 new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc, 2807 new_wm->trans_wm.min_ddb_alloc, 2808 new_wm->sagv.wm0.min_ddb_alloc, 2809 new_wm->sagv.trans_wm.min_ddb_alloc); 2810 } 2811 } 2812 } 2813 2814 static bool skl_plane_selected_wm_equals(struct intel_plane *plane, 2815 const struct skl_pipe_wm *old_pipe_wm, 2816 const struct skl_pipe_wm *new_pipe_wm) 2817 { 2818 struct intel_display *display = to_intel_display(plane); 2819 int level; 2820 2821 for (level = 0; level < display->wm.num_levels; level++) { 2822 /* 2823 * We don't check uv_wm as the hardware doesn't actually 2824 * use it. It only gets used for calculating the required 2825 * ddb allocation. 2826 */ 2827 if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level), 2828 skl_plane_wm_level(new_pipe_wm, plane->id, level))) 2829 return false; 2830 } 2831 2832 if (HAS_HW_SAGV_WM(display)) { 2833 const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id]; 2834 const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id]; 2835 2836 if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) || 2837 !skl_wm_level_equals(&old_wm->sagv.trans_wm, &new_wm->sagv.trans_wm)) 2838 return false; 2839 } 2840 2841 return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id), 2842 skl_plane_trans_wm(new_pipe_wm, plane->id)); 2843 } 2844 2845 /* 2846 * To make sure the cursor watermark registers are always consistent 2847 * with our computed state the following scenario needs special 2848 * treatment: 2849 * 2850 * 1. enable cursor 2851 * 2. move cursor entirely offscreen 2852 * 3. disable cursor 2853 * 2854 * Step 2. does call .disable_plane() but does not zero the watermarks 2855 * (since we consider an offscreen cursor still active for the purposes 2856 * of watermarks). Step 3. would not normally call .disable_plane() 2857 * because the actual plane visibility isn't changing, and we don't 2858 * deallocate the cursor ddb until the pipe gets disabled. So we must 2859 * force step 3. to call .disable_plane() to update the watermark 2860 * registers properly. 2861 * 2862 * Other planes do not suffer from this issues as their watermarks are 2863 * calculated based on the actual plane visibility. The only time this 2864 * can trigger for the other planes is during the initial readout as the 2865 * default value of the watermarks registers is not zero. 2866 */ 2867 static int skl_wm_add_affected_planes(struct intel_atomic_state *state, 2868 struct intel_crtc *crtc) 2869 { 2870 struct intel_display *display = to_intel_display(state); 2871 const struct intel_crtc_state *old_crtc_state = 2872 intel_atomic_get_old_crtc_state(state, crtc); 2873 struct intel_crtc_state *new_crtc_state = 2874 intel_atomic_get_new_crtc_state(state, crtc); 2875 struct intel_plane *plane; 2876 2877 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 2878 struct intel_plane_state *plane_state; 2879 enum plane_id plane_id = plane->id; 2880 2881 /* 2882 * Force a full wm update for every plane on modeset. 2883 * Required because the reset value of the wm registers 2884 * is non-zero, whereas we want all disabled planes to 2885 * have zero watermarks. So if we turn off the relevant 2886 * power well the hardware state will go out of sync 2887 * with the software state. 2888 */ 2889 if (!intel_crtc_needs_modeset(new_crtc_state) && 2890 skl_plane_selected_wm_equals(plane, 2891 &old_crtc_state->wm.skl.optimal, 2892 &new_crtc_state->wm.skl.optimal)) 2893 continue; 2894 2895 if (new_crtc_state->do_async_flip) { 2896 drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change watermarks during async flip\n", 2897 plane->base.base.id, plane->base.name); 2898 return -EINVAL; 2899 } 2900 2901 plane_state = intel_atomic_get_plane_state(state, plane); 2902 if (IS_ERR(plane_state)) 2903 return PTR_ERR(plane_state); 2904 2905 new_crtc_state->update_planes |= BIT(plane_id); 2906 new_crtc_state->async_flip_planes = 0; 2907 new_crtc_state->do_async_flip = false; 2908 } 2909 2910 return 0; 2911 } 2912 2913 /* 2914 * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline: 2915 * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from 2916 * watermark level1 and up and above. If watermark level 1 is 2917 * invalid program it with all 1's. 2918 * Program PKG_C_LATENCY Added Wake Time = DSB execution time 2919 * If Variable Refresh Rate where Vmin != Vmax != Flipline: 2920 * Program DEEP PKG_C_LATENCY Pkg C with all 1's. 2921 * Program PKG_C_LATENCY Added Wake Time = 0 2922 */ 2923 void 2924 intel_program_dpkgc_latency(struct intel_atomic_state *state) 2925 { 2926 struct intel_display *display = to_intel_display(state); 2927 struct intel_crtc *crtc; 2928 struct intel_crtc_state *new_crtc_state; 2929 u32 latency = LNL_PKG_C_LATENCY_MASK; 2930 u32 added_wake_time = 0; 2931 u32 max_linetime = 0; 2932 u32 clear, val; 2933 bool fixed_refresh_rate = false; 2934 int i; 2935 2936 if (DISPLAY_VER(display) < 20) 2937 return; 2938 2939 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2940 if (!new_crtc_state->vrr.enable || 2941 (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax && 2942 new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline)) 2943 fixed_refresh_rate = true; 2944 2945 max_linetime = max(new_crtc_state->linetime, max_linetime); 2946 } 2947 2948 if (fixed_refresh_rate) { 2949 added_wake_time = DSB_EXE_TIME + 2950 display->sagv.block_time_us; 2951 2952 latency = skl_watermark_max_latency(display, 1); 2953 2954 /* Wa_22020432604 */ 2955 if ((DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30) && !latency) { 2956 latency += added_wake_time; 2957 added_wake_time = 0; 2958 } 2959 2960 /* Wa_22020299601 */ 2961 if ((latency && max_linetime) && 2962 (DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30)) { 2963 latency = max_linetime * DIV_ROUND_UP(latency, max_linetime); 2964 } else if (!latency) { 2965 latency = LNL_PKG_C_LATENCY_MASK; 2966 } 2967 } 2968 2969 clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; 2970 val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, latency) | 2971 REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time); 2972 2973 intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val); 2974 } 2975 2976 static int 2977 skl_compute_wm(struct intel_atomic_state *state) 2978 { 2979 struct intel_display *display = to_intel_display(state); 2980 struct intel_crtc *crtc; 2981 struct intel_crtc_state __maybe_unused *new_crtc_state; 2982 int ret, i; 2983 2984 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2985 ret = skl_build_pipe_wm(state, crtc); 2986 if (ret) 2987 return ret; 2988 } 2989 2990 ret = skl_compute_ddb(state); 2991 if (ret) 2992 return ret; 2993 2994 /* 2995 * skl_compute_ddb() will have adjusted the final watermarks 2996 * based on how much ddb is available. Now we can actually 2997 * check if the final watermarks changed. 2998 */ 2999 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 3000 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal; 3001 3002 /* 3003 * We store use_sagv_wm in the crtc state rather than relying on 3004 * that bw state since we have no convenient way to get at the 3005 * latter from the plane commit hooks (especially in the legacy 3006 * cursor case). 3007 * 3008 * drm_atomic_check_only() gets upset if we pull more crtcs 3009 * into the state, so we have to calculate this based on the 3010 * individual intel_crtc_can_enable_sagv() rather than 3011 * the overall intel_can_enable_sagv(). Otherwise the 3012 * crtcs not included in the commit would not switch to the 3013 * SAGV watermarks when we are about to enable SAGV, and that 3014 * would lead to underruns. This does mean extra power draw 3015 * when only a subset of the crtcs are blocking SAGV as the 3016 * other crtcs can't be allowed to use the more optimal 3017 * normal (ie. non-SAGV) watermarks. 3018 */ 3019 pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(display) && 3020 DISPLAY_VER(display) >= 12 && 3021 intel_crtc_can_enable_sagv(new_crtc_state); 3022 3023 ret = skl_wm_add_affected_planes(state, crtc); 3024 if (ret) 3025 return ret; 3026 } 3027 3028 skl_print_wm_changes(state); 3029 3030 return 0; 3031 } 3032 3033 static void skl_wm_level_from_reg_val(struct intel_display *display, 3034 u32 val, struct skl_wm_level *level) 3035 { 3036 level->enable = val & PLANE_WM_EN; 3037 level->ignore_lines = val & PLANE_WM_IGNORE_LINES; 3038 level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val); 3039 level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); 3040 level->auto_min_alloc_wm_enable = DISPLAY_VER(display) >= 30 ? 3041 val & PLANE_WM_AUTO_MIN_ALLOC_EN : 0; 3042 } 3043 3044 static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, 3045 struct skl_pipe_wm *out) 3046 { 3047 struct intel_display *display = to_intel_display(crtc); 3048 enum pipe pipe = crtc->pipe; 3049 enum plane_id plane_id; 3050 int level; 3051 u32 val; 3052 3053 for_each_plane_id_on_crtc(crtc, plane_id) { 3054 struct skl_plane_wm *wm = &out->planes[plane_id]; 3055 3056 for (level = 0; level < display->wm.num_levels; level++) { 3057 if (plane_id != PLANE_CURSOR) 3058 val = intel_de_read(display, PLANE_WM(pipe, plane_id, level)); 3059 else 3060 val = intel_de_read(display, CUR_WM(pipe, level)); 3061 3062 skl_wm_level_from_reg_val(display, val, &wm->wm[level]); 3063 } 3064 3065 if (plane_id != PLANE_CURSOR) 3066 val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id)); 3067 else 3068 val = intel_de_read(display, CUR_WM_TRANS(pipe)); 3069 3070 skl_wm_level_from_reg_val(display, val, &wm->trans_wm); 3071 3072 if (HAS_HW_SAGV_WM(display)) { 3073 if (plane_id != PLANE_CURSOR) 3074 val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id)); 3075 else 3076 val = intel_de_read(display, CUR_WM_SAGV(pipe)); 3077 3078 skl_wm_level_from_reg_val(display, val, &wm->sagv.wm0); 3079 3080 if (plane_id != PLANE_CURSOR) 3081 val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id)); 3082 else 3083 val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe)); 3084 3085 skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm); 3086 } else if (DISPLAY_VER(display) >= 12) { 3087 wm->sagv.wm0 = wm->wm[0]; 3088 wm->sagv.trans_wm = wm->trans_wm; 3089 } 3090 } 3091 } 3092 3093 static void skl_wm_get_hw_state(struct intel_display *display) 3094 { 3095 struct intel_dbuf_state *dbuf_state = 3096 to_intel_dbuf_state(display->dbuf.obj.state); 3097 struct intel_crtc *crtc; 3098 3099 if (HAS_MBUS_JOINING(display)) 3100 dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 3101 3102 dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw); 3103 dbuf_state->active_pipes = 0; 3104 3105 for_each_intel_crtc(display->drm, crtc) { 3106 struct intel_crtc_state *crtc_state = 3107 to_intel_crtc_state(crtc->base.state); 3108 enum pipe pipe = crtc->pipe; 3109 unsigned int mbus_offset; 3110 enum plane_id plane_id; 3111 u8 slices; 3112 3113 memset(&crtc_state->wm.skl.optimal, 0, 3114 sizeof(crtc_state->wm.skl.optimal)); 3115 if (crtc_state->hw.active) { 3116 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); 3117 dbuf_state->active_pipes |= BIT(pipe); 3118 } 3119 crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal; 3120 3121 memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe])); 3122 3123 for_each_plane_id_on_crtc(crtc, plane_id) { 3124 struct skl_ddb_entry *ddb = 3125 &crtc_state->wm.skl.plane_ddb[plane_id]; 3126 struct skl_ddb_entry *ddb_y = 3127 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 3128 u16 *min_ddb = 3129 &crtc_state->wm.skl.plane_min_ddb[plane_id]; 3130 u16 *interim_ddb = 3131 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; 3132 3133 if (!crtc_state->hw.active) 3134 continue; 3135 3136 skl_ddb_get_hw_plane_state(display, crtc->pipe, 3137 plane_id, ddb, ddb_y, 3138 min_ddb, interim_ddb); 3139 3140 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb); 3141 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y); 3142 } 3143 3144 dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state); 3145 3146 /* 3147 * Used for checking overlaps, so we need absolute 3148 * offsets instead of MBUS relative offsets. 3149 */ 3150 slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, 3151 dbuf_state->joined_mbus); 3152 mbus_offset = mbus_ddb_offset(display, slices); 3153 crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start; 3154 crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end; 3155 3156 /* The slices actually used by the planes on the pipe */ 3157 dbuf_state->slices[pipe] = 3158 skl_ddb_dbuf_slice_mask(display, &crtc_state->wm.skl.ddb); 3159 3160 drm_dbg_kms(display->drm, 3161 "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n", 3162 crtc->base.base.id, crtc->base.name, 3163 dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start, 3164 dbuf_state->ddb[pipe].end, dbuf_state->active_pipes, 3165 str_yes_no(dbuf_state->joined_mbus)); 3166 } 3167 3168 dbuf_state->enabled_slices = display->dbuf.enabled_slices; 3169 } 3170 3171 bool skl_watermark_ipc_enabled(struct intel_display *display) 3172 { 3173 return display->wm.ipc_enabled; 3174 } 3175 3176 void skl_watermark_ipc_update(struct intel_display *display) 3177 { 3178 if (!HAS_IPC(display)) 3179 return; 3180 3181 intel_de_rmw(display, DISP_ARB_CTL2, DISP_IPC_ENABLE, 3182 skl_watermark_ipc_enabled(display) ? DISP_IPC_ENABLE : 0); 3183 } 3184 3185 static bool skl_watermark_ipc_can_enable(struct intel_display *display) 3186 { 3187 struct drm_i915_private *i915 = to_i915(display->drm); 3188 3189 /* Display WA #0477 WaDisableIPC: skl */ 3190 if (display->platform.skylake) 3191 return false; 3192 3193 /* Display WA #1141: SKL:all KBL:all CFL */ 3194 if (display->platform.kabylake || 3195 display->platform.coffeelake || 3196 display->platform.cometlake) 3197 return i915->dram_info.symmetric_memory; 3198 3199 return true; 3200 } 3201 3202 void skl_watermark_ipc_init(struct intel_display *display) 3203 { 3204 if (!HAS_IPC(display)) 3205 return; 3206 3207 display->wm.ipc_enabled = skl_watermark_ipc_can_enable(display); 3208 3209 skl_watermark_ipc_update(display); 3210 } 3211 3212 static void 3213 adjust_wm_latency(struct intel_display *display, 3214 u16 wm[], int num_levels, int read_latency) 3215 { 3216 struct drm_i915_private *i915 = to_i915(display->drm); 3217 bool wm_lv_0_adjust_needed = i915->dram_info.wm_lv_0_adjust_needed; 3218 int i, level; 3219 3220 /* 3221 * If a level n (n > 1) has a 0us latency, all levels m (m >= n) 3222 * need to be disabled. We make sure to sanitize the values out 3223 * of the punit to satisfy this requirement. 3224 */ 3225 for (level = 1; level < num_levels; level++) { 3226 if (wm[level] == 0) { 3227 for (i = level + 1; i < num_levels; i++) 3228 wm[i] = 0; 3229 3230 num_levels = level; 3231 break; 3232 } 3233 } 3234 3235 /* 3236 * WaWmMemoryReadLatency 3237 * 3238 * punit doesn't take into account the read latency so we need 3239 * to add proper adjustment to each valid level we retrieve 3240 * from the punit when level 0 response data is 0us. 3241 */ 3242 if (wm[0] == 0) { 3243 for (level = 0; level < num_levels; level++) 3244 wm[level] += read_latency; 3245 } 3246 3247 /* 3248 * WA Level-0 adjustment for 16GB DIMMs: SKL+ 3249 * If we could not get dimm info enable this WA to prevent from 3250 * any underrun. If not able to get Dimm info assume 16GB dimm 3251 * to avoid any underrun. 3252 */ 3253 if (wm_lv_0_adjust_needed) 3254 wm[0] += 1; 3255 } 3256 3257 static void mtl_read_wm_latency(struct intel_display *display, u16 wm[]) 3258 { 3259 int num_levels = display->wm.num_levels; 3260 u32 val; 3261 3262 val = intel_de_read(display, MTL_LATENCY_LP0_LP1); 3263 wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); 3264 wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); 3265 3266 val = intel_de_read(display, MTL_LATENCY_LP2_LP3); 3267 wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); 3268 wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); 3269 3270 val = intel_de_read(display, MTL_LATENCY_LP4_LP5); 3271 wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); 3272 wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); 3273 3274 adjust_wm_latency(display, wm, num_levels, 6); 3275 } 3276 3277 static void skl_read_wm_latency(struct intel_display *display, u16 wm[]) 3278 { 3279 struct drm_i915_private *i915 = to_i915(display->drm); 3280 int num_levels = display->wm.num_levels; 3281 int read_latency = DISPLAY_VER(display) >= 12 ? 3 : 2; 3282 int mult = display->platform.dg2 ? 2 : 1; 3283 u32 val; 3284 int ret; 3285 3286 /* read the first set of memory latencies[0:3] */ 3287 val = 0; /* data0 to be programmed to 0 for first set */ 3288 ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL); 3289 if (ret) { 3290 drm_err(display->drm, "SKL Mailbox read error = %d\n", ret); 3291 return; 3292 } 3293 3294 wm[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; 3295 wm[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; 3296 wm[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; 3297 wm[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; 3298 3299 /* read the second set of memory latencies[4:7] */ 3300 val = 1; /* data0 to be programmed to 1 for second set */ 3301 ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL); 3302 if (ret) { 3303 drm_err(display->drm, "SKL Mailbox read error = %d\n", ret); 3304 return; 3305 } 3306 3307 wm[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; 3308 wm[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; 3309 wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; 3310 wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; 3311 3312 adjust_wm_latency(display, wm, num_levels, read_latency); 3313 } 3314 3315 static void skl_setup_wm_latency(struct intel_display *display) 3316 { 3317 if (HAS_HW_SAGV_WM(display)) 3318 display->wm.num_levels = 6; 3319 else 3320 display->wm.num_levels = 8; 3321 3322 if (DISPLAY_VER(display) >= 14) 3323 mtl_read_wm_latency(display, display->wm.skl_latency); 3324 else 3325 skl_read_wm_latency(display, display->wm.skl_latency); 3326 3327 intel_print_wm_latency(display, "Gen9 Plane", display->wm.skl_latency); 3328 } 3329 3330 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj) 3331 { 3332 struct intel_dbuf_state *dbuf_state; 3333 3334 dbuf_state = kmemdup(obj->state, sizeof(*dbuf_state), GFP_KERNEL); 3335 if (!dbuf_state) 3336 return NULL; 3337 3338 return &dbuf_state->base; 3339 } 3340 3341 static void intel_dbuf_destroy_state(struct intel_global_obj *obj, 3342 struct intel_global_state *state) 3343 { 3344 kfree(state); 3345 } 3346 3347 static const struct intel_global_state_funcs intel_dbuf_funcs = { 3348 .atomic_duplicate_state = intel_dbuf_duplicate_state, 3349 .atomic_destroy_state = intel_dbuf_destroy_state, 3350 }; 3351 3352 struct intel_dbuf_state * 3353 intel_atomic_get_dbuf_state(struct intel_atomic_state *state) 3354 { 3355 struct intel_display *display = to_intel_display(state); 3356 struct intel_global_state *dbuf_state; 3357 3358 dbuf_state = intel_atomic_get_global_obj_state(state, &display->dbuf.obj); 3359 if (IS_ERR(dbuf_state)) 3360 return ERR_CAST(dbuf_state); 3361 3362 return to_intel_dbuf_state(dbuf_state); 3363 } 3364 3365 int intel_dbuf_init(struct intel_display *display) 3366 { 3367 struct intel_dbuf_state *dbuf_state; 3368 3369 dbuf_state = kzalloc(sizeof(*dbuf_state), GFP_KERNEL); 3370 if (!dbuf_state) 3371 return -ENOMEM; 3372 3373 intel_atomic_global_obj_init(display, &display->dbuf.obj, 3374 &dbuf_state->base, &intel_dbuf_funcs); 3375 3376 return 0; 3377 } 3378 3379 static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes) 3380 { 3381 switch (pipe) { 3382 case PIPE_A: 3383 case PIPE_D: 3384 active_pipes &= BIT(PIPE_A) | BIT(PIPE_D); 3385 break; 3386 case PIPE_B: 3387 case PIPE_C: 3388 active_pipes &= BIT(PIPE_B) | BIT(PIPE_C); 3389 break; 3390 default: /* to suppress compiler warning */ 3391 MISSING_CASE(pipe); 3392 return false; 3393 } 3394 3395 return is_power_of_2(active_pipes); 3396 } 3397 3398 static u32 pipe_mbus_dbox_ctl(const struct intel_crtc *crtc, 3399 const struct intel_dbuf_state *dbuf_state) 3400 { 3401 struct intel_display *display = to_intel_display(crtc); 3402 u32 val = 0; 3403 3404 if (DISPLAY_VER(display) >= 14) 3405 val |= MBUS_DBOX_I_CREDIT(2); 3406 3407 if (DISPLAY_VER(display) >= 12) { 3408 val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16); 3409 val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1); 3410 val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN; 3411 } 3412 3413 if (DISPLAY_VER(display) >= 14) 3414 val |= dbuf_state->joined_mbus ? 3415 MBUS_DBOX_A_CREDIT(12) : MBUS_DBOX_A_CREDIT(8); 3416 else if (display->platform.alderlake_p) 3417 /* Wa_22010947358:adl-p */ 3418 val |= dbuf_state->joined_mbus ? 3419 MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); 3420 else 3421 val |= MBUS_DBOX_A_CREDIT(2); 3422 3423 if (DISPLAY_VER(display) >= 14) { 3424 val |= MBUS_DBOX_B_CREDIT(0xA); 3425 } else if (display->platform.alderlake_p) { 3426 val |= MBUS_DBOX_BW_CREDIT(2); 3427 val |= MBUS_DBOX_B_CREDIT(8); 3428 } else if (DISPLAY_VER(display) >= 12) { 3429 val |= MBUS_DBOX_BW_CREDIT(2); 3430 val |= MBUS_DBOX_B_CREDIT(12); 3431 } else { 3432 val |= MBUS_DBOX_BW_CREDIT(1); 3433 val |= MBUS_DBOX_B_CREDIT(8); 3434 } 3435 3436 if (DISPLAY_VERx100(display) == 1400) { 3437 if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, dbuf_state->active_pipes)) 3438 val |= MBUS_DBOX_BW_8CREDITS_MTL; 3439 else 3440 val |= MBUS_DBOX_BW_4CREDITS_MTL; 3441 } 3442 3443 return val; 3444 } 3445 3446 static void pipe_mbus_dbox_ctl_update(struct intel_display *display, 3447 const struct intel_dbuf_state *dbuf_state) 3448 { 3449 struct intel_crtc *crtc; 3450 3451 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, dbuf_state->active_pipes) 3452 intel_de_write(display, PIPE_MBUS_DBOX_CTL(crtc->pipe), 3453 pipe_mbus_dbox_ctl(crtc, dbuf_state)); 3454 } 3455 3456 static void intel_mbus_dbox_update(struct intel_atomic_state *state) 3457 { 3458 struct intel_display *display = to_intel_display(state); 3459 const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; 3460 3461 if (DISPLAY_VER(display) < 11) 3462 return; 3463 3464 new_dbuf_state = intel_atomic_get_new_dbuf_state(state); 3465 old_dbuf_state = intel_atomic_get_old_dbuf_state(state); 3466 if (!new_dbuf_state || 3467 (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus && 3468 new_dbuf_state->active_pipes == old_dbuf_state->active_pipes)) 3469 return; 3470 3471 pipe_mbus_dbox_ctl_update(display, new_dbuf_state); 3472 } 3473 3474 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, 3475 int ratio) 3476 { 3477 struct intel_dbuf_state *dbuf_state; 3478 3479 dbuf_state = intel_atomic_get_dbuf_state(state); 3480 if (IS_ERR(dbuf_state)) 3481 return PTR_ERR(dbuf_state); 3482 3483 dbuf_state->mdclk_cdclk_ratio = ratio; 3484 3485 return intel_atomic_lock_global_state(&dbuf_state->base); 3486 } 3487 3488 void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display, 3489 int ratio, bool joined_mbus) 3490 { 3491 enum dbuf_slice slice; 3492 3493 if (!HAS_MBUS_JOINING(display)) 3494 return; 3495 3496 if (DISPLAY_VER(display) >= 20) 3497 intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK, 3498 MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1)); 3499 3500 if (joined_mbus) 3501 ratio *= 2; 3502 3503 drm_dbg_kms(display->drm, "Updating dbuf ratio to %d (mbus joined: %s)\n", 3504 ratio, str_yes_no(joined_mbus)); 3505 3506 for_each_dbuf_slice(display, slice) 3507 intel_de_rmw(display, DBUF_CTL_S(slice), 3508 DBUF_MIN_TRACKER_STATE_SERVICE_MASK, 3509 DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1)); 3510 } 3511 3512 static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state) 3513 { 3514 struct intel_display *display = to_intel_display(state); 3515 const struct intel_dbuf_state *old_dbuf_state = 3516 intel_atomic_get_old_dbuf_state(state); 3517 const struct intel_dbuf_state *new_dbuf_state = 3518 intel_atomic_get_new_dbuf_state(state); 3519 int mdclk_cdclk_ratio; 3520 3521 if (intel_cdclk_is_decreasing_later(state)) { 3522 /* cdclk/mdclk will be changed later by intel_set_cdclk_post_plane_update() */ 3523 mdclk_cdclk_ratio = old_dbuf_state->mdclk_cdclk_ratio; 3524 } else { 3525 /* cdclk/mdclk already changed by intel_set_cdclk_pre_plane_update() */ 3526 mdclk_cdclk_ratio = new_dbuf_state->mdclk_cdclk_ratio; 3527 } 3528 3529 intel_dbuf_mdclk_cdclk_ratio_update(display, mdclk_cdclk_ratio, 3530 new_dbuf_state->joined_mbus); 3531 } 3532 3533 static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state, 3534 const struct intel_dbuf_state *dbuf_state) 3535 { 3536 struct intel_display *display = to_intel_display(state); 3537 enum pipe pipe = ffs(dbuf_state->active_pipes) - 1; 3538 const struct intel_crtc_state *new_crtc_state; 3539 struct intel_crtc *crtc; 3540 3541 drm_WARN_ON(display->drm, !dbuf_state->joined_mbus); 3542 drm_WARN_ON(display->drm, !is_power_of_2(dbuf_state->active_pipes)); 3543 3544 crtc = intel_crtc_for_pipe(display, pipe); 3545 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 3546 3547 if (new_crtc_state && !intel_crtc_needs_modeset(new_crtc_state)) 3548 return pipe; 3549 else 3550 return INVALID_PIPE; 3551 } 3552 3553 static void mbus_ctl_join_update(struct intel_display *display, 3554 const struct intel_dbuf_state *dbuf_state, 3555 enum pipe pipe) 3556 { 3557 u32 mbus_ctl; 3558 3559 if (dbuf_state->joined_mbus) 3560 mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN; 3561 else 3562 mbus_ctl = MBUS_HASHING_MODE_2x2; 3563 3564 if (pipe != INVALID_PIPE) 3565 mbus_ctl |= MBUS_JOIN_PIPE_SELECT(pipe); 3566 else 3567 mbus_ctl |= MBUS_JOIN_PIPE_SELECT_NONE; 3568 3569 intel_de_rmw(display, MBUS_CTL, 3570 MBUS_HASHING_MODE_MASK | MBUS_JOIN | 3571 MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl); 3572 } 3573 3574 static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state, 3575 enum pipe pipe) 3576 { 3577 struct intel_display *display = to_intel_display(state); 3578 const struct intel_dbuf_state *old_dbuf_state = 3579 intel_atomic_get_old_dbuf_state(state); 3580 const struct intel_dbuf_state *new_dbuf_state = 3581 intel_atomic_get_new_dbuf_state(state); 3582 3583 drm_dbg_kms(display->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n", 3584 str_yes_no(old_dbuf_state->joined_mbus), 3585 str_yes_no(new_dbuf_state->joined_mbus), 3586 pipe != INVALID_PIPE ? pipe_name(pipe) : '*'); 3587 3588 mbus_ctl_join_update(display, new_dbuf_state, pipe); 3589 } 3590 3591 void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state) 3592 { 3593 const struct intel_dbuf_state *new_dbuf_state = 3594 intel_atomic_get_new_dbuf_state(state); 3595 const struct intel_dbuf_state *old_dbuf_state = 3596 intel_atomic_get_old_dbuf_state(state); 3597 3598 if (!new_dbuf_state) 3599 return; 3600 3601 if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) { 3602 enum pipe pipe = intel_mbus_joined_pipe(state, new_dbuf_state); 3603 3604 WARN_ON(!new_dbuf_state->base.changed); 3605 3606 intel_dbuf_mbus_join_update(state, pipe); 3607 intel_mbus_dbox_update(state); 3608 intel_dbuf_mdclk_min_tracker_update(state); 3609 } 3610 } 3611 3612 void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state) 3613 { 3614 struct intel_display *display = to_intel_display(state); 3615 const struct intel_dbuf_state *new_dbuf_state = 3616 intel_atomic_get_new_dbuf_state(state); 3617 const struct intel_dbuf_state *old_dbuf_state = 3618 intel_atomic_get_old_dbuf_state(state); 3619 3620 if (!new_dbuf_state) 3621 return; 3622 3623 if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) { 3624 enum pipe pipe = intel_mbus_joined_pipe(state, old_dbuf_state); 3625 3626 WARN_ON(!new_dbuf_state->base.changed); 3627 3628 intel_dbuf_mdclk_min_tracker_update(state); 3629 intel_mbus_dbox_update(state); 3630 intel_dbuf_mbus_join_update(state, pipe); 3631 3632 if (pipe != INVALID_PIPE) { 3633 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 3634 3635 intel_crtc_wait_for_next_vblank(crtc); 3636 } 3637 } else if (old_dbuf_state->joined_mbus == new_dbuf_state->joined_mbus && 3638 old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) { 3639 WARN_ON(!new_dbuf_state->base.changed); 3640 3641 intel_dbuf_mdclk_min_tracker_update(state); 3642 intel_mbus_dbox_update(state); 3643 } 3644 3645 } 3646 3647 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) 3648 { 3649 struct intel_display *display = to_intel_display(state); 3650 const struct intel_dbuf_state *new_dbuf_state = 3651 intel_atomic_get_new_dbuf_state(state); 3652 const struct intel_dbuf_state *old_dbuf_state = 3653 intel_atomic_get_old_dbuf_state(state); 3654 u8 old_slices, new_slices; 3655 3656 if (!new_dbuf_state) 3657 return; 3658 3659 old_slices = old_dbuf_state->enabled_slices; 3660 new_slices = old_dbuf_state->enabled_slices | new_dbuf_state->enabled_slices; 3661 3662 if (old_slices == new_slices) 3663 return; 3664 3665 WARN_ON(!new_dbuf_state->base.changed); 3666 3667 gen9_dbuf_slices_update(display, new_slices); 3668 } 3669 3670 void intel_dbuf_post_plane_update(struct intel_atomic_state *state) 3671 { 3672 struct intel_display *display = to_intel_display(state); 3673 const struct intel_dbuf_state *new_dbuf_state = 3674 intel_atomic_get_new_dbuf_state(state); 3675 const struct intel_dbuf_state *old_dbuf_state = 3676 intel_atomic_get_old_dbuf_state(state); 3677 u8 old_slices, new_slices; 3678 3679 if (!new_dbuf_state) 3680 return; 3681 3682 old_slices = old_dbuf_state->enabled_slices | new_dbuf_state->enabled_slices; 3683 new_slices = new_dbuf_state->enabled_slices; 3684 3685 if (old_slices == new_slices) 3686 return; 3687 3688 WARN_ON(!new_dbuf_state->base.changed); 3689 3690 gen9_dbuf_slices_update(display, new_slices); 3691 } 3692 3693 static void skl_mbus_sanitize(struct intel_display *display) 3694 { 3695 struct intel_dbuf_state *dbuf_state = 3696 to_intel_dbuf_state(display->dbuf.obj.state); 3697 3698 if (!HAS_MBUS_JOINING(display)) 3699 return; 3700 3701 if (!dbuf_state->joined_mbus || 3702 adlp_check_mbus_joined(dbuf_state->active_pipes)) 3703 return; 3704 3705 drm_dbg_kms(display->drm, "Disabling redundant MBUS joining (active pipes 0x%x)\n", 3706 dbuf_state->active_pipes); 3707 3708 dbuf_state->joined_mbus = false; 3709 intel_dbuf_mdclk_cdclk_ratio_update(display, 3710 dbuf_state->mdclk_cdclk_ratio, 3711 dbuf_state->joined_mbus); 3712 pipe_mbus_dbox_ctl_update(display, dbuf_state); 3713 mbus_ctl_join_update(display, dbuf_state, INVALID_PIPE); 3714 } 3715 3716 static bool skl_dbuf_is_misconfigured(struct intel_display *display) 3717 { 3718 const struct intel_dbuf_state *dbuf_state = 3719 to_intel_dbuf_state(display->dbuf.obj.state); 3720 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 3721 struct intel_crtc *crtc; 3722 3723 for_each_intel_crtc(display->drm, crtc) { 3724 const struct intel_crtc_state *crtc_state = 3725 to_intel_crtc_state(crtc->base.state); 3726 3727 entries[crtc->pipe] = crtc_state->wm.skl.ddb; 3728 } 3729 3730 for_each_intel_crtc(display->drm, crtc) { 3731 const struct intel_crtc_state *crtc_state = 3732 to_intel_crtc_state(crtc->base.state); 3733 u8 slices; 3734 3735 slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, 3736 dbuf_state->joined_mbus); 3737 if (dbuf_state->slices[crtc->pipe] & ~slices) 3738 return true; 3739 3740 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries, 3741 I915_MAX_PIPES, crtc->pipe)) 3742 return true; 3743 } 3744 3745 return false; 3746 } 3747 3748 static void skl_dbuf_sanitize(struct intel_display *display) 3749 { 3750 struct intel_crtc *crtc; 3751 3752 /* 3753 * On TGL/RKL (at least) the BIOS likes to assign the planes 3754 * to the wrong DBUF slices. This will cause an infinite loop 3755 * in skl_commit_modeset_enables() as it can't find a way to 3756 * transition between the old bogus DBUF layout to the new 3757 * proper DBUF layout without DBUF allocation overlaps between 3758 * the planes (which cannot be allowed or else the hardware 3759 * may hang). If we detect a bogus DBUF layout just turn off 3760 * all the planes so that skl_commit_modeset_enables() can 3761 * simply ignore them. 3762 */ 3763 if (!skl_dbuf_is_misconfigured(display)) 3764 return; 3765 3766 drm_dbg_kms(display->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n"); 3767 3768 for_each_intel_crtc(display->drm, crtc) { 3769 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3770 const struct intel_plane_state *plane_state = 3771 to_intel_plane_state(plane->base.state); 3772 struct intel_crtc_state *crtc_state = 3773 to_intel_crtc_state(crtc->base.state); 3774 3775 if (plane_state->uapi.visible) 3776 intel_plane_disable_noatomic(crtc, plane); 3777 3778 drm_WARN_ON(display->drm, crtc_state->active_planes != 0); 3779 3780 memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); 3781 } 3782 } 3783 3784 static void skl_wm_sanitize(struct intel_display *display) 3785 { 3786 skl_mbus_sanitize(display); 3787 skl_dbuf_sanitize(display); 3788 } 3789 3790 void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc) 3791 { 3792 struct intel_display *display = to_intel_display(crtc); 3793 struct intel_crtc_state *crtc_state = 3794 to_intel_crtc_state(crtc->base.state); 3795 struct intel_dbuf_state *dbuf_state = 3796 to_intel_dbuf_state(display->dbuf.obj.state); 3797 enum pipe pipe = crtc->pipe; 3798 3799 if (DISPLAY_VER(display) < 9) 3800 return; 3801 3802 dbuf_state->active_pipes &= ~BIT(pipe); 3803 3804 dbuf_state->weight[pipe] = 0; 3805 dbuf_state->slices[pipe] = 0; 3806 3807 memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe])); 3808 3809 memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); 3810 } 3811 3812 void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc, 3813 struct intel_plane *plane) 3814 { 3815 struct intel_display *display = to_intel_display(crtc); 3816 struct intel_crtc_state *crtc_state = 3817 to_intel_crtc_state(crtc->base.state); 3818 3819 if (DISPLAY_VER(display) < 9) 3820 return; 3821 3822 skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0); 3823 skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0); 3824 3825 crtc_state->wm.skl.plane_min_ddb[plane->id] = 0; 3826 crtc_state->wm.skl.plane_interim_ddb[plane->id] = 0; 3827 3828 memset(&crtc_state->wm.skl.raw.planes[plane->id], 0, 3829 sizeof(crtc_state->wm.skl.raw.planes[plane->id])); 3830 memset(&crtc_state->wm.skl.optimal.planes[plane->id], 0, 3831 sizeof(crtc_state->wm.skl.optimal.planes[plane->id])); 3832 } 3833 3834 void intel_wm_state_verify(struct intel_atomic_state *state, 3835 struct intel_crtc *crtc) 3836 { 3837 struct intel_display *display = to_intel_display(state); 3838 const struct intel_crtc_state *new_crtc_state = 3839 intel_atomic_get_new_crtc_state(state, crtc); 3840 struct skl_hw_state { 3841 struct skl_ddb_entry ddb[I915_MAX_PLANES]; 3842 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 3843 u16 min_ddb[I915_MAX_PLANES]; 3844 u16 interim_ddb[I915_MAX_PLANES]; 3845 struct skl_pipe_wm wm; 3846 } *hw; 3847 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 3848 struct intel_plane *plane; 3849 u8 hw_enabled_slices; 3850 int level; 3851 3852 if (DISPLAY_VER(display) < 9 || !new_crtc_state->hw.active) 3853 return; 3854 3855 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 3856 if (!hw) 3857 return; 3858 3859 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 3860 3861 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y, hw->min_ddb, hw->interim_ddb); 3862 3863 hw_enabled_slices = intel_enabled_dbuf_slices_mask(display); 3864 3865 if (DISPLAY_VER(display) >= 11 && 3866 hw_enabled_slices != display->dbuf.enabled_slices) 3867 drm_err(display->drm, 3868 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 3869 display->dbuf.enabled_slices, 3870 hw_enabled_slices); 3871 3872 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 3873 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 3874 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 3875 3876 /* Watermarks */ 3877 for (level = 0; level < display->wm.num_levels; level++) { 3878 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 3879 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 3880 3881 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 3882 continue; 3883 3884 drm_err(display->drm, 3885 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3886 plane->base.base.id, plane->base.name, level, 3887 sw_wm_level->enable, 3888 sw_wm_level->blocks, 3889 sw_wm_level->lines, 3890 hw_wm_level->enable, 3891 hw_wm_level->blocks, 3892 hw_wm_level->lines); 3893 } 3894 3895 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 3896 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 3897 3898 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3899 drm_err(display->drm, 3900 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3901 plane->base.base.id, plane->base.name, 3902 sw_wm_level->enable, 3903 sw_wm_level->blocks, 3904 sw_wm_level->lines, 3905 hw_wm_level->enable, 3906 hw_wm_level->blocks, 3907 hw_wm_level->lines); 3908 } 3909 3910 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 3911 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 3912 3913 if (HAS_HW_SAGV_WM(display) && 3914 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3915 drm_err(display->drm, 3916 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3917 plane->base.base.id, plane->base.name, 3918 sw_wm_level->enable, 3919 sw_wm_level->blocks, 3920 sw_wm_level->lines, 3921 hw_wm_level->enable, 3922 hw_wm_level->blocks, 3923 hw_wm_level->lines); 3924 } 3925 3926 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 3927 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 3928 3929 if (HAS_HW_SAGV_WM(display) && 3930 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3931 drm_err(display->drm, 3932 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3933 plane->base.base.id, plane->base.name, 3934 sw_wm_level->enable, 3935 sw_wm_level->blocks, 3936 sw_wm_level->lines, 3937 hw_wm_level->enable, 3938 hw_wm_level->blocks, 3939 hw_wm_level->lines); 3940 } 3941 3942 /* DDB */ 3943 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 3944 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 3945 3946 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 3947 drm_err(display->drm, 3948 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 3949 plane->base.base.id, plane->base.name, 3950 sw_ddb_entry->start, sw_ddb_entry->end, 3951 hw_ddb_entry->start, hw_ddb_entry->end); 3952 } 3953 } 3954 3955 kfree(hw); 3956 } 3957 3958 static const struct intel_wm_funcs skl_wm_funcs = { 3959 .compute_global_watermarks = skl_compute_wm, 3960 .get_hw_state = skl_wm_get_hw_state, 3961 .sanitize = skl_wm_sanitize, 3962 }; 3963 3964 void skl_wm_init(struct intel_display *display) 3965 { 3966 intel_sagv_init(display); 3967 3968 skl_setup_wm_latency(display); 3969 3970 display->funcs.wm = &skl_wm_funcs; 3971 } 3972 3973 static int skl_watermark_ipc_status_show(struct seq_file *m, void *data) 3974 { 3975 struct intel_display *display = m->private; 3976 3977 seq_printf(m, "Isochronous Priority Control: %s\n", 3978 str_yes_no(skl_watermark_ipc_enabled(display))); 3979 return 0; 3980 } 3981 3982 static int skl_watermark_ipc_status_open(struct inode *inode, struct file *file) 3983 { 3984 struct intel_display *display = inode->i_private; 3985 3986 return single_open(file, skl_watermark_ipc_status_show, display); 3987 } 3988 3989 static ssize_t skl_watermark_ipc_status_write(struct file *file, 3990 const char __user *ubuf, 3991 size_t len, loff_t *offp) 3992 { 3993 struct seq_file *m = file->private_data; 3994 struct intel_display *display = m->private; 3995 bool enable; 3996 int ret; 3997 3998 ret = kstrtobool_from_user(ubuf, len, &enable); 3999 if (ret < 0) 4000 return ret; 4001 4002 with_intel_display_rpm(display) { 4003 if (!skl_watermark_ipc_enabled(display) && enable) 4004 drm_info(display->drm, 4005 "Enabling IPC: WM will be proper only after next commit\n"); 4006 display->wm.ipc_enabled = enable; 4007 skl_watermark_ipc_update(display); 4008 } 4009 4010 return len; 4011 } 4012 4013 static const struct file_operations skl_watermark_ipc_status_fops = { 4014 .owner = THIS_MODULE, 4015 .open = skl_watermark_ipc_status_open, 4016 .read = seq_read, 4017 .llseek = seq_lseek, 4018 .release = single_release, 4019 .write = skl_watermark_ipc_status_write 4020 }; 4021 4022 static int intel_sagv_status_show(struct seq_file *m, void *unused) 4023 { 4024 struct intel_display *display = m->private; 4025 static const char * const sagv_status[] = { 4026 [I915_SAGV_UNKNOWN] = "unknown", 4027 [I915_SAGV_DISABLED] = "disabled", 4028 [I915_SAGV_ENABLED] = "enabled", 4029 [I915_SAGV_NOT_CONTROLLED] = "not controlled", 4030 }; 4031 4032 seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(display))); 4033 seq_printf(m, "SAGV modparam: %s\n", 4034 str_enabled_disabled(display->params.enable_sagv)); 4035 seq_printf(m, "SAGV status: %s\n", sagv_status[display->sagv.status]); 4036 seq_printf(m, "SAGV block time: %d usec\n", display->sagv.block_time_us); 4037 4038 return 0; 4039 } 4040 4041 DEFINE_SHOW_ATTRIBUTE(intel_sagv_status); 4042 4043 void skl_watermark_debugfs_register(struct intel_display *display) 4044 { 4045 struct drm_minor *minor = display->drm->primary; 4046 4047 if (HAS_IPC(display)) 4048 debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, 4049 display, &skl_watermark_ipc_status_fops); 4050 4051 if (HAS_SAGV(display)) 4052 debugfs_create_file("i915_sagv_status", 0444, minor->debugfs_root, 4053 display, &intel_sagv_status_fops); 4054 } 4055 4056 unsigned int skl_watermark_max_latency(struct intel_display *display, int initial_wm_level) 4057 { 4058 int level; 4059 4060 for (level = display->wm.num_levels - 1; level >= initial_wm_level; level--) { 4061 unsigned int latency = skl_wm_latency(display, level, NULL); 4062 4063 if (latency) 4064 return latency; 4065 } 4066 4067 return 0; 4068 } 4069