1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <linux/debugfs.h> 7 8 #include <drm/drm_blend.h> 9 #include <drm/drm_file.h> 10 #include <drm/drm_print.h> 11 12 #include "soc/intel_dram.h" 13 #include "i915_reg.h" 14 #include "i915_utils.h" 15 #include "i9xx_wm.h" 16 #include "intel_atomic.h" 17 #include "intel_bw.h" 18 #include "intel_cdclk.h" 19 #include "intel_crtc.h" 20 #include "intel_cursor_regs.h" 21 #include "intel_de.h" 22 #include "intel_display.h" 23 #include "intel_display_power.h" 24 #include "intel_display_regs.h" 25 #include "intel_display_rpm.h" 26 #include "intel_display_types.h" 27 #include "intel_fb.h" 28 #include "intel_fixed.h" 29 #include "intel_flipq.h" 30 #include "intel_pcode.h" 31 #include "intel_plane.h" 32 #include "intel_wm.h" 33 #include "skl_universal_plane_regs.h" 34 #include "skl_watermark.h" 35 #include "skl_watermark_regs.h" 36 37 struct intel_dbuf_state { 38 struct intel_global_state base; 39 40 struct skl_ddb_entry ddb[I915_MAX_PIPES]; 41 unsigned int weight[I915_MAX_PIPES]; 42 u8 slices[I915_MAX_PIPES]; 43 u8 enabled_slices; 44 u8 active_pipes; 45 u8 mdclk_cdclk_ratio; 46 bool joined_mbus; 47 }; 48 49 #define to_intel_dbuf_state(global_state) \ 50 container_of_const((global_state), struct intel_dbuf_state, base) 51 52 #define intel_atomic_get_old_dbuf_state(state) \ 53 to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->dbuf.obj)) 54 #define intel_atomic_get_new_dbuf_state(state) \ 55 to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->dbuf.obj)) 56 57 static void skl_sagv_disable(struct intel_display *display); 58 59 /* Stores plane specific WM parameters */ 60 struct skl_wm_params { 61 bool x_tiled, y_tiled; 62 bool rc_surface; 63 bool is_planar; 64 u32 width; 65 u8 cpp; 66 u32 plane_pixel_rate; 67 u32 y_min_scanlines; 68 u32 plane_bytes_per_line; 69 uint_fixed_16_16_t plane_blocks_per_line; 70 uint_fixed_16_16_t y_tile_minimum; 71 u32 linetime_us; 72 u32 dbuf_block_size; 73 }; 74 75 u8 intel_enabled_dbuf_slices_mask(struct intel_display *display) 76 { 77 u8 enabled_slices = 0; 78 enum dbuf_slice slice; 79 80 for_each_dbuf_slice(display, slice) { 81 if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE) 82 enabled_slices |= BIT(slice); 83 } 84 85 return enabled_slices; 86 } 87 88 /* 89 * FIXME: We still don't have the proper code detect if we need to apply the WA, 90 * so assume we'll always need it in order to avoid underruns. 91 */ 92 static bool skl_needs_memory_bw_wa(struct intel_display *display) 93 { 94 return DISPLAY_VER(display) == 9; 95 } 96 97 bool 98 intel_has_sagv(struct intel_display *display) 99 { 100 return HAS_SAGV(display) && display->sagv.status != I915_SAGV_NOT_CONTROLLED; 101 } 102 103 static u32 104 intel_sagv_block_time(struct intel_display *display) 105 { 106 if (DISPLAY_VER(display) >= 14) { 107 u32 val; 108 109 val = intel_de_read(display, MTL_LATENCY_SAGV); 110 111 return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); 112 } else if (DISPLAY_VER(display) >= 12) { 113 u32 val = 0; 114 int ret; 115 116 ret = intel_pcode_read(display->drm, 117 GEN12_PCODE_READ_SAGV_BLOCK_TIME_US, 118 &val, NULL); 119 if (ret) { 120 drm_dbg_kms(display->drm, "Couldn't read SAGV block time!\n"); 121 return 0; 122 } 123 124 return val; 125 } else if (DISPLAY_VER(display) == 11) { 126 return 10; 127 } else if (HAS_SAGV(display)) { 128 return 30; 129 } else { 130 return 0; 131 } 132 } 133 134 static void intel_sagv_init(struct intel_display *display) 135 { 136 if (!HAS_SAGV(display)) 137 display->sagv.status = I915_SAGV_NOT_CONTROLLED; 138 139 /* 140 * Probe to see if we have working SAGV control. 141 * For icl+ this was already determined by intel_bw_init_hw(). 142 */ 143 if (DISPLAY_VER(display) < 11) 144 skl_sagv_disable(display); 145 146 drm_WARN_ON(display->drm, display->sagv.status == I915_SAGV_UNKNOWN); 147 148 display->sagv.block_time_us = intel_sagv_block_time(display); 149 150 drm_dbg_kms(display->drm, "SAGV supported: %s, original SAGV block time: %u us\n", 151 str_yes_no(intel_has_sagv(display)), display->sagv.block_time_us); 152 153 /* avoid overflow when adding with wm0 latency/etc. */ 154 if (drm_WARN(display->drm, display->sagv.block_time_us > U16_MAX, 155 "Excessive SAGV block time %u, ignoring\n", 156 display->sagv.block_time_us)) 157 display->sagv.block_time_us = 0; 158 159 if (!intel_has_sagv(display)) 160 display->sagv.block_time_us = 0; 161 } 162 163 /* 164 * SAGV dynamically adjusts the system agent voltage and clock frequencies 165 * depending on power and performance requirements. The display engine access 166 * to system memory is blocked during the adjustment time. Because of the 167 * blocking time, having this enabled can cause full system hangs and/or pipe 168 * underruns if we don't meet all of the following requirements: 169 * 170 * - <= 1 pipe enabled 171 * - All planes can enable watermarks for latencies >= SAGV engine block time 172 * - We're not using an interlaced display configuration 173 */ 174 static void skl_sagv_enable(struct intel_display *display) 175 { 176 int ret; 177 178 if (!intel_has_sagv(display)) 179 return; 180 181 if (display->sagv.status == I915_SAGV_ENABLED) 182 return; 183 184 drm_dbg_kms(display->drm, "Enabling SAGV\n"); 185 ret = intel_pcode_write(display->drm, GEN9_PCODE_SAGV_CONTROL, 186 GEN9_SAGV_ENABLE); 187 188 /* We don't need to wait for SAGV when enabling */ 189 190 /* 191 * Some skl systems, pre-release machines in particular, 192 * don't actually have SAGV. 193 */ 194 if (display->platform.skylake && ret == -ENXIO) { 195 drm_dbg(display->drm, "No SAGV found on system, ignoring\n"); 196 display->sagv.status = I915_SAGV_NOT_CONTROLLED; 197 return; 198 } else if (ret < 0) { 199 drm_err(display->drm, "Failed to enable SAGV\n"); 200 return; 201 } 202 203 display->sagv.status = I915_SAGV_ENABLED; 204 } 205 206 static void skl_sagv_disable(struct intel_display *display) 207 { 208 int ret; 209 210 if (!intel_has_sagv(display)) 211 return; 212 213 if (display->sagv.status == I915_SAGV_DISABLED) 214 return; 215 216 drm_dbg_kms(display->drm, "Disabling SAGV\n"); 217 /* bspec says to keep retrying for at least 1 ms */ 218 ret = intel_pcode_request(display->drm, GEN9_PCODE_SAGV_CONTROL, 219 GEN9_SAGV_DISABLE, 220 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 1); 221 /* 222 * Some skl systems, pre-release machines in particular, 223 * don't actually have SAGV. 224 */ 225 if (display->platform.skylake && ret == -ENXIO) { 226 drm_dbg(display->drm, "No SAGV found on system, ignoring\n"); 227 display->sagv.status = I915_SAGV_NOT_CONTROLLED; 228 return; 229 } else if (ret < 0) { 230 drm_err(display->drm, "Failed to disable SAGV (%d)\n", ret); 231 return; 232 } 233 234 display->sagv.status = I915_SAGV_DISABLED; 235 } 236 237 static void skl_sagv_pre_plane_update(struct intel_atomic_state *state) 238 { 239 struct intel_display *display = to_intel_display(state); 240 const struct intel_bw_state *new_bw_state = 241 intel_atomic_get_new_bw_state(state); 242 243 if (!new_bw_state) 244 return; 245 246 if (!intel_bw_can_enable_sagv(display, new_bw_state)) 247 skl_sagv_disable(display); 248 } 249 250 static void skl_sagv_post_plane_update(struct intel_atomic_state *state) 251 { 252 struct intel_display *display = to_intel_display(state); 253 const struct intel_bw_state *new_bw_state = 254 intel_atomic_get_new_bw_state(state); 255 256 if (!new_bw_state) 257 return; 258 259 if (intel_bw_can_enable_sagv(display, new_bw_state)) 260 skl_sagv_enable(display); 261 } 262 263 void intel_sagv_pre_plane_update(struct intel_atomic_state *state) 264 { 265 struct intel_display *display = to_intel_display(state); 266 267 /* 268 * Just return if we can't control SAGV or don't have it. 269 * This is different from situation when we have SAGV but just can't 270 * afford it due to DBuf limitation - in case if SAGV is completely 271 * disabled in a BIOS, we are not even allowed to send a PCode request, 272 * as it will throw an error. So have to check it here. 273 */ 274 if (!intel_has_sagv(display)) 275 return; 276 277 if (DISPLAY_VER(display) >= 11) 278 icl_sagv_pre_plane_update(state); 279 else 280 skl_sagv_pre_plane_update(state); 281 } 282 283 void intel_sagv_post_plane_update(struct intel_atomic_state *state) 284 { 285 struct intel_display *display = to_intel_display(state); 286 287 /* 288 * Just return if we can't control SAGV or don't have it. 289 * This is different from situation when we have SAGV but just can't 290 * afford it due to DBuf limitation - in case if SAGV is completely 291 * disabled in a BIOS, we are not even allowed to send a PCode request, 292 * as it will throw an error. So have to check it here. 293 */ 294 if (!intel_has_sagv(display)) 295 return; 296 297 if (DISPLAY_VER(display) >= 11) 298 icl_sagv_post_plane_update(state); 299 else 300 skl_sagv_post_plane_update(state); 301 } 302 303 static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) 304 { 305 struct intel_display *display = to_intel_display(crtc_state); 306 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 307 enum plane_id plane_id; 308 int max_level = INT_MAX; 309 310 if (!intel_has_sagv(display)) 311 return false; 312 313 if (!crtc_state->hw.active) 314 return true; 315 316 if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE) 317 return false; 318 319 for_each_plane_id_on_crtc(crtc, plane_id) { 320 const struct skl_plane_wm *wm = 321 &crtc_state->wm.skl.optimal.planes[plane_id]; 322 int level; 323 324 /* Skip this plane if it's not enabled */ 325 if (!wm->wm[0].enable) 326 continue; 327 328 /* Find the highest enabled wm level for this plane */ 329 for (level = display->wm.num_levels - 1; 330 !wm->wm[level].enable; --level) 331 { } 332 333 /* Highest common enabled wm level for all planes */ 334 max_level = min(level, max_level); 335 } 336 337 /* No enabled planes? */ 338 if (max_level == INT_MAX) 339 return true; 340 341 for_each_plane_id_on_crtc(crtc, plane_id) { 342 const struct skl_plane_wm *wm = 343 &crtc_state->wm.skl.optimal.planes[plane_id]; 344 345 /* 346 * All enabled planes must have enabled a common wm level that 347 * can tolerate memory latencies higher than sagv_block_time_us 348 */ 349 if (wm->wm[0].enable && !wm->wm[max_level].can_sagv) 350 return false; 351 } 352 353 return true; 354 } 355 356 static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) 357 { 358 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 359 enum plane_id plane_id; 360 361 if (!crtc_state->hw.active) 362 return true; 363 364 for_each_plane_id_on_crtc(crtc, plane_id) { 365 const struct skl_plane_wm *wm = 366 &crtc_state->wm.skl.optimal.planes[plane_id]; 367 368 if (wm->wm[0].enable && !wm->sagv.wm0.enable) 369 return false; 370 } 371 372 return true; 373 } 374 375 bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) 376 { 377 struct intel_display *display = to_intel_display(crtc_state); 378 379 if (!display->params.enable_sagv) 380 return false; 381 382 /* 383 * SAGV is initially forced off because its current 384 * state can't be queried from pcode. Allow SAGV to 385 * be enabled upon the first real commit. 386 */ 387 if (crtc_state->inherited) 388 return false; 389 390 if (DISPLAY_VER(display) >= 12) 391 return tgl_crtc_can_enable_sagv(crtc_state); 392 else 393 return skl_crtc_can_enable_sagv(crtc_state); 394 } 395 396 static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry, 397 u16 start, u16 end) 398 { 399 entry->start = start; 400 entry->end = end; 401 402 return end; 403 } 404 405 static int intel_dbuf_slice_size(struct intel_display *display) 406 { 407 return DISPLAY_INFO(display)->dbuf.size / 408 hweight8(DISPLAY_INFO(display)->dbuf.slice_mask); 409 } 410 411 static void 412 skl_ddb_entry_for_slices(struct intel_display *display, u8 slice_mask, 413 struct skl_ddb_entry *ddb) 414 { 415 int slice_size = intel_dbuf_slice_size(display); 416 417 if (!slice_mask) { 418 ddb->start = 0; 419 ddb->end = 0; 420 return; 421 } 422 423 ddb->start = (ffs(slice_mask) - 1) * slice_size; 424 ddb->end = fls(slice_mask) * slice_size; 425 426 WARN_ON(ddb->start >= ddb->end); 427 WARN_ON(ddb->end > DISPLAY_INFO(display)->dbuf.size); 428 } 429 430 static unsigned int mbus_ddb_offset(struct intel_display *display, u8 slice_mask) 431 { 432 struct skl_ddb_entry ddb; 433 434 if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2))) 435 slice_mask = BIT(DBUF_S1); 436 else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4))) 437 slice_mask = BIT(DBUF_S3); 438 439 skl_ddb_entry_for_slices(display, slice_mask, &ddb); 440 441 return ddb.start; 442 } 443 444 u32 skl_ddb_dbuf_slice_mask(struct intel_display *display, 445 const struct skl_ddb_entry *entry) 446 { 447 int slice_size = intel_dbuf_slice_size(display); 448 enum dbuf_slice start_slice, end_slice; 449 u8 slice_mask = 0; 450 451 if (!skl_ddb_entry_size(entry)) 452 return 0; 453 454 start_slice = entry->start / slice_size; 455 end_slice = (entry->end - 1) / slice_size; 456 457 /* 458 * Per plane DDB entry can in a really worst case be on multiple slices 459 * but single entry is anyway contiguous. 460 */ 461 while (start_slice <= end_slice) { 462 slice_mask |= BIT(start_slice); 463 start_slice++; 464 } 465 466 return slice_mask; 467 } 468 469 static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_state) 470 { 471 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 472 int hdisplay, vdisplay; 473 474 if (!crtc_state->hw.active) 475 return 0; 476 477 /* 478 * Watermark/ddb requirement highly depends upon width of the 479 * framebuffer, So instead of allocating DDB equally among pipes 480 * distribute DDB based on resolution/width of the display. 481 */ 482 drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay); 483 484 return hdisplay; 485 } 486 487 static void intel_crtc_dbuf_weights(const struct intel_dbuf_state *dbuf_state, 488 enum pipe for_pipe, 489 unsigned int *weight_start, 490 unsigned int *weight_end, 491 unsigned int *weight_total) 492 { 493 struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev); 494 enum pipe pipe; 495 496 *weight_start = 0; 497 *weight_end = 0; 498 *weight_total = 0; 499 500 for_each_pipe(display, pipe) { 501 int weight = dbuf_state->weight[pipe]; 502 503 /* 504 * Do not account pipes using other slice sets 505 * luckily as of current BSpec slice sets do not partially 506 * intersect(pipes share either same one slice or same slice set 507 * i.e no partial intersection), so it is enough to check for 508 * equality for now. 509 */ 510 if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe]) 511 continue; 512 513 *weight_total += weight; 514 if (pipe < for_pipe) { 515 *weight_start += weight; 516 *weight_end += weight; 517 } else if (pipe == for_pipe) { 518 *weight_end += weight; 519 } 520 } 521 } 522 523 static int 524 skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc) 525 { 526 struct intel_display *display = to_intel_display(crtc); 527 unsigned int weight_total, weight_start, weight_end; 528 const struct intel_dbuf_state *old_dbuf_state = 529 intel_atomic_get_old_dbuf_state(state); 530 struct intel_dbuf_state *new_dbuf_state = 531 intel_atomic_get_new_dbuf_state(state); 532 struct intel_crtc_state *crtc_state; 533 struct skl_ddb_entry ddb_slices; 534 enum pipe pipe = crtc->pipe; 535 unsigned int mbus_offset = 0; 536 u32 ddb_range_size; 537 u32 dbuf_slice_mask; 538 u32 start, end; 539 int ret; 540 541 if (new_dbuf_state->weight[pipe] == 0) { 542 skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 0, 0); 543 goto out; 544 } 545 546 dbuf_slice_mask = new_dbuf_state->slices[pipe]; 547 548 skl_ddb_entry_for_slices(display, dbuf_slice_mask, &ddb_slices); 549 mbus_offset = mbus_ddb_offset(display, dbuf_slice_mask); 550 ddb_range_size = skl_ddb_entry_size(&ddb_slices); 551 552 intel_crtc_dbuf_weights(new_dbuf_state, pipe, 553 &weight_start, &weight_end, &weight_total); 554 555 start = ddb_range_size * weight_start / weight_total; 556 end = ddb_range_size * weight_end / weight_total; 557 558 skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 559 ddb_slices.start - mbus_offset + start, 560 ddb_slices.start - mbus_offset + end); 561 562 out: 563 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] && 564 skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe], 565 &new_dbuf_state->ddb[pipe])) 566 return 0; 567 568 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 569 if (ret) 570 return ret; 571 572 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 573 if (IS_ERR(crtc_state)) 574 return PTR_ERR(crtc_state); 575 576 /* 577 * Used for checking overlaps, so we need absolute 578 * offsets instead of MBUS relative offsets. 579 */ 580 crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start; 581 crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end; 582 583 drm_dbg_kms(display->drm, 584 "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n", 585 crtc->base.base.id, crtc->base.name, 586 old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe], 587 old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end, 588 new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end, 589 old_dbuf_state->active_pipes, new_dbuf_state->active_pipes); 590 591 return 0; 592 } 593 594 static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state, 595 int width, const struct drm_format_info *format, 596 u64 modifier, unsigned int rotation, 597 u32 plane_pixel_rate, struct skl_wm_params *wp, 598 int color_plane, unsigned int pan_x); 599 600 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, 601 struct intel_plane *plane, 602 int level, 603 unsigned int latency, 604 const struct skl_wm_params *wp, 605 const struct skl_wm_level *result_prev, 606 struct skl_wm_level *result /* out */); 607 608 static unsigned int skl_wm_latency(struct intel_display *display, int level, 609 const struct skl_wm_params *wp) 610 { 611 unsigned int latency = display->wm.skl_latency[level]; 612 613 if (latency == 0) 614 return 0; 615 616 /* 617 * WaIncreaseLatencyIPCEnabled: kbl,cfl 618 * Display WA #1141: kbl,cfl 619 */ 620 if ((display->platform.kabylake || display->platform.coffeelake || 621 display->platform.cometlake) && skl_watermark_ipc_enabled(display)) 622 latency += 4; 623 624 if (skl_needs_memory_bw_wa(display) && wp && wp->x_tiled) 625 latency += 15; 626 627 return latency; 628 } 629 630 static unsigned int 631 skl_cursor_allocation(const struct intel_crtc_state *crtc_state, 632 int num_active) 633 { 634 struct intel_display *display = to_intel_display(crtc_state); 635 struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor); 636 struct skl_wm_level wm = {}; 637 int ret, min_ddb_alloc = 0; 638 struct skl_wm_params wp; 639 int level; 640 641 ret = skl_compute_wm_params(crtc_state, 256, 642 drm_format_info(DRM_FORMAT_ARGB8888), 643 DRM_FORMAT_MOD_LINEAR, 644 DRM_MODE_ROTATE_0, 645 crtc_state->pixel_rate, &wp, 0, 0); 646 drm_WARN_ON(display->drm, ret); 647 648 for (level = 0; level < display->wm.num_levels; level++) { 649 unsigned int latency = skl_wm_latency(display, level, &wp); 650 651 skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm); 652 if (wm.min_ddb_alloc == U16_MAX) 653 break; 654 655 min_ddb_alloc = wm.min_ddb_alloc; 656 } 657 658 return max(num_active == 1 ? 32 : 8, min_ddb_alloc); 659 } 660 661 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) 662 { 663 skl_ddb_entry_init(entry, 664 REG_FIELD_GET(PLANE_BUF_START_MASK, reg), 665 REG_FIELD_GET(PLANE_BUF_END_MASK, reg)); 666 if (entry->end) 667 entry->end++; 668 } 669 670 static void 671 skl_ddb_get_hw_plane_state(struct intel_display *display, 672 const enum pipe pipe, 673 const enum plane_id plane_id, 674 struct skl_ddb_entry *ddb, 675 struct skl_ddb_entry *ddb_y, 676 u16 *min_ddb, u16 *interim_ddb) 677 { 678 u32 val; 679 680 /* Cursor doesn't support NV12/planar, so no extra calculation needed */ 681 if (plane_id == PLANE_CURSOR) { 682 val = intel_de_read(display, CUR_BUF_CFG(pipe)); 683 skl_ddb_entry_init_from_hw(ddb, val); 684 return; 685 } 686 687 val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id)); 688 skl_ddb_entry_init_from_hw(ddb, val); 689 690 if (DISPLAY_VER(display) >= 30) { 691 val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id)); 692 693 *min_ddb = REG_FIELD_GET(PLANE_MIN_DBUF_BLOCKS_MASK, val); 694 *interim_ddb = REG_FIELD_GET(PLANE_INTERIM_DBUF_BLOCKS_MASK, val); 695 } 696 697 if (DISPLAY_VER(display) >= 11) 698 return; 699 700 val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id)); 701 skl_ddb_entry_init_from_hw(ddb_y, val); 702 } 703 704 static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, 705 struct skl_ddb_entry *ddb, 706 struct skl_ddb_entry *ddb_y, 707 u16 *min_ddb, u16 *interim_ddb) 708 { 709 struct intel_display *display = to_intel_display(crtc); 710 enum intel_display_power_domain power_domain; 711 enum pipe pipe = crtc->pipe; 712 intel_wakeref_t wakeref; 713 enum plane_id plane_id; 714 715 power_domain = POWER_DOMAIN_PIPE(pipe); 716 wakeref = intel_display_power_get_if_enabled(display, power_domain); 717 if (!wakeref) 718 return; 719 720 for_each_plane_id_on_crtc(crtc, plane_id) 721 skl_ddb_get_hw_plane_state(display, pipe, 722 plane_id, 723 &ddb[plane_id], 724 &ddb_y[plane_id], 725 &min_ddb[plane_id], 726 &interim_ddb[plane_id]); 727 728 intel_display_power_put(display, power_domain, wakeref); 729 } 730 731 struct dbuf_slice_conf_entry { 732 u8 active_pipes; 733 u8 dbuf_mask[I915_MAX_PIPES]; 734 bool join_mbus; 735 }; 736 737 /* 738 * Table taken from Bspec 12716 739 * Pipes do have some preferred DBuf slice affinity, 740 * plus there are some hardcoded requirements on how 741 * those should be distributed for multipipe scenarios. 742 * For more DBuf slices algorithm can get even more messy 743 * and less readable, so decided to use a table almost 744 * as is from BSpec itself - that way it is at least easier 745 * to compare, change and check. 746 */ 747 static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] = 748 /* Autogenerated with igt/tools/intel_dbuf_map tool: */ 749 { 750 { 751 .active_pipes = BIT(PIPE_A), 752 .dbuf_mask = { 753 [PIPE_A] = BIT(DBUF_S1), 754 }, 755 }, 756 { 757 .active_pipes = BIT(PIPE_B), 758 .dbuf_mask = { 759 [PIPE_B] = BIT(DBUF_S1), 760 }, 761 }, 762 { 763 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 764 .dbuf_mask = { 765 [PIPE_A] = BIT(DBUF_S1), 766 [PIPE_B] = BIT(DBUF_S2), 767 }, 768 }, 769 { 770 .active_pipes = BIT(PIPE_C), 771 .dbuf_mask = { 772 [PIPE_C] = BIT(DBUF_S2), 773 }, 774 }, 775 { 776 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 777 .dbuf_mask = { 778 [PIPE_A] = BIT(DBUF_S1), 779 [PIPE_C] = BIT(DBUF_S2), 780 }, 781 }, 782 { 783 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 784 .dbuf_mask = { 785 [PIPE_B] = BIT(DBUF_S1), 786 [PIPE_C] = BIT(DBUF_S2), 787 }, 788 }, 789 { 790 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 791 .dbuf_mask = { 792 [PIPE_A] = BIT(DBUF_S1), 793 [PIPE_B] = BIT(DBUF_S1), 794 [PIPE_C] = BIT(DBUF_S2), 795 }, 796 }, 797 {} 798 }; 799 800 /* 801 * Table taken from Bspec 49255 802 * Pipes do have some preferred DBuf slice affinity, 803 * plus there are some hardcoded requirements on how 804 * those should be distributed for multipipe scenarios. 805 * For more DBuf slices algorithm can get even more messy 806 * and less readable, so decided to use a table almost 807 * as is from BSpec itself - that way it is at least easier 808 * to compare, change and check. 809 */ 810 static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = 811 /* Autogenerated with igt/tools/intel_dbuf_map tool: */ 812 { 813 { 814 .active_pipes = BIT(PIPE_A), 815 .dbuf_mask = { 816 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 817 }, 818 }, 819 { 820 .active_pipes = BIT(PIPE_B), 821 .dbuf_mask = { 822 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 823 }, 824 }, 825 { 826 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 827 .dbuf_mask = { 828 [PIPE_A] = BIT(DBUF_S2), 829 [PIPE_B] = BIT(DBUF_S1), 830 }, 831 }, 832 { 833 .active_pipes = BIT(PIPE_C), 834 .dbuf_mask = { 835 [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1), 836 }, 837 }, 838 { 839 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 840 .dbuf_mask = { 841 [PIPE_A] = BIT(DBUF_S1), 842 [PIPE_C] = BIT(DBUF_S2), 843 }, 844 }, 845 { 846 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 847 .dbuf_mask = { 848 [PIPE_B] = BIT(DBUF_S1), 849 [PIPE_C] = BIT(DBUF_S2), 850 }, 851 }, 852 { 853 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 854 .dbuf_mask = { 855 [PIPE_A] = BIT(DBUF_S1), 856 [PIPE_B] = BIT(DBUF_S1), 857 [PIPE_C] = BIT(DBUF_S2), 858 }, 859 }, 860 { 861 .active_pipes = BIT(PIPE_D), 862 .dbuf_mask = { 863 [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1), 864 }, 865 }, 866 { 867 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), 868 .dbuf_mask = { 869 [PIPE_A] = BIT(DBUF_S1), 870 [PIPE_D] = BIT(DBUF_S2), 871 }, 872 }, 873 { 874 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), 875 .dbuf_mask = { 876 [PIPE_B] = BIT(DBUF_S1), 877 [PIPE_D] = BIT(DBUF_S2), 878 }, 879 }, 880 { 881 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), 882 .dbuf_mask = { 883 [PIPE_A] = BIT(DBUF_S1), 884 [PIPE_B] = BIT(DBUF_S1), 885 [PIPE_D] = BIT(DBUF_S2), 886 }, 887 }, 888 { 889 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), 890 .dbuf_mask = { 891 [PIPE_C] = BIT(DBUF_S1), 892 [PIPE_D] = BIT(DBUF_S2), 893 }, 894 }, 895 { 896 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), 897 .dbuf_mask = { 898 [PIPE_A] = BIT(DBUF_S1), 899 [PIPE_C] = BIT(DBUF_S2), 900 [PIPE_D] = BIT(DBUF_S2), 901 }, 902 }, 903 { 904 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 905 .dbuf_mask = { 906 [PIPE_B] = BIT(DBUF_S1), 907 [PIPE_C] = BIT(DBUF_S2), 908 [PIPE_D] = BIT(DBUF_S2), 909 }, 910 }, 911 { 912 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 913 .dbuf_mask = { 914 [PIPE_A] = BIT(DBUF_S1), 915 [PIPE_B] = BIT(DBUF_S1), 916 [PIPE_C] = BIT(DBUF_S2), 917 [PIPE_D] = BIT(DBUF_S2), 918 }, 919 }, 920 {} 921 }; 922 923 static const struct dbuf_slice_conf_entry dg2_allowed_dbufs[] = { 924 { 925 .active_pipes = BIT(PIPE_A), 926 .dbuf_mask = { 927 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 928 }, 929 }, 930 { 931 .active_pipes = BIT(PIPE_B), 932 .dbuf_mask = { 933 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 934 }, 935 }, 936 { 937 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 938 .dbuf_mask = { 939 [PIPE_A] = BIT(DBUF_S1), 940 [PIPE_B] = BIT(DBUF_S2), 941 }, 942 }, 943 { 944 .active_pipes = BIT(PIPE_C), 945 .dbuf_mask = { 946 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 947 }, 948 }, 949 { 950 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 951 .dbuf_mask = { 952 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 953 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 954 }, 955 }, 956 { 957 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 958 .dbuf_mask = { 959 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 960 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 961 }, 962 }, 963 { 964 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 965 .dbuf_mask = { 966 [PIPE_A] = BIT(DBUF_S1), 967 [PIPE_B] = BIT(DBUF_S2), 968 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 969 }, 970 }, 971 { 972 .active_pipes = BIT(PIPE_D), 973 .dbuf_mask = { 974 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 975 }, 976 }, 977 { 978 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), 979 .dbuf_mask = { 980 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 981 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 982 }, 983 }, 984 { 985 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), 986 .dbuf_mask = { 987 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 988 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 989 }, 990 }, 991 { 992 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), 993 .dbuf_mask = { 994 [PIPE_A] = BIT(DBUF_S1), 995 [PIPE_B] = BIT(DBUF_S2), 996 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 997 }, 998 }, 999 { 1000 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), 1001 .dbuf_mask = { 1002 [PIPE_C] = BIT(DBUF_S3), 1003 [PIPE_D] = BIT(DBUF_S4), 1004 }, 1005 }, 1006 { 1007 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), 1008 .dbuf_mask = { 1009 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1010 [PIPE_C] = BIT(DBUF_S3), 1011 [PIPE_D] = BIT(DBUF_S4), 1012 }, 1013 }, 1014 { 1015 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1016 .dbuf_mask = { 1017 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 1018 [PIPE_C] = BIT(DBUF_S3), 1019 [PIPE_D] = BIT(DBUF_S4), 1020 }, 1021 }, 1022 { 1023 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1024 .dbuf_mask = { 1025 [PIPE_A] = BIT(DBUF_S1), 1026 [PIPE_B] = BIT(DBUF_S2), 1027 [PIPE_C] = BIT(DBUF_S3), 1028 [PIPE_D] = BIT(DBUF_S4), 1029 }, 1030 }, 1031 {} 1032 }; 1033 1034 static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = { 1035 /* 1036 * Keep the join_mbus cases first so check_mbus_joined() 1037 * will prefer them over the !join_mbus cases. 1038 */ 1039 { 1040 .active_pipes = BIT(PIPE_A), 1041 .dbuf_mask = { 1042 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4), 1043 }, 1044 .join_mbus = true, 1045 }, 1046 { 1047 .active_pipes = BIT(PIPE_B), 1048 .dbuf_mask = { 1049 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4), 1050 }, 1051 .join_mbus = true, 1052 }, 1053 { 1054 .active_pipes = BIT(PIPE_A), 1055 .dbuf_mask = { 1056 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1057 }, 1058 .join_mbus = false, 1059 }, 1060 { 1061 .active_pipes = BIT(PIPE_B), 1062 .dbuf_mask = { 1063 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1064 }, 1065 .join_mbus = false, 1066 }, 1067 { 1068 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 1069 .dbuf_mask = { 1070 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1071 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1072 }, 1073 }, 1074 { 1075 .active_pipes = BIT(PIPE_C), 1076 .dbuf_mask = { 1077 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1078 }, 1079 }, 1080 { 1081 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 1082 .dbuf_mask = { 1083 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1084 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1085 }, 1086 }, 1087 { 1088 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 1089 .dbuf_mask = { 1090 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1091 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1092 }, 1093 }, 1094 { 1095 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 1096 .dbuf_mask = { 1097 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1098 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1099 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1100 }, 1101 }, 1102 { 1103 .active_pipes = BIT(PIPE_D), 1104 .dbuf_mask = { 1105 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1106 }, 1107 }, 1108 { 1109 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), 1110 .dbuf_mask = { 1111 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1112 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1113 }, 1114 }, 1115 { 1116 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), 1117 .dbuf_mask = { 1118 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1119 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1120 }, 1121 }, 1122 { 1123 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), 1124 .dbuf_mask = { 1125 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1126 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1127 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1128 }, 1129 }, 1130 { 1131 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), 1132 .dbuf_mask = { 1133 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1134 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1135 }, 1136 }, 1137 { 1138 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), 1139 .dbuf_mask = { 1140 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1141 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1142 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1143 }, 1144 }, 1145 { 1146 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1147 .dbuf_mask = { 1148 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1149 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1150 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1151 }, 1152 }, 1153 { 1154 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1155 .dbuf_mask = { 1156 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1157 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1158 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1159 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1160 }, 1161 }, 1162 {} 1163 1164 }; 1165 1166 static bool check_mbus_joined(u8 active_pipes, 1167 const struct dbuf_slice_conf_entry *dbuf_slices) 1168 { 1169 int i; 1170 1171 for (i = 0; dbuf_slices[i].active_pipes != 0; i++) { 1172 if (dbuf_slices[i].active_pipes == active_pipes) 1173 return dbuf_slices[i].join_mbus; 1174 } 1175 return false; 1176 } 1177 1178 static bool adlp_check_mbus_joined(u8 active_pipes) 1179 { 1180 return check_mbus_joined(active_pipes, adlp_allowed_dbufs); 1181 } 1182 1183 static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus, 1184 const struct dbuf_slice_conf_entry *dbuf_slices) 1185 { 1186 int i; 1187 1188 for (i = 0; dbuf_slices[i].active_pipes != 0; i++) { 1189 if (dbuf_slices[i].active_pipes == active_pipes && 1190 dbuf_slices[i].join_mbus == join_mbus) 1191 return dbuf_slices[i].dbuf_mask[pipe]; 1192 } 1193 return 0; 1194 } 1195 1196 /* 1197 * This function finds an entry with same enabled pipe configuration and 1198 * returns correspondent DBuf slice mask as stated in BSpec for particular 1199 * platform. 1200 */ 1201 static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1202 { 1203 /* 1204 * FIXME: For ICL this is still a bit unclear as prev BSpec revision 1205 * required calculating "pipe ratio" in order to determine 1206 * if one or two slices can be used for single pipe configurations 1207 * as additional constraint to the existing table. 1208 * However based on recent info, it should be not "pipe ratio" 1209 * but rather ratio between pixel_rate and cdclk with additional 1210 * constants, so for now we are using only table until this is 1211 * clarified. Also this is the reason why crtc_state param is 1212 * still here - we will need it once those additional constraints 1213 * pop up. 1214 */ 1215 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1216 icl_allowed_dbufs); 1217 } 1218 1219 static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1220 { 1221 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1222 tgl_allowed_dbufs); 1223 } 1224 1225 static u8 adlp_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1226 { 1227 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1228 adlp_allowed_dbufs); 1229 } 1230 1231 static u8 dg2_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1232 { 1233 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1234 dg2_allowed_dbufs); 1235 } 1236 1237 static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool join_mbus) 1238 { 1239 struct intel_display *display = to_intel_display(crtc); 1240 enum pipe pipe = crtc->pipe; 1241 1242 if (display->platform.dg2) 1243 return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1244 else if (DISPLAY_VER(display) >= 13) 1245 return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1246 else if (DISPLAY_VER(display) == 12) 1247 return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1248 else if (DISPLAY_VER(display) == 11) 1249 return icl_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1250 /* 1251 * For anything else just return one slice yet. 1252 * Should be extended for other platforms. 1253 */ 1254 return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0; 1255 } 1256 1257 static bool 1258 use_minimal_wm0_only(const struct intel_crtc_state *crtc_state, 1259 struct intel_plane *plane) 1260 { 1261 struct intel_display *display = to_intel_display(plane); 1262 1263 /* Xe3+ are auto minimum DDB capble. So don't force minimal wm0 */ 1264 return IS_DISPLAY_VER(display, 13, 20) && 1265 crtc_state->uapi.async_flip && 1266 plane->async_flip; 1267 } 1268 1269 unsigned int 1270 skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, 1271 struct intel_plane *plane, int width, int height, 1272 int cpp) 1273 { 1274 /* 1275 * We calculate extra ddb based on ratio plane rate/total data rate 1276 * in case, in some cases we should not allocate extra ddb for the plane, 1277 * so do not count its data rate, if this is the case. 1278 */ 1279 if (use_minimal_wm0_only(crtc_state, plane)) 1280 return 0; 1281 1282 return width * height * cpp; 1283 } 1284 1285 static u64 1286 skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state) 1287 { 1288 struct intel_display *display = to_intel_display(crtc_state); 1289 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1290 enum plane_id plane_id; 1291 u64 data_rate = 0; 1292 1293 for_each_plane_id_on_crtc(crtc, plane_id) { 1294 if (plane_id == PLANE_CURSOR) 1295 continue; 1296 1297 data_rate += crtc_state->rel_data_rate[plane_id]; 1298 1299 if (DISPLAY_VER(display) < 11) 1300 data_rate += crtc_state->rel_data_rate_y[plane_id]; 1301 } 1302 1303 return data_rate; 1304 } 1305 1306 const struct skl_wm_level * 1307 skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, 1308 enum plane_id plane_id, 1309 int level) 1310 { 1311 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 1312 1313 if (level == 0 && pipe_wm->use_sagv_wm) 1314 return &wm->sagv.wm0; 1315 1316 return &wm->wm[level]; 1317 } 1318 1319 const struct skl_wm_level * 1320 skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm, 1321 enum plane_id plane_id) 1322 { 1323 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 1324 1325 if (pipe_wm->use_sagv_wm) 1326 return &wm->sagv.trans_wm; 1327 1328 return &wm->trans_wm; 1329 } 1330 1331 /* 1332 * We only disable the watermarks for each plane if 1333 * they exceed the ddb allocation of said plane. This 1334 * is done so that we don't end up touching cursor 1335 * watermarks needlessly when some other plane reduces 1336 * our max possible watermark level. 1337 * 1338 * Bspec has this to say about the PLANE_WM enable bit: 1339 * "All the watermarks at this level for all enabled 1340 * planes must be enabled before the level will be used." 1341 * So this is actually safe to do. 1342 */ 1343 static void 1344 skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb) 1345 { 1346 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) 1347 memset(wm, 0, sizeof(*wm)); 1348 } 1349 1350 static void 1351 skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm, 1352 const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb) 1353 { 1354 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) || 1355 uv_wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) { 1356 memset(wm, 0, sizeof(*wm)); 1357 memset(uv_wm, 0, sizeof(*uv_wm)); 1358 } 1359 } 1360 1361 static bool skl_need_wm_copy_wa(struct intel_display *display, int level, 1362 const struct skl_plane_wm *wm) 1363 { 1364 /* 1365 * Wa_1408961008:icl, ehl 1366 * Wa_14012656716:tgl, adl 1367 * Wa_14017887344:icl 1368 * Wa_14017868169:adl, tgl 1369 * Due to some power saving optimizations, different subsystems 1370 * like PSR, might still use even disabled wm level registers, 1371 * for "reference", so lets keep at least the values sane. 1372 * Considering amount of WA requiring us to do similar things, was 1373 * decided to simply do it for all of the platforms, as those wm 1374 * levels are disabled, this isn't going to do harm anyway. 1375 */ 1376 return level > 0 && !wm->wm[level].enable; 1377 } 1378 1379 struct skl_plane_ddb_iter { 1380 u64 data_rate; 1381 u16 start, size; 1382 }; 1383 1384 static void 1385 skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter, 1386 struct skl_ddb_entry *ddb, 1387 const struct skl_wm_level *wm, 1388 u64 data_rate) 1389 { 1390 u16 size, extra = 0; 1391 1392 if (data_rate) { 1393 extra = min_t(u16, iter->size, 1394 DIV64_U64_ROUND_UP(iter->size * data_rate, 1395 iter->data_rate)); 1396 iter->size -= extra; 1397 iter->data_rate -= data_rate; 1398 } 1399 1400 /* 1401 * Keep ddb entry of all disabled planes explicitly zeroed 1402 * to avoid skl_ddb_add_affected_planes() adding them to 1403 * the state when other planes change their allocations. 1404 */ 1405 size = wm->min_ddb_alloc + extra; 1406 if (size) 1407 iter->start = skl_ddb_entry_init(ddb, iter->start, 1408 iter->start + size); 1409 } 1410 1411 static int 1412 skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, 1413 struct intel_crtc *crtc) 1414 { 1415 struct intel_crtc_state *crtc_state = 1416 intel_atomic_get_new_crtc_state(state, crtc); 1417 const struct intel_dbuf_state *dbuf_state = 1418 intel_atomic_get_new_dbuf_state(state); 1419 const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe]; 1420 struct intel_display *display = to_intel_display(state); 1421 int num_active = hweight8(dbuf_state->active_pipes); 1422 struct skl_plane_ddb_iter iter; 1423 enum plane_id plane_id; 1424 u16 cursor_size; 1425 u32 blocks; 1426 int level; 1427 1428 /* Clear the partitioning for disabled planes. */ 1429 memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb)); 1430 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); 1431 memset(crtc_state->wm.skl.plane_min_ddb, 0, 1432 sizeof(crtc_state->wm.skl.plane_min_ddb)); 1433 memset(crtc_state->wm.skl.plane_interim_ddb, 0, 1434 sizeof(crtc_state->wm.skl.plane_interim_ddb)); 1435 1436 if (!crtc_state->hw.active) 1437 return 0; 1438 1439 iter.start = alloc->start; 1440 iter.size = skl_ddb_entry_size(alloc); 1441 if (iter.size == 0) 1442 return 0; 1443 1444 /* Allocate fixed number of blocks for cursor. */ 1445 cursor_size = skl_cursor_allocation(crtc_state, num_active); 1446 iter.size -= cursor_size; 1447 skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR], 1448 alloc->end - cursor_size, alloc->end); 1449 1450 iter.data_rate = skl_total_relative_data_rate(crtc_state); 1451 1452 /* 1453 * Find the highest watermark level for which we can satisfy the block 1454 * requirement of active planes. 1455 */ 1456 for (level = display->wm.num_levels - 1; level >= 0; level--) { 1457 blocks = 0; 1458 for_each_plane_id_on_crtc(crtc, plane_id) { 1459 const struct skl_plane_wm *wm = 1460 &crtc_state->wm.skl.optimal.planes[plane_id]; 1461 1462 if (plane_id == PLANE_CURSOR) { 1463 const struct skl_ddb_entry *ddb = 1464 &crtc_state->wm.skl.plane_ddb[plane_id]; 1465 1466 if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) { 1467 drm_WARN_ON(display->drm, 1468 wm->wm[level].min_ddb_alloc != U16_MAX); 1469 blocks = U32_MAX; 1470 break; 1471 } 1472 continue; 1473 } 1474 1475 blocks += wm->wm[level].min_ddb_alloc; 1476 blocks += wm->uv_wm[level].min_ddb_alloc; 1477 } 1478 1479 if (blocks <= iter.size) { 1480 iter.size -= blocks; 1481 break; 1482 } 1483 } 1484 1485 if (level < 0) { 1486 drm_dbg_kms(display->drm, 1487 "Requested display configuration exceeds system DDB limitations"); 1488 drm_dbg_kms(display->drm, "minimum required %d/%d\n", 1489 blocks, iter.size); 1490 return -EINVAL; 1491 } 1492 1493 /* avoid the WARN later when we don't allocate any extra DDB */ 1494 if (iter.data_rate == 0) 1495 iter.size = 0; 1496 1497 /* 1498 * Grant each plane the blocks it requires at the highest achievable 1499 * watermark level, plus an extra share of the leftover blocks 1500 * proportional to its relative data rate. 1501 */ 1502 for_each_plane_id_on_crtc(crtc, plane_id) { 1503 struct skl_ddb_entry *ddb = 1504 &crtc_state->wm.skl.plane_ddb[plane_id]; 1505 struct skl_ddb_entry *ddb_y = 1506 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 1507 u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id]; 1508 u16 *interim_ddb = 1509 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; 1510 const struct skl_plane_wm *wm = 1511 &crtc_state->wm.skl.optimal.planes[plane_id]; 1512 1513 if (plane_id == PLANE_CURSOR) 1514 continue; 1515 1516 if (DISPLAY_VER(display) < 11 && 1517 crtc_state->nv12_planes & BIT(plane_id)) { 1518 skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level], 1519 crtc_state->rel_data_rate_y[plane_id]); 1520 skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level], 1521 crtc_state->rel_data_rate[plane_id]); 1522 } else { 1523 skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level], 1524 crtc_state->rel_data_rate[plane_id]); 1525 } 1526 1527 if (DISPLAY_VER(display) >= 30) { 1528 *min_ddb = wm->wm[0].min_ddb_alloc; 1529 *interim_ddb = wm->sagv.wm0.min_ddb_alloc; 1530 } 1531 } 1532 drm_WARN_ON(display->drm, iter.size != 0 || iter.data_rate != 0); 1533 1534 /* 1535 * When we calculated watermark values we didn't know how high 1536 * of a level we'd actually be able to hit, so we just marked 1537 * all levels as "enabled." Go back now and disable the ones 1538 * that aren't actually possible. 1539 */ 1540 for (level++; level < display->wm.num_levels; level++) { 1541 for_each_plane_id_on_crtc(crtc, plane_id) { 1542 const struct skl_ddb_entry *ddb = 1543 &crtc_state->wm.skl.plane_ddb[plane_id]; 1544 const struct skl_ddb_entry *ddb_y = 1545 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 1546 struct skl_plane_wm *wm = 1547 &crtc_state->wm.skl.optimal.planes[plane_id]; 1548 1549 if (DISPLAY_VER(display) < 11 && 1550 crtc_state->nv12_planes & BIT(plane_id)) 1551 skl_check_nv12_wm_level(&wm->wm[level], 1552 &wm->uv_wm[level], 1553 ddb_y, ddb); 1554 else 1555 skl_check_wm_level(&wm->wm[level], ddb); 1556 1557 if (skl_need_wm_copy_wa(display, level, wm)) { 1558 wm->wm[level].blocks = wm->wm[level - 1].blocks; 1559 wm->wm[level].lines = wm->wm[level - 1].lines; 1560 wm->wm[level].ignore_lines = wm->wm[level - 1].ignore_lines; 1561 } 1562 } 1563 } 1564 1565 /* 1566 * Go back and disable the transition and SAGV watermarks 1567 * if it turns out we don't have enough DDB blocks for them. 1568 */ 1569 for_each_plane_id_on_crtc(crtc, plane_id) { 1570 const struct skl_ddb_entry *ddb = 1571 &crtc_state->wm.skl.plane_ddb[plane_id]; 1572 const struct skl_ddb_entry *ddb_y = 1573 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 1574 u16 *interim_ddb = 1575 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; 1576 struct skl_plane_wm *wm = 1577 &crtc_state->wm.skl.optimal.planes[plane_id]; 1578 1579 if (DISPLAY_VER(display) < 11 && 1580 crtc_state->nv12_planes & BIT(plane_id)) { 1581 skl_check_wm_level(&wm->trans_wm, ddb_y); 1582 } else { 1583 WARN_ON(skl_ddb_entry_size(ddb_y)); 1584 1585 skl_check_wm_level(&wm->trans_wm, ddb); 1586 } 1587 1588 skl_check_wm_level(&wm->sagv.wm0, ddb); 1589 if (DISPLAY_VER(display) >= 30) 1590 *interim_ddb = wm->sagv.wm0.min_ddb_alloc; 1591 1592 skl_check_wm_level(&wm->sagv.trans_wm, ddb); 1593 } 1594 1595 return 0; 1596 } 1597 1598 /* 1599 * The max latency should be 257 (max the punit can code is 255 and we add 2us 1600 * for the read latency) and cpp should always be <= 8, so that 1601 * should allow pixel_rate up to ~2 GHz which seems sufficient since max 1602 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. 1603 */ 1604 static uint_fixed_16_16_t 1605 skl_wm_method1(struct intel_display *display, u32 pixel_rate, 1606 u8 cpp, u32 latency, u32 dbuf_block_size) 1607 { 1608 u32 wm_intermediate_val; 1609 uint_fixed_16_16_t ret; 1610 1611 if (latency == 0) 1612 return FP_16_16_MAX; 1613 1614 wm_intermediate_val = latency * pixel_rate * cpp; 1615 ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size); 1616 1617 if (DISPLAY_VER(display) >= 10) 1618 ret = add_fixed16_u32(ret, 1); 1619 1620 return ret; 1621 } 1622 1623 static uint_fixed_16_16_t 1624 skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency, 1625 uint_fixed_16_16_t plane_blocks_per_line) 1626 { 1627 u32 wm_intermediate_val; 1628 uint_fixed_16_16_t ret; 1629 1630 if (latency == 0) 1631 return FP_16_16_MAX; 1632 1633 wm_intermediate_val = latency * pixel_rate; 1634 wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val, 1635 pipe_htotal * 1000); 1636 ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line); 1637 return ret; 1638 } 1639 1640 static uint_fixed_16_16_t 1641 intel_get_linetime_us(const struct intel_crtc_state *crtc_state) 1642 { 1643 struct intel_display *display = to_intel_display(crtc_state); 1644 u32 pixel_rate; 1645 u32 crtc_htotal; 1646 uint_fixed_16_16_t linetime_us; 1647 1648 if (!crtc_state->hw.active) 1649 return u32_to_fixed16(0); 1650 1651 pixel_rate = crtc_state->pixel_rate; 1652 1653 if (drm_WARN_ON(display->drm, pixel_rate == 0)) 1654 return u32_to_fixed16(0); 1655 1656 crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal; 1657 linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate); 1658 1659 return linetime_us; 1660 } 1661 1662 static int 1663 skl_compute_wm_params(const struct intel_crtc_state *crtc_state, 1664 int width, const struct drm_format_info *format, 1665 u64 modifier, unsigned int rotation, 1666 u32 plane_pixel_rate, struct skl_wm_params *wp, 1667 int color_plane, unsigned int pan_x) 1668 { 1669 struct intel_display *display = to_intel_display(crtc_state); 1670 u32 interm_pbpl; 1671 1672 /* only planar format has two planes */ 1673 if (color_plane == 1 && 1674 !intel_format_info_is_yuv_semiplanar(format, modifier)) { 1675 drm_dbg_kms(display->drm, 1676 "Non planar format have single plane\n"); 1677 return -EINVAL; 1678 } 1679 1680 wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; 1681 wp->y_tiled = modifier != I915_FORMAT_MOD_X_TILED && 1682 intel_fb_is_tiled_modifier(modifier); 1683 wp->rc_surface = intel_fb_is_ccs_modifier(modifier); 1684 wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); 1685 1686 wp->width = width; 1687 if (color_plane == 1 && wp->is_planar) 1688 wp->width /= 2; 1689 1690 wp->cpp = format->cpp[color_plane]; 1691 wp->plane_pixel_rate = plane_pixel_rate; 1692 1693 if (DISPLAY_VER(display) >= 11 && 1694 modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1) 1695 wp->dbuf_block_size = 256; 1696 else 1697 wp->dbuf_block_size = 512; 1698 1699 if (drm_rotation_90_or_270(rotation)) { 1700 switch (wp->cpp) { 1701 case 1: 1702 wp->y_min_scanlines = 16; 1703 break; 1704 case 2: 1705 wp->y_min_scanlines = 8; 1706 break; 1707 case 4: 1708 wp->y_min_scanlines = 4; 1709 break; 1710 default: 1711 MISSING_CASE(wp->cpp); 1712 return -EINVAL; 1713 } 1714 } else { 1715 wp->y_min_scanlines = 4; 1716 } 1717 1718 if (skl_needs_memory_bw_wa(display)) 1719 wp->y_min_scanlines *= 2; 1720 1721 wp->plane_bytes_per_line = wp->width * wp->cpp; 1722 if (wp->y_tiled) { 1723 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line * 1724 wp->y_min_scanlines, 1725 wp->dbuf_block_size); 1726 1727 if (DISPLAY_VER(display) >= 30) 1728 interm_pbpl += (pan_x != 0); 1729 else if (DISPLAY_VER(display) >= 10) 1730 interm_pbpl++; 1731 1732 wp->plane_blocks_per_line = div_fixed16(interm_pbpl, 1733 wp->y_min_scanlines); 1734 } else { 1735 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 1736 wp->dbuf_block_size); 1737 1738 if (!wp->x_tiled || DISPLAY_VER(display) >= 10) 1739 interm_pbpl++; 1740 1741 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl); 1742 } 1743 1744 wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines, 1745 wp->plane_blocks_per_line); 1746 1747 wp->linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(crtc_state)); 1748 1749 return 0; 1750 } 1751 1752 static int 1753 skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state, 1754 const struct intel_plane_state *plane_state, 1755 struct skl_wm_params *wp, int color_plane) 1756 { 1757 const struct drm_framebuffer *fb = plane_state->hw.fb; 1758 int width; 1759 1760 /* 1761 * Src coordinates are already rotated by 270 degrees for 1762 * the 90/270 degree plane rotation cases (to match the 1763 * GTT mapping), hence no need to account for rotation here. 1764 */ 1765 width = drm_rect_width(&plane_state->uapi.src) >> 16; 1766 1767 return skl_compute_wm_params(crtc_state, width, 1768 fb->format, fb->modifier, 1769 plane_state->hw.rotation, 1770 intel_plane_pixel_rate(crtc_state, plane_state), 1771 wp, color_plane, 1772 plane_state->uapi.src.x1); 1773 } 1774 1775 static bool skl_wm_has_lines(struct intel_display *display, int level) 1776 { 1777 if (DISPLAY_VER(display) >= 10) 1778 return true; 1779 1780 /* The number of lines are ignored for the level 0 watermark. */ 1781 return level > 0; 1782 } 1783 1784 static int skl_wm_max_lines(struct intel_display *display) 1785 { 1786 if (DISPLAY_VER(display) >= 13) 1787 return 255; 1788 else 1789 return 31; 1790 } 1791 1792 static bool xe3_auto_min_alloc_capable(struct intel_plane *plane, int level) 1793 { 1794 struct intel_display *display = to_intel_display(plane); 1795 1796 return DISPLAY_VER(display) >= 30 && level == 0 && plane->id != PLANE_CURSOR; 1797 } 1798 1799 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, 1800 struct intel_plane *plane, 1801 int level, 1802 unsigned int latency, 1803 const struct skl_wm_params *wp, 1804 const struct skl_wm_level *result_prev, 1805 struct skl_wm_level *result /* out */) 1806 { 1807 struct intel_display *display = to_intel_display(crtc_state); 1808 uint_fixed_16_16_t method1, method2; 1809 uint_fixed_16_16_t selected_result; 1810 u32 blocks, lines, min_ddb_alloc = 0; 1811 1812 if (latency == 0 || 1813 (use_minimal_wm0_only(crtc_state, plane) && level > 0)) { 1814 /* reject it */ 1815 result->min_ddb_alloc = U16_MAX; 1816 return; 1817 } 1818 1819 method1 = skl_wm_method1(display, wp->plane_pixel_rate, 1820 wp->cpp, latency, wp->dbuf_block_size); 1821 method2 = skl_wm_method2(wp->plane_pixel_rate, 1822 crtc_state->hw.pipe_mode.crtc_htotal, 1823 latency, 1824 wp->plane_blocks_per_line); 1825 1826 if (wp->y_tiled) { 1827 selected_result = max_fixed16(method2, wp->y_tile_minimum); 1828 } else { 1829 if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal / 1830 wp->dbuf_block_size < 1) && 1831 (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) { 1832 selected_result = method2; 1833 } else if (latency >= wp->linetime_us) { 1834 if (DISPLAY_VER(display) == 9) 1835 selected_result = min_fixed16(method1, method2); 1836 else 1837 selected_result = method2; 1838 } else { 1839 selected_result = method1; 1840 } 1841 } 1842 1843 blocks = fixed16_to_u32_round_up(selected_result); 1844 if (DISPLAY_VER(display) < 30) 1845 blocks++; 1846 1847 /* 1848 * Lets have blocks at minimum equivalent to plane_blocks_per_line 1849 * as there will be at minimum one line for lines configuration. This 1850 * is a work around for FIFO underruns observed with resolutions like 1851 * 4k 60 Hz in single channel DRAM configurations. 1852 * 1853 * As per the Bspec 49325, if the ddb allocation can hold at least 1854 * one plane_blocks_per_line, we should have selected method2 in 1855 * the above logic. Assuming that modern versions have enough dbuf 1856 * and method2 guarantees blocks equivalent to at least 1 line, 1857 * select the blocks as plane_blocks_per_line. 1858 * 1859 * TODO: Revisit the logic when we have better understanding on DRAM 1860 * channels' impact on the level 0 memory latency and the relevant 1861 * wm calculations. 1862 */ 1863 if (skl_wm_has_lines(display, level)) 1864 blocks = max(blocks, 1865 fixed16_to_u32_round_up(wp->plane_blocks_per_line)); 1866 lines = div_round_up_fixed16(selected_result, 1867 wp->plane_blocks_per_line); 1868 1869 if (DISPLAY_VER(display) == 9) { 1870 /* Display WA #1125: skl,bxt,kbl */ 1871 if (level == 0 && wp->rc_surface) 1872 blocks += fixed16_to_u32_round_up(wp->y_tile_minimum); 1873 1874 /* Display WA #1126: skl,bxt,kbl */ 1875 if (level >= 1 && level <= 7) { 1876 if (wp->y_tiled) { 1877 blocks += fixed16_to_u32_round_up(wp->y_tile_minimum); 1878 lines += wp->y_min_scanlines; 1879 } else { 1880 blocks++; 1881 } 1882 1883 /* 1884 * Make sure result blocks for higher latency levels are 1885 * at least as high as level below the current level. 1886 * Assumption in DDB algorithm optimization for special 1887 * cases. Also covers Display WA #1125 for RC. 1888 */ 1889 if (result_prev->blocks > blocks) 1890 blocks = result_prev->blocks; 1891 } 1892 } 1893 1894 if (DISPLAY_VER(display) >= 11) { 1895 if (wp->y_tiled) { 1896 int extra_lines; 1897 1898 if (lines % wp->y_min_scanlines == 0) 1899 extra_lines = wp->y_min_scanlines; 1900 else 1901 extra_lines = wp->y_min_scanlines * 2 - 1902 lines % wp->y_min_scanlines; 1903 1904 min_ddb_alloc = mul_round_up_u32_fixed16(lines + extra_lines, 1905 wp->plane_blocks_per_line); 1906 } else { 1907 min_ddb_alloc = blocks + DIV_ROUND_UP(blocks, 10); 1908 } 1909 } 1910 1911 if (!skl_wm_has_lines(display, level)) 1912 lines = 0; 1913 1914 if (lines > skl_wm_max_lines(display)) { 1915 /* reject it */ 1916 result->min_ddb_alloc = U16_MAX; 1917 return; 1918 } 1919 1920 /* 1921 * If lines is valid, assume we can use this watermark level 1922 * for now. We'll come back and disable it after we calculate the 1923 * DDB allocation if it turns out we don't actually have enough 1924 * blocks to satisfy it. 1925 */ 1926 result->blocks = blocks; 1927 result->lines = lines; 1928 /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */ 1929 result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1; 1930 result->enable = true; 1931 result->auto_min_alloc_wm_enable = xe3_auto_min_alloc_capable(plane, level); 1932 1933 if (DISPLAY_VER(display) < 12 && display->sagv.block_time_us) 1934 result->can_sagv = latency >= display->sagv.block_time_us; 1935 } 1936 1937 static void 1938 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state, 1939 struct intel_plane *plane, 1940 const struct skl_wm_params *wm_params, 1941 struct skl_wm_level *levels) 1942 { 1943 struct intel_display *display = to_intel_display(crtc_state); 1944 struct skl_wm_level *result_prev = &levels[0]; 1945 int level; 1946 1947 for (level = 0; level < display->wm.num_levels; level++) { 1948 struct skl_wm_level *result = &levels[level]; 1949 unsigned int latency = skl_wm_latency(display, level, wm_params); 1950 1951 skl_compute_plane_wm(crtc_state, plane, level, latency, 1952 wm_params, result_prev, result); 1953 1954 result_prev = result; 1955 } 1956 } 1957 1958 static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state, 1959 struct intel_plane *plane, 1960 const struct skl_wm_params *wm_params, 1961 struct skl_plane_wm *plane_wm) 1962 { 1963 struct intel_display *display = to_intel_display(crtc_state); 1964 struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0; 1965 struct skl_wm_level *levels = plane_wm->wm; 1966 unsigned int latency = 0; 1967 1968 if (display->sagv.block_time_us) 1969 latency = display->sagv.block_time_us + 1970 skl_wm_latency(display, 0, wm_params); 1971 1972 skl_compute_plane_wm(crtc_state, plane, 0, latency, 1973 wm_params, &levels[0], 1974 sagv_wm); 1975 } 1976 1977 static void skl_compute_transition_wm(struct intel_display *display, 1978 struct skl_wm_level *trans_wm, 1979 const struct skl_wm_level *wm0, 1980 const struct skl_wm_params *wp) 1981 { 1982 u16 trans_min, trans_amount, trans_y_tile_min; 1983 u16 wm0_blocks, trans_offset, blocks; 1984 1985 /* Transition WM don't make any sense if ipc is disabled */ 1986 if (!skl_watermark_ipc_enabled(display)) 1987 return; 1988 1989 /* 1990 * WaDisableTWM:skl,kbl,cfl,bxt 1991 * Transition WM are not recommended by HW team for GEN9 1992 */ 1993 if (DISPLAY_VER(display) == 9) 1994 return; 1995 1996 if (DISPLAY_VER(display) >= 11) 1997 trans_min = 4; 1998 else 1999 trans_min = 14; 2000 2001 /* Display WA #1140: glk,cnl */ 2002 if (DISPLAY_VER(display) == 10) 2003 trans_amount = 0; 2004 else 2005 trans_amount = 10; /* This is configurable amount */ 2006 2007 trans_offset = trans_min + trans_amount; 2008 2009 /* 2010 * The spec asks for Selected Result Blocks for wm0 (the real value), 2011 * not Result Blocks (the integer value). Pay attention to the capital 2012 * letters. The value wm_l0->blocks is actually Result Blocks, but 2013 * since Result Blocks is the ceiling of Selected Result Blocks plus 1, 2014 * and since we later will have to get the ceiling of the sum in the 2015 * transition watermarks calculation, we can just pretend Selected 2016 * Result Blocks is Result Blocks minus 1 and it should work for the 2017 * current platforms. 2018 */ 2019 wm0_blocks = wm0->blocks - 1; 2020 2021 if (wp->y_tiled) { 2022 trans_y_tile_min = 2023 (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum); 2024 blocks = max(wm0_blocks, trans_y_tile_min) + trans_offset; 2025 } else { 2026 blocks = wm0_blocks + trans_offset; 2027 } 2028 blocks++; 2029 2030 /* 2031 * Just assume we can enable the transition watermark. After 2032 * computing the DDB we'll come back and disable it if that 2033 * assumption turns out to be false. 2034 */ 2035 trans_wm->blocks = blocks; 2036 trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1); 2037 trans_wm->enable = true; 2038 } 2039 2040 static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state, 2041 const struct intel_plane_state *plane_state, 2042 struct intel_plane *plane, int color_plane) 2043 { 2044 struct intel_display *display = to_intel_display(crtc_state); 2045 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id]; 2046 struct skl_wm_params wm_params; 2047 int ret; 2048 2049 ret = skl_compute_plane_wm_params(crtc_state, plane_state, 2050 &wm_params, color_plane); 2051 if (ret) 2052 return ret; 2053 2054 skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm); 2055 2056 skl_compute_transition_wm(display, &wm->trans_wm, 2057 &wm->wm[0], &wm_params); 2058 2059 if (DISPLAY_VER(display) >= 12) { 2060 tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm); 2061 2062 skl_compute_transition_wm(display, &wm->sagv.trans_wm, 2063 &wm->sagv.wm0, &wm_params); 2064 } 2065 2066 return 0; 2067 } 2068 2069 static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state, 2070 const struct intel_plane_state *plane_state, 2071 struct intel_plane *plane) 2072 { 2073 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id]; 2074 struct skl_wm_params wm_params; 2075 int ret; 2076 2077 wm->is_planar = true; 2078 2079 /* uv plane watermarks must also be validated for NV12/Planar */ 2080 ret = skl_compute_plane_wm_params(crtc_state, plane_state, 2081 &wm_params, 1); 2082 if (ret) 2083 return ret; 2084 2085 skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm); 2086 2087 return 0; 2088 } 2089 2090 static int skl_build_plane_wm(struct intel_crtc_state *crtc_state, 2091 const struct intel_plane_state *plane_state) 2092 { 2093 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2094 enum plane_id plane_id = plane->id; 2095 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; 2096 const struct drm_framebuffer *fb = plane_state->hw.fb; 2097 int ret; 2098 2099 memset(wm, 0, sizeof(*wm)); 2100 2101 if (!intel_wm_plane_visible(crtc_state, plane_state)) 2102 return 0; 2103 2104 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2105 plane, 0); 2106 if (ret) 2107 return ret; 2108 2109 if (fb->format->is_yuv && fb->format->num_planes > 1) { 2110 ret = skl_build_plane_wm_uv(crtc_state, plane_state, 2111 plane); 2112 if (ret) 2113 return ret; 2114 } 2115 2116 return 0; 2117 } 2118 2119 static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, 2120 const struct intel_plane_state *plane_state) 2121 { 2122 struct intel_display *display = to_intel_display(plane_state); 2123 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2124 enum plane_id plane_id = plane->id; 2125 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; 2126 int ret; 2127 2128 /* Watermarks calculated on UV plane */ 2129 if (plane_state->is_y_plane) 2130 return 0; 2131 2132 memset(wm, 0, sizeof(*wm)); 2133 2134 if (plane_state->planar_linked_plane) { 2135 const struct drm_framebuffer *fb = plane_state->hw.fb; 2136 2137 drm_WARN_ON(display->drm, 2138 !intel_wm_plane_visible(crtc_state, plane_state)); 2139 drm_WARN_ON(display->drm, !fb->format->is_yuv || 2140 fb->format->num_planes == 1); 2141 2142 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2143 plane_state->planar_linked_plane, 0); 2144 if (ret) 2145 return ret; 2146 2147 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2148 plane, 1); 2149 if (ret) 2150 return ret; 2151 } else if (intel_wm_plane_visible(crtc_state, plane_state)) { 2152 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2153 plane, 0); 2154 if (ret) 2155 return ret; 2156 } 2157 2158 return 0; 2159 } 2160 2161 static int 2162 cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) 2163 { 2164 struct intel_display *display = to_intel_display(crtc_state); 2165 struct intel_atomic_state *state = 2166 to_intel_atomic_state(crtc_state->uapi.state); 2167 const struct intel_cdclk_state *cdclk_state; 2168 2169 cdclk_state = intel_atomic_get_cdclk_state(state); 2170 if (IS_ERR(cdclk_state)) { 2171 drm_WARN_ON(display->drm, PTR_ERR(cdclk_state)); 2172 return 1; 2173 } 2174 2175 return min(1, DIV_ROUND_UP(crtc_state->pixel_rate, 2176 2 * intel_cdclk_logical(cdclk_state))); 2177 } 2178 2179 static int 2180 dsc_prefill_latency(const struct intel_crtc_state *crtc_state) 2181 { 2182 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2183 const struct intel_crtc_scaler_state *scaler_state = 2184 &crtc_state->scaler_state; 2185 int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, 2186 crtc_state->hw.adjusted_mode.clock); 2187 int num_scaler_users = hweight32(scaler_state->scaler_users); 2188 int chroma_downscaling_factor = 2189 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; 2190 u32 dsc_prefill_latency = 0; 2191 2192 if (!crtc_state->dsc.compression_enable || 2193 !num_scaler_users || 2194 num_scaler_users > crtc->num_scalers) 2195 return dsc_prefill_latency; 2196 2197 dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10); 2198 2199 for (int i = 0; i < num_scaler_users; i++) { 2200 u64 hscale_k, vscale_k; 2201 2202 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16); 2203 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16); 2204 dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k, 2205 1000000); 2206 } 2207 2208 dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state); 2209 2210 return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency); 2211 } 2212 2213 static int 2214 scaler_prefill_latency(const struct intel_crtc_state *crtc_state) 2215 { 2216 const struct intel_crtc_scaler_state *scaler_state = 2217 &crtc_state->scaler_state; 2218 int num_scaler_users = hweight32(scaler_state->scaler_users); 2219 int scaler_prefill_latency = 0; 2220 int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, 2221 crtc_state->hw.adjusted_mode.clock); 2222 2223 if (!num_scaler_users) 2224 return scaler_prefill_latency; 2225 2226 scaler_prefill_latency = 4 * linetime; 2227 2228 if (num_scaler_users > 1) { 2229 u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16); 2230 u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16); 2231 int chroma_downscaling_factor = 2232 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; 2233 int latency; 2234 2235 latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k * 2236 chroma_downscaling_factor), 1000000); 2237 scaler_prefill_latency += latency; 2238 } 2239 2240 scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state); 2241 2242 return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency); 2243 } 2244 2245 static bool 2246 skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, 2247 int wm0_lines, int latency) 2248 { 2249 const struct drm_display_mode *adjusted_mode = 2250 &crtc_state->hw.adjusted_mode; 2251 2252 return crtc_state->framestart_delay + 2253 intel_usecs_to_scanlines(adjusted_mode, latency) + 2254 scaler_prefill_latency(crtc_state) + 2255 dsc_prefill_latency(crtc_state) + 2256 wm0_lines > 2257 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start; 2258 } 2259 2260 static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state) 2261 { 2262 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2263 enum plane_id plane_id; 2264 int wm0_lines = 0; 2265 2266 for_each_plane_id_on_crtc(crtc, plane_id) { 2267 const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; 2268 2269 /* FIXME what about !skl_wm_has_lines() platforms? */ 2270 wm0_lines = max_t(int, wm0_lines, wm->wm[0].lines); 2271 } 2272 2273 return wm0_lines; 2274 } 2275 2276 static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state, 2277 int wm0_lines) 2278 { 2279 struct intel_display *display = to_intel_display(crtc_state); 2280 int level; 2281 2282 for (level = display->wm.num_levels - 1; level >= 0; level--) { 2283 int latency; 2284 2285 /* FIXME should we care about the latency w/a's? */ 2286 latency = skl_wm_latency(display, level, NULL); 2287 if (latency == 0) 2288 continue; 2289 2290 /* FIXME is it correct to use 0 latency for wm0 here? */ 2291 if (level == 0) 2292 latency = 0; 2293 2294 if (!skl_is_vblank_too_short(crtc_state, wm0_lines, latency)) 2295 return level; 2296 } 2297 2298 return -EINVAL; 2299 } 2300 2301 static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state) 2302 { 2303 struct intel_display *display = to_intel_display(crtc_state); 2304 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2305 int wm0_lines, level; 2306 2307 if (!crtc_state->hw.active) 2308 return 0; 2309 2310 wm0_lines = skl_max_wm0_lines(crtc_state); 2311 2312 level = skl_max_wm_level_for_vblank(crtc_state, wm0_lines); 2313 if (level < 0) 2314 return level; 2315 2316 /* 2317 * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_* 2318 * based on whether we're limited by the vblank duration. 2319 */ 2320 crtc_state->wm_level_disabled = level < display->wm.num_levels - 1; 2321 2322 for (level++; level < display->wm.num_levels; level++) { 2323 enum plane_id plane_id; 2324 2325 for_each_plane_id_on_crtc(crtc, plane_id) { 2326 struct skl_plane_wm *wm = 2327 &crtc_state->wm.skl.optimal.planes[plane_id]; 2328 2329 /* 2330 * FIXME just clear enable or flag the entire 2331 * thing as bad via min_ddb_alloc=U16_MAX? 2332 */ 2333 wm->wm[level].enable = false; 2334 wm->uv_wm[level].enable = false; 2335 } 2336 } 2337 2338 if (DISPLAY_VER(display) >= 12 && 2339 display->sagv.block_time_us && 2340 skl_is_vblank_too_short(crtc_state, wm0_lines, 2341 display->sagv.block_time_us)) { 2342 enum plane_id plane_id; 2343 2344 for_each_plane_id_on_crtc(crtc, plane_id) { 2345 struct skl_plane_wm *wm = 2346 &crtc_state->wm.skl.optimal.planes[plane_id]; 2347 2348 wm->sagv.wm0.enable = false; 2349 wm->sagv.trans_wm.enable = false; 2350 } 2351 } 2352 2353 return 0; 2354 } 2355 2356 static int skl_build_pipe_wm(struct intel_atomic_state *state, 2357 struct intel_crtc *crtc) 2358 { 2359 struct intel_display *display = to_intel_display(crtc); 2360 struct intel_crtc_state *crtc_state = 2361 intel_atomic_get_new_crtc_state(state, crtc); 2362 const struct intel_plane_state *plane_state; 2363 struct intel_plane *plane; 2364 int ret, i; 2365 2366 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 2367 /* 2368 * FIXME should perhaps check {old,new}_plane_crtc->hw.crtc 2369 * instead but we don't populate that correctly for NV12 Y 2370 * planes so for now hack this. 2371 */ 2372 if (plane->pipe != crtc->pipe) 2373 continue; 2374 2375 if (DISPLAY_VER(display) >= 11) 2376 ret = icl_build_plane_wm(crtc_state, plane_state); 2377 else 2378 ret = skl_build_plane_wm(crtc_state, plane_state); 2379 if (ret) 2380 return ret; 2381 } 2382 2383 crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw; 2384 2385 return skl_wm_check_vblank(crtc_state); 2386 } 2387 2388 static bool skl_wm_level_equals(const struct skl_wm_level *l1, 2389 const struct skl_wm_level *l2) 2390 { 2391 return l1->enable == l2->enable && 2392 l1->ignore_lines == l2->ignore_lines && 2393 l1->lines == l2->lines && 2394 l1->blocks == l2->blocks && 2395 l1->auto_min_alloc_wm_enable == l2->auto_min_alloc_wm_enable; 2396 } 2397 2398 static bool skl_plane_wm_equals(struct intel_display *display, 2399 const struct skl_plane_wm *wm1, 2400 const struct skl_plane_wm *wm2) 2401 { 2402 int level; 2403 2404 for (level = 0; level < display->wm.num_levels; level++) { 2405 /* 2406 * We don't check uv_wm as the hardware doesn't actually 2407 * use it. It only gets used for calculating the required 2408 * ddb allocation. 2409 */ 2410 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level])) 2411 return false; 2412 } 2413 2414 return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) && 2415 skl_wm_level_equals(&wm1->sagv.wm0, &wm2->sagv.wm0) && 2416 skl_wm_level_equals(&wm1->sagv.trans_wm, &wm2->sagv.trans_wm); 2417 } 2418 2419 static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, 2420 const struct skl_ddb_entry *b) 2421 { 2422 return a->start < b->end && b->start < a->end; 2423 } 2424 2425 static void skl_ddb_entry_union(struct skl_ddb_entry *a, 2426 const struct skl_ddb_entry *b) 2427 { 2428 if (a->end && b->end) { 2429 a->start = min(a->start, b->start); 2430 a->end = max(a->end, b->end); 2431 } else if (b->end) { 2432 a->start = b->start; 2433 a->end = b->end; 2434 } 2435 } 2436 2437 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, 2438 const struct skl_ddb_entry *entries, 2439 int num_entries, int ignore_idx) 2440 { 2441 int i; 2442 2443 for (i = 0; i < num_entries; i++) { 2444 if (i != ignore_idx && 2445 skl_ddb_entries_overlap(ddb, &entries[i])) 2446 return true; 2447 } 2448 2449 return false; 2450 } 2451 2452 static int 2453 skl_ddb_add_affected_planes(struct intel_atomic_state *state, 2454 struct intel_crtc *crtc) 2455 { 2456 struct intel_display *display = to_intel_display(state); 2457 const struct intel_crtc_state *old_crtc_state = 2458 intel_atomic_get_old_crtc_state(state, crtc); 2459 struct intel_crtc_state *new_crtc_state = 2460 intel_atomic_get_new_crtc_state(state, crtc); 2461 struct intel_plane *plane; 2462 2463 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 2464 struct intel_plane_state *plane_state; 2465 enum plane_id plane_id = plane->id; 2466 2467 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id], 2468 &new_crtc_state->wm.skl.plane_ddb[plane_id]) && 2469 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id], 2470 &new_crtc_state->wm.skl.plane_ddb_y[plane_id])) 2471 continue; 2472 2473 if (new_crtc_state->do_async_flip) { 2474 drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change DDB during async flip\n", 2475 plane->base.base.id, plane->base.name); 2476 return -EINVAL; 2477 } 2478 2479 plane_state = intel_atomic_get_plane_state(state, plane); 2480 if (IS_ERR(plane_state)) 2481 return PTR_ERR(plane_state); 2482 2483 new_crtc_state->update_planes |= BIT(plane_id); 2484 new_crtc_state->async_flip_planes = 0; 2485 new_crtc_state->do_async_flip = false; 2486 } 2487 2488 return 0; 2489 } 2490 2491 static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state) 2492 { 2493 struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev); 2494 u8 enabled_slices; 2495 enum pipe pipe; 2496 2497 /* 2498 * FIXME: For now we always enable slice S1 as per 2499 * the Bspec display initialization sequence. 2500 */ 2501 enabled_slices = BIT(DBUF_S1); 2502 2503 for_each_pipe(display, pipe) 2504 enabled_slices |= dbuf_state->slices[pipe]; 2505 2506 return enabled_slices; 2507 } 2508 2509 static int 2510 skl_compute_ddb(struct intel_atomic_state *state) 2511 { 2512 struct intel_display *display = to_intel_display(state); 2513 const struct intel_dbuf_state *old_dbuf_state; 2514 struct intel_dbuf_state *new_dbuf_state = NULL; 2515 struct intel_crtc_state *new_crtc_state; 2516 struct intel_crtc *crtc; 2517 int ret, i; 2518 2519 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2520 new_dbuf_state = intel_atomic_get_dbuf_state(state); 2521 if (IS_ERR(new_dbuf_state)) 2522 return PTR_ERR(new_dbuf_state); 2523 2524 old_dbuf_state = intel_atomic_get_old_dbuf_state(state); 2525 break; 2526 } 2527 2528 if (!new_dbuf_state) 2529 return 0; 2530 2531 new_dbuf_state->active_pipes = 2532 intel_calc_active_pipes(state, old_dbuf_state->active_pipes); 2533 2534 if (old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) { 2535 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 2536 if (ret) 2537 return ret; 2538 } 2539 2540 if (HAS_MBUS_JOINING(display)) { 2541 new_dbuf_state->joined_mbus = 2542 adlp_check_mbus_joined(new_dbuf_state->active_pipes); 2543 2544 if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) { 2545 ret = intel_cdclk_state_set_joined_mbus(state, new_dbuf_state->joined_mbus); 2546 if (ret) 2547 return ret; 2548 } 2549 } 2550 2551 for_each_intel_crtc(display->drm, crtc) { 2552 enum pipe pipe = crtc->pipe; 2553 2554 new_dbuf_state->slices[pipe] = 2555 skl_compute_dbuf_slices(crtc, new_dbuf_state->active_pipes, 2556 new_dbuf_state->joined_mbus); 2557 2558 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe]) 2559 continue; 2560 2561 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 2562 if (ret) 2563 return ret; 2564 } 2565 2566 new_dbuf_state->enabled_slices = intel_dbuf_enabled_slices(new_dbuf_state); 2567 2568 if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices || 2569 old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) { 2570 ret = intel_atomic_serialize_global_state(&new_dbuf_state->base); 2571 if (ret) 2572 return ret; 2573 2574 drm_dbg_kms(display->drm, 2575 "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n", 2576 old_dbuf_state->enabled_slices, 2577 new_dbuf_state->enabled_slices, 2578 DISPLAY_INFO(display)->dbuf.slice_mask, 2579 str_yes_no(old_dbuf_state->joined_mbus), 2580 str_yes_no(new_dbuf_state->joined_mbus)); 2581 } 2582 2583 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2584 enum pipe pipe = crtc->pipe; 2585 2586 new_dbuf_state->weight[pipe] = intel_crtc_ddb_weight(new_crtc_state); 2587 2588 if (old_dbuf_state->weight[pipe] == new_dbuf_state->weight[pipe]) 2589 continue; 2590 2591 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 2592 if (ret) 2593 return ret; 2594 } 2595 2596 for_each_intel_crtc(display->drm, crtc) { 2597 ret = skl_crtc_allocate_ddb(state, crtc); 2598 if (ret) 2599 return ret; 2600 } 2601 2602 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2603 ret = skl_crtc_allocate_plane_ddb(state, crtc); 2604 if (ret) 2605 return ret; 2606 2607 ret = skl_ddb_add_affected_planes(state, crtc); 2608 if (ret) 2609 return ret; 2610 } 2611 2612 return 0; 2613 } 2614 2615 static char enast(bool enable) 2616 { 2617 return enable ? '*' : ' '; 2618 } 2619 2620 static noinline_for_stack void 2621 skl_print_plane_changes(struct intel_display *display, 2622 struct intel_plane *plane, 2623 const struct skl_plane_wm *old_wm, 2624 const struct skl_plane_wm *new_wm) 2625 { 2626 drm_dbg_kms(display->drm, 2627 "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm" 2628 " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n", 2629 plane->base.base.id, plane->base.name, 2630 enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable), 2631 enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable), 2632 enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable), 2633 enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable), 2634 enast(old_wm->trans_wm.enable), 2635 enast(old_wm->sagv.wm0.enable), 2636 enast(old_wm->sagv.trans_wm.enable), 2637 enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable), 2638 enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable), 2639 enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable), 2640 enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable), 2641 enast(new_wm->trans_wm.enable), 2642 enast(new_wm->sagv.wm0.enable), 2643 enast(new_wm->sagv.trans_wm.enable)); 2644 2645 drm_dbg_kms(display->drm, 2646 "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d" 2647 " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n", 2648 plane->base.base.id, plane->base.name, 2649 enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines, 2650 enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines, 2651 enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines, 2652 enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines, 2653 enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines, 2654 enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines, 2655 enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines, 2656 enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines, 2657 enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines, 2658 enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines, 2659 enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines, 2660 enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines, 2661 enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines, 2662 enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines, 2663 enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines, 2664 enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines, 2665 enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines, 2666 enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines, 2667 enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines, 2668 enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines, 2669 enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines, 2670 enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines); 2671 2672 drm_dbg_kms(display->drm, 2673 "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" 2674 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", 2675 plane->base.base.id, plane->base.name, 2676 old_wm->wm[0].blocks, old_wm->wm[1].blocks, 2677 old_wm->wm[2].blocks, old_wm->wm[3].blocks, 2678 old_wm->wm[4].blocks, old_wm->wm[5].blocks, 2679 old_wm->wm[6].blocks, old_wm->wm[7].blocks, 2680 old_wm->trans_wm.blocks, 2681 old_wm->sagv.wm0.blocks, 2682 old_wm->sagv.trans_wm.blocks, 2683 new_wm->wm[0].blocks, new_wm->wm[1].blocks, 2684 new_wm->wm[2].blocks, new_wm->wm[3].blocks, 2685 new_wm->wm[4].blocks, new_wm->wm[5].blocks, 2686 new_wm->wm[6].blocks, new_wm->wm[7].blocks, 2687 new_wm->trans_wm.blocks, 2688 new_wm->sagv.wm0.blocks, 2689 new_wm->sagv.trans_wm.blocks); 2690 2691 drm_dbg_kms(display->drm, 2692 "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" 2693 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", 2694 plane->base.base.id, plane->base.name, 2695 old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc, 2696 old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc, 2697 old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc, 2698 old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc, 2699 old_wm->trans_wm.min_ddb_alloc, 2700 old_wm->sagv.wm0.min_ddb_alloc, 2701 old_wm->sagv.trans_wm.min_ddb_alloc, 2702 new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc, 2703 new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc, 2704 new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc, 2705 new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc, 2706 new_wm->trans_wm.min_ddb_alloc, 2707 new_wm->sagv.wm0.min_ddb_alloc, 2708 new_wm->sagv.trans_wm.min_ddb_alloc); 2709 } 2710 2711 static void 2712 skl_print_wm_changes(struct intel_atomic_state *state) 2713 { 2714 struct intel_display *display = to_intel_display(state); 2715 const struct intel_crtc_state *old_crtc_state; 2716 const struct intel_crtc_state *new_crtc_state; 2717 struct intel_plane *plane; 2718 struct intel_crtc *crtc; 2719 int i; 2720 2721 if (!drm_debug_enabled(DRM_UT_KMS)) 2722 return; 2723 2724 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 2725 new_crtc_state, i) { 2726 const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm; 2727 2728 old_pipe_wm = &old_crtc_state->wm.skl.optimal; 2729 new_pipe_wm = &new_crtc_state->wm.skl.optimal; 2730 2731 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 2732 enum plane_id plane_id = plane->id; 2733 const struct skl_ddb_entry *old, *new; 2734 2735 old = &old_crtc_state->wm.skl.plane_ddb[plane_id]; 2736 new = &new_crtc_state->wm.skl.plane_ddb[plane_id]; 2737 2738 if (skl_ddb_entry_equal(old, new)) 2739 continue; 2740 drm_dbg_kms(display->drm, 2741 "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n", 2742 plane->base.base.id, plane->base.name, 2743 old->start, old->end, new->start, new->end, 2744 skl_ddb_entry_size(old), skl_ddb_entry_size(new)); 2745 } 2746 2747 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 2748 enum plane_id plane_id = plane->id; 2749 const struct skl_plane_wm *old_wm, *new_wm; 2750 2751 old_wm = &old_pipe_wm->planes[plane_id]; 2752 new_wm = &new_pipe_wm->planes[plane_id]; 2753 2754 if (skl_plane_wm_equals(display, old_wm, new_wm)) 2755 continue; 2756 2757 skl_print_plane_changes(display, plane, old_wm, new_wm); 2758 } 2759 } 2760 } 2761 2762 static bool skl_plane_selected_wm_equals(struct intel_plane *plane, 2763 const struct skl_pipe_wm *old_pipe_wm, 2764 const struct skl_pipe_wm *new_pipe_wm) 2765 { 2766 struct intel_display *display = to_intel_display(plane); 2767 int level; 2768 2769 for (level = 0; level < display->wm.num_levels; level++) { 2770 /* 2771 * We don't check uv_wm as the hardware doesn't actually 2772 * use it. It only gets used for calculating the required 2773 * ddb allocation. 2774 */ 2775 if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level), 2776 skl_plane_wm_level(new_pipe_wm, plane->id, level))) 2777 return false; 2778 } 2779 2780 if (HAS_HW_SAGV_WM(display)) { 2781 const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id]; 2782 const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id]; 2783 2784 if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) || 2785 !skl_wm_level_equals(&old_wm->sagv.trans_wm, &new_wm->sagv.trans_wm)) 2786 return false; 2787 } 2788 2789 return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id), 2790 skl_plane_trans_wm(new_pipe_wm, plane->id)); 2791 } 2792 2793 /* 2794 * To make sure the cursor watermark registers are always consistent 2795 * with our computed state the following scenario needs special 2796 * treatment: 2797 * 2798 * 1. enable cursor 2799 * 2. move cursor entirely offscreen 2800 * 3. disable cursor 2801 * 2802 * Step 2. does call .disable_plane() but does not zero the watermarks 2803 * (since we consider an offscreen cursor still active for the purposes 2804 * of watermarks). Step 3. would not normally call .disable_plane() 2805 * because the actual plane visibility isn't changing, and we don't 2806 * deallocate the cursor ddb until the pipe gets disabled. So we must 2807 * force step 3. to call .disable_plane() to update the watermark 2808 * registers properly. 2809 * 2810 * Other planes do not suffer from this issues as their watermarks are 2811 * calculated based on the actual plane visibility. The only time this 2812 * can trigger for the other planes is during the initial readout as the 2813 * default value of the watermarks registers is not zero. 2814 */ 2815 static int skl_wm_add_affected_planes(struct intel_atomic_state *state, 2816 struct intel_crtc *crtc) 2817 { 2818 struct intel_display *display = to_intel_display(state); 2819 const struct intel_crtc_state *old_crtc_state = 2820 intel_atomic_get_old_crtc_state(state, crtc); 2821 struct intel_crtc_state *new_crtc_state = 2822 intel_atomic_get_new_crtc_state(state, crtc); 2823 struct intel_plane *plane; 2824 2825 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 2826 struct intel_plane_state *plane_state; 2827 enum plane_id plane_id = plane->id; 2828 2829 /* 2830 * Force a full wm update for every plane on modeset. 2831 * Required because the reset value of the wm registers 2832 * is non-zero, whereas we want all disabled planes to 2833 * have zero watermarks. So if we turn off the relevant 2834 * power well the hardware state will go out of sync 2835 * with the software state. 2836 */ 2837 if (!intel_crtc_needs_modeset(new_crtc_state) && 2838 skl_plane_selected_wm_equals(plane, 2839 &old_crtc_state->wm.skl.optimal, 2840 &new_crtc_state->wm.skl.optimal)) 2841 continue; 2842 2843 if (new_crtc_state->do_async_flip) { 2844 drm_dbg_kms(display->drm, "[PLANE:%d:%s] Can't change watermarks during async flip\n", 2845 plane->base.base.id, plane->base.name); 2846 return -EINVAL; 2847 } 2848 2849 plane_state = intel_atomic_get_plane_state(state, plane); 2850 if (IS_ERR(plane_state)) 2851 return PTR_ERR(plane_state); 2852 2853 new_crtc_state->update_planes |= BIT(plane_id); 2854 new_crtc_state->async_flip_planes = 0; 2855 new_crtc_state->do_async_flip = false; 2856 } 2857 2858 return 0; 2859 } 2860 2861 static int pkgc_max_linetime(struct intel_atomic_state *state) 2862 { 2863 struct intel_display *display = to_intel_display(state); 2864 const struct intel_crtc_state *crtc_state; 2865 struct intel_crtc *crtc; 2866 int i, max_linetime; 2867 2868 /* 2869 * Apparenty the hardware uses WM_LINETIME internally for 2870 * this stuff, compute everything based on that. 2871 */ 2872 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2873 display->pkgc.disable[crtc->pipe] = crtc_state->vrr.enable; 2874 display->pkgc.linetime[crtc->pipe] = DIV_ROUND_UP(crtc_state->linetime, 8); 2875 } 2876 2877 max_linetime = 0; 2878 for_each_intel_crtc(display->drm, crtc) { 2879 if (display->pkgc.disable[crtc->pipe]) 2880 return 0; 2881 2882 max_linetime = max(display->pkgc.linetime[crtc->pipe], max_linetime); 2883 } 2884 2885 return max_linetime; 2886 } 2887 2888 void 2889 intel_program_dpkgc_latency(struct intel_atomic_state *state) 2890 { 2891 struct intel_display *display = to_intel_display(state); 2892 int max_linetime, latency, added_wake_time = 0; 2893 2894 if (DISPLAY_VER(display) < 20) 2895 return; 2896 2897 mutex_lock(&display->wm.wm_mutex); 2898 2899 latency = skl_watermark_max_latency(display, 1); 2900 2901 /* FIXME runtime changes to enable_flipq are racy */ 2902 if (display->params.enable_flipq) 2903 added_wake_time = intel_flipq_exec_time_us(display); 2904 2905 /* 2906 * Wa_22020432604 2907 * "PKG_C_LATENCY Added Wake Time field is not working" 2908 */ 2909 if (latency && IS_DISPLAY_VER(display, 20, 30)) { 2910 latency += added_wake_time; 2911 added_wake_time = 0; 2912 } 2913 2914 max_linetime = pkgc_max_linetime(state); 2915 2916 if (max_linetime == 0 || latency == 0) { 2917 latency = REG_FIELD_GET(LNL_PKG_C_LATENCY_MASK, 2918 LNL_PKG_C_LATENCY_MASK); 2919 added_wake_time = 0; 2920 } else { 2921 /* 2922 * Wa_22020299601 2923 * "Increase the latency programmed in PKG_C_LATENCY Pkg C Latency to be a 2924 * multiple of the pipeline time from WM_LINETIME" 2925 */ 2926 latency = roundup(latency, max_linetime); 2927 } 2928 2929 intel_de_write(display, LNL_PKG_C_LATENCY, 2930 REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time) | 2931 REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, latency)); 2932 2933 mutex_unlock(&display->wm.wm_mutex); 2934 } 2935 2936 static int 2937 skl_compute_wm(struct intel_atomic_state *state) 2938 { 2939 struct intel_display *display = to_intel_display(state); 2940 struct intel_crtc *crtc; 2941 struct intel_crtc_state __maybe_unused *new_crtc_state; 2942 int ret, i; 2943 2944 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2945 ret = skl_build_pipe_wm(state, crtc); 2946 if (ret) 2947 return ret; 2948 } 2949 2950 ret = skl_compute_ddb(state); 2951 if (ret) 2952 return ret; 2953 2954 /* 2955 * skl_compute_ddb() will have adjusted the final watermarks 2956 * based on how much ddb is available. Now we can actually 2957 * check if the final watermarks changed. 2958 */ 2959 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2960 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal; 2961 2962 /* 2963 * We store use_sagv_wm in the crtc state rather than relying on 2964 * that bw state since we have no convenient way to get at the 2965 * latter from the plane commit hooks (especially in the legacy 2966 * cursor case). 2967 * 2968 * drm_atomic_check_only() gets upset if we pull more crtcs 2969 * into the state, so we have to calculate this based on the 2970 * individual intel_crtc_can_enable_sagv() rather than 2971 * the overall intel_bw_can_enable_sagv(). Otherwise the 2972 * crtcs not included in the commit would not switch to the 2973 * SAGV watermarks when we are about to enable SAGV, and that 2974 * would lead to underruns. This does mean extra power draw 2975 * when only a subset of the crtcs are blocking SAGV as the 2976 * other crtcs can't be allowed to use the more optimal 2977 * normal (ie. non-SAGV) watermarks. 2978 */ 2979 pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(display) && 2980 DISPLAY_VER(display) >= 12 && 2981 intel_crtc_can_enable_sagv(new_crtc_state); 2982 2983 ret = skl_wm_add_affected_planes(state, crtc); 2984 if (ret) 2985 return ret; 2986 } 2987 2988 skl_print_wm_changes(state); 2989 2990 return 0; 2991 } 2992 2993 static void skl_wm_level_from_reg_val(struct intel_display *display, 2994 u32 val, struct skl_wm_level *level) 2995 { 2996 level->enable = val & PLANE_WM_EN; 2997 level->ignore_lines = val & PLANE_WM_IGNORE_LINES; 2998 level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val); 2999 level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); 3000 level->auto_min_alloc_wm_enable = DISPLAY_VER(display) >= 30 ? 3001 val & PLANE_WM_AUTO_MIN_ALLOC_EN : 0; 3002 } 3003 3004 static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, 3005 struct skl_pipe_wm *out) 3006 { 3007 struct intel_display *display = to_intel_display(crtc); 3008 enum pipe pipe = crtc->pipe; 3009 enum plane_id plane_id; 3010 int level; 3011 u32 val; 3012 3013 for_each_plane_id_on_crtc(crtc, plane_id) { 3014 struct skl_plane_wm *wm = &out->planes[plane_id]; 3015 3016 for (level = 0; level < display->wm.num_levels; level++) { 3017 if (plane_id != PLANE_CURSOR) 3018 val = intel_de_read(display, PLANE_WM(pipe, plane_id, level)); 3019 else 3020 val = intel_de_read(display, CUR_WM(pipe, level)); 3021 3022 skl_wm_level_from_reg_val(display, val, &wm->wm[level]); 3023 } 3024 3025 if (plane_id != PLANE_CURSOR) 3026 val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id)); 3027 else 3028 val = intel_de_read(display, CUR_WM_TRANS(pipe)); 3029 3030 skl_wm_level_from_reg_val(display, val, &wm->trans_wm); 3031 3032 if (HAS_HW_SAGV_WM(display)) { 3033 if (plane_id != PLANE_CURSOR) 3034 val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id)); 3035 else 3036 val = intel_de_read(display, CUR_WM_SAGV(pipe)); 3037 3038 skl_wm_level_from_reg_val(display, val, &wm->sagv.wm0); 3039 3040 if (plane_id != PLANE_CURSOR) 3041 val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id)); 3042 else 3043 val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe)); 3044 3045 skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm); 3046 } else if (DISPLAY_VER(display) >= 12) { 3047 wm->sagv.wm0 = wm->wm[0]; 3048 wm->sagv.trans_wm = wm->trans_wm; 3049 } 3050 } 3051 } 3052 3053 static void skl_wm_get_hw_state(struct intel_display *display) 3054 { 3055 struct intel_dbuf_state *dbuf_state = 3056 to_intel_dbuf_state(display->dbuf.obj.state); 3057 struct intel_crtc *crtc; 3058 3059 if (HAS_MBUS_JOINING(display)) 3060 dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 3061 3062 dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw); 3063 dbuf_state->active_pipes = 0; 3064 3065 for_each_intel_crtc(display->drm, crtc) { 3066 struct intel_crtc_state *crtc_state = 3067 to_intel_crtc_state(crtc->base.state); 3068 enum pipe pipe = crtc->pipe; 3069 unsigned int mbus_offset; 3070 enum plane_id plane_id; 3071 u8 slices; 3072 3073 memset(&crtc_state->wm.skl.optimal, 0, 3074 sizeof(crtc_state->wm.skl.optimal)); 3075 if (crtc_state->hw.active) { 3076 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); 3077 dbuf_state->active_pipes |= BIT(pipe); 3078 } 3079 crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal; 3080 3081 memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe])); 3082 3083 for_each_plane_id_on_crtc(crtc, plane_id) { 3084 struct skl_ddb_entry *ddb = 3085 &crtc_state->wm.skl.plane_ddb[plane_id]; 3086 struct skl_ddb_entry *ddb_y = 3087 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 3088 u16 *min_ddb = 3089 &crtc_state->wm.skl.plane_min_ddb[plane_id]; 3090 u16 *interim_ddb = 3091 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; 3092 3093 if (!crtc_state->hw.active) 3094 continue; 3095 3096 skl_ddb_get_hw_plane_state(display, crtc->pipe, 3097 plane_id, ddb, ddb_y, 3098 min_ddb, interim_ddb); 3099 3100 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb); 3101 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y); 3102 } 3103 3104 dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state); 3105 3106 /* 3107 * Used for checking overlaps, so we need absolute 3108 * offsets instead of MBUS relative offsets. 3109 */ 3110 slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, 3111 dbuf_state->joined_mbus); 3112 mbus_offset = mbus_ddb_offset(display, slices); 3113 crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start; 3114 crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end; 3115 3116 /* The slices actually used by the planes on the pipe */ 3117 dbuf_state->slices[pipe] = 3118 skl_ddb_dbuf_slice_mask(display, &crtc_state->wm.skl.ddb); 3119 3120 drm_dbg_kms(display->drm, 3121 "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n", 3122 crtc->base.base.id, crtc->base.name, 3123 dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start, 3124 dbuf_state->ddb[pipe].end, dbuf_state->active_pipes, 3125 str_yes_no(dbuf_state->joined_mbus)); 3126 } 3127 3128 dbuf_state->enabled_slices = display->dbuf.enabled_slices; 3129 } 3130 3131 bool skl_watermark_ipc_enabled(struct intel_display *display) 3132 { 3133 return display->wm.ipc_enabled; 3134 } 3135 3136 void skl_watermark_ipc_update(struct intel_display *display) 3137 { 3138 if (!HAS_IPC(display)) 3139 return; 3140 3141 intel_de_rmw(display, DISP_ARB_CTL2, DISP_IPC_ENABLE, 3142 skl_watermark_ipc_enabled(display) ? DISP_IPC_ENABLE : 0); 3143 } 3144 3145 static bool skl_watermark_ipc_can_enable(struct intel_display *display) 3146 { 3147 /* Display WA #0477 WaDisableIPC: skl */ 3148 if (display->platform.skylake) 3149 return false; 3150 3151 /* Display WA #1141: SKL:all KBL:all CFL */ 3152 if (display->platform.kabylake || 3153 display->platform.coffeelake || 3154 display->platform.cometlake) { 3155 const struct dram_info *dram_info = intel_dram_info(display->drm); 3156 3157 return dram_info->symmetric_memory; 3158 } 3159 3160 return true; 3161 } 3162 3163 void skl_watermark_ipc_init(struct intel_display *display) 3164 { 3165 if (!HAS_IPC(display)) 3166 return; 3167 3168 display->wm.ipc_enabled = skl_watermark_ipc_can_enable(display); 3169 3170 skl_watermark_ipc_update(display); 3171 } 3172 3173 static void 3174 adjust_wm_latency(struct intel_display *display, 3175 u16 wm[], int num_levels, int read_latency) 3176 { 3177 const struct dram_info *dram_info = intel_dram_info(display->drm); 3178 int i, level; 3179 3180 /* 3181 * If a level n (n > 1) has a 0us latency, all levels m (m >= n) 3182 * need to be disabled. We make sure to sanitize the values out 3183 * of the punit to satisfy this requirement. 3184 */ 3185 for (level = 1; level < num_levels; level++) { 3186 if (wm[level] == 0) { 3187 for (i = level + 1; i < num_levels; i++) 3188 wm[i] = 0; 3189 3190 num_levels = level; 3191 break; 3192 } 3193 } 3194 3195 /* 3196 * WaWmMemoryReadLatency 3197 * 3198 * punit doesn't take into account the read latency so we need 3199 * to add proper adjustment to each valid level we retrieve 3200 * from the punit when level 0 response data is 0us. 3201 */ 3202 if (wm[0] == 0) { 3203 for (level = 0; level < num_levels; level++) 3204 wm[level] += read_latency; 3205 } 3206 3207 /* 3208 * WA Level-0 adjustment for 16GB DIMMs: SKL+ 3209 * If we could not get dimm info enable this WA to prevent from 3210 * any underrun. If not able to get Dimm info assume 16GB dimm 3211 * to avoid any underrun. 3212 */ 3213 if (!display->platform.dg2 && dram_info->wm_lv_0_adjust_needed) 3214 wm[0] += 1; 3215 } 3216 3217 static void mtl_read_wm_latency(struct intel_display *display, u16 wm[]) 3218 { 3219 int num_levels = display->wm.num_levels; 3220 u32 val; 3221 3222 val = intel_de_read(display, MTL_LATENCY_LP0_LP1); 3223 wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); 3224 wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); 3225 3226 val = intel_de_read(display, MTL_LATENCY_LP2_LP3); 3227 wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); 3228 wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); 3229 3230 val = intel_de_read(display, MTL_LATENCY_LP4_LP5); 3231 wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); 3232 wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); 3233 3234 adjust_wm_latency(display, wm, num_levels, 6); 3235 } 3236 3237 static void skl_read_wm_latency(struct intel_display *display, u16 wm[]) 3238 { 3239 int num_levels = display->wm.num_levels; 3240 int read_latency = DISPLAY_VER(display) >= 12 ? 3 : 2; 3241 int mult = display->platform.dg2 ? 2 : 1; 3242 u32 val; 3243 int ret; 3244 3245 /* read the first set of memory latencies[0:3] */ 3246 val = 0; /* data0 to be programmed to 0 for first set */ 3247 ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL); 3248 if (ret) { 3249 drm_err(display->drm, "SKL Mailbox read error = %d\n", ret); 3250 return; 3251 } 3252 3253 wm[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; 3254 wm[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; 3255 wm[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; 3256 wm[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; 3257 3258 /* read the second set of memory latencies[4:7] */ 3259 val = 1; /* data0 to be programmed to 1 for second set */ 3260 ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL); 3261 if (ret) { 3262 drm_err(display->drm, "SKL Mailbox read error = %d\n", ret); 3263 return; 3264 } 3265 3266 wm[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; 3267 wm[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; 3268 wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; 3269 wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; 3270 3271 adjust_wm_latency(display, wm, num_levels, read_latency); 3272 } 3273 3274 static void skl_setup_wm_latency(struct intel_display *display) 3275 { 3276 if (HAS_HW_SAGV_WM(display)) 3277 display->wm.num_levels = 6; 3278 else 3279 display->wm.num_levels = 8; 3280 3281 if (DISPLAY_VER(display) >= 14) 3282 mtl_read_wm_latency(display, display->wm.skl_latency); 3283 else 3284 skl_read_wm_latency(display, display->wm.skl_latency); 3285 3286 intel_print_wm_latency(display, "Gen9 Plane", display->wm.skl_latency); 3287 } 3288 3289 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj) 3290 { 3291 struct intel_dbuf_state *dbuf_state; 3292 3293 dbuf_state = kmemdup(obj->state, sizeof(*dbuf_state), GFP_KERNEL); 3294 if (!dbuf_state) 3295 return NULL; 3296 3297 return &dbuf_state->base; 3298 } 3299 3300 static void intel_dbuf_destroy_state(struct intel_global_obj *obj, 3301 struct intel_global_state *state) 3302 { 3303 kfree(state); 3304 } 3305 3306 static const struct intel_global_state_funcs intel_dbuf_funcs = { 3307 .atomic_duplicate_state = intel_dbuf_duplicate_state, 3308 .atomic_destroy_state = intel_dbuf_destroy_state, 3309 }; 3310 3311 struct intel_dbuf_state * 3312 intel_atomic_get_dbuf_state(struct intel_atomic_state *state) 3313 { 3314 struct intel_display *display = to_intel_display(state); 3315 struct intel_global_state *dbuf_state; 3316 3317 dbuf_state = intel_atomic_get_global_obj_state(state, &display->dbuf.obj); 3318 if (IS_ERR(dbuf_state)) 3319 return ERR_CAST(dbuf_state); 3320 3321 return to_intel_dbuf_state(dbuf_state); 3322 } 3323 3324 int intel_dbuf_init(struct intel_display *display) 3325 { 3326 struct intel_dbuf_state *dbuf_state; 3327 3328 dbuf_state = kzalloc(sizeof(*dbuf_state), GFP_KERNEL); 3329 if (!dbuf_state) 3330 return -ENOMEM; 3331 3332 intel_atomic_global_obj_init(display, &display->dbuf.obj, 3333 &dbuf_state->base, &intel_dbuf_funcs); 3334 3335 return 0; 3336 } 3337 3338 static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes) 3339 { 3340 switch (pipe) { 3341 case PIPE_A: 3342 case PIPE_D: 3343 active_pipes &= BIT(PIPE_A) | BIT(PIPE_D); 3344 break; 3345 case PIPE_B: 3346 case PIPE_C: 3347 active_pipes &= BIT(PIPE_B) | BIT(PIPE_C); 3348 break; 3349 default: /* to suppress compiler warning */ 3350 MISSING_CASE(pipe); 3351 return false; 3352 } 3353 3354 return is_power_of_2(active_pipes); 3355 } 3356 3357 static u32 pipe_mbus_dbox_ctl(const struct intel_crtc *crtc, 3358 const struct intel_dbuf_state *dbuf_state) 3359 { 3360 struct intel_display *display = to_intel_display(crtc); 3361 u32 val = 0; 3362 3363 if (DISPLAY_VER(display) >= 14) 3364 val |= MBUS_DBOX_I_CREDIT(2); 3365 3366 if (DISPLAY_VER(display) >= 12) { 3367 val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16); 3368 val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1); 3369 val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN; 3370 } 3371 3372 if (DISPLAY_VER(display) >= 14) 3373 val |= dbuf_state->joined_mbus ? 3374 MBUS_DBOX_A_CREDIT(12) : MBUS_DBOX_A_CREDIT(8); 3375 else if (display->platform.alderlake_p) 3376 /* Wa_22010947358:adl-p */ 3377 val |= dbuf_state->joined_mbus ? 3378 MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); 3379 else 3380 val |= MBUS_DBOX_A_CREDIT(2); 3381 3382 if (DISPLAY_VER(display) >= 14) { 3383 val |= MBUS_DBOX_B_CREDIT(0xA); 3384 } else if (display->platform.alderlake_p) { 3385 val |= MBUS_DBOX_BW_CREDIT(2); 3386 val |= MBUS_DBOX_B_CREDIT(8); 3387 } else if (DISPLAY_VER(display) >= 12) { 3388 val |= MBUS_DBOX_BW_CREDIT(2); 3389 val |= MBUS_DBOX_B_CREDIT(12); 3390 } else { 3391 val |= MBUS_DBOX_BW_CREDIT(1); 3392 val |= MBUS_DBOX_B_CREDIT(8); 3393 } 3394 3395 if (DISPLAY_VERx100(display) == 1400) { 3396 if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, dbuf_state->active_pipes)) 3397 val |= MBUS_DBOX_BW_8CREDITS_MTL; 3398 else 3399 val |= MBUS_DBOX_BW_4CREDITS_MTL; 3400 } 3401 3402 return val; 3403 } 3404 3405 static void pipe_mbus_dbox_ctl_update(struct intel_display *display, 3406 const struct intel_dbuf_state *dbuf_state) 3407 { 3408 struct intel_crtc *crtc; 3409 3410 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, dbuf_state->active_pipes) 3411 intel_de_write(display, PIPE_MBUS_DBOX_CTL(crtc->pipe), 3412 pipe_mbus_dbox_ctl(crtc, dbuf_state)); 3413 } 3414 3415 static void intel_mbus_dbox_update(struct intel_atomic_state *state) 3416 { 3417 struct intel_display *display = to_intel_display(state); 3418 const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; 3419 3420 if (DISPLAY_VER(display) < 11) 3421 return; 3422 3423 new_dbuf_state = intel_atomic_get_new_dbuf_state(state); 3424 old_dbuf_state = intel_atomic_get_old_dbuf_state(state); 3425 if (!new_dbuf_state || 3426 (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus && 3427 new_dbuf_state->active_pipes == old_dbuf_state->active_pipes)) 3428 return; 3429 3430 pipe_mbus_dbox_ctl_update(display, new_dbuf_state); 3431 } 3432 3433 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, 3434 int ratio) 3435 { 3436 struct intel_dbuf_state *dbuf_state; 3437 3438 dbuf_state = intel_atomic_get_dbuf_state(state); 3439 if (IS_ERR(dbuf_state)) 3440 return PTR_ERR(dbuf_state); 3441 3442 dbuf_state->mdclk_cdclk_ratio = ratio; 3443 3444 return intel_atomic_lock_global_state(&dbuf_state->base); 3445 } 3446 3447 void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display, 3448 int ratio, bool joined_mbus) 3449 { 3450 enum dbuf_slice slice; 3451 3452 if (!HAS_MBUS_JOINING(display)) 3453 return; 3454 3455 if (DISPLAY_VER(display) >= 20) 3456 intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK, 3457 MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1)); 3458 3459 if (joined_mbus) 3460 ratio *= 2; 3461 3462 drm_dbg_kms(display->drm, "Updating dbuf ratio to %d (mbus joined: %s)\n", 3463 ratio, str_yes_no(joined_mbus)); 3464 3465 for_each_dbuf_slice(display, slice) 3466 intel_de_rmw(display, DBUF_CTL_S(slice), 3467 DBUF_MIN_TRACKER_STATE_SERVICE_MASK, 3468 DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1)); 3469 } 3470 3471 static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state) 3472 { 3473 struct intel_display *display = to_intel_display(state); 3474 const struct intel_dbuf_state *old_dbuf_state = 3475 intel_atomic_get_old_dbuf_state(state); 3476 const struct intel_dbuf_state *new_dbuf_state = 3477 intel_atomic_get_new_dbuf_state(state); 3478 int mdclk_cdclk_ratio; 3479 3480 if (intel_cdclk_is_decreasing_later(state)) { 3481 /* cdclk/mdclk will be changed later by intel_set_cdclk_post_plane_update() */ 3482 mdclk_cdclk_ratio = old_dbuf_state->mdclk_cdclk_ratio; 3483 } else { 3484 /* cdclk/mdclk already changed by intel_set_cdclk_pre_plane_update() */ 3485 mdclk_cdclk_ratio = new_dbuf_state->mdclk_cdclk_ratio; 3486 } 3487 3488 intel_dbuf_mdclk_cdclk_ratio_update(display, mdclk_cdclk_ratio, 3489 new_dbuf_state->joined_mbus); 3490 } 3491 3492 static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state, 3493 const struct intel_dbuf_state *dbuf_state) 3494 { 3495 struct intel_display *display = to_intel_display(state); 3496 enum pipe pipe = ffs(dbuf_state->active_pipes) - 1; 3497 const struct intel_crtc_state *new_crtc_state; 3498 struct intel_crtc *crtc; 3499 3500 drm_WARN_ON(display->drm, !dbuf_state->joined_mbus); 3501 drm_WARN_ON(display->drm, !is_power_of_2(dbuf_state->active_pipes)); 3502 3503 crtc = intel_crtc_for_pipe(display, pipe); 3504 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 3505 3506 if (new_crtc_state && !intel_crtc_needs_modeset(new_crtc_state)) 3507 return pipe; 3508 else 3509 return INVALID_PIPE; 3510 } 3511 3512 static void mbus_ctl_join_update(struct intel_display *display, 3513 const struct intel_dbuf_state *dbuf_state, 3514 enum pipe pipe) 3515 { 3516 u32 mbus_ctl; 3517 3518 if (dbuf_state->joined_mbus) 3519 mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN; 3520 else 3521 mbus_ctl = MBUS_HASHING_MODE_2x2; 3522 3523 if (pipe != INVALID_PIPE) 3524 mbus_ctl |= MBUS_JOIN_PIPE_SELECT(pipe); 3525 else 3526 mbus_ctl |= MBUS_JOIN_PIPE_SELECT_NONE; 3527 3528 intel_de_rmw(display, MBUS_CTL, 3529 MBUS_HASHING_MODE_MASK | MBUS_JOIN | 3530 MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl); 3531 } 3532 3533 static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state, 3534 enum pipe pipe) 3535 { 3536 struct intel_display *display = to_intel_display(state); 3537 const struct intel_dbuf_state *old_dbuf_state = 3538 intel_atomic_get_old_dbuf_state(state); 3539 const struct intel_dbuf_state *new_dbuf_state = 3540 intel_atomic_get_new_dbuf_state(state); 3541 3542 drm_dbg_kms(display->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n", 3543 str_yes_no(old_dbuf_state->joined_mbus), 3544 str_yes_no(new_dbuf_state->joined_mbus), 3545 pipe != INVALID_PIPE ? pipe_name(pipe) : '*'); 3546 3547 mbus_ctl_join_update(display, new_dbuf_state, pipe); 3548 } 3549 3550 void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state) 3551 { 3552 const struct intel_dbuf_state *new_dbuf_state = 3553 intel_atomic_get_new_dbuf_state(state); 3554 const struct intel_dbuf_state *old_dbuf_state = 3555 intel_atomic_get_old_dbuf_state(state); 3556 3557 if (!new_dbuf_state) 3558 return; 3559 3560 if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) { 3561 enum pipe pipe = intel_mbus_joined_pipe(state, new_dbuf_state); 3562 3563 WARN_ON(!new_dbuf_state->base.changed); 3564 3565 intel_dbuf_mbus_join_update(state, pipe); 3566 intel_mbus_dbox_update(state); 3567 intel_dbuf_mdclk_min_tracker_update(state); 3568 } 3569 } 3570 3571 void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state) 3572 { 3573 struct intel_display *display = to_intel_display(state); 3574 const struct intel_dbuf_state *new_dbuf_state = 3575 intel_atomic_get_new_dbuf_state(state); 3576 const struct intel_dbuf_state *old_dbuf_state = 3577 intel_atomic_get_old_dbuf_state(state); 3578 3579 if (!new_dbuf_state) 3580 return; 3581 3582 if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) { 3583 enum pipe pipe = intel_mbus_joined_pipe(state, old_dbuf_state); 3584 3585 WARN_ON(!new_dbuf_state->base.changed); 3586 3587 intel_dbuf_mdclk_min_tracker_update(state); 3588 intel_mbus_dbox_update(state); 3589 intel_dbuf_mbus_join_update(state, pipe); 3590 3591 if (pipe != INVALID_PIPE) { 3592 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 3593 3594 intel_crtc_wait_for_next_vblank(crtc); 3595 } 3596 } else if (old_dbuf_state->joined_mbus == new_dbuf_state->joined_mbus && 3597 old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) { 3598 WARN_ON(!new_dbuf_state->base.changed); 3599 3600 intel_dbuf_mdclk_min_tracker_update(state); 3601 intel_mbus_dbox_update(state); 3602 } 3603 3604 } 3605 3606 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) 3607 { 3608 struct intel_display *display = to_intel_display(state); 3609 const struct intel_dbuf_state *new_dbuf_state = 3610 intel_atomic_get_new_dbuf_state(state); 3611 const struct intel_dbuf_state *old_dbuf_state = 3612 intel_atomic_get_old_dbuf_state(state); 3613 u8 old_slices, new_slices; 3614 3615 if (!new_dbuf_state) 3616 return; 3617 3618 old_slices = old_dbuf_state->enabled_slices; 3619 new_slices = old_dbuf_state->enabled_slices | new_dbuf_state->enabled_slices; 3620 3621 if (old_slices == new_slices) 3622 return; 3623 3624 WARN_ON(!new_dbuf_state->base.changed); 3625 3626 gen9_dbuf_slices_update(display, new_slices); 3627 } 3628 3629 void intel_dbuf_post_plane_update(struct intel_atomic_state *state) 3630 { 3631 struct intel_display *display = to_intel_display(state); 3632 const struct intel_dbuf_state *new_dbuf_state = 3633 intel_atomic_get_new_dbuf_state(state); 3634 const struct intel_dbuf_state *old_dbuf_state = 3635 intel_atomic_get_old_dbuf_state(state); 3636 u8 old_slices, new_slices; 3637 3638 if (!new_dbuf_state) 3639 return; 3640 3641 old_slices = old_dbuf_state->enabled_slices | new_dbuf_state->enabled_slices; 3642 new_slices = new_dbuf_state->enabled_slices; 3643 3644 if (old_slices == new_slices) 3645 return; 3646 3647 WARN_ON(!new_dbuf_state->base.changed); 3648 3649 gen9_dbuf_slices_update(display, new_slices); 3650 } 3651 3652 int intel_dbuf_num_enabled_slices(const struct intel_dbuf_state *dbuf_state) 3653 { 3654 return hweight8(dbuf_state->enabled_slices); 3655 } 3656 3657 int intel_dbuf_num_active_pipes(const struct intel_dbuf_state *dbuf_state) 3658 { 3659 return hweight8(dbuf_state->active_pipes); 3660 } 3661 3662 bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state) 3663 { 3664 struct intel_display *display = to_intel_display(state); 3665 const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; 3666 3667 new_dbuf_state = intel_atomic_get_new_dbuf_state(state); 3668 old_dbuf_state = intel_atomic_get_old_dbuf_state(state); 3669 3670 if (new_dbuf_state && 3671 new_dbuf_state->active_pipes != old_dbuf_state->active_pipes) 3672 return true; 3673 3674 if (DISPLAY_VER(display) < 30) { 3675 if (new_dbuf_state && 3676 new_dbuf_state->enabled_slices != 3677 old_dbuf_state->enabled_slices) 3678 return true; 3679 } 3680 3681 return false; 3682 } 3683 3684 static void skl_mbus_sanitize(struct intel_display *display) 3685 { 3686 struct intel_dbuf_state *dbuf_state = 3687 to_intel_dbuf_state(display->dbuf.obj.state); 3688 3689 if (!HAS_MBUS_JOINING(display)) 3690 return; 3691 3692 if (!dbuf_state->joined_mbus || 3693 adlp_check_mbus_joined(dbuf_state->active_pipes)) 3694 return; 3695 3696 drm_dbg_kms(display->drm, "Disabling redundant MBUS joining (active pipes 0x%x)\n", 3697 dbuf_state->active_pipes); 3698 3699 dbuf_state->joined_mbus = false; 3700 intel_dbuf_mdclk_cdclk_ratio_update(display, 3701 dbuf_state->mdclk_cdclk_ratio, 3702 dbuf_state->joined_mbus); 3703 pipe_mbus_dbox_ctl_update(display, dbuf_state); 3704 mbus_ctl_join_update(display, dbuf_state, INVALID_PIPE); 3705 } 3706 3707 static bool skl_dbuf_is_misconfigured(struct intel_display *display) 3708 { 3709 const struct intel_dbuf_state *dbuf_state = 3710 to_intel_dbuf_state(display->dbuf.obj.state); 3711 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 3712 struct intel_crtc *crtc; 3713 3714 for_each_intel_crtc(display->drm, crtc) { 3715 const struct intel_crtc_state *crtc_state = 3716 to_intel_crtc_state(crtc->base.state); 3717 3718 entries[crtc->pipe] = crtc_state->wm.skl.ddb; 3719 } 3720 3721 for_each_intel_crtc(display->drm, crtc) { 3722 const struct intel_crtc_state *crtc_state = 3723 to_intel_crtc_state(crtc->base.state); 3724 u8 slices; 3725 3726 slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, 3727 dbuf_state->joined_mbus); 3728 if (dbuf_state->slices[crtc->pipe] & ~slices) 3729 return true; 3730 3731 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries, 3732 I915_MAX_PIPES, crtc->pipe)) 3733 return true; 3734 } 3735 3736 return false; 3737 } 3738 3739 static void skl_dbuf_sanitize(struct intel_display *display) 3740 { 3741 struct intel_crtc *crtc; 3742 3743 /* 3744 * On TGL/RKL (at least) the BIOS likes to assign the planes 3745 * to the wrong DBUF slices. This will cause an infinite loop 3746 * in skl_commit_modeset_enables() as it can't find a way to 3747 * transition between the old bogus DBUF layout to the new 3748 * proper DBUF layout without DBUF allocation overlaps between 3749 * the planes (which cannot be allowed or else the hardware 3750 * may hang). If we detect a bogus DBUF layout just turn off 3751 * all the planes so that skl_commit_modeset_enables() can 3752 * simply ignore them. 3753 */ 3754 if (!skl_dbuf_is_misconfigured(display)) 3755 return; 3756 3757 drm_dbg_kms(display->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n"); 3758 3759 for_each_intel_crtc(display->drm, crtc) { 3760 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3761 const struct intel_plane_state *plane_state = 3762 to_intel_plane_state(plane->base.state); 3763 struct intel_crtc_state *crtc_state = 3764 to_intel_crtc_state(crtc->base.state); 3765 3766 if (plane_state->uapi.visible) 3767 intel_plane_disable_noatomic(crtc, plane); 3768 3769 drm_WARN_ON(display->drm, crtc_state->active_planes != 0); 3770 3771 memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); 3772 } 3773 } 3774 3775 static void skl_wm_sanitize(struct intel_display *display) 3776 { 3777 skl_mbus_sanitize(display); 3778 skl_dbuf_sanitize(display); 3779 } 3780 3781 void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc) 3782 { 3783 struct intel_display *display = to_intel_display(crtc); 3784 struct intel_crtc_state *crtc_state = 3785 to_intel_crtc_state(crtc->base.state); 3786 struct intel_dbuf_state *dbuf_state = 3787 to_intel_dbuf_state(display->dbuf.obj.state); 3788 enum pipe pipe = crtc->pipe; 3789 3790 if (DISPLAY_VER(display) < 9) 3791 return; 3792 3793 dbuf_state->active_pipes &= ~BIT(pipe); 3794 3795 dbuf_state->weight[pipe] = 0; 3796 dbuf_state->slices[pipe] = 0; 3797 3798 memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe])); 3799 3800 memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); 3801 } 3802 3803 void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc, 3804 struct intel_plane *plane) 3805 { 3806 struct intel_display *display = to_intel_display(crtc); 3807 struct intel_crtc_state *crtc_state = 3808 to_intel_crtc_state(crtc->base.state); 3809 3810 if (DISPLAY_VER(display) < 9) 3811 return; 3812 3813 skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0); 3814 skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0); 3815 3816 crtc_state->wm.skl.plane_min_ddb[plane->id] = 0; 3817 crtc_state->wm.skl.plane_interim_ddb[plane->id] = 0; 3818 3819 memset(&crtc_state->wm.skl.raw.planes[plane->id], 0, 3820 sizeof(crtc_state->wm.skl.raw.planes[plane->id])); 3821 memset(&crtc_state->wm.skl.optimal.planes[plane->id], 0, 3822 sizeof(crtc_state->wm.skl.optimal.planes[plane->id])); 3823 } 3824 3825 void intel_wm_state_verify(struct intel_atomic_state *state, 3826 struct intel_crtc *crtc) 3827 { 3828 struct intel_display *display = to_intel_display(state); 3829 const struct intel_crtc_state *new_crtc_state = 3830 intel_atomic_get_new_crtc_state(state, crtc); 3831 struct skl_hw_state { 3832 struct skl_ddb_entry ddb[I915_MAX_PLANES]; 3833 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 3834 u16 min_ddb[I915_MAX_PLANES]; 3835 u16 interim_ddb[I915_MAX_PLANES]; 3836 struct skl_pipe_wm wm; 3837 } *hw; 3838 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 3839 struct intel_plane *plane; 3840 u8 hw_enabled_slices; 3841 int level; 3842 3843 if (DISPLAY_VER(display) < 9 || !new_crtc_state->hw.active) 3844 return; 3845 3846 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 3847 if (!hw) 3848 return; 3849 3850 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 3851 3852 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y, hw->min_ddb, hw->interim_ddb); 3853 3854 hw_enabled_slices = intel_enabled_dbuf_slices_mask(display); 3855 3856 if (DISPLAY_VER(display) >= 11 && 3857 hw_enabled_slices != display->dbuf.enabled_slices) 3858 drm_err(display->drm, 3859 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 3860 display->dbuf.enabled_slices, 3861 hw_enabled_slices); 3862 3863 for_each_intel_plane_on_crtc(display->drm, crtc, plane) { 3864 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 3865 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 3866 3867 /* Watermarks */ 3868 for (level = 0; level < display->wm.num_levels; level++) { 3869 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 3870 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 3871 3872 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 3873 continue; 3874 3875 drm_err(display->drm, 3876 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3877 plane->base.base.id, plane->base.name, level, 3878 sw_wm_level->enable, 3879 sw_wm_level->blocks, 3880 sw_wm_level->lines, 3881 hw_wm_level->enable, 3882 hw_wm_level->blocks, 3883 hw_wm_level->lines); 3884 } 3885 3886 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 3887 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 3888 3889 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3890 drm_err(display->drm, 3891 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3892 plane->base.base.id, plane->base.name, 3893 sw_wm_level->enable, 3894 sw_wm_level->blocks, 3895 sw_wm_level->lines, 3896 hw_wm_level->enable, 3897 hw_wm_level->blocks, 3898 hw_wm_level->lines); 3899 } 3900 3901 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 3902 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 3903 3904 if (HAS_HW_SAGV_WM(display) && 3905 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3906 drm_err(display->drm, 3907 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3908 plane->base.base.id, plane->base.name, 3909 sw_wm_level->enable, 3910 sw_wm_level->blocks, 3911 sw_wm_level->lines, 3912 hw_wm_level->enable, 3913 hw_wm_level->blocks, 3914 hw_wm_level->lines); 3915 } 3916 3917 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 3918 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 3919 3920 if (HAS_HW_SAGV_WM(display) && 3921 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3922 drm_err(display->drm, 3923 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3924 plane->base.base.id, plane->base.name, 3925 sw_wm_level->enable, 3926 sw_wm_level->blocks, 3927 sw_wm_level->lines, 3928 hw_wm_level->enable, 3929 hw_wm_level->blocks, 3930 hw_wm_level->lines); 3931 } 3932 3933 /* DDB */ 3934 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 3935 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 3936 3937 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 3938 drm_err(display->drm, 3939 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 3940 plane->base.base.id, plane->base.name, 3941 sw_ddb_entry->start, sw_ddb_entry->end, 3942 hw_ddb_entry->start, hw_ddb_entry->end); 3943 } 3944 } 3945 3946 kfree(hw); 3947 } 3948 3949 static const struct intel_wm_funcs skl_wm_funcs = { 3950 .compute_global_watermarks = skl_compute_wm, 3951 .get_hw_state = skl_wm_get_hw_state, 3952 .sanitize = skl_wm_sanitize, 3953 }; 3954 3955 void skl_wm_init(struct intel_display *display) 3956 { 3957 intel_sagv_init(display); 3958 3959 skl_setup_wm_latency(display); 3960 3961 display->funcs.wm = &skl_wm_funcs; 3962 } 3963 3964 static int skl_watermark_ipc_status_show(struct seq_file *m, void *data) 3965 { 3966 struct intel_display *display = m->private; 3967 3968 seq_printf(m, "Isochronous Priority Control: %s\n", 3969 str_yes_no(skl_watermark_ipc_enabled(display))); 3970 return 0; 3971 } 3972 3973 static int skl_watermark_ipc_status_open(struct inode *inode, struct file *file) 3974 { 3975 struct intel_display *display = inode->i_private; 3976 3977 return single_open(file, skl_watermark_ipc_status_show, display); 3978 } 3979 3980 static ssize_t skl_watermark_ipc_status_write(struct file *file, 3981 const char __user *ubuf, 3982 size_t len, loff_t *offp) 3983 { 3984 struct seq_file *m = file->private_data; 3985 struct intel_display *display = m->private; 3986 bool enable; 3987 int ret; 3988 3989 ret = kstrtobool_from_user(ubuf, len, &enable); 3990 if (ret < 0) 3991 return ret; 3992 3993 with_intel_display_rpm(display) { 3994 if (!skl_watermark_ipc_enabled(display) && enable) 3995 drm_info(display->drm, 3996 "Enabling IPC: WM will be proper only after next commit\n"); 3997 display->wm.ipc_enabled = enable; 3998 skl_watermark_ipc_update(display); 3999 } 4000 4001 return len; 4002 } 4003 4004 static const struct file_operations skl_watermark_ipc_status_fops = { 4005 .owner = THIS_MODULE, 4006 .open = skl_watermark_ipc_status_open, 4007 .read = seq_read, 4008 .llseek = seq_lseek, 4009 .release = single_release, 4010 .write = skl_watermark_ipc_status_write 4011 }; 4012 4013 static int intel_sagv_status_show(struct seq_file *m, void *unused) 4014 { 4015 struct intel_display *display = m->private; 4016 static const char * const sagv_status[] = { 4017 [I915_SAGV_UNKNOWN] = "unknown", 4018 [I915_SAGV_DISABLED] = "disabled", 4019 [I915_SAGV_ENABLED] = "enabled", 4020 [I915_SAGV_NOT_CONTROLLED] = "not controlled", 4021 }; 4022 4023 seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(display))); 4024 seq_printf(m, "SAGV modparam: %s\n", 4025 str_enabled_disabled(display->params.enable_sagv)); 4026 seq_printf(m, "SAGV status: %s\n", sagv_status[display->sagv.status]); 4027 seq_printf(m, "SAGV block time: %d usec\n", display->sagv.block_time_us); 4028 4029 return 0; 4030 } 4031 4032 DEFINE_SHOW_ATTRIBUTE(intel_sagv_status); 4033 4034 void skl_watermark_debugfs_register(struct intel_display *display) 4035 { 4036 struct drm_minor *minor = display->drm->primary; 4037 4038 if (HAS_IPC(display)) 4039 debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, 4040 display, &skl_watermark_ipc_status_fops); 4041 4042 if (HAS_SAGV(display)) 4043 debugfs_create_file("i915_sagv_status", 0444, minor->debugfs_root, 4044 display, &intel_sagv_status_fops); 4045 } 4046 4047 unsigned int skl_watermark_max_latency(struct intel_display *display, int initial_wm_level) 4048 { 4049 int level; 4050 4051 for (level = display->wm.num_levels - 1; level >= initial_wm_level; level--) { 4052 unsigned int latency = skl_wm_latency(display, level, NULL); 4053 4054 if (latency) 4055 return latency; 4056 } 4057 4058 return 0; 4059 } 4060