1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 */ 27 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include "intel_connector.h" 38 #include "intel_de.h" 39 #include "intel_display_driver.h" 40 #include "intel_display_regs.h" 41 #include "intel_display_types.h" 42 #include "intel_display_utils.h" 43 #include "intel_dvo.h" 44 #include "intel_dvo_dev.h" 45 #include "intel_dvo_regs.h" 46 #include "intel_gmbus.h" 47 #include "intel_panel.h" 48 49 #define INTEL_DVO_CHIP_NONE 0 50 #define INTEL_DVO_CHIP_LVDS 1 51 #define INTEL_DVO_CHIP_TMDS 2 52 #define INTEL_DVO_CHIP_TVOUT 4 53 #define INTEL_DVO_CHIP_LVDS_NO_FIXED 5 54 55 #define SIL164_ADDR 0x38 56 #define CH7xxx_ADDR 0x76 57 #define TFP410_ADDR 0x38 58 #define NS2501_ADDR 0x38 59 60 static const struct intel_dvo_device intel_dvo_devices[] = { 61 { 62 .type = INTEL_DVO_CHIP_TMDS, 63 .name = "sil164", 64 .port = PORT_C, 65 .target_addr = SIL164_ADDR, 66 .dev_ops = &sil164_ops, 67 }, 68 { 69 .type = INTEL_DVO_CHIP_TMDS, 70 .name = "ch7xxx", 71 .port = PORT_C, 72 .target_addr = CH7xxx_ADDR, 73 .dev_ops = &ch7xxx_ops, 74 }, 75 { 76 .type = INTEL_DVO_CHIP_TMDS, 77 .name = "ch7xxx", 78 .port = PORT_C, 79 .target_addr = 0x75, /* For some ch7010 */ 80 .dev_ops = &ch7xxx_ops, 81 }, 82 { 83 .type = INTEL_DVO_CHIP_LVDS, 84 .name = "ivch", 85 .port = PORT_A, 86 .target_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ 87 .dev_ops = &ivch_ops, 88 }, 89 { 90 .type = INTEL_DVO_CHIP_TMDS, 91 .name = "tfp410", 92 .port = PORT_C, 93 .target_addr = TFP410_ADDR, 94 .dev_ops = &tfp410_ops, 95 }, 96 { 97 .type = INTEL_DVO_CHIP_LVDS, 98 .name = "ch7017", 99 .port = PORT_C, 100 .target_addr = 0x75, 101 .gpio = GMBUS_PIN_DPB, 102 .dev_ops = &ch7017_ops, 103 }, 104 { 105 .type = INTEL_DVO_CHIP_LVDS_NO_FIXED, 106 .name = "ns2501", 107 .port = PORT_B, 108 .target_addr = NS2501_ADDR, 109 .dev_ops = &ns2501_ops, 110 }, 111 }; 112 113 struct intel_dvo { 114 struct intel_encoder base; 115 116 struct intel_dvo_device dev; 117 118 struct intel_connector *attached_connector; 119 }; 120 121 static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) 122 { 123 return container_of(encoder, struct intel_dvo, base); 124 } 125 126 static struct intel_dvo *intel_attached_dvo(struct intel_connector *connector) 127 { 128 return enc_to_dvo(intel_attached_encoder(connector)); 129 } 130 131 static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) 132 { 133 struct intel_display *display = to_intel_display(connector); 134 struct intel_encoder *encoder = intel_attached_encoder(connector); 135 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 136 enum port port = encoder->port; 137 u32 tmp; 138 139 tmp = intel_de_read(display, DVO(port)); 140 141 if (!(tmp & DVO_ENABLE)) 142 return false; 143 144 return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); 145 } 146 147 static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, 148 enum pipe *pipe) 149 { 150 struct intel_display *display = to_intel_display(encoder); 151 enum port port = encoder->port; 152 u32 tmp; 153 154 tmp = intel_de_read(display, DVO(port)); 155 156 *pipe = REG_FIELD_GET(DVO_PIPE_SEL_MASK, tmp); 157 158 return tmp & DVO_ENABLE; 159 } 160 161 static void intel_dvo_get_config(struct intel_encoder *encoder, 162 struct intel_crtc_state *pipe_config) 163 { 164 struct intel_display *display = to_intel_display(encoder); 165 enum port port = encoder->port; 166 u32 tmp, flags = 0; 167 168 pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); 169 170 tmp = intel_de_read(display, DVO(port)); 171 if (tmp & DVO_HSYNC_ACTIVE_HIGH) 172 flags |= DRM_MODE_FLAG_PHSYNC; 173 else 174 flags |= DRM_MODE_FLAG_NHSYNC; 175 if (tmp & DVO_VSYNC_ACTIVE_HIGH) 176 flags |= DRM_MODE_FLAG_PVSYNC; 177 else 178 flags |= DRM_MODE_FLAG_NVSYNC; 179 180 pipe_config->hw.adjusted_mode.flags |= flags; 181 182 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 183 } 184 185 static void intel_disable_dvo(struct intel_atomic_state *state, 186 struct intel_encoder *encoder, 187 const struct intel_crtc_state *old_crtc_state, 188 const struct drm_connector_state *old_conn_state) 189 { 190 struct intel_display *display = to_intel_display(encoder); 191 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 192 enum port port = encoder->port; 193 194 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); 195 196 intel_de_rmw(display, DVO(port), DVO_ENABLE, 0); 197 intel_de_posting_read(display, DVO(port)); 198 } 199 200 static void intel_enable_dvo(struct intel_atomic_state *state, 201 struct intel_encoder *encoder, 202 const struct intel_crtc_state *pipe_config, 203 const struct drm_connector_state *conn_state) 204 { 205 struct intel_display *display = to_intel_display(encoder); 206 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 207 enum port port = encoder->port; 208 209 intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, 210 &pipe_config->hw.mode, 211 &pipe_config->hw.adjusted_mode); 212 213 intel_de_rmw(display, DVO(port), 0, DVO_ENABLE); 214 intel_de_posting_read(display, DVO(port)); 215 216 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); 217 } 218 219 static enum drm_mode_status 220 intel_dvo_mode_valid(struct drm_connector *_connector, 221 const struct drm_display_mode *mode) 222 { 223 struct intel_display *display = to_intel_display(_connector->dev); 224 struct intel_connector *connector = to_intel_connector(_connector); 225 struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 226 int max_dotclk = display->cdclk.max_dotclk_freq; 227 int target_clock = mode->clock; 228 enum drm_mode_status status; 229 230 status = intel_cpu_transcoder_mode_valid(display, mode); 231 if (status != MODE_OK) 232 return status; 233 234 /* XXX: Validate clock range */ 235 status = intel_panel_mode_valid(connector, mode, &target_clock); 236 if (status != MODE_OK) 237 return status; 238 239 if (target_clock > max_dotclk) 240 return MODE_CLOCK_HIGH; 241 242 return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); 243 } 244 245 static int intel_dvo_compute_config(struct intel_atomic_state *state, 246 struct intel_encoder *encoder, 247 struct intel_crtc_state *pipe_config, 248 struct drm_connector_state *conn_state) 249 { 250 struct intel_connector *connector = to_intel_connector(conn_state->connector); 251 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 252 int ret; 253 254 /* 255 * If we have timings from the BIOS for the panel, put them in 256 * to the adjusted mode. The CRTC will be set up for this mode, 257 * with the panel scaling set up to source from the H/VDisplay 258 * of the original mode. 259 */ 260 ret = intel_panel_compute_config(state, pipe_config, connector); 261 if (ret) 262 return ret; 263 264 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 265 return -EINVAL; 266 267 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 268 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 269 270 return 0; 271 } 272 273 static void intel_dvo_pre_enable(struct intel_atomic_state *state, 274 struct intel_encoder *encoder, 275 const struct intel_crtc_state *pipe_config, 276 const struct drm_connector_state *conn_state) 277 { 278 struct intel_display *display = to_intel_display(encoder); 279 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 280 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 281 enum port port = encoder->port; 282 enum pipe pipe = crtc->pipe; 283 u32 dvo_val; 284 285 /* Save the active data order, since I don't know what it should be set to. */ 286 dvo_val = intel_de_read(display, DVO(port)) & 287 (DVO_DEDICATED_INT_ENABLE | 288 DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_MASK); 289 dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | 290 DVO_BLANK_ACTIVE_HIGH; 291 292 dvo_val |= DVO_PIPE_SEL(pipe); 293 dvo_val |= DVO_PIPE_STALL; 294 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 295 dvo_val |= DVO_HSYNC_ACTIVE_HIGH; 296 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 297 dvo_val |= DVO_VSYNC_ACTIVE_HIGH; 298 299 intel_de_write(display, DVO_SRCDIM(port), 300 DVO_SRCDIM_HORIZONTAL(adjusted_mode->crtc_hdisplay) | 301 DVO_SRCDIM_VERTICAL(adjusted_mode->crtc_vdisplay)); 302 intel_de_write(display, DVO(port), dvo_val); 303 } 304 305 static enum drm_connector_status 306 intel_dvo_detect(struct drm_connector *_connector, bool force) 307 { 308 struct intel_display *display = to_intel_display(_connector->dev); 309 struct intel_connector *connector = to_intel_connector(_connector); 310 struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 311 312 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 313 connector->base.base.id, connector->base.name); 314 315 if (!intel_display_device_enabled(display)) 316 return connector_status_disconnected; 317 318 if (!intel_display_driver_check_access(display)) 319 return connector->base.status; 320 321 return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); 322 } 323 324 static int intel_dvo_get_modes(struct drm_connector *_connector) 325 { 326 struct intel_display *display = to_intel_display(_connector->dev); 327 struct intel_connector *connector = to_intel_connector(_connector); 328 int num_modes; 329 330 if (!intel_display_driver_check_access(display)) 331 return drm_edid_connector_add_modes(&connector->base); 332 333 /* 334 * We should probably have an i2c driver get_modes function for those 335 * devices which will have a fixed set of modes determined by the chip 336 * (TV-out, for example), but for now with just TMDS and LVDS, 337 * that's not the case. 338 */ 339 num_modes = intel_ddc_get_modes(&connector->base, connector->base.ddc); 340 if (num_modes) 341 return num_modes; 342 343 return intel_panel_get_modes(connector); 344 } 345 346 static const struct drm_connector_funcs intel_dvo_connector_funcs = { 347 .detect = intel_dvo_detect, 348 .late_register = intel_connector_register, 349 .early_unregister = intel_connector_unregister, 350 .destroy = intel_connector_destroy, 351 .fill_modes = drm_helper_probe_single_connector_modes, 352 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 353 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 354 }; 355 356 static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { 357 .mode_valid = intel_dvo_mode_valid, 358 .get_modes = intel_dvo_get_modes, 359 }; 360 361 static void intel_dvo_enc_destroy(struct drm_encoder *encoder) 362 { 363 struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)); 364 365 if (intel_dvo->dev.dev_ops->destroy) 366 intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); 367 368 intel_encoder_destroy(encoder); 369 } 370 371 static const struct drm_encoder_funcs intel_dvo_enc_funcs = { 372 .destroy = intel_dvo_enc_destroy, 373 }; 374 375 static int intel_dvo_encoder_type(const struct intel_dvo_device *dvo) 376 { 377 switch (dvo->type) { 378 case INTEL_DVO_CHIP_TMDS: 379 return DRM_MODE_ENCODER_TMDS; 380 case INTEL_DVO_CHIP_LVDS_NO_FIXED: 381 case INTEL_DVO_CHIP_LVDS: 382 return DRM_MODE_ENCODER_LVDS; 383 default: 384 MISSING_CASE(dvo->type); 385 return DRM_MODE_ENCODER_NONE; 386 } 387 } 388 389 static int intel_dvo_connector_type(const struct intel_dvo_device *dvo) 390 { 391 switch (dvo->type) { 392 case INTEL_DVO_CHIP_TMDS: 393 return DRM_MODE_CONNECTOR_DVII; 394 case INTEL_DVO_CHIP_LVDS_NO_FIXED: 395 case INTEL_DVO_CHIP_LVDS: 396 return DRM_MODE_CONNECTOR_LVDS; 397 default: 398 MISSING_CASE(dvo->type); 399 return DRM_MODE_CONNECTOR_Unknown; 400 } 401 } 402 403 static bool intel_dvo_init_dev(struct intel_display *display, 404 struct intel_dvo *intel_dvo, 405 const struct intel_dvo_device *dvo) 406 { 407 struct i2c_adapter *i2c; 408 u32 dpll[I915_MAX_PIPES]; 409 enum pipe pipe; 410 int gpio; 411 bool ret; 412 413 /* 414 * Allow the I2C driver info to specify the GPIO to be used in 415 * special cases, but otherwise default to what's defined 416 * in the spec. 417 */ 418 if (intel_gmbus_is_valid_pin(display, dvo->gpio)) 419 gpio = dvo->gpio; 420 else if (dvo->type == INTEL_DVO_CHIP_LVDS) 421 gpio = GMBUS_PIN_SSC; 422 else 423 gpio = GMBUS_PIN_DPB; 424 425 /* 426 * Set up the I2C bus necessary for the chip we're probing. 427 * It appears that everything is on GPIOE except for panels 428 * on i830 laptops, which are on GPIOB (DVOA). 429 */ 430 i2c = intel_gmbus_get_adapter(display, gpio); 431 432 intel_dvo->dev = *dvo; 433 434 /* 435 * GMBUS NAK handling seems to be unstable, hence let the 436 * transmitter detection run in bit banging mode for now. 437 */ 438 intel_gmbus_force_bit(i2c, true); 439 440 /* 441 * ns2501 requires the DVO 2x clock before it will 442 * respond to i2c accesses, so make sure we have 443 * the clock enabled before we attempt to initialize 444 * the device. 445 */ 446 for_each_pipe(display, pipe) 447 dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0, 448 DPLL_DVO_2X_MODE); 449 450 ret = dvo->dev_ops->init(&intel_dvo->dev, i2c); 451 452 /* restore the DVO 2x clock state to original */ 453 for_each_pipe(display, pipe) { 454 intel_de_write(display, DPLL(display, pipe), dpll[pipe]); 455 } 456 457 intel_gmbus_force_bit(i2c, false); 458 459 return ret; 460 } 461 462 static bool intel_dvo_probe(struct intel_display *display, 463 struct intel_dvo *intel_dvo) 464 { 465 int i; 466 467 /* Now, try to find a controller */ 468 for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { 469 if (intel_dvo_init_dev(display, intel_dvo, 470 &intel_dvo_devices[i])) 471 return true; 472 } 473 474 return false; 475 } 476 477 void intel_dvo_init(struct intel_display *display) 478 { 479 struct intel_connector *connector; 480 struct intel_encoder *encoder; 481 struct intel_dvo *intel_dvo; 482 483 intel_dvo = kzalloc_obj(*intel_dvo); 484 if (!intel_dvo) 485 return; 486 487 connector = intel_connector_alloc(); 488 if (!connector) { 489 kfree(intel_dvo); 490 return; 491 } 492 493 intel_dvo->attached_connector = connector; 494 495 encoder = &intel_dvo->base; 496 497 encoder->disable = intel_disable_dvo; 498 encoder->enable = intel_enable_dvo; 499 encoder->get_hw_state = intel_dvo_get_hw_state; 500 encoder->get_config = intel_dvo_get_config; 501 encoder->compute_config = intel_dvo_compute_config; 502 encoder->pre_enable = intel_dvo_pre_enable; 503 connector->get_hw_state = intel_dvo_connector_get_hw_state; 504 505 if (!intel_dvo_probe(display, intel_dvo)) { 506 kfree(intel_dvo); 507 intel_connector_free(connector); 508 return; 509 } 510 511 assert_port_valid(display, intel_dvo->dev.port); 512 513 encoder->type = INTEL_OUTPUT_DVO; 514 encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 515 encoder->port = intel_dvo->dev.port; 516 encoder->pipe_mask = ~0; 517 518 if (intel_dvo->dev.type != INTEL_DVO_CHIP_LVDS) 519 encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG) | 520 BIT(INTEL_OUTPUT_DVO); 521 522 drm_encoder_init(display->drm, &encoder->base, 523 &intel_dvo_enc_funcs, 524 intel_dvo_encoder_type(&intel_dvo->dev), 525 "DVO %c", port_name(encoder->port)); 526 527 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] detected %s\n", 528 encoder->base.base.id, encoder->base.name, 529 intel_dvo->dev.name); 530 531 if (intel_dvo->dev.type == INTEL_DVO_CHIP_TMDS) 532 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 533 DRM_CONNECTOR_POLL_DISCONNECT; 534 connector->base.polled = connector->polled; 535 536 drm_connector_init_with_ddc(display->drm, &connector->base, 537 &intel_dvo_connector_funcs, 538 intel_dvo_connector_type(&intel_dvo->dev), 539 intel_gmbus_get_adapter(display, GMBUS_PIN_DPC)); 540 541 drm_connector_helper_add(&connector->base, 542 &intel_dvo_connector_helper_funcs); 543 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; 544 545 intel_connector_attach_encoder(connector, encoder); 546 547 if (intel_dvo->dev.type == INTEL_DVO_CHIP_LVDS) { 548 /* 549 * For our LVDS chipsets, we should hopefully be able 550 * to dig the fixed panel mode out of the BIOS data. 551 * However, it's in a different format from the BIOS 552 * data on chipsets with integrated LVDS (stored in AIM 553 * headers, likely), so for now, just get the current 554 * mode being output through DVO. 555 */ 556 intel_panel_add_encoder_fixed_mode(connector, encoder); 557 558 intel_panel_init(connector, NULL); 559 } 560 } 561