1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include "i915_drv.h" 9 #include "i915_irq.h" 10 #include "i915_reg.h" 11 #include "intel_backlight_regs.h" 12 #include "intel_cdclk.h" 13 #include "intel_clock_gating.h" 14 #include "intel_combo_phy.h" 15 #include "intel_de.h" 16 #include "intel_display_power.h" 17 #include "intel_display_power_map.h" 18 #include "intel_display_power_well.h" 19 #include "intel_display_types.h" 20 #include "intel_dmc.h" 21 #include "intel_mchbar_regs.h" 22 #include "intel_pch_refclk.h" 23 #include "intel_pcode.h" 24 #include "intel_pmdemand.h" 25 #include "intel_pps_regs.h" 26 #include "intel_snps_phy.h" 27 #include "skl_watermark.h" 28 #include "skl_watermark_regs.h" 29 #include "vlv_sideband.h" 30 31 #define for_each_power_domain_well(__display, __power_well, __domain) \ 32 for_each_power_well((__display), __power_well) \ 33 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 34 35 #define for_each_power_domain_well_reverse(__display, __power_well, __domain) \ 36 for_each_power_well_reverse((__display), __power_well) \ 37 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 38 39 static const char * 40 intel_display_power_domain_str(enum intel_display_power_domain domain) 41 { 42 switch (domain) { 43 case POWER_DOMAIN_DISPLAY_CORE: 44 return "DISPLAY_CORE"; 45 case POWER_DOMAIN_PIPE_A: 46 return "PIPE_A"; 47 case POWER_DOMAIN_PIPE_B: 48 return "PIPE_B"; 49 case POWER_DOMAIN_PIPE_C: 50 return "PIPE_C"; 51 case POWER_DOMAIN_PIPE_D: 52 return "PIPE_D"; 53 case POWER_DOMAIN_PIPE_PANEL_FITTER_A: 54 return "PIPE_PANEL_FITTER_A"; 55 case POWER_DOMAIN_PIPE_PANEL_FITTER_B: 56 return "PIPE_PANEL_FITTER_B"; 57 case POWER_DOMAIN_PIPE_PANEL_FITTER_C: 58 return "PIPE_PANEL_FITTER_C"; 59 case POWER_DOMAIN_PIPE_PANEL_FITTER_D: 60 return "PIPE_PANEL_FITTER_D"; 61 case POWER_DOMAIN_TRANSCODER_A: 62 return "TRANSCODER_A"; 63 case POWER_DOMAIN_TRANSCODER_B: 64 return "TRANSCODER_B"; 65 case POWER_DOMAIN_TRANSCODER_C: 66 return "TRANSCODER_C"; 67 case POWER_DOMAIN_TRANSCODER_D: 68 return "TRANSCODER_D"; 69 case POWER_DOMAIN_TRANSCODER_EDP: 70 return "TRANSCODER_EDP"; 71 case POWER_DOMAIN_TRANSCODER_DSI_A: 72 return "TRANSCODER_DSI_A"; 73 case POWER_DOMAIN_TRANSCODER_DSI_C: 74 return "TRANSCODER_DSI_C"; 75 case POWER_DOMAIN_TRANSCODER_VDSC_PW2: 76 return "TRANSCODER_VDSC_PW2"; 77 case POWER_DOMAIN_PORT_DDI_LANES_A: 78 return "PORT_DDI_LANES_A"; 79 case POWER_DOMAIN_PORT_DDI_LANES_B: 80 return "PORT_DDI_LANES_B"; 81 case POWER_DOMAIN_PORT_DDI_LANES_C: 82 return "PORT_DDI_LANES_C"; 83 case POWER_DOMAIN_PORT_DDI_LANES_D: 84 return "PORT_DDI_LANES_D"; 85 case POWER_DOMAIN_PORT_DDI_LANES_E: 86 return "PORT_DDI_LANES_E"; 87 case POWER_DOMAIN_PORT_DDI_LANES_F: 88 return "PORT_DDI_LANES_F"; 89 case POWER_DOMAIN_PORT_DDI_LANES_TC1: 90 return "PORT_DDI_LANES_TC1"; 91 case POWER_DOMAIN_PORT_DDI_LANES_TC2: 92 return "PORT_DDI_LANES_TC2"; 93 case POWER_DOMAIN_PORT_DDI_LANES_TC3: 94 return "PORT_DDI_LANES_TC3"; 95 case POWER_DOMAIN_PORT_DDI_LANES_TC4: 96 return "PORT_DDI_LANES_TC4"; 97 case POWER_DOMAIN_PORT_DDI_LANES_TC5: 98 return "PORT_DDI_LANES_TC5"; 99 case POWER_DOMAIN_PORT_DDI_LANES_TC6: 100 return "PORT_DDI_LANES_TC6"; 101 case POWER_DOMAIN_PORT_DDI_IO_A: 102 return "PORT_DDI_IO_A"; 103 case POWER_DOMAIN_PORT_DDI_IO_B: 104 return "PORT_DDI_IO_B"; 105 case POWER_DOMAIN_PORT_DDI_IO_C: 106 return "PORT_DDI_IO_C"; 107 case POWER_DOMAIN_PORT_DDI_IO_D: 108 return "PORT_DDI_IO_D"; 109 case POWER_DOMAIN_PORT_DDI_IO_E: 110 return "PORT_DDI_IO_E"; 111 case POWER_DOMAIN_PORT_DDI_IO_F: 112 return "PORT_DDI_IO_F"; 113 case POWER_DOMAIN_PORT_DDI_IO_TC1: 114 return "PORT_DDI_IO_TC1"; 115 case POWER_DOMAIN_PORT_DDI_IO_TC2: 116 return "PORT_DDI_IO_TC2"; 117 case POWER_DOMAIN_PORT_DDI_IO_TC3: 118 return "PORT_DDI_IO_TC3"; 119 case POWER_DOMAIN_PORT_DDI_IO_TC4: 120 return "PORT_DDI_IO_TC4"; 121 case POWER_DOMAIN_PORT_DDI_IO_TC5: 122 return "PORT_DDI_IO_TC5"; 123 case POWER_DOMAIN_PORT_DDI_IO_TC6: 124 return "PORT_DDI_IO_TC6"; 125 case POWER_DOMAIN_PORT_DSI: 126 return "PORT_DSI"; 127 case POWER_DOMAIN_PORT_CRT: 128 return "PORT_CRT"; 129 case POWER_DOMAIN_PORT_OTHER: 130 return "PORT_OTHER"; 131 case POWER_DOMAIN_VGA: 132 return "VGA"; 133 case POWER_DOMAIN_AUDIO_MMIO: 134 return "AUDIO_MMIO"; 135 case POWER_DOMAIN_AUDIO_PLAYBACK: 136 return "AUDIO_PLAYBACK"; 137 case POWER_DOMAIN_AUX_IO_A: 138 return "AUX_IO_A"; 139 case POWER_DOMAIN_AUX_IO_B: 140 return "AUX_IO_B"; 141 case POWER_DOMAIN_AUX_IO_C: 142 return "AUX_IO_C"; 143 case POWER_DOMAIN_AUX_IO_D: 144 return "AUX_IO_D"; 145 case POWER_DOMAIN_AUX_IO_E: 146 return "AUX_IO_E"; 147 case POWER_DOMAIN_AUX_IO_F: 148 return "AUX_IO_F"; 149 case POWER_DOMAIN_AUX_A: 150 return "AUX_A"; 151 case POWER_DOMAIN_AUX_B: 152 return "AUX_B"; 153 case POWER_DOMAIN_AUX_C: 154 return "AUX_C"; 155 case POWER_DOMAIN_AUX_D: 156 return "AUX_D"; 157 case POWER_DOMAIN_AUX_E: 158 return "AUX_E"; 159 case POWER_DOMAIN_AUX_F: 160 return "AUX_F"; 161 case POWER_DOMAIN_AUX_USBC1: 162 return "AUX_USBC1"; 163 case POWER_DOMAIN_AUX_USBC2: 164 return "AUX_USBC2"; 165 case POWER_DOMAIN_AUX_USBC3: 166 return "AUX_USBC3"; 167 case POWER_DOMAIN_AUX_USBC4: 168 return "AUX_USBC4"; 169 case POWER_DOMAIN_AUX_USBC5: 170 return "AUX_USBC5"; 171 case POWER_DOMAIN_AUX_USBC6: 172 return "AUX_USBC6"; 173 case POWER_DOMAIN_AUX_TBT1: 174 return "AUX_TBT1"; 175 case POWER_DOMAIN_AUX_TBT2: 176 return "AUX_TBT2"; 177 case POWER_DOMAIN_AUX_TBT3: 178 return "AUX_TBT3"; 179 case POWER_DOMAIN_AUX_TBT4: 180 return "AUX_TBT4"; 181 case POWER_DOMAIN_AUX_TBT5: 182 return "AUX_TBT5"; 183 case POWER_DOMAIN_AUX_TBT6: 184 return "AUX_TBT6"; 185 case POWER_DOMAIN_GMBUS: 186 return "GMBUS"; 187 case POWER_DOMAIN_INIT: 188 return "INIT"; 189 case POWER_DOMAIN_GT_IRQ: 190 return "GT_IRQ"; 191 case POWER_DOMAIN_DC_OFF: 192 return "DC_OFF"; 193 case POWER_DOMAIN_TC_COLD_OFF: 194 return "TC_COLD_OFF"; 195 default: 196 MISSING_CASE(domain); 197 return "?"; 198 } 199 } 200 201 static bool __intel_display_power_is_enabled(struct intel_display *display, 202 enum intel_display_power_domain domain) 203 { 204 struct i915_power_well *power_well; 205 bool is_enabled; 206 207 if (pm_runtime_suspended(display->drm->dev)) 208 return false; 209 210 is_enabled = true; 211 212 for_each_power_domain_well_reverse(display, power_well, domain) { 213 if (intel_power_well_is_always_on(power_well)) 214 continue; 215 216 if (!intel_power_well_is_enabled_cached(power_well)) { 217 is_enabled = false; 218 break; 219 } 220 } 221 222 return is_enabled; 223 } 224 225 /** 226 * intel_display_power_is_enabled - check for a power domain 227 * @dev_priv: i915 device instance 228 * @domain: power domain to check 229 * 230 * This function can be used to check the hw power domain state. It is mostly 231 * used in hardware state readout functions. Everywhere else code should rely 232 * upon explicit power domain reference counting to ensure that the hardware 233 * block is powered up before accessing it. 234 * 235 * Callers must hold the relevant modesetting locks to ensure that concurrent 236 * threads can't disable the power well while the caller tries to read a few 237 * registers. 238 * 239 * Returns: 240 * True when the power domain is enabled, false otherwise. 241 */ 242 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 243 enum intel_display_power_domain domain) 244 { 245 struct intel_display *display = &dev_priv->display; 246 struct i915_power_domains *power_domains = &display->power.domains; 247 bool ret; 248 249 mutex_lock(&power_domains->lock); 250 ret = __intel_display_power_is_enabled(display, domain); 251 mutex_unlock(&power_domains->lock); 252 253 return ret; 254 } 255 256 static u32 257 sanitize_target_dc_state(struct intel_display *display, 258 u32 target_dc_state) 259 { 260 struct i915_power_domains *power_domains = &display->power.domains; 261 static const u32 states[] = { 262 DC_STATE_EN_UPTO_DC6, 263 DC_STATE_EN_UPTO_DC5, 264 DC_STATE_EN_DC3CO, 265 DC_STATE_DISABLE, 266 }; 267 int i; 268 269 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { 270 if (target_dc_state != states[i]) 271 continue; 272 273 if (power_domains->allowed_dc_mask & target_dc_state) 274 break; 275 276 target_dc_state = states[i + 1]; 277 } 278 279 return target_dc_state; 280 } 281 282 /** 283 * intel_display_power_set_target_dc_state - Set target dc state. 284 * @display: display device 285 * @state: state which needs to be set as target_dc_state. 286 * 287 * This function set the "DC off" power well target_dc_state, 288 * based upon this target_dc_stste, "DC off" power well will 289 * enable desired DC state. 290 */ 291 void intel_display_power_set_target_dc_state(struct intel_display *display, 292 u32 state) 293 { 294 struct i915_power_well *power_well; 295 bool dc_off_enabled; 296 struct i915_power_domains *power_domains = &display->power.domains; 297 298 mutex_lock(&power_domains->lock); 299 power_well = lookup_power_well(display, SKL_DISP_DC_OFF); 300 301 if (drm_WARN_ON(display->drm, !power_well)) 302 goto unlock; 303 304 state = sanitize_target_dc_state(display, state); 305 306 if (state == power_domains->target_dc_state) 307 goto unlock; 308 309 dc_off_enabled = intel_power_well_is_enabled(display, power_well); 310 /* 311 * If DC off power well is disabled, need to enable and disable the 312 * DC off power well to effect target DC state. 313 */ 314 if (!dc_off_enabled) 315 intel_power_well_enable(display, power_well); 316 317 power_domains->target_dc_state = state; 318 319 if (!dc_off_enabled) 320 intel_power_well_disable(display, power_well); 321 322 unlock: 323 mutex_unlock(&power_domains->lock); 324 } 325 326 static void __async_put_domains_mask(struct i915_power_domains *power_domains, 327 struct intel_power_domain_mask *mask) 328 { 329 bitmap_or(mask->bits, 330 power_domains->async_put_domains[0].bits, 331 power_domains->async_put_domains[1].bits, 332 POWER_DOMAIN_NUM); 333 } 334 335 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 336 337 static bool 338 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 339 { 340 struct intel_display *display = container_of(power_domains, 341 struct intel_display, 342 power.domains); 343 344 return !drm_WARN_ON(display->drm, 345 bitmap_intersects(power_domains->async_put_domains[0].bits, 346 power_domains->async_put_domains[1].bits, 347 POWER_DOMAIN_NUM)); 348 } 349 350 static bool 351 __async_put_domains_state_ok(struct i915_power_domains *power_domains) 352 { 353 struct intel_display *display = container_of(power_domains, 354 struct intel_display, 355 power.domains); 356 struct intel_power_domain_mask async_put_mask; 357 enum intel_display_power_domain domain; 358 bool err = false; 359 360 err |= !assert_async_put_domain_masks_disjoint(power_domains); 361 __async_put_domains_mask(power_domains, &async_put_mask); 362 err |= drm_WARN_ON(display->drm, 363 !!power_domains->async_put_wakeref != 364 !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)); 365 366 for_each_power_domain(domain, &async_put_mask) 367 err |= drm_WARN_ON(display->drm, 368 power_domains->domain_use_count[domain] != 1); 369 370 return !err; 371 } 372 373 static void print_power_domains(struct i915_power_domains *power_domains, 374 const char *prefix, struct intel_power_domain_mask *mask) 375 { 376 struct intel_display *display = container_of(power_domains, 377 struct intel_display, 378 power.domains); 379 enum intel_display_power_domain domain; 380 381 drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); 382 for_each_power_domain(domain, mask) 383 drm_dbg_kms(display->drm, "%s use_count %d\n", 384 intel_display_power_domain_str(domain), 385 power_domains->domain_use_count[domain]); 386 } 387 388 static void 389 print_async_put_domains_state(struct i915_power_domains *power_domains) 390 { 391 struct intel_display *display = container_of(power_domains, 392 struct intel_display, 393 power.domains); 394 395 drm_dbg_kms(display->drm, "async_put_wakeref: %s\n", 396 str_yes_no(power_domains->async_put_wakeref)); 397 398 print_power_domains(power_domains, "async_put_domains[0]", 399 &power_domains->async_put_domains[0]); 400 print_power_domains(power_domains, "async_put_domains[1]", 401 &power_domains->async_put_domains[1]); 402 } 403 404 static void 405 verify_async_put_domains_state(struct i915_power_domains *power_domains) 406 { 407 if (!__async_put_domains_state_ok(power_domains)) 408 print_async_put_domains_state(power_domains); 409 } 410 411 #else 412 413 static void 414 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 415 { 416 } 417 418 static void 419 verify_async_put_domains_state(struct i915_power_domains *power_domains) 420 { 421 } 422 423 #endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */ 424 425 static void async_put_domains_mask(struct i915_power_domains *power_domains, 426 struct intel_power_domain_mask *mask) 427 428 { 429 assert_async_put_domain_masks_disjoint(power_domains); 430 431 __async_put_domains_mask(power_domains, mask); 432 } 433 434 static void 435 async_put_domains_clear_domain(struct i915_power_domains *power_domains, 436 enum intel_display_power_domain domain) 437 { 438 assert_async_put_domain_masks_disjoint(power_domains); 439 440 clear_bit(domain, power_domains->async_put_domains[0].bits); 441 clear_bit(domain, power_domains->async_put_domains[1].bits); 442 } 443 444 static void 445 cancel_async_put_work(struct i915_power_domains *power_domains, bool sync) 446 { 447 if (sync) 448 cancel_delayed_work_sync(&power_domains->async_put_work); 449 else 450 cancel_delayed_work(&power_domains->async_put_work); 451 452 power_domains->async_put_next_delay = 0; 453 } 454 455 static bool 456 intel_display_power_grab_async_put_ref(struct intel_display *display, 457 enum intel_display_power_domain domain) 458 { 459 struct drm_i915_private *dev_priv = to_i915(display->drm); 460 struct i915_power_domains *power_domains = &display->power.domains; 461 struct intel_power_domain_mask async_put_mask; 462 bool ret = false; 463 464 async_put_domains_mask(power_domains, &async_put_mask); 465 if (!test_bit(domain, async_put_mask.bits)) 466 goto out_verify; 467 468 async_put_domains_clear_domain(power_domains, domain); 469 470 ret = true; 471 472 async_put_domains_mask(power_domains, &async_put_mask); 473 if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)) 474 goto out_verify; 475 476 cancel_async_put_work(power_domains, false); 477 intel_runtime_pm_put_raw(&dev_priv->runtime_pm, 478 fetch_and_zero(&power_domains->async_put_wakeref)); 479 out_verify: 480 verify_async_put_domains_state(power_domains); 481 482 return ret; 483 } 484 485 static void 486 __intel_display_power_get_domain(struct intel_display *display, 487 enum intel_display_power_domain domain) 488 { 489 struct i915_power_domains *power_domains = &display->power.domains; 490 struct i915_power_well *power_well; 491 492 if (intel_display_power_grab_async_put_ref(display, domain)) 493 return; 494 495 for_each_power_domain_well(display, power_well, domain) 496 intel_power_well_get(display, power_well); 497 498 power_domains->domain_use_count[domain]++; 499 } 500 501 /** 502 * intel_display_power_get - grab a power domain reference 503 * @dev_priv: i915 device instance 504 * @domain: power domain to reference 505 * 506 * This function grabs a power domain reference for @domain and ensures that the 507 * power domain and all its parents are powered up. Therefore users should only 508 * grab a reference to the innermost power domain they need. 509 * 510 * Any power domain reference obtained by this function must have a symmetric 511 * call to intel_display_power_put() to release the reference again. 512 */ 513 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 514 enum intel_display_power_domain domain) 515 { 516 struct intel_display *display = &dev_priv->display; 517 struct i915_power_domains *power_domains = &display->power.domains; 518 intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 519 520 mutex_lock(&power_domains->lock); 521 __intel_display_power_get_domain(display, domain); 522 mutex_unlock(&power_domains->lock); 523 524 return wakeref; 525 } 526 527 /** 528 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 529 * @dev_priv: i915 device instance 530 * @domain: power domain to reference 531 * 532 * This function grabs a power domain reference for @domain and ensures that the 533 * power domain and all its parents are powered up. Therefore users should only 534 * grab a reference to the innermost power domain they need. 535 * 536 * Any power domain reference obtained by this function must have a symmetric 537 * call to intel_display_power_put() to release the reference again. 538 */ 539 intel_wakeref_t 540 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 541 enum intel_display_power_domain domain) 542 { 543 struct intel_display *display = &dev_priv->display; 544 struct i915_power_domains *power_domains = &display->power.domains; 545 intel_wakeref_t wakeref; 546 bool is_enabled; 547 548 wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm); 549 if (!wakeref) 550 return NULL; 551 552 mutex_lock(&power_domains->lock); 553 554 if (__intel_display_power_is_enabled(display, domain)) { 555 __intel_display_power_get_domain(display, domain); 556 is_enabled = true; 557 } else { 558 is_enabled = false; 559 } 560 561 mutex_unlock(&power_domains->lock); 562 563 if (!is_enabled) { 564 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 565 wakeref = NULL; 566 } 567 568 return wakeref; 569 } 570 571 static void 572 __intel_display_power_put_domain(struct intel_display *display, 573 enum intel_display_power_domain domain) 574 { 575 struct i915_power_domains *power_domains = &display->power.domains; 576 struct i915_power_well *power_well; 577 const char *name = intel_display_power_domain_str(domain); 578 struct intel_power_domain_mask async_put_mask; 579 580 drm_WARN(display->drm, !power_domains->domain_use_count[domain], 581 "Use count on domain %s is already zero\n", 582 name); 583 async_put_domains_mask(power_domains, &async_put_mask); 584 drm_WARN(display->drm, 585 test_bit(domain, async_put_mask.bits), 586 "Async disabling of domain %s is pending\n", 587 name); 588 589 power_domains->domain_use_count[domain]--; 590 591 for_each_power_domain_well_reverse(display, power_well, domain) 592 intel_power_well_put(display, power_well); 593 } 594 595 static void __intel_display_power_put(struct intel_display *display, 596 enum intel_display_power_domain domain) 597 { 598 struct i915_power_domains *power_domains = &display->power.domains; 599 600 mutex_lock(&power_domains->lock); 601 __intel_display_power_put_domain(display, domain); 602 mutex_unlock(&power_domains->lock); 603 } 604 605 static void 606 queue_async_put_domains_work(struct i915_power_domains *power_domains, 607 intel_wakeref_t wakeref, 608 int delay_ms) 609 { 610 struct intel_display *display = container_of(power_domains, 611 struct intel_display, 612 power.domains); 613 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); 614 power_domains->async_put_wakeref = wakeref; 615 drm_WARN_ON(display->drm, !queue_delayed_work(system_unbound_wq, 616 &power_domains->async_put_work, 617 msecs_to_jiffies(delay_ms))); 618 } 619 620 static void 621 release_async_put_domains(struct i915_power_domains *power_domains, 622 struct intel_power_domain_mask *mask) 623 { 624 struct intel_display *display = container_of(power_domains, 625 struct intel_display, 626 power.domains); 627 struct drm_i915_private *dev_priv = to_i915(display->drm); 628 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 629 enum intel_display_power_domain domain; 630 intel_wakeref_t wakeref; 631 632 wakeref = intel_runtime_pm_get_noresume(rpm); 633 634 for_each_power_domain(domain, mask) { 635 /* Clear before put, so put's sanity check is happy. */ 636 async_put_domains_clear_domain(power_domains, domain); 637 __intel_display_power_put_domain(display, domain); 638 } 639 640 intel_runtime_pm_put(rpm, wakeref); 641 } 642 643 static void 644 intel_display_power_put_async_work(struct work_struct *work) 645 { 646 struct intel_display *display = container_of(work, struct intel_display, 647 power.domains.async_put_work.work); 648 struct drm_i915_private *dev_priv = to_i915(display->drm); 649 struct i915_power_domains *power_domains = &display->power.domains; 650 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 651 intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm); 652 intel_wakeref_t old_work_wakeref = NULL; 653 654 mutex_lock(&power_domains->lock); 655 656 /* 657 * Bail out if all the domain refs pending to be released were grabbed 658 * by subsequent gets or a flush_work. 659 */ 660 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 661 if (!old_work_wakeref) 662 goto out_verify; 663 664 release_async_put_domains(power_domains, 665 &power_domains->async_put_domains[0]); 666 667 /* 668 * Cancel the work that got queued after this one got dequeued, 669 * since here we released the corresponding async-put reference. 670 */ 671 cancel_async_put_work(power_domains, false); 672 673 /* Requeue the work if more domains were async put meanwhile. */ 674 if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) { 675 bitmap_copy(power_domains->async_put_domains[0].bits, 676 power_domains->async_put_domains[1].bits, 677 POWER_DOMAIN_NUM); 678 bitmap_zero(power_domains->async_put_domains[1].bits, 679 POWER_DOMAIN_NUM); 680 queue_async_put_domains_work(power_domains, 681 fetch_and_zero(&new_work_wakeref), 682 power_domains->async_put_next_delay); 683 power_domains->async_put_next_delay = 0; 684 } 685 686 out_verify: 687 verify_async_put_domains_state(power_domains); 688 689 mutex_unlock(&power_domains->lock); 690 691 if (old_work_wakeref) 692 intel_runtime_pm_put_raw(rpm, old_work_wakeref); 693 if (new_work_wakeref) 694 intel_runtime_pm_put_raw(rpm, new_work_wakeref); 695 } 696 697 /** 698 * __intel_display_power_put_async - release a power domain reference asynchronously 699 * @i915: i915 device instance 700 * @domain: power domain to reference 701 * @wakeref: wakeref acquired for the reference that is being released 702 * @delay_ms: delay of powering down the power domain 703 * 704 * This function drops the power domain reference obtained by 705 * intel_display_power_get*() and schedules a work to power down the 706 * corresponding hardware block if this is the last reference. 707 * The power down is delayed by @delay_ms if this is >= 0, or by a default 708 * 100 ms otherwise. 709 */ 710 void __intel_display_power_put_async(struct drm_i915_private *i915, 711 enum intel_display_power_domain domain, 712 intel_wakeref_t wakeref, 713 int delay_ms) 714 { 715 struct intel_display *display = &i915->display; 716 struct i915_power_domains *power_domains = &display->power.domains; 717 struct intel_runtime_pm *rpm = &i915->runtime_pm; 718 intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm); 719 720 delay_ms = delay_ms >= 0 ? delay_ms : 100; 721 722 mutex_lock(&power_domains->lock); 723 724 if (power_domains->domain_use_count[domain] > 1) { 725 __intel_display_power_put_domain(display, domain); 726 727 goto out_verify; 728 } 729 730 drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1); 731 732 /* Let a pending work requeue itself or queue a new one. */ 733 if (power_domains->async_put_wakeref) { 734 set_bit(domain, power_domains->async_put_domains[1].bits); 735 power_domains->async_put_next_delay = max(power_domains->async_put_next_delay, 736 delay_ms); 737 } else { 738 set_bit(domain, power_domains->async_put_domains[0].bits); 739 queue_async_put_domains_work(power_domains, 740 fetch_and_zero(&work_wakeref), 741 delay_ms); 742 } 743 744 out_verify: 745 verify_async_put_domains_state(power_domains); 746 747 mutex_unlock(&power_domains->lock); 748 749 if (work_wakeref) 750 intel_runtime_pm_put_raw(rpm, work_wakeref); 751 752 intel_runtime_pm_put(rpm, wakeref); 753 } 754 755 /** 756 * intel_display_power_flush_work - flushes the async display power disabling work 757 * @i915: i915 device instance 758 * 759 * Flushes any pending work that was scheduled by a preceding 760 * intel_display_power_put_async() call, completing the disabling of the 761 * corresponding power domains. 762 * 763 * Note that the work handler function may still be running after this 764 * function returns; to ensure that the work handler isn't running use 765 * intel_display_power_flush_work_sync() instead. 766 */ 767 void intel_display_power_flush_work(struct drm_i915_private *i915) 768 { 769 struct intel_display *display = &i915->display; 770 struct i915_power_domains *power_domains = &display->power.domains; 771 struct intel_power_domain_mask async_put_mask; 772 intel_wakeref_t work_wakeref; 773 774 mutex_lock(&power_domains->lock); 775 776 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 777 if (!work_wakeref) 778 goto out_verify; 779 780 async_put_domains_mask(power_domains, &async_put_mask); 781 release_async_put_domains(power_domains, &async_put_mask); 782 cancel_async_put_work(power_domains, false); 783 784 out_verify: 785 verify_async_put_domains_state(power_domains); 786 787 mutex_unlock(&power_domains->lock); 788 789 if (work_wakeref) 790 intel_runtime_pm_put_raw(&i915->runtime_pm, work_wakeref); 791 } 792 793 /** 794 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work 795 * @display: display device instance 796 * 797 * Like intel_display_power_flush_work(), but also ensure that the work 798 * handler function is not running any more when this function returns. 799 */ 800 static void 801 intel_display_power_flush_work_sync(struct intel_display *display) 802 { 803 struct drm_i915_private *i915 = to_i915(display->drm); 804 struct i915_power_domains *power_domains = &display->power.domains; 805 806 intel_display_power_flush_work(i915); 807 cancel_async_put_work(power_domains, true); 808 809 verify_async_put_domains_state(power_domains); 810 811 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); 812 } 813 814 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 815 /** 816 * intel_display_power_put - release a power domain reference 817 * @dev_priv: i915 device instance 818 * @domain: power domain to reference 819 * @wakeref: wakeref acquired for the reference that is being released 820 * 821 * This function drops the power domain reference obtained by 822 * intel_display_power_get() and might power down the corresponding hardware 823 * block right away if this is the last reference. 824 */ 825 void intel_display_power_put(struct drm_i915_private *dev_priv, 826 enum intel_display_power_domain domain, 827 intel_wakeref_t wakeref) 828 { 829 struct intel_display *display = &dev_priv->display; 830 831 __intel_display_power_put(display, domain); 832 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 833 } 834 #else 835 /** 836 * intel_display_power_put_unchecked - release an unchecked power domain reference 837 * @dev_priv: i915 device instance 838 * @domain: power domain to reference 839 * 840 * This function drops the power domain reference obtained by 841 * intel_display_power_get() and might power down the corresponding hardware 842 * block right away if this is the last reference. 843 * 844 * This function is only for the power domain code's internal use to suppress wakeref 845 * tracking when the correspondig debug kconfig option is disabled, should not 846 * be used otherwise. 847 */ 848 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 849 enum intel_display_power_domain domain) 850 { 851 struct intel_display *display = &dev_priv->display; 852 853 __intel_display_power_put(display, domain); 854 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); 855 } 856 #endif 857 858 void 859 intel_display_power_get_in_set(struct drm_i915_private *i915, 860 struct intel_display_power_domain_set *power_domain_set, 861 enum intel_display_power_domain domain) 862 { 863 struct intel_display *display = &i915->display; 864 intel_wakeref_t __maybe_unused wf; 865 866 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); 867 868 wf = intel_display_power_get(i915, domain); 869 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 870 power_domain_set->wakerefs[domain] = wf; 871 #endif 872 set_bit(domain, power_domain_set->mask.bits); 873 } 874 875 bool 876 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 877 struct intel_display_power_domain_set *power_domain_set, 878 enum intel_display_power_domain domain) 879 { 880 struct intel_display *display = &i915->display; 881 intel_wakeref_t wf; 882 883 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); 884 885 wf = intel_display_power_get_if_enabled(i915, domain); 886 if (!wf) 887 return false; 888 889 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 890 power_domain_set->wakerefs[domain] = wf; 891 #endif 892 set_bit(domain, power_domain_set->mask.bits); 893 894 return true; 895 } 896 897 void 898 intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 899 struct intel_display_power_domain_set *power_domain_set, 900 struct intel_power_domain_mask *mask) 901 { 902 struct intel_display *display = &i915->display; 903 enum intel_display_power_domain domain; 904 905 drm_WARN_ON(display->drm, 906 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM)); 907 908 for_each_power_domain(domain, mask) { 909 intel_wakeref_t __maybe_unused wf = INTEL_WAKEREF_DEF; 910 911 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 912 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]); 913 #endif 914 intel_display_power_put(i915, domain, wf); 915 clear_bit(domain, power_domain_set->mask.bits); 916 } 917 } 918 919 static int 920 sanitize_disable_power_well_option(int disable_power_well) 921 { 922 if (disable_power_well >= 0) 923 return !!disable_power_well; 924 925 return 1; 926 } 927 928 static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc) 929 { 930 u32 mask; 931 int requested_dc; 932 int max_dc; 933 934 if (!HAS_DISPLAY(display)) 935 return 0; 936 937 if (DISPLAY_VER(display) >= 20) 938 max_dc = 2; 939 else if (display->platform.dg2) 940 max_dc = 1; 941 else if (display->platform.dg1) 942 max_dc = 3; 943 else if (DISPLAY_VER(display) >= 12) 944 max_dc = 4; 945 else if (display->platform.geminilake || display->platform.broxton) 946 max_dc = 1; 947 else if (DISPLAY_VER(display) >= 9) 948 max_dc = 2; 949 else 950 max_dc = 0; 951 952 /* 953 * DC9 has a separate HW flow from the rest of the DC states, 954 * not depending on the DMC firmware. It's needed by system 955 * suspend/resume, so allow it unconditionally. 956 */ 957 mask = display->platform.geminilake || display->platform.broxton || 958 DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0; 959 960 if (!display->params.disable_power_well) 961 max_dc = 0; 962 963 if (enable_dc >= 0 && enable_dc <= max_dc) { 964 requested_dc = enable_dc; 965 } else if (enable_dc == -1) { 966 requested_dc = max_dc; 967 } else if (enable_dc > max_dc && enable_dc <= 4) { 968 drm_dbg_kms(display->drm, 969 "Adjusting requested max DC state (%d->%d)\n", 970 enable_dc, max_dc); 971 requested_dc = max_dc; 972 } else { 973 drm_err(display->drm, 974 "Unexpected value for enable_dc (%d)\n", enable_dc); 975 requested_dc = max_dc; 976 } 977 978 switch (requested_dc) { 979 case 4: 980 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6; 981 break; 982 case 3: 983 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5; 984 break; 985 case 2: 986 mask |= DC_STATE_EN_UPTO_DC6; 987 break; 988 case 1: 989 mask |= DC_STATE_EN_UPTO_DC5; 990 break; 991 } 992 993 drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask); 994 995 return mask; 996 } 997 998 /** 999 * intel_power_domains_init - initializes the power domain structures 1000 * @display: display device instance 1001 * 1002 * Initializes the power domain structures for @dev_priv depending upon the 1003 * supported platform. 1004 */ 1005 int intel_power_domains_init(struct intel_display *display) 1006 { 1007 struct i915_power_domains *power_domains = &display->power.domains; 1008 1009 display->params.disable_power_well = 1010 sanitize_disable_power_well_option(display->params.disable_power_well); 1011 power_domains->allowed_dc_mask = 1012 get_allowed_dc_mask(display, display->params.enable_dc); 1013 1014 power_domains->target_dc_state = 1015 sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1016 1017 mutex_init(&power_domains->lock); 1018 1019 INIT_DELAYED_WORK(&power_domains->async_put_work, 1020 intel_display_power_put_async_work); 1021 1022 return intel_display_power_map_init(power_domains); 1023 } 1024 1025 /** 1026 * intel_power_domains_cleanup - clean up power domains resources 1027 * @display: display device instance 1028 * 1029 * Release any resources acquired by intel_power_domains_init() 1030 */ 1031 void intel_power_domains_cleanup(struct intel_display *display) 1032 { 1033 intel_display_power_map_cleanup(&display->power.domains); 1034 } 1035 1036 static void intel_power_domains_sync_hw(struct intel_display *display) 1037 { 1038 struct i915_power_domains *power_domains = &display->power.domains; 1039 struct i915_power_well *power_well; 1040 1041 mutex_lock(&power_domains->lock); 1042 for_each_power_well(display, power_well) 1043 intel_power_well_sync_hw(display, power_well); 1044 mutex_unlock(&power_domains->lock); 1045 } 1046 1047 static void gen9_dbuf_slice_set(struct intel_display *display, 1048 enum dbuf_slice slice, bool enable) 1049 { 1050 i915_reg_t reg = DBUF_CTL_S(slice); 1051 bool state; 1052 1053 intel_de_rmw(display, reg, DBUF_POWER_REQUEST, 1054 enable ? DBUF_POWER_REQUEST : 0); 1055 intel_de_posting_read(display, reg); 1056 udelay(10); 1057 1058 state = intel_de_read(display, reg) & DBUF_POWER_STATE; 1059 drm_WARN(display->drm, enable != state, 1060 "DBuf slice %d power %s timeout!\n", 1061 slice, str_enable_disable(enable)); 1062 } 1063 1064 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 1065 u8 req_slices) 1066 { 1067 struct intel_display *display = &dev_priv->display; 1068 struct i915_power_domains *power_domains = &display->power.domains; 1069 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; 1070 enum dbuf_slice slice; 1071 1072 drm_WARN(display->drm, req_slices & ~slice_mask, 1073 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n", 1074 req_slices, slice_mask); 1075 1076 drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n", 1077 req_slices); 1078 1079 /* 1080 * Might be running this in parallel to gen9_dc_off_power_well_enable 1081 * being called from intel_dp_detect for instance, 1082 * which causes assertion triggered by race condition, 1083 * as gen9_assert_dbuf_enabled might preempt this when registers 1084 * were already updated, while dev_priv was not. 1085 */ 1086 mutex_lock(&power_domains->lock); 1087 1088 for_each_dbuf_slice(display, slice) 1089 gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice)); 1090 1091 display->dbuf.enabled_slices = req_slices; 1092 1093 mutex_unlock(&power_domains->lock); 1094 } 1095 1096 static void gen9_dbuf_enable(struct intel_display *display) 1097 { 1098 struct drm_i915_private *dev_priv = to_i915(display->drm); 1099 u8 slices_mask; 1100 1101 display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); 1102 1103 slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices; 1104 1105 if (DISPLAY_VER(display) >= 14) 1106 intel_pmdemand_program_dbuf(display, slices_mask); 1107 1108 /* 1109 * Just power up at least 1 slice, we will 1110 * figure out later which slices we have and what we need. 1111 */ 1112 gen9_dbuf_slices_update(dev_priv, slices_mask); 1113 } 1114 1115 static void gen9_dbuf_disable(struct intel_display *display) 1116 { 1117 struct drm_i915_private *dev_priv = to_i915(display->drm); 1118 1119 gen9_dbuf_slices_update(dev_priv, 0); 1120 1121 if (DISPLAY_VER(display) >= 14) 1122 intel_pmdemand_program_dbuf(display, 0); 1123 } 1124 1125 static void gen12_dbuf_slices_config(struct intel_display *display) 1126 { 1127 enum dbuf_slice slice; 1128 1129 for_each_dbuf_slice(display, slice) 1130 intel_de_rmw(display, DBUF_CTL_S(slice), 1131 DBUF_TRACKER_STATE_SERVICE_MASK, 1132 DBUF_TRACKER_STATE_SERVICE(8)); 1133 } 1134 1135 static void icl_mbus_init(struct intel_display *display) 1136 { 1137 unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask; 1138 u32 mask, val, i; 1139 1140 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1141 return; 1142 1143 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | 1144 MBUS_ABOX_BT_CREDIT_POOL2_MASK | 1145 MBUS_ABOX_B_CREDIT_MASK | 1146 MBUS_ABOX_BW_CREDIT_MASK; 1147 val = MBUS_ABOX_BT_CREDIT_POOL1(16) | 1148 MBUS_ABOX_BT_CREDIT_POOL2(16) | 1149 MBUS_ABOX_B_CREDIT(1) | 1150 MBUS_ABOX_BW_CREDIT(1); 1151 1152 /* 1153 * gen12 platforms that use abox1 and abox2 for pixel data reads still 1154 * expect us to program the abox_ctl0 register as well, even though 1155 * we don't have to program other instance-0 registers like BW_BUDDY. 1156 */ 1157 if (DISPLAY_VER(display) == 12) 1158 abox_regs |= BIT(0); 1159 1160 for_each_set_bit(i, &abox_regs, sizeof(abox_regs)) 1161 intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val); 1162 } 1163 1164 static void hsw_assert_cdclk(struct intel_display *display) 1165 { 1166 u32 val = intel_de_read(display, LCPLL_CTL); 1167 1168 /* 1169 * The LCPLL register should be turned on by the BIOS. For now 1170 * let's just check its state and print errors in case 1171 * something is wrong. Don't even try to turn it on. 1172 */ 1173 1174 if (val & LCPLL_CD_SOURCE_FCLK) 1175 drm_err(display->drm, "CDCLK source is not LCPLL\n"); 1176 1177 if (val & LCPLL_PLL_DISABLE) 1178 drm_err(display->drm, "LCPLL is disabled\n"); 1179 1180 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC) 1181 drm_err(display->drm, "LCPLL not using non-SSC reference\n"); 1182 } 1183 1184 static void assert_can_disable_lcpll(struct intel_display *display) 1185 { 1186 struct drm_i915_private *dev_priv = to_i915(display->drm); 1187 struct intel_crtc *crtc; 1188 1189 for_each_intel_crtc(display->drm, crtc) 1190 INTEL_DISPLAY_STATE_WARN(display, crtc->active, 1191 "CRTC for pipe %c enabled\n", 1192 pipe_name(crtc->pipe)); 1193 1194 INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2), 1195 "Display power well on\n"); 1196 INTEL_DISPLAY_STATE_WARN(display, 1197 intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE, 1198 "SPLL enabled\n"); 1199 INTEL_DISPLAY_STATE_WARN(display, 1200 intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, 1201 "WRPLL1 enabled\n"); 1202 INTEL_DISPLAY_STATE_WARN(display, 1203 intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, 1204 "WRPLL2 enabled\n"); 1205 INTEL_DISPLAY_STATE_WARN(display, 1206 intel_de_read(display, PP_STATUS(display, 0)) & PP_ON, 1207 "Panel power on\n"); 1208 INTEL_DISPLAY_STATE_WARN(display, 1209 intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 1210 "CPU PWM1 enabled\n"); 1211 if (display->platform.haswell) 1212 INTEL_DISPLAY_STATE_WARN(display, 1213 intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 1214 "CPU PWM2 enabled\n"); 1215 INTEL_DISPLAY_STATE_WARN(display, 1216 intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, 1217 "PCH PWM1 enabled\n"); 1218 INTEL_DISPLAY_STATE_WARN(display, 1219 (intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 1220 "Utility pin enabled in PWM mode\n"); 1221 INTEL_DISPLAY_STATE_WARN(display, 1222 intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE, 1223 "PCH GTC enabled\n"); 1224 1225 /* 1226 * In theory we can still leave IRQs enabled, as long as only the HPD 1227 * interrupts remain enabled. We used to check for that, but since it's 1228 * gen-specific and since we only disable LCPLL after we fully disable 1229 * the interrupts, the check below should be enough. 1230 */ 1231 INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv), 1232 "IRQs enabled\n"); 1233 } 1234 1235 static u32 hsw_read_dcomp(struct intel_display *display) 1236 { 1237 if (display->platform.haswell) 1238 return intel_de_read(display, D_COMP_HSW); 1239 else 1240 return intel_de_read(display, D_COMP_BDW); 1241 } 1242 1243 static void hsw_write_dcomp(struct intel_display *display, u32 val) 1244 { 1245 struct drm_i915_private *dev_priv = to_i915(display->drm); 1246 1247 if (display->platform.haswell) { 1248 if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val)) 1249 drm_dbg_kms(display->drm, "Failed to write to D_COMP\n"); 1250 } else { 1251 intel_de_write(display, D_COMP_BDW, val); 1252 intel_de_posting_read(display, D_COMP_BDW); 1253 } 1254 } 1255 1256 /* 1257 * This function implements pieces of two sequences from BSpec: 1258 * - Sequence for display software to disable LCPLL 1259 * - Sequence for display software to allow package C8+ 1260 * The steps implemented here are just the steps that actually touch the LCPLL 1261 * register. Callers should take care of disabling all the display engine 1262 * functions, doing the mode unset, fixing interrupts, etc. 1263 */ 1264 static void hsw_disable_lcpll(struct intel_display *display, 1265 bool switch_to_fclk, bool allow_power_down) 1266 { 1267 u32 val; 1268 1269 assert_can_disable_lcpll(display); 1270 1271 val = intel_de_read(display, LCPLL_CTL); 1272 1273 if (switch_to_fclk) { 1274 val |= LCPLL_CD_SOURCE_FCLK; 1275 intel_de_write(display, LCPLL_CTL, val); 1276 1277 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & 1278 LCPLL_CD_SOURCE_FCLK_DONE, 1)) 1279 drm_err(display->drm, "Switching to FCLK failed\n"); 1280 1281 val = intel_de_read(display, LCPLL_CTL); 1282 } 1283 1284 val |= LCPLL_PLL_DISABLE; 1285 intel_de_write(display, LCPLL_CTL, val); 1286 intel_de_posting_read(display, LCPLL_CTL); 1287 1288 if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) 1289 drm_err(display->drm, "LCPLL still locked\n"); 1290 1291 val = hsw_read_dcomp(display); 1292 val |= D_COMP_COMP_DISABLE; 1293 hsw_write_dcomp(display, val); 1294 ndelay(100); 1295 1296 if (wait_for((hsw_read_dcomp(display) & 1297 D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) 1298 drm_err(display->drm, "D_COMP RCOMP still in progress\n"); 1299 1300 if (allow_power_down) { 1301 intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); 1302 intel_de_posting_read(display, LCPLL_CTL); 1303 } 1304 } 1305 1306 /* 1307 * Fully restores LCPLL, disallowing power down and switching back to LCPLL 1308 * source. 1309 */ 1310 static void hsw_restore_lcpll(struct intel_display *display) 1311 { 1312 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); 1313 u32 val; 1314 1315 val = intel_de_read(display, LCPLL_CTL); 1316 1317 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | 1318 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) 1319 return; 1320 1321 /* 1322 * Make sure we're not on PC8 state before disabling PC8, otherwise 1323 * we'll hang the machine. To prevent PC8 state, just enable force_wake. 1324 */ 1325 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); 1326 1327 if (val & LCPLL_POWER_DOWN_ALLOW) { 1328 val &= ~LCPLL_POWER_DOWN_ALLOW; 1329 intel_de_write(display, LCPLL_CTL, val); 1330 intel_de_posting_read(display, LCPLL_CTL); 1331 } 1332 1333 val = hsw_read_dcomp(display); 1334 val |= D_COMP_COMP_FORCE; 1335 val &= ~D_COMP_COMP_DISABLE; 1336 hsw_write_dcomp(display, val); 1337 1338 val = intel_de_read(display, LCPLL_CTL); 1339 val &= ~LCPLL_PLL_DISABLE; 1340 intel_de_write(display, LCPLL_CTL, val); 1341 1342 if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) 1343 drm_err(display->drm, "LCPLL not locked yet\n"); 1344 1345 if (val & LCPLL_CD_SOURCE_FCLK) { 1346 intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); 1347 1348 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & 1349 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 1350 drm_err(display->drm, 1351 "Switching back to LCPLL failed\n"); 1352 } 1353 1354 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); 1355 1356 intel_update_cdclk(display); 1357 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1358 } 1359 1360 /* 1361 * Package states C8 and deeper are really deep PC states that can only be 1362 * reached when all the devices on the system allow it, so even if the graphics 1363 * device allows PC8+, it doesn't mean the system will actually get to these 1364 * states. Our driver only allows PC8+ when going into runtime PM. 1365 * 1366 * The requirements for PC8+ are that all the outputs are disabled, the power 1367 * well is disabled and most interrupts are disabled, and these are also 1368 * requirements for runtime PM. When these conditions are met, we manually do 1369 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk 1370 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard 1371 * hang the machine. 1372 * 1373 * When we really reach PC8 or deeper states (not just when we allow it) we lose 1374 * the state of some registers, so when we come back from PC8+ we need to 1375 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't 1376 * need to take care of the registers kept by RC6. Notice that this happens even 1377 * if we don't put the device in PCI D3 state (which is what currently happens 1378 * because of the runtime PM support). 1379 * 1380 * For more, read "Display Sequences for Package C8" on the hardware 1381 * documentation. 1382 */ 1383 static void hsw_enable_pc8(struct intel_display *display) 1384 { 1385 struct drm_i915_private *dev_priv = to_i915(display->drm); 1386 1387 drm_dbg_kms(display->drm, "Enabling package C8+\n"); 1388 1389 if (HAS_PCH_LPT_LP(dev_priv)) 1390 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1391 PCH_LP_PARTITION_LEVEL_DISABLE, 0); 1392 1393 lpt_disable_clkout_dp(dev_priv); 1394 hsw_disable_lcpll(display, true, true); 1395 } 1396 1397 static void hsw_disable_pc8(struct intel_display *display) 1398 { 1399 struct drm_i915_private *dev_priv = to_i915(display->drm); 1400 1401 drm_dbg_kms(display->drm, "Disabling package C8+\n"); 1402 1403 hsw_restore_lcpll(display); 1404 intel_init_pch_refclk(dev_priv); 1405 1406 /* Many display registers don't survive PC8+ */ 1407 #ifdef I915 /* FIXME */ 1408 intel_clock_gating_init(dev_priv); 1409 #endif 1410 } 1411 1412 static void intel_pch_reset_handshake(struct intel_display *display, 1413 bool enable) 1414 { 1415 i915_reg_t reg; 1416 u32 reset_bits; 1417 1418 if (display->platform.ivybridge) { 1419 reg = GEN7_MSG_CTL; 1420 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK; 1421 } else { 1422 reg = HSW_NDE_RSTWRN_OPT; 1423 reset_bits = RESET_PCH_HANDSHAKE_ENABLE; 1424 } 1425 1426 if (DISPLAY_VER(display) >= 14) 1427 reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; 1428 1429 intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0); 1430 } 1431 1432 static void skl_display_core_init(struct intel_display *display, 1433 bool resume) 1434 { 1435 struct drm_i915_private *dev_priv = to_i915(display->drm); 1436 struct i915_power_domains *power_domains = &display->power.domains; 1437 struct i915_power_well *well; 1438 1439 gen9_set_dc_state(display, DC_STATE_DISABLE); 1440 1441 /* enable PCH reset handshake */ 1442 intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv)); 1443 1444 if (!HAS_DISPLAY(display)) 1445 return; 1446 1447 /* enable PG1 and Misc I/O */ 1448 mutex_lock(&power_domains->lock); 1449 1450 well = lookup_power_well(display, SKL_DISP_PW_1); 1451 intel_power_well_enable(display, well); 1452 1453 well = lookup_power_well(display, SKL_DISP_PW_MISC_IO); 1454 intel_power_well_enable(display, well); 1455 1456 mutex_unlock(&power_domains->lock); 1457 1458 intel_cdclk_init_hw(display); 1459 1460 gen9_dbuf_enable(display); 1461 1462 if (resume) 1463 intel_dmc_load_program(display); 1464 } 1465 1466 static void skl_display_core_uninit(struct intel_display *display) 1467 { 1468 struct i915_power_domains *power_domains = &display->power.domains; 1469 struct i915_power_well *well; 1470 1471 if (!HAS_DISPLAY(display)) 1472 return; 1473 1474 gen9_disable_dc_states(display); 1475 /* TODO: disable DMC program */ 1476 1477 gen9_dbuf_disable(display); 1478 1479 intel_cdclk_uninit_hw(display); 1480 1481 /* The spec doesn't call for removing the reset handshake flag */ 1482 /* disable PG1 and Misc I/O */ 1483 1484 mutex_lock(&power_domains->lock); 1485 1486 /* 1487 * BSpec says to keep the MISC IO power well enabled here, only 1488 * remove our request for power well 1. 1489 * Note that even though the driver's request is removed power well 1 1490 * may stay enabled after this due to DMC's own request on it. 1491 */ 1492 well = lookup_power_well(display, SKL_DISP_PW_1); 1493 intel_power_well_disable(display, well); 1494 1495 mutex_unlock(&power_domains->lock); 1496 1497 usleep_range(10, 30); /* 10 us delay per Bspec */ 1498 } 1499 1500 static void bxt_display_core_init(struct intel_display *display, bool resume) 1501 { 1502 struct i915_power_domains *power_domains = &display->power.domains; 1503 struct i915_power_well *well; 1504 1505 gen9_set_dc_state(display, DC_STATE_DISABLE); 1506 1507 /* 1508 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 1509 * or else the reset will hang because there is no PCH to respond. 1510 * Move the handshake programming to initialization sequence. 1511 * Previously was left up to BIOS. 1512 */ 1513 intel_pch_reset_handshake(display, false); 1514 1515 if (!HAS_DISPLAY(display)) 1516 return; 1517 1518 /* Enable PG1 */ 1519 mutex_lock(&power_domains->lock); 1520 1521 well = lookup_power_well(display, SKL_DISP_PW_1); 1522 intel_power_well_enable(display, well); 1523 1524 mutex_unlock(&power_domains->lock); 1525 1526 intel_cdclk_init_hw(display); 1527 1528 gen9_dbuf_enable(display); 1529 1530 if (resume) 1531 intel_dmc_load_program(display); 1532 } 1533 1534 static void bxt_display_core_uninit(struct intel_display *display) 1535 { 1536 struct i915_power_domains *power_domains = &display->power.domains; 1537 struct i915_power_well *well; 1538 1539 if (!HAS_DISPLAY(display)) 1540 return; 1541 1542 gen9_disable_dc_states(display); 1543 /* TODO: disable DMC program */ 1544 1545 gen9_dbuf_disable(display); 1546 1547 intel_cdclk_uninit_hw(display); 1548 1549 /* The spec doesn't call for removing the reset handshake flag */ 1550 1551 /* 1552 * Disable PW1 (PG1). 1553 * Note that even though the driver's request is removed power well 1 1554 * may stay enabled after this due to DMC's own request on it. 1555 */ 1556 mutex_lock(&power_domains->lock); 1557 1558 well = lookup_power_well(display, SKL_DISP_PW_1); 1559 intel_power_well_disable(display, well); 1560 1561 mutex_unlock(&power_domains->lock); 1562 1563 usleep_range(10, 30); /* 10 us delay per Bspec */ 1564 } 1565 1566 struct buddy_page_mask { 1567 u32 page_mask; 1568 u8 type; 1569 u8 num_channels; 1570 }; 1571 1572 static const struct buddy_page_mask tgl_buddy_page_masks[] = { 1573 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF }, 1574 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF }, 1575 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C }, 1576 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C }, 1577 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F }, 1578 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E }, 1579 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 }, 1580 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 }, 1581 {} 1582 }; 1583 1584 static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = { 1585 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 }, 1586 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 }, 1587 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 }, 1588 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 }, 1589 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 }, 1590 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 }, 1591 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 }, 1592 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 }, 1593 {} 1594 }; 1595 1596 static void tgl_bw_buddy_init(struct intel_display *display) 1597 { 1598 struct drm_i915_private *dev_priv = to_i915(display->drm); 1599 enum intel_dram_type type = dev_priv->dram_info.type; 1600 u8 num_channels = dev_priv->dram_info.num_channels; 1601 const struct buddy_page_mask *table; 1602 unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; 1603 int config, i; 1604 1605 /* BW_BUDDY registers are not used on dgpu's beyond DG1 */ 1606 if (display->platform.dgfx && !display->platform.dg1) 1607 return; 1608 1609 if (display->platform.alderlake_s || 1610 (display->platform.rocketlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))) 1611 /* Wa_1409767108 */ 1612 table = wa_1409767108_buddy_page_masks; 1613 else 1614 table = tgl_buddy_page_masks; 1615 1616 for (config = 0; table[config].page_mask != 0; config++) 1617 if (table[config].num_channels == num_channels && 1618 table[config].type == type) 1619 break; 1620 1621 if (table[config].page_mask == 0) { 1622 drm_dbg_kms(display->drm, 1623 "Unknown memory configuration; disabling address buddy logic.\n"); 1624 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) 1625 intel_de_write(display, BW_BUDDY_CTL(i), 1626 BW_BUDDY_DISABLE); 1627 } else { 1628 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) { 1629 intel_de_write(display, BW_BUDDY_PAGE_MASK(i), 1630 table[config].page_mask); 1631 1632 /* Wa_22010178259:tgl,dg1,rkl,adl-s */ 1633 if (DISPLAY_VER(display) == 12) 1634 intel_de_rmw(display, BW_BUDDY_CTL(i), 1635 BW_BUDDY_TLB_REQ_TIMER_MASK, 1636 BW_BUDDY_TLB_REQ_TIMER(0x8)); 1637 } 1638 } 1639 } 1640 1641 static void icl_display_core_init(struct intel_display *display, 1642 bool resume) 1643 { 1644 struct drm_i915_private *dev_priv = to_i915(display->drm); 1645 struct i915_power_domains *power_domains = &display->power.domains; 1646 struct i915_power_well *well; 1647 1648 gen9_set_dc_state(display, DC_STATE_DISABLE); 1649 1650 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ 1651 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && 1652 INTEL_PCH_TYPE(dev_priv) < PCH_DG1) 1653 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0, 1654 PCH_DPMGUNIT_CLOCK_GATE_DISABLE); 1655 1656 /* 1. Enable PCH reset handshake. */ 1657 intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv)); 1658 1659 if (!HAS_DISPLAY(display)) 1660 return; 1661 1662 /* 2. Initialize all combo phys */ 1663 intel_combo_phy_init(dev_priv); 1664 1665 /* 1666 * 3. Enable Power Well 1 (PG1). 1667 * The AUX IO power wells will be enabled on demand. 1668 */ 1669 mutex_lock(&power_domains->lock); 1670 well = lookup_power_well(display, SKL_DISP_PW_1); 1671 intel_power_well_enable(display, well); 1672 mutex_unlock(&power_domains->lock); 1673 1674 if (DISPLAY_VER(display) == 14) 1675 intel_de_rmw(display, DC_STATE_EN, 1676 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0); 1677 1678 /* 4. Enable CDCLK. */ 1679 intel_cdclk_init_hw(display); 1680 1681 if (DISPLAY_VER(display) == 12 || display->platform.dg2) 1682 gen12_dbuf_slices_config(display); 1683 1684 /* 5. Enable DBUF. */ 1685 gen9_dbuf_enable(display); 1686 1687 /* 6. Setup MBUS. */ 1688 icl_mbus_init(display); 1689 1690 /* 7. Program arbiter BW_BUDDY registers */ 1691 if (DISPLAY_VER(display) >= 12) 1692 tgl_bw_buddy_init(display); 1693 1694 /* 8. Ensure PHYs have completed calibration and adaptation */ 1695 if (display->platform.dg2) 1696 intel_snps_phy_wait_for_calibration(dev_priv); 1697 1698 /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ 1699 if (DISPLAY_VERx100(display) == 1401) 1700 intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); 1701 1702 if (resume) 1703 intel_dmc_load_program(display); 1704 1705 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */ 1706 if (IS_DISPLAY_VERx100(display, 1200, 1300)) 1707 intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0, 1708 DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | 1709 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR); 1710 1711 /* Wa_14011503030:xelpd */ 1712 if (DISPLAY_VER(display) == 13) 1713 intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); 1714 1715 /* Wa_15013987218 */ 1716 if (DISPLAY_VER(display) == 20) { 1717 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1718 0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE); 1719 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1720 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0); 1721 } 1722 } 1723 1724 static void icl_display_core_uninit(struct intel_display *display) 1725 { 1726 struct drm_i915_private *dev_priv = to_i915(display->drm); 1727 struct i915_power_domains *power_domains = &display->power.domains; 1728 struct i915_power_well *well; 1729 1730 if (!HAS_DISPLAY(display)) 1731 return; 1732 1733 gen9_disable_dc_states(display); 1734 intel_dmc_disable_program(display); 1735 1736 /* 1. Disable all display engine functions -> aready done */ 1737 1738 /* 2. Disable DBUF */ 1739 gen9_dbuf_disable(display); 1740 1741 /* 3. Disable CD clock */ 1742 intel_cdclk_uninit_hw(display); 1743 1744 if (DISPLAY_VER(display) == 14) 1745 intel_de_rmw(display, DC_STATE_EN, 0, 1746 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH); 1747 1748 /* 1749 * 4. Disable Power Well 1 (PG1). 1750 * The AUX IO power wells are toggled on demand, so they are already 1751 * disabled at this point. 1752 */ 1753 mutex_lock(&power_domains->lock); 1754 well = lookup_power_well(display, SKL_DISP_PW_1); 1755 intel_power_well_disable(display, well); 1756 mutex_unlock(&power_domains->lock); 1757 1758 /* 5. */ 1759 intel_combo_phy_uninit(dev_priv); 1760 } 1761 1762 static void chv_phy_control_init(struct intel_display *display) 1763 { 1764 struct i915_power_well *cmn_bc = 1765 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1766 struct i915_power_well *cmn_d = 1767 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1768 1769 /* 1770 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 1771 * workaround never ever read DISPLAY_PHY_CONTROL, and 1772 * instead maintain a shadow copy ourselves. Use the actual 1773 * power well state and lane status to reconstruct the 1774 * expected initial value. 1775 */ 1776 display->power.chv_phy_control = 1777 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 1778 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 1779 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 1780 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 1781 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 1782 1783 /* 1784 * If all lanes are disabled we leave the override disabled 1785 * with all power down bits cleared to match the state we 1786 * would use after disabling the port. Otherwise enable the 1787 * override and set the lane powerdown bits accding to the 1788 * current lane status. 1789 */ 1790 if (intel_power_well_is_enabled(display, cmn_bc)) { 1791 u32 status = intel_de_read(display, DPLL(display, PIPE_A)); 1792 unsigned int mask; 1793 1794 mask = status & DPLL_PORTB_READY_MASK; 1795 if (mask == 0xf) 1796 mask = 0x0; 1797 else 1798 display->power.chv_phy_control |= 1799 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 1800 1801 display->power.chv_phy_control |= 1802 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 1803 1804 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 1805 if (mask == 0xf) 1806 mask = 0x0; 1807 else 1808 display->power.chv_phy_control |= 1809 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 1810 1811 display->power.chv_phy_control |= 1812 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 1813 1814 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 1815 1816 display->power.chv_phy_assert[DPIO_PHY0] = false; 1817 } else { 1818 display->power.chv_phy_assert[DPIO_PHY0] = true; 1819 } 1820 1821 if (intel_power_well_is_enabled(display, cmn_d)) { 1822 u32 status = intel_de_read(display, DPIO_PHY_STATUS); 1823 unsigned int mask; 1824 1825 mask = status & DPLL_PORTD_READY_MASK; 1826 1827 if (mask == 0xf) 1828 mask = 0x0; 1829 else 1830 display->power.chv_phy_control |= 1831 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 1832 1833 display->power.chv_phy_control |= 1834 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 1835 1836 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 1837 1838 display->power.chv_phy_assert[DPIO_PHY1] = false; 1839 } else { 1840 display->power.chv_phy_assert[DPIO_PHY1] = true; 1841 } 1842 1843 drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n", 1844 display->power.chv_phy_control); 1845 1846 /* Defer application of initial phy_control to enabling the powerwell */ 1847 } 1848 1849 static void vlv_cmnlane_wa(struct intel_display *display) 1850 { 1851 struct i915_power_well *cmn = 1852 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1853 struct i915_power_well *disp2d = 1854 lookup_power_well(display, VLV_DISP_PW_DISP2D); 1855 1856 /* If the display might be already active skip this */ 1857 if (intel_power_well_is_enabled(display, cmn) && 1858 intel_power_well_is_enabled(display, disp2d) && 1859 intel_de_read(display, DPIO_CTL) & DPIO_CMNRST) 1860 return; 1861 1862 drm_dbg_kms(display->drm, "toggling display PHY side reset\n"); 1863 1864 /* cmnlane needs DPLL registers */ 1865 intel_power_well_enable(display, disp2d); 1866 1867 /* 1868 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 1869 * Need to assert and de-assert PHY SB reset by gating the 1870 * common lane power, then un-gating it. 1871 * Simply ungating isn't enough to reset the PHY enough to get 1872 * ports and lanes running. 1873 */ 1874 intel_power_well_disable(display, cmn); 1875 } 1876 1877 static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0) 1878 { 1879 struct drm_i915_private *dev_priv = to_i915(display->drm); 1880 bool ret; 1881 1882 vlv_punit_get(dev_priv); 1883 ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; 1884 vlv_punit_put(dev_priv); 1885 1886 return ret; 1887 } 1888 1889 static void assert_ved_power_gated(struct intel_display *display) 1890 { 1891 drm_WARN(display->drm, 1892 !vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0), 1893 "VED not power gated\n"); 1894 } 1895 1896 static void assert_isp_power_gated(struct intel_display *display) 1897 { 1898 static const struct pci_device_id isp_ids[] = { 1899 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)}, 1900 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)}, 1901 {} 1902 }; 1903 1904 drm_WARN(display->drm, !pci_dev_present(isp_ids) && 1905 !vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0), 1906 "ISP not power gated\n"); 1907 } 1908 1909 static void intel_power_domains_verify_state(struct intel_display *display); 1910 1911 /** 1912 * intel_power_domains_init_hw - initialize hardware power domain state 1913 * @display: display device instance 1914 * @resume: Called from resume code paths or not 1915 * 1916 * This function initializes the hardware power domain state and enables all 1917 * power wells belonging to the INIT power domain. Power wells in other 1918 * domains (and not in the INIT domain) are referenced or disabled by 1919 * intel_modeset_readout_hw_state(). After that the reference count of each 1920 * power well must match its HW enabled state, see 1921 * intel_power_domains_verify_state(). 1922 * 1923 * It will return with power domains disabled (to be enabled later by 1924 * intel_power_domains_enable()) and must be paired with 1925 * intel_power_domains_driver_remove(). 1926 */ 1927 void intel_power_domains_init_hw(struct intel_display *display, bool resume) 1928 { 1929 struct drm_i915_private *i915 = to_i915(display->drm); 1930 struct i915_power_domains *power_domains = &display->power.domains; 1931 1932 power_domains->initializing = true; 1933 1934 if (DISPLAY_VER(display) >= 11) { 1935 icl_display_core_init(display, resume); 1936 } else if (display->platform.geminilake || display->platform.broxton) { 1937 bxt_display_core_init(display, resume); 1938 } else if (DISPLAY_VER(display) == 9) { 1939 skl_display_core_init(display, resume); 1940 } else if (display->platform.cherryview) { 1941 mutex_lock(&power_domains->lock); 1942 chv_phy_control_init(display); 1943 mutex_unlock(&power_domains->lock); 1944 assert_isp_power_gated(display); 1945 } else if (display->platform.valleyview) { 1946 mutex_lock(&power_domains->lock); 1947 vlv_cmnlane_wa(display); 1948 mutex_unlock(&power_domains->lock); 1949 assert_ved_power_gated(display); 1950 assert_isp_power_gated(display); 1951 } else if (display->platform.broadwell || display->platform.haswell) { 1952 hsw_assert_cdclk(display); 1953 intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915)); 1954 } else if (display->platform.ivybridge) { 1955 intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915)); 1956 } 1957 1958 /* 1959 * Keep all power wells enabled for any dependent HW access during 1960 * initialization and to make sure we keep BIOS enabled display HW 1961 * resources powered until display HW readout is complete. We drop 1962 * this reference in intel_power_domains_enable(). 1963 */ 1964 drm_WARN_ON(display->drm, power_domains->init_wakeref); 1965 power_domains->init_wakeref = 1966 intel_display_power_get(i915, POWER_DOMAIN_INIT); 1967 1968 /* Disable power support if the user asked so. */ 1969 if (!display->params.disable_power_well) { 1970 drm_WARN_ON(display->drm, power_domains->disable_wakeref); 1971 display->power.domains.disable_wakeref = intel_display_power_get(i915, 1972 POWER_DOMAIN_INIT); 1973 } 1974 intel_power_domains_sync_hw(display); 1975 1976 power_domains->initializing = false; 1977 } 1978 1979 /** 1980 * intel_power_domains_driver_remove - deinitialize hw power domain state 1981 * @display: display device instance 1982 * 1983 * De-initializes the display power domain HW state. It also ensures that the 1984 * device stays powered up so that the driver can be reloaded. 1985 * 1986 * It must be called with power domains already disabled (after a call to 1987 * intel_power_domains_disable()) and must be paired with 1988 * intel_power_domains_init_hw(). 1989 */ 1990 void intel_power_domains_driver_remove(struct intel_display *display) 1991 { 1992 struct drm_i915_private *i915 = to_i915(display->drm); 1993 intel_wakeref_t wakeref __maybe_unused = 1994 fetch_and_zero(&display->power.domains.init_wakeref); 1995 1996 /* Remove the refcount we took to keep power well support disabled. */ 1997 if (!display->params.disable_power_well) 1998 intel_display_power_put(i915, POWER_DOMAIN_INIT, 1999 fetch_and_zero(&display->power.domains.disable_wakeref)); 2000 2001 intel_display_power_flush_work_sync(display); 2002 2003 intel_power_domains_verify_state(display); 2004 2005 /* Keep the power well enabled, but cancel its rpm wakeref. */ 2006 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 2007 } 2008 2009 /** 2010 * intel_power_domains_sanitize_state - sanitize power domains state 2011 * @display: display device instance 2012 * 2013 * Sanitize the power domains state during driver loading and system resume. 2014 * The function will disable all display power wells that BIOS has enabled 2015 * without a user for it (any user for a power well has taken a reference 2016 * on it by the time this function is called, after the state of all the 2017 * pipe, encoder, etc. HW resources have been sanitized). 2018 */ 2019 void intel_power_domains_sanitize_state(struct intel_display *display) 2020 { 2021 struct i915_power_domains *power_domains = &display->power.domains; 2022 struct i915_power_well *power_well; 2023 2024 mutex_lock(&power_domains->lock); 2025 2026 for_each_power_well_reverse(display, power_well) { 2027 if (power_well->desc->always_on || power_well->count || 2028 !intel_power_well_is_enabled(display, power_well)) 2029 continue; 2030 2031 drm_dbg_kms(display->drm, 2032 "BIOS left unused %s power well enabled, disabling it\n", 2033 intel_power_well_name(power_well)); 2034 intel_power_well_disable(display, power_well); 2035 } 2036 2037 mutex_unlock(&power_domains->lock); 2038 } 2039 2040 /** 2041 * intel_power_domains_enable - enable toggling of display power wells 2042 * @display: display device instance 2043 * 2044 * Enable the ondemand enabling/disabling of the display power wells. Note that 2045 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled 2046 * only at specific points of the display modeset sequence, thus they are not 2047 * affected by the intel_power_domains_enable()/disable() calls. The purpose 2048 * of these function is to keep the rest of power wells enabled until the end 2049 * of display HW readout (which will acquire the power references reflecting 2050 * the current HW state). 2051 */ 2052 void intel_power_domains_enable(struct intel_display *display) 2053 { 2054 struct drm_i915_private *i915 = to_i915(display->drm); 2055 intel_wakeref_t wakeref __maybe_unused = 2056 fetch_and_zero(&display->power.domains.init_wakeref); 2057 2058 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 2059 intel_power_domains_verify_state(display); 2060 } 2061 2062 /** 2063 * intel_power_domains_disable - disable toggling of display power wells 2064 * @display: display device instance 2065 * 2066 * Disable the ondemand enabling/disabling of the display power wells. See 2067 * intel_power_domains_enable() for which power wells this call controls. 2068 */ 2069 void intel_power_domains_disable(struct intel_display *display) 2070 { 2071 struct drm_i915_private *i915 = to_i915(display->drm); 2072 struct i915_power_domains *power_domains = &display->power.domains; 2073 2074 drm_WARN_ON(display->drm, power_domains->init_wakeref); 2075 power_domains->init_wakeref = 2076 intel_display_power_get(i915, POWER_DOMAIN_INIT); 2077 2078 intel_power_domains_verify_state(display); 2079 } 2080 2081 /** 2082 * intel_power_domains_suspend - suspend power domain state 2083 * @display: display device instance 2084 * @s2idle: specifies whether we go to idle, or deeper sleep 2085 * 2086 * This function prepares the hardware power domain state before entering 2087 * system suspend. 2088 * 2089 * It must be called with power domains already disabled (after a call to 2090 * intel_power_domains_disable()) and paired with intel_power_domains_resume(). 2091 */ 2092 void intel_power_domains_suspend(struct intel_display *display, bool s2idle) 2093 { 2094 struct drm_i915_private *i915 = to_i915(display->drm); 2095 struct i915_power_domains *power_domains = &display->power.domains; 2096 intel_wakeref_t wakeref __maybe_unused = 2097 fetch_and_zero(&power_domains->init_wakeref); 2098 2099 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 2100 2101 /* 2102 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 2103 * support don't manually deinit the power domains. This also means the 2104 * DMC firmware will stay active, it will power down any HW 2105 * resources as required and also enable deeper system power states 2106 * that would be blocked if the firmware was inactive. 2107 */ 2108 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle && 2109 intel_dmc_has_payload(display)) { 2110 intel_display_power_flush_work(i915); 2111 intel_power_domains_verify_state(display); 2112 return; 2113 } 2114 2115 /* 2116 * Even if power well support was disabled we still want to disable 2117 * power wells if power domains must be deinitialized for suspend. 2118 */ 2119 if (!display->params.disable_power_well) 2120 intel_display_power_put(i915, POWER_DOMAIN_INIT, 2121 fetch_and_zero(&display->power.domains.disable_wakeref)); 2122 2123 intel_display_power_flush_work(i915); 2124 intel_power_domains_verify_state(display); 2125 2126 if (DISPLAY_VER(display) >= 11) 2127 icl_display_core_uninit(display); 2128 else if (display->platform.geminilake || display->platform.broxton) 2129 bxt_display_core_uninit(display); 2130 else if (DISPLAY_VER(display) == 9) 2131 skl_display_core_uninit(display); 2132 2133 power_domains->display_core_suspended = true; 2134 } 2135 2136 /** 2137 * intel_power_domains_resume - resume power domain state 2138 * @display: display device instance 2139 * 2140 * This function resume the hardware power domain state during system resume. 2141 * 2142 * It will return with power domain support disabled (to be enabled later by 2143 * intel_power_domains_enable()) and must be paired with 2144 * intel_power_domains_suspend(). 2145 */ 2146 void intel_power_domains_resume(struct intel_display *display) 2147 { 2148 struct drm_i915_private *i915 = to_i915(display->drm); 2149 struct i915_power_domains *power_domains = &display->power.domains; 2150 2151 if (power_domains->display_core_suspended) { 2152 intel_power_domains_init_hw(display, true); 2153 power_domains->display_core_suspended = false; 2154 } else { 2155 drm_WARN_ON(display->drm, power_domains->init_wakeref); 2156 power_domains->init_wakeref = 2157 intel_display_power_get(i915, POWER_DOMAIN_INIT); 2158 } 2159 2160 intel_power_domains_verify_state(display); 2161 } 2162 2163 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 2164 2165 static void intel_power_domains_dump_info(struct intel_display *display) 2166 { 2167 struct i915_power_domains *power_domains = &display->power.domains; 2168 struct i915_power_well *power_well; 2169 2170 for_each_power_well(display, power_well) { 2171 enum intel_display_power_domain domain; 2172 2173 drm_dbg_kms(display->drm, "%-25s %d\n", 2174 intel_power_well_name(power_well), intel_power_well_refcount(power_well)); 2175 2176 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2177 drm_dbg_kms(display->drm, " %-23s %d\n", 2178 intel_display_power_domain_str(domain), 2179 power_domains->domain_use_count[domain]); 2180 } 2181 } 2182 2183 /** 2184 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 2185 * @display: display device instance 2186 * 2187 * Verify if the reference count of each power well matches its HW enabled 2188 * state and the total refcount of the domains it belongs to. This must be 2189 * called after modeset HW state sanitization, which is responsible for 2190 * acquiring reference counts for any power wells in use and disabling the 2191 * ones left on by BIOS but not required by any active output. 2192 */ 2193 static void intel_power_domains_verify_state(struct intel_display *display) 2194 { 2195 struct i915_power_domains *power_domains = &display->power.domains; 2196 struct i915_power_well *power_well; 2197 bool dump_domain_info; 2198 2199 mutex_lock(&power_domains->lock); 2200 2201 verify_async_put_domains_state(power_domains); 2202 2203 dump_domain_info = false; 2204 for_each_power_well(display, power_well) { 2205 enum intel_display_power_domain domain; 2206 int domains_count; 2207 bool enabled; 2208 2209 enabled = intel_power_well_is_enabled(display, power_well); 2210 if ((intel_power_well_refcount(power_well) || 2211 intel_power_well_is_always_on(power_well)) != 2212 enabled) 2213 drm_err(display->drm, 2214 "power well %s state mismatch (refcount %d/enabled %d)", 2215 intel_power_well_name(power_well), 2216 intel_power_well_refcount(power_well), enabled); 2217 2218 domains_count = 0; 2219 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2220 domains_count += power_domains->domain_use_count[domain]; 2221 2222 if (intel_power_well_refcount(power_well) != domains_count) { 2223 drm_err(display->drm, 2224 "power well %s refcount/domain refcount mismatch " 2225 "(refcount %d/domains refcount %d)\n", 2226 intel_power_well_name(power_well), 2227 intel_power_well_refcount(power_well), 2228 domains_count); 2229 dump_domain_info = true; 2230 } 2231 } 2232 2233 if (dump_domain_info) { 2234 static bool dumped; 2235 2236 if (!dumped) { 2237 intel_power_domains_dump_info(display); 2238 dumped = true; 2239 } 2240 } 2241 2242 mutex_unlock(&power_domains->lock); 2243 } 2244 2245 #else 2246 2247 static void intel_power_domains_verify_state(struct intel_display *display) 2248 { 2249 } 2250 2251 #endif 2252 2253 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle) 2254 { 2255 struct drm_i915_private *i915 = to_i915(display->drm); 2256 2257 intel_power_domains_suspend(display, s2idle); 2258 2259 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || 2260 display->platform.broxton) { 2261 bxt_enable_dc9(display); 2262 } else if (display->platform.haswell || display->platform.broadwell) { 2263 hsw_enable_pc8(display); 2264 } 2265 2266 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2267 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) 2268 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); 2269 } 2270 2271 void intel_display_power_resume_early(struct intel_display *display) 2272 { 2273 struct drm_i915_private *i915 = to_i915(display->drm); 2274 2275 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || 2276 display->platform.broxton) { 2277 gen9_sanitize_dc_state(display); 2278 bxt_disable_dc9(display); 2279 } else if (display->platform.haswell || display->platform.broadwell) { 2280 hsw_disable_pc8(display); 2281 } 2282 2283 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2284 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) 2285 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); 2286 2287 intel_power_domains_resume(display); 2288 } 2289 2290 void intel_display_power_suspend(struct intel_display *display) 2291 { 2292 if (DISPLAY_VER(display) >= 11) { 2293 icl_display_core_uninit(display); 2294 bxt_enable_dc9(display); 2295 } else if (display->platform.geminilake || display->platform.broxton) { 2296 bxt_display_core_uninit(display); 2297 bxt_enable_dc9(display); 2298 } else if (display->platform.haswell || display->platform.broadwell) { 2299 hsw_enable_pc8(display); 2300 } 2301 } 2302 2303 void intel_display_power_resume(struct intel_display *display) 2304 { 2305 struct i915_power_domains *power_domains = &display->power.domains; 2306 2307 if (DISPLAY_VER(display) >= 11) { 2308 bxt_disable_dc9(display); 2309 icl_display_core_init(display, true); 2310 if (intel_dmc_has_payload(display)) { 2311 if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 2312 skl_enable_dc6(display); 2313 else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 2314 gen9_enable_dc5(display); 2315 } 2316 } else if (display->platform.geminilake || display->platform.broxton) { 2317 bxt_disable_dc9(display); 2318 bxt_display_core_init(display, true); 2319 if (intel_dmc_has_payload(display) && 2320 (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) 2321 gen9_enable_dc5(display); 2322 } else if (display->platform.haswell || display->platform.broadwell) { 2323 hsw_disable_pc8(display); 2324 } 2325 } 2326 2327 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m) 2328 { 2329 struct intel_display *display = &i915->display; 2330 struct i915_power_domains *power_domains = &display->power.domains; 2331 int i; 2332 2333 mutex_lock(&power_domains->lock); 2334 2335 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); 2336 for (i = 0; i < power_domains->power_well_count; i++) { 2337 struct i915_power_well *power_well; 2338 enum intel_display_power_domain power_domain; 2339 2340 power_well = &power_domains->power_wells[i]; 2341 seq_printf(m, "%-25s %d\n", intel_power_well_name(power_well), 2342 intel_power_well_refcount(power_well)); 2343 2344 for_each_power_domain(power_domain, intel_power_well_domains(power_well)) 2345 seq_printf(m, " %-23s %d\n", 2346 intel_display_power_domain_str(power_domain), 2347 power_domains->domain_use_count[power_domain]); 2348 } 2349 2350 mutex_unlock(&power_domains->lock); 2351 } 2352 2353 struct intel_ddi_port_domains { 2354 enum port port_start; 2355 enum port port_end; 2356 enum aux_ch aux_ch_start; 2357 enum aux_ch aux_ch_end; 2358 2359 enum intel_display_power_domain ddi_lanes; 2360 enum intel_display_power_domain ddi_io; 2361 enum intel_display_power_domain aux_io; 2362 enum intel_display_power_domain aux_legacy_usbc; 2363 enum intel_display_power_domain aux_tbt; 2364 }; 2365 2366 static const struct intel_ddi_port_domains 2367 i9xx_port_domains[] = { 2368 { 2369 .port_start = PORT_A, 2370 .port_end = PORT_F, 2371 .aux_ch_start = AUX_CH_A, 2372 .aux_ch_end = AUX_CH_F, 2373 2374 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2375 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2376 .aux_io = POWER_DOMAIN_AUX_IO_A, 2377 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2378 .aux_tbt = POWER_DOMAIN_INVALID, 2379 }, 2380 }; 2381 2382 static const struct intel_ddi_port_domains 2383 d11_port_domains[] = { 2384 { 2385 .port_start = PORT_A, 2386 .port_end = PORT_B, 2387 .aux_ch_start = AUX_CH_A, 2388 .aux_ch_end = AUX_CH_B, 2389 2390 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2391 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2392 .aux_io = POWER_DOMAIN_AUX_IO_A, 2393 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2394 .aux_tbt = POWER_DOMAIN_INVALID, 2395 }, { 2396 .port_start = PORT_C, 2397 .port_end = PORT_F, 2398 .aux_ch_start = AUX_CH_C, 2399 .aux_ch_end = AUX_CH_F, 2400 2401 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C, 2402 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C, 2403 .aux_io = POWER_DOMAIN_AUX_IO_C, 2404 .aux_legacy_usbc = POWER_DOMAIN_AUX_C, 2405 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2406 }, 2407 }; 2408 2409 static const struct intel_ddi_port_domains 2410 d12_port_domains[] = { 2411 { 2412 .port_start = PORT_A, 2413 .port_end = PORT_C, 2414 .aux_ch_start = AUX_CH_A, 2415 .aux_ch_end = AUX_CH_C, 2416 2417 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2418 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2419 .aux_io = POWER_DOMAIN_AUX_IO_A, 2420 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2421 .aux_tbt = POWER_DOMAIN_INVALID, 2422 }, { 2423 .port_start = PORT_TC1, 2424 .port_end = PORT_TC6, 2425 .aux_ch_start = AUX_CH_USBC1, 2426 .aux_ch_end = AUX_CH_USBC6, 2427 2428 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2429 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2430 .aux_io = POWER_DOMAIN_INVALID, 2431 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2432 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2433 }, 2434 }; 2435 2436 static const struct intel_ddi_port_domains 2437 d13_port_domains[] = { 2438 { 2439 .port_start = PORT_A, 2440 .port_end = PORT_C, 2441 .aux_ch_start = AUX_CH_A, 2442 .aux_ch_end = AUX_CH_C, 2443 2444 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2445 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2446 .aux_io = POWER_DOMAIN_AUX_IO_A, 2447 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2448 .aux_tbt = POWER_DOMAIN_INVALID, 2449 }, { 2450 .port_start = PORT_TC1, 2451 .port_end = PORT_TC4, 2452 .aux_ch_start = AUX_CH_USBC1, 2453 .aux_ch_end = AUX_CH_USBC4, 2454 2455 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2456 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2457 .aux_io = POWER_DOMAIN_INVALID, 2458 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2459 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2460 }, { 2461 .port_start = PORT_D_XELPD, 2462 .port_end = PORT_E_XELPD, 2463 .aux_ch_start = AUX_CH_D_XELPD, 2464 .aux_ch_end = AUX_CH_E_XELPD, 2465 2466 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D, 2467 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D, 2468 .aux_io = POWER_DOMAIN_AUX_IO_D, 2469 .aux_legacy_usbc = POWER_DOMAIN_AUX_D, 2470 .aux_tbt = POWER_DOMAIN_INVALID, 2471 }, 2472 }; 2473 2474 static void 2475 intel_port_domains_for_platform(struct intel_display *display, 2476 const struct intel_ddi_port_domains **domains, 2477 int *domains_size) 2478 { 2479 if (DISPLAY_VER(display) >= 13) { 2480 *domains = d13_port_domains; 2481 *domains_size = ARRAY_SIZE(d13_port_domains); 2482 } else if (DISPLAY_VER(display) >= 12) { 2483 *domains = d12_port_domains; 2484 *domains_size = ARRAY_SIZE(d12_port_domains); 2485 } else if (DISPLAY_VER(display) >= 11) { 2486 *domains = d11_port_domains; 2487 *domains_size = ARRAY_SIZE(d11_port_domains); 2488 } else { 2489 *domains = i9xx_port_domains; 2490 *domains_size = ARRAY_SIZE(i9xx_port_domains); 2491 } 2492 } 2493 2494 static const struct intel_ddi_port_domains * 2495 intel_port_domains_for_port(struct intel_display *display, enum port port) 2496 { 2497 const struct intel_ddi_port_domains *domains; 2498 int domains_size; 2499 int i; 2500 2501 intel_port_domains_for_platform(display, &domains, &domains_size); 2502 for (i = 0; i < domains_size; i++) 2503 if (port >= domains[i].port_start && port <= domains[i].port_end) 2504 return &domains[i]; 2505 2506 return NULL; 2507 } 2508 2509 enum intel_display_power_domain 2510 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port) 2511 { 2512 struct intel_display *display = &i915->display; 2513 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); 2514 2515 if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) 2516 return POWER_DOMAIN_PORT_DDI_IO_A; 2517 2518 return domains->ddi_io + (int)(port - domains->port_start); 2519 } 2520 2521 enum intel_display_power_domain 2522 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port) 2523 { 2524 struct intel_display *display = &i915->display; 2525 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); 2526 2527 if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) 2528 return POWER_DOMAIN_PORT_DDI_LANES_A; 2529 2530 return domains->ddi_lanes + (int)(port - domains->port_start); 2531 } 2532 2533 static const struct intel_ddi_port_domains * 2534 intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch) 2535 { 2536 const struct intel_ddi_port_domains *domains; 2537 int domains_size; 2538 int i; 2539 2540 intel_port_domains_for_platform(display, &domains, &domains_size); 2541 for (i = 0; i < domains_size; i++) 2542 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end) 2543 return &domains[i]; 2544 2545 return NULL; 2546 } 2547 2548 enum intel_display_power_domain 2549 intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2550 { 2551 struct intel_display *display = &i915->display; 2552 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2553 2554 if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) 2555 return POWER_DOMAIN_AUX_IO_A; 2556 2557 return domains->aux_io + (int)(aux_ch - domains->aux_ch_start); 2558 } 2559 2560 enum intel_display_power_domain 2561 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2562 { 2563 struct intel_display *display = &i915->display; 2564 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2565 2566 if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) 2567 return POWER_DOMAIN_AUX_A; 2568 2569 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start); 2570 } 2571 2572 enum intel_display_power_domain 2573 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2574 { 2575 struct intel_display *display = &i915->display; 2576 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2577 2578 if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) 2579 return POWER_DOMAIN_AUX_TBT1; 2580 2581 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start); 2582 } 2583