1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include "i915_drv.h" 9 #include "i915_irq.h" 10 #include "i915_reg.h" 11 #include "intel_backlight_regs.h" 12 #include "intel_cdclk.h" 13 #include "intel_clock_gating.h" 14 #include "intel_combo_phy.h" 15 #include "intel_de.h" 16 #include "intel_display_power.h" 17 #include "intel_display_power_map.h" 18 #include "intel_display_power_well.h" 19 #include "intel_display_rpm.h" 20 #include "intel_display_types.h" 21 #include "intel_dmc.h" 22 #include "intel_mchbar_regs.h" 23 #include "intel_pch_refclk.h" 24 #include "intel_pcode.h" 25 #include "intel_pmdemand.h" 26 #include "intel_pps_regs.h" 27 #include "intel_snps_phy.h" 28 #include "skl_watermark.h" 29 #include "skl_watermark_regs.h" 30 #include "vlv_sideband.h" 31 32 #define for_each_power_domain_well(__display, __power_well, __domain) \ 33 for_each_power_well((__display), __power_well) \ 34 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 35 36 #define for_each_power_domain_well_reverse(__display, __power_well, __domain) \ 37 for_each_power_well_reverse((__display), __power_well) \ 38 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 39 40 static const char * 41 intel_display_power_domain_str(enum intel_display_power_domain domain) 42 { 43 switch (domain) { 44 case POWER_DOMAIN_DISPLAY_CORE: 45 return "DISPLAY_CORE"; 46 case POWER_DOMAIN_PIPE_A: 47 return "PIPE_A"; 48 case POWER_DOMAIN_PIPE_B: 49 return "PIPE_B"; 50 case POWER_DOMAIN_PIPE_C: 51 return "PIPE_C"; 52 case POWER_DOMAIN_PIPE_D: 53 return "PIPE_D"; 54 case POWER_DOMAIN_PIPE_PANEL_FITTER_A: 55 return "PIPE_PANEL_FITTER_A"; 56 case POWER_DOMAIN_PIPE_PANEL_FITTER_B: 57 return "PIPE_PANEL_FITTER_B"; 58 case POWER_DOMAIN_PIPE_PANEL_FITTER_C: 59 return "PIPE_PANEL_FITTER_C"; 60 case POWER_DOMAIN_PIPE_PANEL_FITTER_D: 61 return "PIPE_PANEL_FITTER_D"; 62 case POWER_DOMAIN_TRANSCODER_A: 63 return "TRANSCODER_A"; 64 case POWER_DOMAIN_TRANSCODER_B: 65 return "TRANSCODER_B"; 66 case POWER_DOMAIN_TRANSCODER_C: 67 return "TRANSCODER_C"; 68 case POWER_DOMAIN_TRANSCODER_D: 69 return "TRANSCODER_D"; 70 case POWER_DOMAIN_TRANSCODER_EDP: 71 return "TRANSCODER_EDP"; 72 case POWER_DOMAIN_TRANSCODER_DSI_A: 73 return "TRANSCODER_DSI_A"; 74 case POWER_DOMAIN_TRANSCODER_DSI_C: 75 return "TRANSCODER_DSI_C"; 76 case POWER_DOMAIN_TRANSCODER_VDSC_PW2: 77 return "TRANSCODER_VDSC_PW2"; 78 case POWER_DOMAIN_PORT_DDI_LANES_A: 79 return "PORT_DDI_LANES_A"; 80 case POWER_DOMAIN_PORT_DDI_LANES_B: 81 return "PORT_DDI_LANES_B"; 82 case POWER_DOMAIN_PORT_DDI_LANES_C: 83 return "PORT_DDI_LANES_C"; 84 case POWER_DOMAIN_PORT_DDI_LANES_D: 85 return "PORT_DDI_LANES_D"; 86 case POWER_DOMAIN_PORT_DDI_LANES_E: 87 return "PORT_DDI_LANES_E"; 88 case POWER_DOMAIN_PORT_DDI_LANES_F: 89 return "PORT_DDI_LANES_F"; 90 case POWER_DOMAIN_PORT_DDI_LANES_TC1: 91 return "PORT_DDI_LANES_TC1"; 92 case POWER_DOMAIN_PORT_DDI_LANES_TC2: 93 return "PORT_DDI_LANES_TC2"; 94 case POWER_DOMAIN_PORT_DDI_LANES_TC3: 95 return "PORT_DDI_LANES_TC3"; 96 case POWER_DOMAIN_PORT_DDI_LANES_TC4: 97 return "PORT_DDI_LANES_TC4"; 98 case POWER_DOMAIN_PORT_DDI_LANES_TC5: 99 return "PORT_DDI_LANES_TC5"; 100 case POWER_DOMAIN_PORT_DDI_LANES_TC6: 101 return "PORT_DDI_LANES_TC6"; 102 case POWER_DOMAIN_PORT_DDI_IO_A: 103 return "PORT_DDI_IO_A"; 104 case POWER_DOMAIN_PORT_DDI_IO_B: 105 return "PORT_DDI_IO_B"; 106 case POWER_DOMAIN_PORT_DDI_IO_C: 107 return "PORT_DDI_IO_C"; 108 case POWER_DOMAIN_PORT_DDI_IO_D: 109 return "PORT_DDI_IO_D"; 110 case POWER_DOMAIN_PORT_DDI_IO_E: 111 return "PORT_DDI_IO_E"; 112 case POWER_DOMAIN_PORT_DDI_IO_F: 113 return "PORT_DDI_IO_F"; 114 case POWER_DOMAIN_PORT_DDI_IO_TC1: 115 return "PORT_DDI_IO_TC1"; 116 case POWER_DOMAIN_PORT_DDI_IO_TC2: 117 return "PORT_DDI_IO_TC2"; 118 case POWER_DOMAIN_PORT_DDI_IO_TC3: 119 return "PORT_DDI_IO_TC3"; 120 case POWER_DOMAIN_PORT_DDI_IO_TC4: 121 return "PORT_DDI_IO_TC4"; 122 case POWER_DOMAIN_PORT_DDI_IO_TC5: 123 return "PORT_DDI_IO_TC5"; 124 case POWER_DOMAIN_PORT_DDI_IO_TC6: 125 return "PORT_DDI_IO_TC6"; 126 case POWER_DOMAIN_PORT_DSI: 127 return "PORT_DSI"; 128 case POWER_DOMAIN_PORT_CRT: 129 return "PORT_CRT"; 130 case POWER_DOMAIN_PORT_OTHER: 131 return "PORT_OTHER"; 132 case POWER_DOMAIN_VGA: 133 return "VGA"; 134 case POWER_DOMAIN_AUDIO_MMIO: 135 return "AUDIO_MMIO"; 136 case POWER_DOMAIN_AUDIO_PLAYBACK: 137 return "AUDIO_PLAYBACK"; 138 case POWER_DOMAIN_AUX_IO_A: 139 return "AUX_IO_A"; 140 case POWER_DOMAIN_AUX_IO_B: 141 return "AUX_IO_B"; 142 case POWER_DOMAIN_AUX_IO_C: 143 return "AUX_IO_C"; 144 case POWER_DOMAIN_AUX_IO_D: 145 return "AUX_IO_D"; 146 case POWER_DOMAIN_AUX_IO_E: 147 return "AUX_IO_E"; 148 case POWER_DOMAIN_AUX_IO_F: 149 return "AUX_IO_F"; 150 case POWER_DOMAIN_AUX_A: 151 return "AUX_A"; 152 case POWER_DOMAIN_AUX_B: 153 return "AUX_B"; 154 case POWER_DOMAIN_AUX_C: 155 return "AUX_C"; 156 case POWER_DOMAIN_AUX_D: 157 return "AUX_D"; 158 case POWER_DOMAIN_AUX_E: 159 return "AUX_E"; 160 case POWER_DOMAIN_AUX_F: 161 return "AUX_F"; 162 case POWER_DOMAIN_AUX_USBC1: 163 return "AUX_USBC1"; 164 case POWER_DOMAIN_AUX_USBC2: 165 return "AUX_USBC2"; 166 case POWER_DOMAIN_AUX_USBC3: 167 return "AUX_USBC3"; 168 case POWER_DOMAIN_AUX_USBC4: 169 return "AUX_USBC4"; 170 case POWER_DOMAIN_AUX_USBC5: 171 return "AUX_USBC5"; 172 case POWER_DOMAIN_AUX_USBC6: 173 return "AUX_USBC6"; 174 case POWER_DOMAIN_AUX_TBT1: 175 return "AUX_TBT1"; 176 case POWER_DOMAIN_AUX_TBT2: 177 return "AUX_TBT2"; 178 case POWER_DOMAIN_AUX_TBT3: 179 return "AUX_TBT3"; 180 case POWER_DOMAIN_AUX_TBT4: 181 return "AUX_TBT4"; 182 case POWER_DOMAIN_AUX_TBT5: 183 return "AUX_TBT5"; 184 case POWER_DOMAIN_AUX_TBT6: 185 return "AUX_TBT6"; 186 case POWER_DOMAIN_GMBUS: 187 return "GMBUS"; 188 case POWER_DOMAIN_INIT: 189 return "INIT"; 190 case POWER_DOMAIN_GT_IRQ: 191 return "GT_IRQ"; 192 case POWER_DOMAIN_DC_OFF: 193 return "DC_OFF"; 194 case POWER_DOMAIN_TC_COLD_OFF: 195 return "TC_COLD_OFF"; 196 default: 197 MISSING_CASE(domain); 198 return "?"; 199 } 200 } 201 202 static bool __intel_display_power_is_enabled(struct intel_display *display, 203 enum intel_display_power_domain domain) 204 { 205 struct i915_power_well *power_well; 206 bool is_enabled; 207 208 if (intel_display_rpm_suspended(display)) 209 return false; 210 211 is_enabled = true; 212 213 for_each_power_domain_well_reverse(display, power_well, domain) { 214 if (intel_power_well_is_always_on(power_well)) 215 continue; 216 217 if (!intel_power_well_is_enabled_cached(power_well)) { 218 is_enabled = false; 219 break; 220 } 221 } 222 223 return is_enabled; 224 } 225 226 /** 227 * intel_display_power_is_enabled - check for a power domain 228 * @display: display device instance 229 * @domain: power domain to check 230 * 231 * This function can be used to check the hw power domain state. It is mostly 232 * used in hardware state readout functions. Everywhere else code should rely 233 * upon explicit power domain reference counting to ensure that the hardware 234 * block is powered up before accessing it. 235 * 236 * Callers must hold the relevant modesetting locks to ensure that concurrent 237 * threads can't disable the power well while the caller tries to read a few 238 * registers. 239 * 240 * Returns: 241 * True when the power domain is enabled, false otherwise. 242 */ 243 bool intel_display_power_is_enabled(struct intel_display *display, 244 enum intel_display_power_domain domain) 245 { 246 struct i915_power_domains *power_domains = &display->power.domains; 247 bool ret; 248 249 mutex_lock(&power_domains->lock); 250 ret = __intel_display_power_is_enabled(display, domain); 251 mutex_unlock(&power_domains->lock); 252 253 return ret; 254 } 255 256 static u32 257 sanitize_target_dc_state(struct intel_display *display, 258 u32 target_dc_state) 259 { 260 struct i915_power_domains *power_domains = &display->power.domains; 261 static const u32 states[] = { 262 DC_STATE_EN_UPTO_DC6, 263 DC_STATE_EN_UPTO_DC5, 264 DC_STATE_EN_DC3CO, 265 DC_STATE_DISABLE, 266 }; 267 int i; 268 269 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { 270 if (target_dc_state != states[i]) 271 continue; 272 273 if (power_domains->allowed_dc_mask & target_dc_state) 274 break; 275 276 target_dc_state = states[i + 1]; 277 } 278 279 return target_dc_state; 280 } 281 282 /** 283 * intel_display_power_set_target_dc_state - Set target dc state. 284 * @display: display device 285 * @state: state which needs to be set as target_dc_state. 286 * 287 * This function set the "DC off" power well target_dc_state, 288 * based upon this target_dc_stste, "DC off" power well will 289 * enable desired DC state. 290 */ 291 void intel_display_power_set_target_dc_state(struct intel_display *display, 292 u32 state) 293 { 294 struct i915_power_well *power_well; 295 bool dc_off_enabled; 296 struct i915_power_domains *power_domains = &display->power.domains; 297 298 mutex_lock(&power_domains->lock); 299 power_well = lookup_power_well(display, SKL_DISP_DC_OFF); 300 301 if (drm_WARN_ON(display->drm, !power_well)) 302 goto unlock; 303 304 state = sanitize_target_dc_state(display, state); 305 306 if (state == power_domains->target_dc_state) 307 goto unlock; 308 309 dc_off_enabled = intel_power_well_is_enabled(display, power_well); 310 /* 311 * If DC off power well is disabled, need to enable and disable the 312 * DC off power well to effect target DC state. 313 */ 314 if (!dc_off_enabled) 315 intel_power_well_enable(display, power_well); 316 317 power_domains->target_dc_state = state; 318 319 if (!dc_off_enabled) 320 intel_power_well_disable(display, power_well); 321 322 unlock: 323 mutex_unlock(&power_domains->lock); 324 } 325 326 static void __async_put_domains_mask(struct i915_power_domains *power_domains, 327 struct intel_power_domain_mask *mask) 328 { 329 bitmap_or(mask->bits, 330 power_domains->async_put_domains[0].bits, 331 power_domains->async_put_domains[1].bits, 332 POWER_DOMAIN_NUM); 333 } 334 335 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 336 337 static bool 338 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 339 { 340 struct intel_display *display = container_of(power_domains, 341 struct intel_display, 342 power.domains); 343 344 return !drm_WARN_ON(display->drm, 345 bitmap_intersects(power_domains->async_put_domains[0].bits, 346 power_domains->async_put_domains[1].bits, 347 POWER_DOMAIN_NUM)); 348 } 349 350 static bool 351 __async_put_domains_state_ok(struct i915_power_domains *power_domains) 352 { 353 struct intel_display *display = container_of(power_domains, 354 struct intel_display, 355 power.domains); 356 struct intel_power_domain_mask async_put_mask; 357 enum intel_display_power_domain domain; 358 bool err = false; 359 360 err |= !assert_async_put_domain_masks_disjoint(power_domains); 361 __async_put_domains_mask(power_domains, &async_put_mask); 362 err |= drm_WARN_ON(display->drm, 363 !!power_domains->async_put_wakeref != 364 !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)); 365 366 for_each_power_domain(domain, &async_put_mask) 367 err |= drm_WARN_ON(display->drm, 368 power_domains->domain_use_count[domain] != 1); 369 370 return !err; 371 } 372 373 static void print_power_domains(struct i915_power_domains *power_domains, 374 const char *prefix, struct intel_power_domain_mask *mask) 375 { 376 struct intel_display *display = container_of(power_domains, 377 struct intel_display, 378 power.domains); 379 enum intel_display_power_domain domain; 380 381 drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); 382 for_each_power_domain(domain, mask) 383 drm_dbg_kms(display->drm, "%s use_count %d\n", 384 intel_display_power_domain_str(domain), 385 power_domains->domain_use_count[domain]); 386 } 387 388 static void 389 print_async_put_domains_state(struct i915_power_domains *power_domains) 390 { 391 struct intel_display *display = container_of(power_domains, 392 struct intel_display, 393 power.domains); 394 395 drm_dbg_kms(display->drm, "async_put_wakeref: %s\n", 396 str_yes_no(power_domains->async_put_wakeref)); 397 398 print_power_domains(power_domains, "async_put_domains[0]", 399 &power_domains->async_put_domains[0]); 400 print_power_domains(power_domains, "async_put_domains[1]", 401 &power_domains->async_put_domains[1]); 402 } 403 404 static void 405 verify_async_put_domains_state(struct i915_power_domains *power_domains) 406 { 407 if (!__async_put_domains_state_ok(power_domains)) 408 print_async_put_domains_state(power_domains); 409 } 410 411 #else 412 413 static void 414 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 415 { 416 } 417 418 static void 419 verify_async_put_domains_state(struct i915_power_domains *power_domains) 420 { 421 } 422 423 #endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */ 424 425 static void async_put_domains_mask(struct i915_power_domains *power_domains, 426 struct intel_power_domain_mask *mask) 427 428 { 429 assert_async_put_domain_masks_disjoint(power_domains); 430 431 __async_put_domains_mask(power_domains, mask); 432 } 433 434 static void 435 async_put_domains_clear_domain(struct i915_power_domains *power_domains, 436 enum intel_display_power_domain domain) 437 { 438 assert_async_put_domain_masks_disjoint(power_domains); 439 440 clear_bit(domain, power_domains->async_put_domains[0].bits); 441 clear_bit(domain, power_domains->async_put_domains[1].bits); 442 } 443 444 static void 445 cancel_async_put_work(struct i915_power_domains *power_domains, bool sync) 446 { 447 if (sync) 448 cancel_delayed_work_sync(&power_domains->async_put_work); 449 else 450 cancel_delayed_work(&power_domains->async_put_work); 451 452 power_domains->async_put_next_delay = 0; 453 } 454 455 static bool 456 intel_display_power_grab_async_put_ref(struct intel_display *display, 457 enum intel_display_power_domain domain) 458 { 459 struct i915_power_domains *power_domains = &display->power.domains; 460 struct intel_power_domain_mask async_put_mask; 461 bool ret = false; 462 463 async_put_domains_mask(power_domains, &async_put_mask); 464 if (!test_bit(domain, async_put_mask.bits)) 465 goto out_verify; 466 467 async_put_domains_clear_domain(power_domains, domain); 468 469 ret = true; 470 471 async_put_domains_mask(power_domains, &async_put_mask); 472 if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)) 473 goto out_verify; 474 475 cancel_async_put_work(power_domains, false); 476 intel_display_rpm_put_raw(display, 477 fetch_and_zero(&power_domains->async_put_wakeref)); 478 out_verify: 479 verify_async_put_domains_state(power_domains); 480 481 return ret; 482 } 483 484 static void 485 __intel_display_power_get_domain(struct intel_display *display, 486 enum intel_display_power_domain domain) 487 { 488 struct i915_power_domains *power_domains = &display->power.domains; 489 struct i915_power_well *power_well; 490 491 if (intel_display_power_grab_async_put_ref(display, domain)) 492 return; 493 494 for_each_power_domain_well(display, power_well, domain) 495 intel_power_well_get(display, power_well); 496 497 power_domains->domain_use_count[domain]++; 498 } 499 500 /** 501 * intel_display_power_get - grab a power domain reference 502 * @display: display device instance 503 * @domain: power domain to reference 504 * 505 * This function grabs a power domain reference for @domain and ensures that the 506 * power domain and all its parents are powered up. Therefore users should only 507 * grab a reference to the innermost power domain they need. 508 * 509 * Any power domain reference obtained by this function must have a symmetric 510 * call to intel_display_power_put() to release the reference again. 511 */ 512 intel_wakeref_t intel_display_power_get(struct intel_display *display, 513 enum intel_display_power_domain domain) 514 { 515 struct i915_power_domains *power_domains = &display->power.domains; 516 struct ref_tracker *wakeref; 517 518 wakeref = intel_display_rpm_get(display); 519 520 mutex_lock(&power_domains->lock); 521 __intel_display_power_get_domain(display, domain); 522 mutex_unlock(&power_domains->lock); 523 524 return wakeref; 525 } 526 527 /** 528 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 529 * @display: display device instance 530 * @domain: power domain to reference 531 * 532 * This function grabs a power domain reference for @domain and ensures that the 533 * power domain and all its parents are powered up. Therefore users should only 534 * grab a reference to the innermost power domain they need. 535 * 536 * Any power domain reference obtained by this function must have a symmetric 537 * call to intel_display_power_put() to release the reference again. 538 */ 539 intel_wakeref_t 540 intel_display_power_get_if_enabled(struct intel_display *display, 541 enum intel_display_power_domain domain) 542 { 543 struct i915_power_domains *power_domains = &display->power.domains; 544 struct ref_tracker *wakeref; 545 bool is_enabled; 546 547 wakeref = intel_display_rpm_get_if_in_use(display); 548 if (!wakeref) 549 return NULL; 550 551 mutex_lock(&power_domains->lock); 552 553 if (__intel_display_power_is_enabled(display, domain)) { 554 __intel_display_power_get_domain(display, domain); 555 is_enabled = true; 556 } else { 557 is_enabled = false; 558 } 559 560 mutex_unlock(&power_domains->lock); 561 562 if (!is_enabled) { 563 intel_display_rpm_put(display, wakeref); 564 wakeref = NULL; 565 } 566 567 return wakeref; 568 } 569 570 static void 571 __intel_display_power_put_domain(struct intel_display *display, 572 enum intel_display_power_domain domain) 573 { 574 struct i915_power_domains *power_domains = &display->power.domains; 575 struct i915_power_well *power_well; 576 const char *name = intel_display_power_domain_str(domain); 577 struct intel_power_domain_mask async_put_mask; 578 579 drm_WARN(display->drm, !power_domains->domain_use_count[domain], 580 "Use count on domain %s is already zero\n", 581 name); 582 async_put_domains_mask(power_domains, &async_put_mask); 583 drm_WARN(display->drm, 584 test_bit(domain, async_put_mask.bits), 585 "Async disabling of domain %s is pending\n", 586 name); 587 588 power_domains->domain_use_count[domain]--; 589 590 for_each_power_domain_well_reverse(display, power_well, domain) 591 intel_power_well_put(display, power_well); 592 } 593 594 static void __intel_display_power_put(struct intel_display *display, 595 enum intel_display_power_domain domain) 596 { 597 struct i915_power_domains *power_domains = &display->power.domains; 598 599 mutex_lock(&power_domains->lock); 600 __intel_display_power_put_domain(display, domain); 601 mutex_unlock(&power_domains->lock); 602 } 603 604 static void 605 queue_async_put_domains_work(struct i915_power_domains *power_domains, 606 intel_wakeref_t wakeref, 607 int delay_ms) 608 { 609 struct intel_display *display = container_of(power_domains, 610 struct intel_display, 611 power.domains); 612 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); 613 power_domains->async_put_wakeref = wakeref; 614 drm_WARN_ON(display->drm, !queue_delayed_work(system_unbound_wq, 615 &power_domains->async_put_work, 616 msecs_to_jiffies(delay_ms))); 617 } 618 619 static void 620 release_async_put_domains(struct i915_power_domains *power_domains, 621 struct intel_power_domain_mask *mask) 622 { 623 struct intel_display *display = container_of(power_domains, 624 struct intel_display, 625 power.domains); 626 enum intel_display_power_domain domain; 627 struct ref_tracker *wakeref; 628 629 wakeref = intel_display_rpm_get_noresume(display); 630 631 for_each_power_domain(domain, mask) { 632 /* Clear before put, so put's sanity check is happy. */ 633 async_put_domains_clear_domain(power_domains, domain); 634 __intel_display_power_put_domain(display, domain); 635 } 636 637 intel_display_rpm_put(display, wakeref); 638 } 639 640 static void 641 intel_display_power_put_async_work(struct work_struct *work) 642 { 643 struct intel_display *display = container_of(work, struct intel_display, 644 power.domains.async_put_work.work); 645 struct i915_power_domains *power_domains = &display->power.domains; 646 struct ref_tracker *new_work_wakeref, *old_work_wakeref = NULL; 647 648 new_work_wakeref = intel_display_rpm_get_raw(display); 649 650 mutex_lock(&power_domains->lock); 651 652 /* 653 * Bail out if all the domain refs pending to be released were grabbed 654 * by subsequent gets or a flush_work. 655 */ 656 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 657 if (!old_work_wakeref) 658 goto out_verify; 659 660 release_async_put_domains(power_domains, 661 &power_domains->async_put_domains[0]); 662 663 /* 664 * Cancel the work that got queued after this one got dequeued, 665 * since here we released the corresponding async-put reference. 666 */ 667 cancel_async_put_work(power_domains, false); 668 669 /* Requeue the work if more domains were async put meanwhile. */ 670 if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) { 671 bitmap_copy(power_domains->async_put_domains[0].bits, 672 power_domains->async_put_domains[1].bits, 673 POWER_DOMAIN_NUM); 674 bitmap_zero(power_domains->async_put_domains[1].bits, 675 POWER_DOMAIN_NUM); 676 queue_async_put_domains_work(power_domains, 677 fetch_and_zero(&new_work_wakeref), 678 power_domains->async_put_next_delay); 679 power_domains->async_put_next_delay = 0; 680 } 681 682 out_verify: 683 verify_async_put_domains_state(power_domains); 684 685 mutex_unlock(&power_domains->lock); 686 687 if (old_work_wakeref) 688 intel_display_rpm_put_raw(display, old_work_wakeref); 689 if (new_work_wakeref) 690 intel_display_rpm_put_raw(display, new_work_wakeref); 691 } 692 693 /** 694 * __intel_display_power_put_async - release a power domain reference asynchronously 695 * @display: display device instance 696 * @domain: power domain to reference 697 * @wakeref: wakeref acquired for the reference that is being released 698 * @delay_ms: delay of powering down the power domain 699 * 700 * This function drops the power domain reference obtained by 701 * intel_display_power_get*() and schedules a work to power down the 702 * corresponding hardware block if this is the last reference. 703 * The power down is delayed by @delay_ms if this is >= 0, or by a default 704 * 100 ms otherwise. 705 */ 706 void __intel_display_power_put_async(struct intel_display *display, 707 enum intel_display_power_domain domain, 708 intel_wakeref_t wakeref, 709 int delay_ms) 710 { 711 struct i915_power_domains *power_domains = &display->power.domains; 712 struct ref_tracker *work_wakeref; 713 714 work_wakeref = intel_display_rpm_get_raw(display); 715 716 delay_ms = delay_ms >= 0 ? delay_ms : 100; 717 718 mutex_lock(&power_domains->lock); 719 720 if (power_domains->domain_use_count[domain] > 1) { 721 __intel_display_power_put_domain(display, domain); 722 723 goto out_verify; 724 } 725 726 drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1); 727 728 /* Let a pending work requeue itself or queue a new one. */ 729 if (power_domains->async_put_wakeref) { 730 set_bit(domain, power_domains->async_put_domains[1].bits); 731 power_domains->async_put_next_delay = max(power_domains->async_put_next_delay, 732 delay_ms); 733 } else { 734 set_bit(domain, power_domains->async_put_domains[0].bits); 735 queue_async_put_domains_work(power_domains, 736 fetch_and_zero(&work_wakeref), 737 delay_ms); 738 } 739 740 out_verify: 741 verify_async_put_domains_state(power_domains); 742 743 mutex_unlock(&power_domains->lock); 744 745 if (work_wakeref) 746 intel_display_rpm_put_raw(display, work_wakeref); 747 748 intel_display_rpm_put(display, wakeref); 749 } 750 751 /** 752 * intel_display_power_flush_work - flushes the async display power disabling work 753 * @display: display device instance 754 * 755 * Flushes any pending work that was scheduled by a preceding 756 * intel_display_power_put_async() call, completing the disabling of the 757 * corresponding power domains. 758 * 759 * Note that the work handler function may still be running after this 760 * function returns; to ensure that the work handler isn't running use 761 * intel_display_power_flush_work_sync() instead. 762 */ 763 void intel_display_power_flush_work(struct intel_display *display) 764 { 765 struct i915_power_domains *power_domains = &display->power.domains; 766 struct intel_power_domain_mask async_put_mask; 767 intel_wakeref_t work_wakeref; 768 769 mutex_lock(&power_domains->lock); 770 771 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 772 if (!work_wakeref) 773 goto out_verify; 774 775 async_put_domains_mask(power_domains, &async_put_mask); 776 release_async_put_domains(power_domains, &async_put_mask); 777 cancel_async_put_work(power_domains, false); 778 779 out_verify: 780 verify_async_put_domains_state(power_domains); 781 782 mutex_unlock(&power_domains->lock); 783 784 if (work_wakeref) 785 intel_display_rpm_put_raw(display, work_wakeref); 786 } 787 788 /** 789 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work 790 * @display: display device instance 791 * 792 * Like intel_display_power_flush_work(), but also ensure that the work 793 * handler function is not running any more when this function returns. 794 */ 795 static void 796 intel_display_power_flush_work_sync(struct intel_display *display) 797 { 798 struct i915_power_domains *power_domains = &display->power.domains; 799 800 intel_display_power_flush_work(display); 801 cancel_async_put_work(power_domains, true); 802 803 verify_async_put_domains_state(power_domains); 804 805 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); 806 } 807 808 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 809 /** 810 * intel_display_power_put - release a power domain reference 811 * @display: display device instance 812 * @domain: power domain to reference 813 * @wakeref: wakeref acquired for the reference that is being released 814 * 815 * This function drops the power domain reference obtained by 816 * intel_display_power_get() and might power down the corresponding hardware 817 * block right away if this is the last reference. 818 */ 819 void intel_display_power_put(struct intel_display *display, 820 enum intel_display_power_domain domain, 821 intel_wakeref_t wakeref) 822 { 823 __intel_display_power_put(display, domain); 824 intel_display_rpm_put(display, wakeref); 825 } 826 #else 827 /** 828 * intel_display_power_put_unchecked - release an unchecked power domain reference 829 * @display: display device instance 830 * @domain: power domain to reference 831 * 832 * This function drops the power domain reference obtained by 833 * intel_display_power_get() and might power down the corresponding hardware 834 * block right away if this is the last reference. 835 * 836 * This function is only for the power domain code's internal use to suppress wakeref 837 * tracking when the corresponding debug kconfig option is disabled, should not 838 * be used otherwise. 839 */ 840 void intel_display_power_put_unchecked(struct intel_display *display, 841 enum intel_display_power_domain domain) 842 { 843 __intel_display_power_put(display, domain); 844 intel_display_rpm_put_unchecked(display); 845 } 846 #endif 847 848 void 849 intel_display_power_get_in_set(struct intel_display *display, 850 struct intel_display_power_domain_set *power_domain_set, 851 enum intel_display_power_domain domain) 852 { 853 intel_wakeref_t __maybe_unused wf; 854 855 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); 856 857 wf = intel_display_power_get(display, domain); 858 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 859 power_domain_set->wakerefs[domain] = wf; 860 #endif 861 set_bit(domain, power_domain_set->mask.bits); 862 } 863 864 bool 865 intel_display_power_get_in_set_if_enabled(struct intel_display *display, 866 struct intel_display_power_domain_set *power_domain_set, 867 enum intel_display_power_domain domain) 868 { 869 intel_wakeref_t wf; 870 871 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); 872 873 wf = intel_display_power_get_if_enabled(display, domain); 874 if (!wf) 875 return false; 876 877 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 878 power_domain_set->wakerefs[domain] = wf; 879 #endif 880 set_bit(domain, power_domain_set->mask.bits); 881 882 return true; 883 } 884 885 void 886 intel_display_power_put_mask_in_set(struct intel_display *display, 887 struct intel_display_power_domain_set *power_domain_set, 888 struct intel_power_domain_mask *mask) 889 { 890 enum intel_display_power_domain domain; 891 892 drm_WARN_ON(display->drm, 893 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM)); 894 895 for_each_power_domain(domain, mask) { 896 intel_wakeref_t __maybe_unused wf = INTEL_WAKEREF_DEF; 897 898 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 899 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]); 900 #endif 901 intel_display_power_put(display, domain, wf); 902 clear_bit(domain, power_domain_set->mask.bits); 903 } 904 } 905 906 static int 907 sanitize_disable_power_well_option(int disable_power_well) 908 { 909 if (disable_power_well >= 0) 910 return !!disable_power_well; 911 912 return 1; 913 } 914 915 static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc) 916 { 917 u32 mask; 918 int requested_dc; 919 int max_dc; 920 921 if (!HAS_DISPLAY(display)) 922 return 0; 923 924 if (DISPLAY_VER(display) >= 20) 925 max_dc = 2; 926 else if (display->platform.dg2) 927 max_dc = 1; 928 else if (display->platform.dg1) 929 max_dc = 3; 930 else if (DISPLAY_VER(display) >= 12) 931 max_dc = 4; 932 else if (display->platform.geminilake || display->platform.broxton) 933 max_dc = 1; 934 else if (DISPLAY_VER(display) >= 9) 935 max_dc = 2; 936 else 937 max_dc = 0; 938 939 /* 940 * DC9 has a separate HW flow from the rest of the DC states, 941 * not depending on the DMC firmware. It's needed by system 942 * suspend/resume, so allow it unconditionally. 943 */ 944 mask = display->platform.geminilake || display->platform.broxton || 945 DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0; 946 947 if (!display->params.disable_power_well) 948 max_dc = 0; 949 950 if (enable_dc >= 0 && enable_dc <= max_dc) { 951 requested_dc = enable_dc; 952 } else if (enable_dc == -1) { 953 requested_dc = max_dc; 954 } else if (enable_dc > max_dc && enable_dc <= 4) { 955 drm_dbg_kms(display->drm, 956 "Adjusting requested max DC state (%d->%d)\n", 957 enable_dc, max_dc); 958 requested_dc = max_dc; 959 } else { 960 drm_err(display->drm, 961 "Unexpected value for enable_dc (%d)\n", enable_dc); 962 requested_dc = max_dc; 963 } 964 965 switch (requested_dc) { 966 case 4: 967 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6; 968 break; 969 case 3: 970 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5; 971 break; 972 case 2: 973 mask |= DC_STATE_EN_UPTO_DC6; 974 break; 975 case 1: 976 mask |= DC_STATE_EN_UPTO_DC5; 977 break; 978 } 979 980 drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask); 981 982 return mask; 983 } 984 985 /** 986 * intel_power_domains_init - initializes the power domain structures 987 * @display: display device instance 988 * 989 * Initializes the power domain structures for @display depending upon the 990 * supported platform. 991 */ 992 int intel_power_domains_init(struct intel_display *display) 993 { 994 struct i915_power_domains *power_domains = &display->power.domains; 995 996 display->params.disable_power_well = 997 sanitize_disable_power_well_option(display->params.disable_power_well); 998 power_domains->allowed_dc_mask = 999 get_allowed_dc_mask(display, display->params.enable_dc); 1000 1001 power_domains->target_dc_state = 1002 sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1003 1004 mutex_init(&power_domains->lock); 1005 1006 INIT_DELAYED_WORK(&power_domains->async_put_work, 1007 intel_display_power_put_async_work); 1008 1009 return intel_display_power_map_init(power_domains); 1010 } 1011 1012 /** 1013 * intel_power_domains_cleanup - clean up power domains resources 1014 * @display: display device instance 1015 * 1016 * Release any resources acquired by intel_power_domains_init() 1017 */ 1018 void intel_power_domains_cleanup(struct intel_display *display) 1019 { 1020 intel_display_power_map_cleanup(&display->power.domains); 1021 } 1022 1023 static void intel_power_domains_sync_hw(struct intel_display *display) 1024 { 1025 struct i915_power_domains *power_domains = &display->power.domains; 1026 struct i915_power_well *power_well; 1027 1028 mutex_lock(&power_domains->lock); 1029 for_each_power_well(display, power_well) 1030 intel_power_well_sync_hw(display, power_well); 1031 mutex_unlock(&power_domains->lock); 1032 } 1033 1034 static void gen9_dbuf_slice_set(struct intel_display *display, 1035 enum dbuf_slice slice, bool enable) 1036 { 1037 i915_reg_t reg = DBUF_CTL_S(slice); 1038 bool state; 1039 1040 intel_de_rmw(display, reg, DBUF_POWER_REQUEST, 1041 enable ? DBUF_POWER_REQUEST : 0); 1042 intel_de_posting_read(display, reg); 1043 udelay(10); 1044 1045 state = intel_de_read(display, reg) & DBUF_POWER_STATE; 1046 drm_WARN(display->drm, enable != state, 1047 "DBuf slice %d power %s timeout!\n", 1048 slice, str_enable_disable(enable)); 1049 } 1050 1051 void gen9_dbuf_slices_update(struct intel_display *display, 1052 u8 req_slices) 1053 { 1054 struct i915_power_domains *power_domains = &display->power.domains; 1055 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; 1056 enum dbuf_slice slice; 1057 1058 drm_WARN(display->drm, req_slices & ~slice_mask, 1059 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n", 1060 req_slices, slice_mask); 1061 1062 drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n", 1063 req_slices); 1064 1065 /* 1066 * Might be running this in parallel to gen9_dc_off_power_well_enable 1067 * being called from intel_dp_detect for instance, 1068 * which causes assertion triggered by race condition, 1069 * as gen9_assert_dbuf_enabled might preempt this when registers 1070 * were already updated, while dev_priv was not. 1071 */ 1072 mutex_lock(&power_domains->lock); 1073 1074 for_each_dbuf_slice(display, slice) 1075 gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice)); 1076 1077 display->dbuf.enabled_slices = req_slices; 1078 1079 mutex_unlock(&power_domains->lock); 1080 } 1081 1082 static void gen9_dbuf_enable(struct intel_display *display) 1083 { 1084 u8 slices_mask; 1085 1086 display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(display); 1087 1088 slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices; 1089 1090 if (DISPLAY_VER(display) >= 14) 1091 intel_pmdemand_program_dbuf(display, slices_mask); 1092 1093 /* 1094 * Just power up at least 1 slice, we will 1095 * figure out later which slices we have and what we need. 1096 */ 1097 gen9_dbuf_slices_update(display, slices_mask); 1098 } 1099 1100 static void gen9_dbuf_disable(struct intel_display *display) 1101 { 1102 gen9_dbuf_slices_update(display, 0); 1103 1104 if (DISPLAY_VER(display) >= 14) 1105 intel_pmdemand_program_dbuf(display, 0); 1106 } 1107 1108 static void gen12_dbuf_slices_config(struct intel_display *display) 1109 { 1110 enum dbuf_slice slice; 1111 1112 for_each_dbuf_slice(display, slice) 1113 intel_de_rmw(display, DBUF_CTL_S(slice), 1114 DBUF_TRACKER_STATE_SERVICE_MASK, 1115 DBUF_TRACKER_STATE_SERVICE(8)); 1116 } 1117 1118 static void icl_mbus_init(struct intel_display *display) 1119 { 1120 unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask; 1121 u32 mask, val, i; 1122 1123 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1124 return; 1125 1126 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | 1127 MBUS_ABOX_BT_CREDIT_POOL2_MASK | 1128 MBUS_ABOX_B_CREDIT_MASK | 1129 MBUS_ABOX_BW_CREDIT_MASK; 1130 val = MBUS_ABOX_BT_CREDIT_POOL1(16) | 1131 MBUS_ABOX_BT_CREDIT_POOL2(16) | 1132 MBUS_ABOX_B_CREDIT(1) | 1133 MBUS_ABOX_BW_CREDIT(1); 1134 1135 /* 1136 * gen12 platforms that use abox1 and abox2 for pixel data reads still 1137 * expect us to program the abox_ctl0 register as well, even though 1138 * we don't have to program other instance-0 registers like BW_BUDDY. 1139 */ 1140 if (DISPLAY_VER(display) == 12) 1141 abox_regs |= BIT(0); 1142 1143 for_each_set_bit(i, &abox_regs, sizeof(abox_regs)) 1144 intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val); 1145 } 1146 1147 static void hsw_assert_cdclk(struct intel_display *display) 1148 { 1149 u32 val = intel_de_read(display, LCPLL_CTL); 1150 1151 /* 1152 * The LCPLL register should be turned on by the BIOS. For now 1153 * let's just check its state and print errors in case 1154 * something is wrong. Don't even try to turn it on. 1155 */ 1156 1157 if (val & LCPLL_CD_SOURCE_FCLK) 1158 drm_err(display->drm, "CDCLK source is not LCPLL\n"); 1159 1160 if (val & LCPLL_PLL_DISABLE) 1161 drm_err(display->drm, "LCPLL is disabled\n"); 1162 1163 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC) 1164 drm_err(display->drm, "LCPLL not using non-SSC reference\n"); 1165 } 1166 1167 static void assert_can_disable_lcpll(struct intel_display *display) 1168 { 1169 struct drm_i915_private *dev_priv = to_i915(display->drm); 1170 struct intel_crtc *crtc; 1171 1172 for_each_intel_crtc(display->drm, crtc) 1173 INTEL_DISPLAY_STATE_WARN(display, crtc->active, 1174 "CRTC for pipe %c enabled\n", 1175 pipe_name(crtc->pipe)); 1176 1177 INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2), 1178 "Display power well on\n"); 1179 INTEL_DISPLAY_STATE_WARN(display, 1180 intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE, 1181 "SPLL enabled\n"); 1182 INTEL_DISPLAY_STATE_WARN(display, 1183 intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, 1184 "WRPLL1 enabled\n"); 1185 INTEL_DISPLAY_STATE_WARN(display, 1186 intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, 1187 "WRPLL2 enabled\n"); 1188 INTEL_DISPLAY_STATE_WARN(display, 1189 intel_de_read(display, PP_STATUS(display, 0)) & PP_ON, 1190 "Panel power on\n"); 1191 INTEL_DISPLAY_STATE_WARN(display, 1192 intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 1193 "CPU PWM1 enabled\n"); 1194 if (display->platform.haswell) 1195 INTEL_DISPLAY_STATE_WARN(display, 1196 intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 1197 "CPU PWM2 enabled\n"); 1198 INTEL_DISPLAY_STATE_WARN(display, 1199 intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, 1200 "PCH PWM1 enabled\n"); 1201 INTEL_DISPLAY_STATE_WARN(display, 1202 (intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 1203 "Utility pin enabled in PWM mode\n"); 1204 INTEL_DISPLAY_STATE_WARN(display, 1205 intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE, 1206 "PCH GTC enabled\n"); 1207 1208 /* 1209 * In theory we can still leave IRQs enabled, as long as only the HPD 1210 * interrupts remain enabled. We used to check for that, but since it's 1211 * gen-specific and since we only disable LCPLL after we fully disable 1212 * the interrupts, the check below should be enough. 1213 */ 1214 INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv), 1215 "IRQs enabled\n"); 1216 } 1217 1218 static u32 hsw_read_dcomp(struct intel_display *display) 1219 { 1220 if (display->platform.haswell) 1221 return intel_de_read(display, D_COMP_HSW); 1222 else 1223 return intel_de_read(display, D_COMP_BDW); 1224 } 1225 1226 static void hsw_write_dcomp(struct intel_display *display, u32 val) 1227 { 1228 struct drm_i915_private *dev_priv = to_i915(display->drm); 1229 1230 if (display->platform.haswell) { 1231 if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val)) 1232 drm_dbg_kms(display->drm, "Failed to write to D_COMP\n"); 1233 } else { 1234 intel_de_write(display, D_COMP_BDW, val); 1235 intel_de_posting_read(display, D_COMP_BDW); 1236 } 1237 } 1238 1239 /* 1240 * This function implements pieces of two sequences from BSpec: 1241 * - Sequence for display software to disable LCPLL 1242 * - Sequence for display software to allow package C8+ 1243 * The steps implemented here are just the steps that actually touch the LCPLL 1244 * register. Callers should take care of disabling all the display engine 1245 * functions, doing the mode unset, fixing interrupts, etc. 1246 */ 1247 static void hsw_disable_lcpll(struct intel_display *display, 1248 bool switch_to_fclk, bool allow_power_down) 1249 { 1250 u32 val; 1251 1252 assert_can_disable_lcpll(display); 1253 1254 val = intel_de_read(display, LCPLL_CTL); 1255 1256 if (switch_to_fclk) { 1257 val |= LCPLL_CD_SOURCE_FCLK; 1258 intel_de_write(display, LCPLL_CTL, val); 1259 1260 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & 1261 LCPLL_CD_SOURCE_FCLK_DONE, 1)) 1262 drm_err(display->drm, "Switching to FCLK failed\n"); 1263 1264 val = intel_de_read(display, LCPLL_CTL); 1265 } 1266 1267 val |= LCPLL_PLL_DISABLE; 1268 intel_de_write(display, LCPLL_CTL, val); 1269 intel_de_posting_read(display, LCPLL_CTL); 1270 1271 if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) 1272 drm_err(display->drm, "LCPLL still locked\n"); 1273 1274 val = hsw_read_dcomp(display); 1275 val |= D_COMP_COMP_DISABLE; 1276 hsw_write_dcomp(display, val); 1277 ndelay(100); 1278 1279 if (wait_for((hsw_read_dcomp(display) & 1280 D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) 1281 drm_err(display->drm, "D_COMP RCOMP still in progress\n"); 1282 1283 if (allow_power_down) { 1284 intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); 1285 intel_de_posting_read(display, LCPLL_CTL); 1286 } 1287 } 1288 1289 /* 1290 * Fully restores LCPLL, disallowing power down and switching back to LCPLL 1291 * source. 1292 */ 1293 static void hsw_restore_lcpll(struct intel_display *display) 1294 { 1295 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); 1296 u32 val; 1297 1298 val = intel_de_read(display, LCPLL_CTL); 1299 1300 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | 1301 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) 1302 return; 1303 1304 /* 1305 * Make sure we're not on PC8 state before disabling PC8, otherwise 1306 * we'll hang the machine. To prevent PC8 state, just enable force_wake. 1307 */ 1308 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); 1309 1310 if (val & LCPLL_POWER_DOWN_ALLOW) { 1311 val &= ~LCPLL_POWER_DOWN_ALLOW; 1312 intel_de_write(display, LCPLL_CTL, val); 1313 intel_de_posting_read(display, LCPLL_CTL); 1314 } 1315 1316 val = hsw_read_dcomp(display); 1317 val |= D_COMP_COMP_FORCE; 1318 val &= ~D_COMP_COMP_DISABLE; 1319 hsw_write_dcomp(display, val); 1320 1321 val = intel_de_read(display, LCPLL_CTL); 1322 val &= ~LCPLL_PLL_DISABLE; 1323 intel_de_write(display, LCPLL_CTL, val); 1324 1325 if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) 1326 drm_err(display->drm, "LCPLL not locked yet\n"); 1327 1328 if (val & LCPLL_CD_SOURCE_FCLK) { 1329 intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); 1330 1331 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & 1332 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 1333 drm_err(display->drm, 1334 "Switching back to LCPLL failed\n"); 1335 } 1336 1337 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); 1338 1339 intel_update_cdclk(display); 1340 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1341 } 1342 1343 /* 1344 * Package states C8 and deeper are really deep PC states that can only be 1345 * reached when all the devices on the system allow it, so even if the graphics 1346 * device allows PC8+, it doesn't mean the system will actually get to these 1347 * states. Our driver only allows PC8+ when going into runtime PM. 1348 * 1349 * The requirements for PC8+ are that all the outputs are disabled, the power 1350 * well is disabled and most interrupts are disabled, and these are also 1351 * requirements for runtime PM. When these conditions are met, we manually do 1352 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk 1353 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard 1354 * hang the machine. 1355 * 1356 * When we really reach PC8 or deeper states (not just when we allow it) we lose 1357 * the state of some registers, so when we come back from PC8+ we need to 1358 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't 1359 * need to take care of the registers kept by RC6. Notice that this happens even 1360 * if we don't put the device in PCI D3 state (which is what currently happens 1361 * because of the runtime PM support). 1362 * 1363 * For more, read "Display Sequences for Package C8" on the hardware 1364 * documentation. 1365 */ 1366 static void hsw_enable_pc8(struct intel_display *display) 1367 { 1368 struct drm_i915_private *dev_priv = to_i915(display->drm); 1369 1370 drm_dbg_kms(display->drm, "Enabling package C8+\n"); 1371 1372 if (HAS_PCH_LPT_LP(dev_priv)) 1373 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1374 PCH_LP_PARTITION_LEVEL_DISABLE, 0); 1375 1376 lpt_disable_clkout_dp(display); 1377 hsw_disable_lcpll(display, true, true); 1378 } 1379 1380 static void hsw_disable_pc8(struct intel_display *display) 1381 { 1382 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); 1383 1384 drm_dbg_kms(display->drm, "Disabling package C8+\n"); 1385 1386 hsw_restore_lcpll(display); 1387 intel_init_pch_refclk(display); 1388 1389 /* Many display registers don't survive PC8+ */ 1390 #ifdef I915 /* FIXME */ 1391 intel_clock_gating_init(dev_priv); 1392 #endif 1393 } 1394 1395 static void intel_pch_reset_handshake(struct intel_display *display, 1396 bool enable) 1397 { 1398 i915_reg_t reg; 1399 u32 reset_bits; 1400 1401 if (display->platform.ivybridge) { 1402 reg = GEN7_MSG_CTL; 1403 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK; 1404 } else { 1405 reg = HSW_NDE_RSTWRN_OPT; 1406 reset_bits = RESET_PCH_HANDSHAKE_ENABLE; 1407 } 1408 1409 if (DISPLAY_VER(display) >= 14) 1410 reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; 1411 1412 intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0); 1413 } 1414 1415 static void skl_display_core_init(struct intel_display *display, 1416 bool resume) 1417 { 1418 struct drm_i915_private *dev_priv = to_i915(display->drm); 1419 struct i915_power_domains *power_domains = &display->power.domains; 1420 struct i915_power_well *well; 1421 1422 gen9_set_dc_state(display, DC_STATE_DISABLE); 1423 1424 /* enable PCH reset handshake */ 1425 intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv)); 1426 1427 if (!HAS_DISPLAY(display)) 1428 return; 1429 1430 /* enable PG1 and Misc I/O */ 1431 mutex_lock(&power_domains->lock); 1432 1433 well = lookup_power_well(display, SKL_DISP_PW_1); 1434 intel_power_well_enable(display, well); 1435 1436 well = lookup_power_well(display, SKL_DISP_PW_MISC_IO); 1437 intel_power_well_enable(display, well); 1438 1439 mutex_unlock(&power_domains->lock); 1440 1441 intel_cdclk_init_hw(display); 1442 1443 gen9_dbuf_enable(display); 1444 1445 if (resume) 1446 intel_dmc_load_program(display); 1447 } 1448 1449 static void skl_display_core_uninit(struct intel_display *display) 1450 { 1451 struct i915_power_domains *power_domains = &display->power.domains; 1452 struct i915_power_well *well; 1453 1454 if (!HAS_DISPLAY(display)) 1455 return; 1456 1457 gen9_disable_dc_states(display); 1458 /* TODO: disable DMC program */ 1459 1460 gen9_dbuf_disable(display); 1461 1462 intel_cdclk_uninit_hw(display); 1463 1464 /* The spec doesn't call for removing the reset handshake flag */ 1465 /* disable PG1 and Misc I/O */ 1466 1467 mutex_lock(&power_domains->lock); 1468 1469 /* 1470 * BSpec says to keep the MISC IO power well enabled here, only 1471 * remove our request for power well 1. 1472 * Note that even though the driver's request is removed power well 1 1473 * may stay enabled after this due to DMC's own request on it. 1474 */ 1475 well = lookup_power_well(display, SKL_DISP_PW_1); 1476 intel_power_well_disable(display, well); 1477 1478 mutex_unlock(&power_domains->lock); 1479 1480 usleep_range(10, 30); /* 10 us delay per Bspec */ 1481 } 1482 1483 static void bxt_display_core_init(struct intel_display *display, bool resume) 1484 { 1485 struct i915_power_domains *power_domains = &display->power.domains; 1486 struct i915_power_well *well; 1487 1488 gen9_set_dc_state(display, DC_STATE_DISABLE); 1489 1490 /* 1491 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 1492 * or else the reset will hang because there is no PCH to respond. 1493 * Move the handshake programming to initialization sequence. 1494 * Previously was left up to BIOS. 1495 */ 1496 intel_pch_reset_handshake(display, false); 1497 1498 if (!HAS_DISPLAY(display)) 1499 return; 1500 1501 /* Enable PG1 */ 1502 mutex_lock(&power_domains->lock); 1503 1504 well = lookup_power_well(display, SKL_DISP_PW_1); 1505 intel_power_well_enable(display, well); 1506 1507 mutex_unlock(&power_domains->lock); 1508 1509 intel_cdclk_init_hw(display); 1510 1511 gen9_dbuf_enable(display); 1512 1513 if (resume) 1514 intel_dmc_load_program(display); 1515 } 1516 1517 static void bxt_display_core_uninit(struct intel_display *display) 1518 { 1519 struct i915_power_domains *power_domains = &display->power.domains; 1520 struct i915_power_well *well; 1521 1522 if (!HAS_DISPLAY(display)) 1523 return; 1524 1525 gen9_disable_dc_states(display); 1526 /* TODO: disable DMC program */ 1527 1528 gen9_dbuf_disable(display); 1529 1530 intel_cdclk_uninit_hw(display); 1531 1532 /* The spec doesn't call for removing the reset handshake flag */ 1533 1534 /* 1535 * Disable PW1 (PG1). 1536 * Note that even though the driver's request is removed power well 1 1537 * may stay enabled after this due to DMC's own request on it. 1538 */ 1539 mutex_lock(&power_domains->lock); 1540 1541 well = lookup_power_well(display, SKL_DISP_PW_1); 1542 intel_power_well_disable(display, well); 1543 1544 mutex_unlock(&power_domains->lock); 1545 1546 usleep_range(10, 30); /* 10 us delay per Bspec */ 1547 } 1548 1549 struct buddy_page_mask { 1550 u32 page_mask; 1551 u8 type; 1552 u8 num_channels; 1553 }; 1554 1555 static const struct buddy_page_mask tgl_buddy_page_masks[] = { 1556 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF }, 1557 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF }, 1558 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C }, 1559 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C }, 1560 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F }, 1561 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E }, 1562 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 }, 1563 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 }, 1564 {} 1565 }; 1566 1567 static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = { 1568 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 }, 1569 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 }, 1570 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 }, 1571 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 }, 1572 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 }, 1573 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 }, 1574 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 }, 1575 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 }, 1576 {} 1577 }; 1578 1579 static void tgl_bw_buddy_init(struct intel_display *display) 1580 { 1581 struct drm_i915_private *dev_priv = to_i915(display->drm); 1582 enum intel_dram_type type = dev_priv->dram_info.type; 1583 u8 num_channels = dev_priv->dram_info.num_channels; 1584 const struct buddy_page_mask *table; 1585 unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; 1586 int config, i; 1587 1588 /* BW_BUDDY registers are not used on dgpu's beyond DG1 */ 1589 if (display->platform.dgfx && !display->platform.dg1) 1590 return; 1591 1592 if (display->platform.alderlake_s || 1593 (display->platform.rocketlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))) 1594 /* Wa_1409767108 */ 1595 table = wa_1409767108_buddy_page_masks; 1596 else 1597 table = tgl_buddy_page_masks; 1598 1599 for (config = 0; table[config].page_mask != 0; config++) 1600 if (table[config].num_channels == num_channels && 1601 table[config].type == type) 1602 break; 1603 1604 if (table[config].page_mask == 0) { 1605 drm_dbg_kms(display->drm, 1606 "Unknown memory configuration; disabling address buddy logic.\n"); 1607 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) 1608 intel_de_write(display, BW_BUDDY_CTL(i), 1609 BW_BUDDY_DISABLE); 1610 } else { 1611 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) { 1612 intel_de_write(display, BW_BUDDY_PAGE_MASK(i), 1613 table[config].page_mask); 1614 1615 /* Wa_22010178259:tgl,dg1,rkl,adl-s */ 1616 if (DISPLAY_VER(display) == 12) 1617 intel_de_rmw(display, BW_BUDDY_CTL(i), 1618 BW_BUDDY_TLB_REQ_TIMER_MASK, 1619 BW_BUDDY_TLB_REQ_TIMER(0x8)); 1620 } 1621 } 1622 } 1623 1624 static void icl_display_core_init(struct intel_display *display, 1625 bool resume) 1626 { 1627 struct drm_i915_private *dev_priv = to_i915(display->drm); 1628 struct i915_power_domains *power_domains = &display->power.domains; 1629 struct i915_power_well *well; 1630 1631 gen9_set_dc_state(display, DC_STATE_DISABLE); 1632 1633 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ 1634 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && 1635 INTEL_PCH_TYPE(dev_priv) < PCH_DG1) 1636 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0, 1637 PCH_DPMGUNIT_CLOCK_GATE_DISABLE); 1638 1639 /* 1. Enable PCH reset handshake. */ 1640 intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv)); 1641 1642 if (!HAS_DISPLAY(display)) 1643 return; 1644 1645 /* 2. Initialize all combo phys */ 1646 intel_combo_phy_init(display); 1647 1648 /* 1649 * 3. Enable Power Well 1 (PG1). 1650 * The AUX IO power wells will be enabled on demand. 1651 */ 1652 mutex_lock(&power_domains->lock); 1653 well = lookup_power_well(display, SKL_DISP_PW_1); 1654 intel_power_well_enable(display, well); 1655 mutex_unlock(&power_domains->lock); 1656 1657 if (DISPLAY_VER(display) == 14) 1658 intel_de_rmw(display, DC_STATE_EN, 1659 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0); 1660 1661 /* 4. Enable CDCLK. */ 1662 intel_cdclk_init_hw(display); 1663 1664 if (DISPLAY_VER(display) == 12 || display->platform.dg2) 1665 gen12_dbuf_slices_config(display); 1666 1667 /* 5. Enable DBUF. */ 1668 gen9_dbuf_enable(display); 1669 1670 /* 6. Setup MBUS. */ 1671 icl_mbus_init(display); 1672 1673 /* 7. Program arbiter BW_BUDDY registers */ 1674 if (DISPLAY_VER(display) >= 12) 1675 tgl_bw_buddy_init(display); 1676 1677 /* 8. Ensure PHYs have completed calibration and adaptation */ 1678 if (display->platform.dg2) 1679 intel_snps_phy_wait_for_calibration(display); 1680 1681 /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ 1682 if (DISPLAY_VERx100(display) == 1401) 1683 intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); 1684 1685 if (resume) 1686 intel_dmc_load_program(display); 1687 1688 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */ 1689 if (IS_DISPLAY_VERx100(display, 1200, 1300)) 1690 intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0, 1691 DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | 1692 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR); 1693 1694 /* Wa_14011503030:xelpd */ 1695 if (DISPLAY_VER(display) == 13) 1696 intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); 1697 1698 /* Wa_15013987218 */ 1699 if (DISPLAY_VER(display) == 20) { 1700 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1701 0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE); 1702 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1703 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0); 1704 } 1705 } 1706 1707 static void icl_display_core_uninit(struct intel_display *display) 1708 { 1709 struct i915_power_domains *power_domains = &display->power.domains; 1710 struct i915_power_well *well; 1711 1712 if (!HAS_DISPLAY(display)) 1713 return; 1714 1715 gen9_disable_dc_states(display); 1716 intel_dmc_disable_program(display); 1717 1718 /* 1. Disable all display engine functions -> already done */ 1719 1720 /* 2. Disable DBUF */ 1721 gen9_dbuf_disable(display); 1722 1723 /* 3. Disable CD clock */ 1724 intel_cdclk_uninit_hw(display); 1725 1726 if (DISPLAY_VER(display) == 14) 1727 intel_de_rmw(display, DC_STATE_EN, 0, 1728 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH); 1729 1730 /* 1731 * 4. Disable Power Well 1 (PG1). 1732 * The AUX IO power wells are toggled on demand, so they are already 1733 * disabled at this point. 1734 */ 1735 mutex_lock(&power_domains->lock); 1736 well = lookup_power_well(display, SKL_DISP_PW_1); 1737 intel_power_well_disable(display, well); 1738 mutex_unlock(&power_domains->lock); 1739 1740 /* 5. */ 1741 intel_combo_phy_uninit(display); 1742 } 1743 1744 static void chv_phy_control_init(struct intel_display *display) 1745 { 1746 struct i915_power_well *cmn_bc = 1747 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1748 struct i915_power_well *cmn_d = 1749 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1750 1751 /* 1752 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 1753 * workaround never ever read DISPLAY_PHY_CONTROL, and 1754 * instead maintain a shadow copy ourselves. Use the actual 1755 * power well state and lane status to reconstruct the 1756 * expected initial value. 1757 */ 1758 display->power.chv_phy_control = 1759 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 1760 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 1761 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 1762 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 1763 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 1764 1765 /* 1766 * If all lanes are disabled we leave the override disabled 1767 * with all power down bits cleared to match the state we 1768 * would use after disabling the port. Otherwise enable the 1769 * override and set the lane powerdown bits accding to the 1770 * current lane status. 1771 */ 1772 if (intel_power_well_is_enabled(display, cmn_bc)) { 1773 u32 status = intel_de_read(display, DPLL(display, PIPE_A)); 1774 unsigned int mask; 1775 1776 mask = status & DPLL_PORTB_READY_MASK; 1777 if (mask == 0xf) 1778 mask = 0x0; 1779 else 1780 display->power.chv_phy_control |= 1781 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 1782 1783 display->power.chv_phy_control |= 1784 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 1785 1786 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 1787 if (mask == 0xf) 1788 mask = 0x0; 1789 else 1790 display->power.chv_phy_control |= 1791 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 1792 1793 display->power.chv_phy_control |= 1794 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 1795 1796 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 1797 1798 display->power.chv_phy_assert[DPIO_PHY0] = false; 1799 } else { 1800 display->power.chv_phy_assert[DPIO_PHY0] = true; 1801 } 1802 1803 if (intel_power_well_is_enabled(display, cmn_d)) { 1804 u32 status = intel_de_read(display, DPIO_PHY_STATUS); 1805 unsigned int mask; 1806 1807 mask = status & DPLL_PORTD_READY_MASK; 1808 1809 if (mask == 0xf) 1810 mask = 0x0; 1811 else 1812 display->power.chv_phy_control |= 1813 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 1814 1815 display->power.chv_phy_control |= 1816 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 1817 1818 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 1819 1820 display->power.chv_phy_assert[DPIO_PHY1] = false; 1821 } else { 1822 display->power.chv_phy_assert[DPIO_PHY1] = true; 1823 } 1824 1825 drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n", 1826 display->power.chv_phy_control); 1827 1828 /* Defer application of initial phy_control to enabling the powerwell */ 1829 } 1830 1831 static void vlv_cmnlane_wa(struct intel_display *display) 1832 { 1833 struct i915_power_well *cmn = 1834 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1835 struct i915_power_well *disp2d = 1836 lookup_power_well(display, VLV_DISP_PW_DISP2D); 1837 1838 /* If the display might be already active skip this */ 1839 if (intel_power_well_is_enabled(display, cmn) && 1840 intel_power_well_is_enabled(display, disp2d) && 1841 intel_de_read(display, DPIO_CTL) & DPIO_CMNRST) 1842 return; 1843 1844 drm_dbg_kms(display->drm, "toggling display PHY side reset\n"); 1845 1846 /* cmnlane needs DPLL registers */ 1847 intel_power_well_enable(display, disp2d); 1848 1849 /* 1850 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 1851 * Need to assert and de-assert PHY SB reset by gating the 1852 * common lane power, then un-gating it. 1853 * Simply ungating isn't enough to reset the PHY enough to get 1854 * ports and lanes running. 1855 */ 1856 intel_power_well_disable(display, cmn); 1857 } 1858 1859 static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0) 1860 { 1861 struct drm_i915_private *dev_priv = to_i915(display->drm); 1862 bool ret; 1863 1864 vlv_punit_get(dev_priv); 1865 ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; 1866 vlv_punit_put(dev_priv); 1867 1868 return ret; 1869 } 1870 1871 static void assert_ved_power_gated(struct intel_display *display) 1872 { 1873 drm_WARN(display->drm, 1874 !vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0), 1875 "VED not power gated\n"); 1876 } 1877 1878 static void assert_isp_power_gated(struct intel_display *display) 1879 { 1880 static const struct pci_device_id isp_ids[] = { 1881 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)}, 1882 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)}, 1883 {} 1884 }; 1885 1886 drm_WARN(display->drm, !pci_dev_present(isp_ids) && 1887 !vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0), 1888 "ISP not power gated\n"); 1889 } 1890 1891 static void intel_power_domains_verify_state(struct intel_display *display); 1892 1893 /** 1894 * intel_power_domains_init_hw - initialize hardware power domain state 1895 * @display: display device instance 1896 * @resume: Called from resume code paths or not 1897 * 1898 * This function initializes the hardware power domain state and enables all 1899 * power wells belonging to the INIT power domain. Power wells in other 1900 * domains (and not in the INIT domain) are referenced or disabled by 1901 * intel_modeset_readout_hw_state(). After that the reference count of each 1902 * power well must match its HW enabled state, see 1903 * intel_power_domains_verify_state(). 1904 * 1905 * It will return with power domains disabled (to be enabled later by 1906 * intel_power_domains_enable()) and must be paired with 1907 * intel_power_domains_driver_remove(). 1908 */ 1909 void intel_power_domains_init_hw(struct intel_display *display, bool resume) 1910 { 1911 struct drm_i915_private *i915 = to_i915(display->drm); 1912 struct i915_power_domains *power_domains = &display->power.domains; 1913 1914 power_domains->initializing = true; 1915 1916 if (DISPLAY_VER(display) >= 11) { 1917 icl_display_core_init(display, resume); 1918 } else if (display->platform.geminilake || display->platform.broxton) { 1919 bxt_display_core_init(display, resume); 1920 } else if (DISPLAY_VER(display) == 9) { 1921 skl_display_core_init(display, resume); 1922 } else if (display->platform.cherryview) { 1923 mutex_lock(&power_domains->lock); 1924 chv_phy_control_init(display); 1925 mutex_unlock(&power_domains->lock); 1926 assert_isp_power_gated(display); 1927 } else if (display->platform.valleyview) { 1928 mutex_lock(&power_domains->lock); 1929 vlv_cmnlane_wa(display); 1930 mutex_unlock(&power_domains->lock); 1931 assert_ved_power_gated(display); 1932 assert_isp_power_gated(display); 1933 } else if (display->platform.broadwell || display->platform.haswell) { 1934 hsw_assert_cdclk(display); 1935 intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915)); 1936 } else if (display->platform.ivybridge) { 1937 intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915)); 1938 } 1939 1940 /* 1941 * Keep all power wells enabled for any dependent HW access during 1942 * initialization and to make sure we keep BIOS enabled display HW 1943 * resources powered until display HW readout is complete. We drop 1944 * this reference in intel_power_domains_enable(). 1945 */ 1946 drm_WARN_ON(display->drm, power_domains->init_wakeref); 1947 power_domains->init_wakeref = 1948 intel_display_power_get(display, POWER_DOMAIN_INIT); 1949 1950 /* Disable power support if the user asked so. */ 1951 if (!display->params.disable_power_well) { 1952 drm_WARN_ON(display->drm, power_domains->disable_wakeref); 1953 display->power.domains.disable_wakeref = intel_display_power_get(display, 1954 POWER_DOMAIN_INIT); 1955 } 1956 intel_power_domains_sync_hw(display); 1957 1958 power_domains->initializing = false; 1959 } 1960 1961 /** 1962 * intel_power_domains_driver_remove - deinitialize hw power domain state 1963 * @display: display device instance 1964 * 1965 * De-initializes the display power domain HW state. It also ensures that the 1966 * device stays powered up so that the driver can be reloaded. 1967 * 1968 * It must be called with power domains already disabled (after a call to 1969 * intel_power_domains_disable()) and must be paired with 1970 * intel_power_domains_init_hw(). 1971 */ 1972 void intel_power_domains_driver_remove(struct intel_display *display) 1973 { 1974 intel_wakeref_t wakeref __maybe_unused = 1975 fetch_and_zero(&display->power.domains.init_wakeref); 1976 1977 /* Remove the refcount we took to keep power well support disabled. */ 1978 if (!display->params.disable_power_well) 1979 intel_display_power_put(display, POWER_DOMAIN_INIT, 1980 fetch_and_zero(&display->power.domains.disable_wakeref)); 1981 1982 intel_display_power_flush_work_sync(display); 1983 1984 intel_power_domains_verify_state(display); 1985 1986 /* Keep the power well enabled, but cancel its rpm wakeref. */ 1987 intel_display_rpm_put(display, wakeref); 1988 } 1989 1990 /** 1991 * intel_power_domains_sanitize_state - sanitize power domains state 1992 * @display: display device instance 1993 * 1994 * Sanitize the power domains state during driver loading and system resume. 1995 * The function will disable all display power wells that BIOS has enabled 1996 * without a user for it (any user for a power well has taken a reference 1997 * on it by the time this function is called, after the state of all the 1998 * pipe, encoder, etc. HW resources have been sanitized). 1999 */ 2000 void intel_power_domains_sanitize_state(struct intel_display *display) 2001 { 2002 struct i915_power_domains *power_domains = &display->power.domains; 2003 struct i915_power_well *power_well; 2004 2005 mutex_lock(&power_domains->lock); 2006 2007 for_each_power_well_reverse(display, power_well) { 2008 if (power_well->desc->always_on || power_well->count || 2009 !intel_power_well_is_enabled(display, power_well)) 2010 continue; 2011 2012 drm_dbg_kms(display->drm, 2013 "BIOS left unused %s power well enabled, disabling it\n", 2014 intel_power_well_name(power_well)); 2015 intel_power_well_disable(display, power_well); 2016 } 2017 2018 mutex_unlock(&power_domains->lock); 2019 } 2020 2021 /** 2022 * intel_power_domains_enable - enable toggling of display power wells 2023 * @display: display device instance 2024 * 2025 * Enable the ondemand enabling/disabling of the display power wells. Note that 2026 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled 2027 * only at specific points of the display modeset sequence, thus they are not 2028 * affected by the intel_power_domains_enable()/disable() calls. The purpose 2029 * of these function is to keep the rest of power wells enabled until the end 2030 * of display HW readout (which will acquire the power references reflecting 2031 * the current HW state). 2032 */ 2033 void intel_power_domains_enable(struct intel_display *display) 2034 { 2035 intel_wakeref_t wakeref __maybe_unused = 2036 fetch_and_zero(&display->power.domains.init_wakeref); 2037 2038 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 2039 intel_power_domains_verify_state(display); 2040 } 2041 2042 /** 2043 * intel_power_domains_disable - disable toggling of display power wells 2044 * @display: display device instance 2045 * 2046 * Disable the ondemand enabling/disabling of the display power wells. See 2047 * intel_power_domains_enable() for which power wells this call controls. 2048 */ 2049 void intel_power_domains_disable(struct intel_display *display) 2050 { 2051 struct i915_power_domains *power_domains = &display->power.domains; 2052 2053 drm_WARN_ON(display->drm, power_domains->init_wakeref); 2054 power_domains->init_wakeref = 2055 intel_display_power_get(display, POWER_DOMAIN_INIT); 2056 2057 intel_power_domains_verify_state(display); 2058 } 2059 2060 /** 2061 * intel_power_domains_suspend - suspend power domain state 2062 * @display: display device instance 2063 * @s2idle: specifies whether we go to idle, or deeper sleep 2064 * 2065 * This function prepares the hardware power domain state before entering 2066 * system suspend. 2067 * 2068 * It must be called with power domains already disabled (after a call to 2069 * intel_power_domains_disable()) and paired with intel_power_domains_resume(). 2070 */ 2071 void intel_power_domains_suspend(struct intel_display *display, bool s2idle) 2072 { 2073 struct i915_power_domains *power_domains = &display->power.domains; 2074 intel_wakeref_t wakeref __maybe_unused = 2075 fetch_and_zero(&power_domains->init_wakeref); 2076 2077 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 2078 2079 /* 2080 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 2081 * support don't manually deinit the power domains. This also means the 2082 * DMC firmware will stay active, it will power down any HW 2083 * resources as required and also enable deeper system power states 2084 * that would be blocked if the firmware was inactive. 2085 */ 2086 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle && 2087 intel_dmc_has_payload(display)) { 2088 intel_display_power_flush_work(display); 2089 intel_power_domains_verify_state(display); 2090 return; 2091 } 2092 2093 /* 2094 * Even if power well support was disabled we still want to disable 2095 * power wells if power domains must be deinitialized for suspend. 2096 */ 2097 if (!display->params.disable_power_well) 2098 intel_display_power_put(display, POWER_DOMAIN_INIT, 2099 fetch_and_zero(&display->power.domains.disable_wakeref)); 2100 2101 intel_display_power_flush_work(display); 2102 intel_power_domains_verify_state(display); 2103 2104 if (DISPLAY_VER(display) >= 11) 2105 icl_display_core_uninit(display); 2106 else if (display->platform.geminilake || display->platform.broxton) 2107 bxt_display_core_uninit(display); 2108 else if (DISPLAY_VER(display) == 9) 2109 skl_display_core_uninit(display); 2110 2111 power_domains->display_core_suspended = true; 2112 } 2113 2114 /** 2115 * intel_power_domains_resume - resume power domain state 2116 * @display: display device instance 2117 * 2118 * This function resume the hardware power domain state during system resume. 2119 * 2120 * It will return with power domain support disabled (to be enabled later by 2121 * intel_power_domains_enable()) and must be paired with 2122 * intel_power_domains_suspend(). 2123 */ 2124 void intel_power_domains_resume(struct intel_display *display) 2125 { 2126 struct i915_power_domains *power_domains = &display->power.domains; 2127 2128 if (power_domains->display_core_suspended) { 2129 intel_power_domains_init_hw(display, true); 2130 power_domains->display_core_suspended = false; 2131 } else { 2132 drm_WARN_ON(display->drm, power_domains->init_wakeref); 2133 power_domains->init_wakeref = 2134 intel_display_power_get(display, POWER_DOMAIN_INIT); 2135 } 2136 2137 intel_power_domains_verify_state(display); 2138 } 2139 2140 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 2141 2142 static void intel_power_domains_dump_info(struct intel_display *display) 2143 { 2144 struct i915_power_domains *power_domains = &display->power.domains; 2145 struct i915_power_well *power_well; 2146 2147 for_each_power_well(display, power_well) { 2148 enum intel_display_power_domain domain; 2149 2150 drm_dbg_kms(display->drm, "%-25s %d\n", 2151 intel_power_well_name(power_well), intel_power_well_refcount(power_well)); 2152 2153 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2154 drm_dbg_kms(display->drm, " %-23s %d\n", 2155 intel_display_power_domain_str(domain), 2156 power_domains->domain_use_count[domain]); 2157 } 2158 } 2159 2160 /** 2161 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 2162 * @display: display device instance 2163 * 2164 * Verify if the reference count of each power well matches its HW enabled 2165 * state and the total refcount of the domains it belongs to. This must be 2166 * called after modeset HW state sanitization, which is responsible for 2167 * acquiring reference counts for any power wells in use and disabling the 2168 * ones left on by BIOS but not required by any active output. 2169 */ 2170 static void intel_power_domains_verify_state(struct intel_display *display) 2171 { 2172 struct i915_power_domains *power_domains = &display->power.domains; 2173 struct i915_power_well *power_well; 2174 bool dump_domain_info; 2175 2176 mutex_lock(&power_domains->lock); 2177 2178 verify_async_put_domains_state(power_domains); 2179 2180 dump_domain_info = false; 2181 for_each_power_well(display, power_well) { 2182 enum intel_display_power_domain domain; 2183 int domains_count; 2184 bool enabled; 2185 2186 enabled = intel_power_well_is_enabled(display, power_well); 2187 if ((intel_power_well_refcount(power_well) || 2188 intel_power_well_is_always_on(power_well)) != 2189 enabled) 2190 drm_err(display->drm, 2191 "power well %s state mismatch (refcount %d/enabled %d)", 2192 intel_power_well_name(power_well), 2193 intel_power_well_refcount(power_well), enabled); 2194 2195 domains_count = 0; 2196 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2197 domains_count += power_domains->domain_use_count[domain]; 2198 2199 if (intel_power_well_refcount(power_well) != domains_count) { 2200 drm_err(display->drm, 2201 "power well %s refcount/domain refcount mismatch " 2202 "(refcount %d/domains refcount %d)\n", 2203 intel_power_well_name(power_well), 2204 intel_power_well_refcount(power_well), 2205 domains_count); 2206 dump_domain_info = true; 2207 } 2208 } 2209 2210 if (dump_domain_info) { 2211 static bool dumped; 2212 2213 if (!dumped) { 2214 intel_power_domains_dump_info(display); 2215 dumped = true; 2216 } 2217 } 2218 2219 mutex_unlock(&power_domains->lock); 2220 } 2221 2222 #else 2223 2224 static void intel_power_domains_verify_state(struct intel_display *display) 2225 { 2226 } 2227 2228 #endif 2229 2230 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle) 2231 { 2232 struct drm_i915_private *i915 = to_i915(display->drm); 2233 2234 intel_power_domains_suspend(display, s2idle); 2235 2236 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || 2237 display->platform.broxton) { 2238 bxt_enable_dc9(display); 2239 } else if (display->platform.haswell || display->platform.broadwell) { 2240 hsw_enable_pc8(display); 2241 } 2242 2243 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2244 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) 2245 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); 2246 } 2247 2248 void intel_display_power_resume_early(struct intel_display *display) 2249 { 2250 struct drm_i915_private *i915 = to_i915(display->drm); 2251 2252 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || 2253 display->platform.broxton) { 2254 gen9_sanitize_dc_state(display); 2255 bxt_disable_dc9(display); 2256 } else if (display->platform.haswell || display->platform.broadwell) { 2257 hsw_disable_pc8(display); 2258 } 2259 2260 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2261 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) 2262 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); 2263 2264 intel_power_domains_resume(display); 2265 } 2266 2267 void intel_display_power_suspend(struct intel_display *display) 2268 { 2269 if (DISPLAY_VER(display) >= 11) { 2270 icl_display_core_uninit(display); 2271 bxt_enable_dc9(display); 2272 } else if (display->platform.geminilake || display->platform.broxton) { 2273 bxt_display_core_uninit(display); 2274 bxt_enable_dc9(display); 2275 } else if (display->platform.haswell || display->platform.broadwell) { 2276 hsw_enable_pc8(display); 2277 } 2278 } 2279 2280 void intel_display_power_resume(struct intel_display *display) 2281 { 2282 struct i915_power_domains *power_domains = &display->power.domains; 2283 2284 if (DISPLAY_VER(display) >= 11) { 2285 bxt_disable_dc9(display); 2286 icl_display_core_init(display, true); 2287 if (intel_dmc_has_payload(display)) { 2288 if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 2289 skl_enable_dc6(display); 2290 else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 2291 gen9_enable_dc5(display); 2292 } 2293 } else if (display->platform.geminilake || display->platform.broxton) { 2294 bxt_disable_dc9(display); 2295 bxt_display_core_init(display, true); 2296 if (intel_dmc_has_payload(display) && 2297 (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) 2298 gen9_enable_dc5(display); 2299 } else if (display->platform.haswell || display->platform.broadwell) { 2300 hsw_disable_pc8(display); 2301 } 2302 } 2303 2304 void intel_display_power_debug(struct intel_display *display, struct seq_file *m) 2305 { 2306 struct i915_power_domains *power_domains = &display->power.domains; 2307 int i; 2308 2309 mutex_lock(&power_domains->lock); 2310 2311 seq_printf(m, "Runtime power status: %s\n", 2312 str_enabled_disabled(!power_domains->init_wakeref)); 2313 2314 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); 2315 for (i = 0; i < power_domains->power_well_count; i++) { 2316 struct i915_power_well *power_well; 2317 enum intel_display_power_domain power_domain; 2318 2319 power_well = &power_domains->power_wells[i]; 2320 seq_printf(m, "%-25s %d\n", intel_power_well_name(power_well), 2321 intel_power_well_refcount(power_well)); 2322 2323 for_each_power_domain(power_domain, intel_power_well_domains(power_well)) 2324 seq_printf(m, " %-23s %d\n", 2325 intel_display_power_domain_str(power_domain), 2326 power_domains->domain_use_count[power_domain]); 2327 } 2328 2329 mutex_unlock(&power_domains->lock); 2330 } 2331 2332 struct intel_ddi_port_domains { 2333 enum port port_start; 2334 enum port port_end; 2335 enum aux_ch aux_ch_start; 2336 enum aux_ch aux_ch_end; 2337 2338 enum intel_display_power_domain ddi_lanes; 2339 enum intel_display_power_domain ddi_io; 2340 enum intel_display_power_domain aux_io; 2341 enum intel_display_power_domain aux_legacy_usbc; 2342 enum intel_display_power_domain aux_tbt; 2343 }; 2344 2345 static const struct intel_ddi_port_domains 2346 i9xx_port_domains[] = { 2347 { 2348 .port_start = PORT_A, 2349 .port_end = PORT_F, 2350 .aux_ch_start = AUX_CH_A, 2351 .aux_ch_end = AUX_CH_F, 2352 2353 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2354 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2355 .aux_io = POWER_DOMAIN_AUX_IO_A, 2356 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2357 .aux_tbt = POWER_DOMAIN_INVALID, 2358 }, 2359 }; 2360 2361 static const struct intel_ddi_port_domains 2362 d11_port_domains[] = { 2363 { 2364 .port_start = PORT_A, 2365 .port_end = PORT_B, 2366 .aux_ch_start = AUX_CH_A, 2367 .aux_ch_end = AUX_CH_B, 2368 2369 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2370 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2371 .aux_io = POWER_DOMAIN_AUX_IO_A, 2372 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2373 .aux_tbt = POWER_DOMAIN_INVALID, 2374 }, { 2375 .port_start = PORT_C, 2376 .port_end = PORT_F, 2377 .aux_ch_start = AUX_CH_C, 2378 .aux_ch_end = AUX_CH_F, 2379 2380 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C, 2381 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C, 2382 .aux_io = POWER_DOMAIN_AUX_IO_C, 2383 .aux_legacy_usbc = POWER_DOMAIN_AUX_C, 2384 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2385 }, 2386 }; 2387 2388 static const struct intel_ddi_port_domains 2389 d12_port_domains[] = { 2390 { 2391 .port_start = PORT_A, 2392 .port_end = PORT_C, 2393 .aux_ch_start = AUX_CH_A, 2394 .aux_ch_end = AUX_CH_C, 2395 2396 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2397 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2398 .aux_io = POWER_DOMAIN_AUX_IO_A, 2399 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2400 .aux_tbt = POWER_DOMAIN_INVALID, 2401 }, { 2402 .port_start = PORT_TC1, 2403 .port_end = PORT_TC6, 2404 .aux_ch_start = AUX_CH_USBC1, 2405 .aux_ch_end = AUX_CH_USBC6, 2406 2407 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2408 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2409 .aux_io = POWER_DOMAIN_INVALID, 2410 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2411 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2412 }, 2413 }; 2414 2415 static const struct intel_ddi_port_domains 2416 d13_port_domains[] = { 2417 { 2418 .port_start = PORT_A, 2419 .port_end = PORT_C, 2420 .aux_ch_start = AUX_CH_A, 2421 .aux_ch_end = AUX_CH_C, 2422 2423 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2424 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2425 .aux_io = POWER_DOMAIN_AUX_IO_A, 2426 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2427 .aux_tbt = POWER_DOMAIN_INVALID, 2428 }, { 2429 .port_start = PORT_TC1, 2430 .port_end = PORT_TC4, 2431 .aux_ch_start = AUX_CH_USBC1, 2432 .aux_ch_end = AUX_CH_USBC4, 2433 2434 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2435 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2436 .aux_io = POWER_DOMAIN_INVALID, 2437 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2438 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2439 }, { 2440 .port_start = PORT_D_XELPD, 2441 .port_end = PORT_E_XELPD, 2442 .aux_ch_start = AUX_CH_D_XELPD, 2443 .aux_ch_end = AUX_CH_E_XELPD, 2444 2445 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D, 2446 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D, 2447 .aux_io = POWER_DOMAIN_AUX_IO_D, 2448 .aux_legacy_usbc = POWER_DOMAIN_AUX_D, 2449 .aux_tbt = POWER_DOMAIN_INVALID, 2450 }, 2451 }; 2452 2453 static void 2454 intel_port_domains_for_platform(struct intel_display *display, 2455 const struct intel_ddi_port_domains **domains, 2456 int *domains_size) 2457 { 2458 if (DISPLAY_VER(display) >= 13) { 2459 *domains = d13_port_domains; 2460 *domains_size = ARRAY_SIZE(d13_port_domains); 2461 } else if (DISPLAY_VER(display) >= 12) { 2462 *domains = d12_port_domains; 2463 *domains_size = ARRAY_SIZE(d12_port_domains); 2464 } else if (DISPLAY_VER(display) >= 11) { 2465 *domains = d11_port_domains; 2466 *domains_size = ARRAY_SIZE(d11_port_domains); 2467 } else { 2468 *domains = i9xx_port_domains; 2469 *domains_size = ARRAY_SIZE(i9xx_port_domains); 2470 } 2471 } 2472 2473 static const struct intel_ddi_port_domains * 2474 intel_port_domains_for_port(struct intel_display *display, enum port port) 2475 { 2476 const struct intel_ddi_port_domains *domains; 2477 int domains_size; 2478 int i; 2479 2480 intel_port_domains_for_platform(display, &domains, &domains_size); 2481 for (i = 0; i < domains_size; i++) 2482 if (port >= domains[i].port_start && port <= domains[i].port_end) 2483 return &domains[i]; 2484 2485 return NULL; 2486 } 2487 2488 enum intel_display_power_domain 2489 intel_display_power_ddi_io_domain(struct intel_display *display, enum port port) 2490 { 2491 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); 2492 2493 if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) 2494 return POWER_DOMAIN_PORT_DDI_IO_A; 2495 2496 return domains->ddi_io + (int)(port - domains->port_start); 2497 } 2498 2499 enum intel_display_power_domain 2500 intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port) 2501 { 2502 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); 2503 2504 if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) 2505 return POWER_DOMAIN_PORT_DDI_LANES_A; 2506 2507 return domains->ddi_lanes + (int)(port - domains->port_start); 2508 } 2509 2510 static const struct intel_ddi_port_domains * 2511 intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch) 2512 { 2513 const struct intel_ddi_port_domains *domains; 2514 int domains_size; 2515 int i; 2516 2517 intel_port_domains_for_platform(display, &domains, &domains_size); 2518 for (i = 0; i < domains_size; i++) 2519 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end) 2520 return &domains[i]; 2521 2522 return NULL; 2523 } 2524 2525 enum intel_display_power_domain 2526 intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch) 2527 { 2528 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2529 2530 if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) 2531 return POWER_DOMAIN_AUX_IO_A; 2532 2533 return domains->aux_io + (int)(aux_ch - domains->aux_ch_start); 2534 } 2535 2536 enum intel_display_power_domain 2537 intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch) 2538 { 2539 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2540 2541 if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) 2542 return POWER_DOMAIN_AUX_A; 2543 2544 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start); 2545 } 2546 2547 enum intel_display_power_domain 2548 intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch) 2549 { 2550 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2551 2552 if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) 2553 return POWER_DOMAIN_AUX_TBT1; 2554 2555 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start); 2556 } 2557