1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include "i915_drv.h" 9 #include "i915_irq.h" 10 #include "i915_reg.h" 11 #include "intel_backlight_regs.h" 12 #include "intel_cdclk.h" 13 #include "intel_clock_gating.h" 14 #include "intel_combo_phy.h" 15 #include "intel_de.h" 16 #include "intel_display_power.h" 17 #include "intel_display_power_map.h" 18 #include "intel_display_power_well.h" 19 #include "intel_display_types.h" 20 #include "intel_dmc.h" 21 #include "intel_mchbar_regs.h" 22 #include "intel_pch_refclk.h" 23 #include "intel_pcode.h" 24 #include "intel_pmdemand.h" 25 #include "intel_pps_regs.h" 26 #include "intel_snps_phy.h" 27 #include "skl_watermark.h" 28 #include "skl_watermark_regs.h" 29 #include "vlv_sideband.h" 30 31 #define for_each_power_domain_well(__dev_priv, __power_well, __domain) \ 32 for_each_power_well(__dev_priv, __power_well) \ 33 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 34 35 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \ 36 for_each_power_well_reverse(__dev_priv, __power_well) \ 37 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 38 39 const char * 40 intel_display_power_domain_str(enum intel_display_power_domain domain) 41 { 42 switch (domain) { 43 case POWER_DOMAIN_DISPLAY_CORE: 44 return "DISPLAY_CORE"; 45 case POWER_DOMAIN_PIPE_A: 46 return "PIPE_A"; 47 case POWER_DOMAIN_PIPE_B: 48 return "PIPE_B"; 49 case POWER_DOMAIN_PIPE_C: 50 return "PIPE_C"; 51 case POWER_DOMAIN_PIPE_D: 52 return "PIPE_D"; 53 case POWER_DOMAIN_PIPE_PANEL_FITTER_A: 54 return "PIPE_PANEL_FITTER_A"; 55 case POWER_DOMAIN_PIPE_PANEL_FITTER_B: 56 return "PIPE_PANEL_FITTER_B"; 57 case POWER_DOMAIN_PIPE_PANEL_FITTER_C: 58 return "PIPE_PANEL_FITTER_C"; 59 case POWER_DOMAIN_PIPE_PANEL_FITTER_D: 60 return "PIPE_PANEL_FITTER_D"; 61 case POWER_DOMAIN_TRANSCODER_A: 62 return "TRANSCODER_A"; 63 case POWER_DOMAIN_TRANSCODER_B: 64 return "TRANSCODER_B"; 65 case POWER_DOMAIN_TRANSCODER_C: 66 return "TRANSCODER_C"; 67 case POWER_DOMAIN_TRANSCODER_D: 68 return "TRANSCODER_D"; 69 case POWER_DOMAIN_TRANSCODER_EDP: 70 return "TRANSCODER_EDP"; 71 case POWER_DOMAIN_TRANSCODER_DSI_A: 72 return "TRANSCODER_DSI_A"; 73 case POWER_DOMAIN_TRANSCODER_DSI_C: 74 return "TRANSCODER_DSI_C"; 75 case POWER_DOMAIN_TRANSCODER_VDSC_PW2: 76 return "TRANSCODER_VDSC_PW2"; 77 case POWER_DOMAIN_PORT_DDI_LANES_A: 78 return "PORT_DDI_LANES_A"; 79 case POWER_DOMAIN_PORT_DDI_LANES_B: 80 return "PORT_DDI_LANES_B"; 81 case POWER_DOMAIN_PORT_DDI_LANES_C: 82 return "PORT_DDI_LANES_C"; 83 case POWER_DOMAIN_PORT_DDI_LANES_D: 84 return "PORT_DDI_LANES_D"; 85 case POWER_DOMAIN_PORT_DDI_LANES_E: 86 return "PORT_DDI_LANES_E"; 87 case POWER_DOMAIN_PORT_DDI_LANES_F: 88 return "PORT_DDI_LANES_F"; 89 case POWER_DOMAIN_PORT_DDI_LANES_TC1: 90 return "PORT_DDI_LANES_TC1"; 91 case POWER_DOMAIN_PORT_DDI_LANES_TC2: 92 return "PORT_DDI_LANES_TC2"; 93 case POWER_DOMAIN_PORT_DDI_LANES_TC3: 94 return "PORT_DDI_LANES_TC3"; 95 case POWER_DOMAIN_PORT_DDI_LANES_TC4: 96 return "PORT_DDI_LANES_TC4"; 97 case POWER_DOMAIN_PORT_DDI_LANES_TC5: 98 return "PORT_DDI_LANES_TC5"; 99 case POWER_DOMAIN_PORT_DDI_LANES_TC6: 100 return "PORT_DDI_LANES_TC6"; 101 case POWER_DOMAIN_PORT_DDI_IO_A: 102 return "PORT_DDI_IO_A"; 103 case POWER_DOMAIN_PORT_DDI_IO_B: 104 return "PORT_DDI_IO_B"; 105 case POWER_DOMAIN_PORT_DDI_IO_C: 106 return "PORT_DDI_IO_C"; 107 case POWER_DOMAIN_PORT_DDI_IO_D: 108 return "PORT_DDI_IO_D"; 109 case POWER_DOMAIN_PORT_DDI_IO_E: 110 return "PORT_DDI_IO_E"; 111 case POWER_DOMAIN_PORT_DDI_IO_F: 112 return "PORT_DDI_IO_F"; 113 case POWER_DOMAIN_PORT_DDI_IO_TC1: 114 return "PORT_DDI_IO_TC1"; 115 case POWER_DOMAIN_PORT_DDI_IO_TC2: 116 return "PORT_DDI_IO_TC2"; 117 case POWER_DOMAIN_PORT_DDI_IO_TC3: 118 return "PORT_DDI_IO_TC3"; 119 case POWER_DOMAIN_PORT_DDI_IO_TC4: 120 return "PORT_DDI_IO_TC4"; 121 case POWER_DOMAIN_PORT_DDI_IO_TC5: 122 return "PORT_DDI_IO_TC5"; 123 case POWER_DOMAIN_PORT_DDI_IO_TC6: 124 return "PORT_DDI_IO_TC6"; 125 case POWER_DOMAIN_PORT_DSI: 126 return "PORT_DSI"; 127 case POWER_DOMAIN_PORT_CRT: 128 return "PORT_CRT"; 129 case POWER_DOMAIN_PORT_OTHER: 130 return "PORT_OTHER"; 131 case POWER_DOMAIN_VGA: 132 return "VGA"; 133 case POWER_DOMAIN_AUDIO_MMIO: 134 return "AUDIO_MMIO"; 135 case POWER_DOMAIN_AUDIO_PLAYBACK: 136 return "AUDIO_PLAYBACK"; 137 case POWER_DOMAIN_AUX_IO_A: 138 return "AUX_IO_A"; 139 case POWER_DOMAIN_AUX_IO_B: 140 return "AUX_IO_B"; 141 case POWER_DOMAIN_AUX_IO_C: 142 return "AUX_IO_C"; 143 case POWER_DOMAIN_AUX_IO_D: 144 return "AUX_IO_D"; 145 case POWER_DOMAIN_AUX_IO_E: 146 return "AUX_IO_E"; 147 case POWER_DOMAIN_AUX_IO_F: 148 return "AUX_IO_F"; 149 case POWER_DOMAIN_AUX_A: 150 return "AUX_A"; 151 case POWER_DOMAIN_AUX_B: 152 return "AUX_B"; 153 case POWER_DOMAIN_AUX_C: 154 return "AUX_C"; 155 case POWER_DOMAIN_AUX_D: 156 return "AUX_D"; 157 case POWER_DOMAIN_AUX_E: 158 return "AUX_E"; 159 case POWER_DOMAIN_AUX_F: 160 return "AUX_F"; 161 case POWER_DOMAIN_AUX_USBC1: 162 return "AUX_USBC1"; 163 case POWER_DOMAIN_AUX_USBC2: 164 return "AUX_USBC2"; 165 case POWER_DOMAIN_AUX_USBC3: 166 return "AUX_USBC3"; 167 case POWER_DOMAIN_AUX_USBC4: 168 return "AUX_USBC4"; 169 case POWER_DOMAIN_AUX_USBC5: 170 return "AUX_USBC5"; 171 case POWER_DOMAIN_AUX_USBC6: 172 return "AUX_USBC6"; 173 case POWER_DOMAIN_AUX_TBT1: 174 return "AUX_TBT1"; 175 case POWER_DOMAIN_AUX_TBT2: 176 return "AUX_TBT2"; 177 case POWER_DOMAIN_AUX_TBT3: 178 return "AUX_TBT3"; 179 case POWER_DOMAIN_AUX_TBT4: 180 return "AUX_TBT4"; 181 case POWER_DOMAIN_AUX_TBT5: 182 return "AUX_TBT5"; 183 case POWER_DOMAIN_AUX_TBT6: 184 return "AUX_TBT6"; 185 case POWER_DOMAIN_GMBUS: 186 return "GMBUS"; 187 case POWER_DOMAIN_INIT: 188 return "INIT"; 189 case POWER_DOMAIN_GT_IRQ: 190 return "GT_IRQ"; 191 case POWER_DOMAIN_DC_OFF: 192 return "DC_OFF"; 193 case POWER_DOMAIN_TC_COLD_OFF: 194 return "TC_COLD_OFF"; 195 default: 196 MISSING_CASE(domain); 197 return "?"; 198 } 199 } 200 201 /** 202 * __intel_display_power_is_enabled - unlocked check for a power domain 203 * @dev_priv: i915 device instance 204 * @domain: power domain to check 205 * 206 * This is the unlocked version of intel_display_power_is_enabled() and should 207 * only be used from error capture and recovery code where deadlocks are 208 * possible. 209 * 210 * Returns: 211 * True when the power domain is enabled, false otherwise. 212 */ 213 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 214 enum intel_display_power_domain domain) 215 { 216 struct i915_power_well *power_well; 217 bool is_enabled; 218 219 if (pm_runtime_suspended(dev_priv->drm.dev)) 220 return false; 221 222 is_enabled = true; 223 224 for_each_power_domain_well_reverse(dev_priv, power_well, domain) { 225 if (intel_power_well_is_always_on(power_well)) 226 continue; 227 228 if (!intel_power_well_is_enabled_cached(power_well)) { 229 is_enabled = false; 230 break; 231 } 232 } 233 234 return is_enabled; 235 } 236 237 /** 238 * intel_display_power_is_enabled - check for a power domain 239 * @dev_priv: i915 device instance 240 * @domain: power domain to check 241 * 242 * This function can be used to check the hw power domain state. It is mostly 243 * used in hardware state readout functions. Everywhere else code should rely 244 * upon explicit power domain reference counting to ensure that the hardware 245 * block is powered up before accessing it. 246 * 247 * Callers must hold the relevant modesetting locks to ensure that concurrent 248 * threads can't disable the power well while the caller tries to read a few 249 * registers. 250 * 251 * Returns: 252 * True when the power domain is enabled, false otherwise. 253 */ 254 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 255 enum intel_display_power_domain domain) 256 { 257 struct i915_power_domains *power_domains; 258 bool ret; 259 260 power_domains = &dev_priv->display.power.domains; 261 262 mutex_lock(&power_domains->lock); 263 ret = __intel_display_power_is_enabled(dev_priv, domain); 264 mutex_unlock(&power_domains->lock); 265 266 return ret; 267 } 268 269 static u32 270 sanitize_target_dc_state(struct drm_i915_private *i915, 271 u32 target_dc_state) 272 { 273 struct i915_power_domains *power_domains = &i915->display.power.domains; 274 static const u32 states[] = { 275 DC_STATE_EN_UPTO_DC6, 276 DC_STATE_EN_UPTO_DC5, 277 DC_STATE_EN_DC3CO, 278 DC_STATE_DISABLE, 279 }; 280 int i; 281 282 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { 283 if (target_dc_state != states[i]) 284 continue; 285 286 if (power_domains->allowed_dc_mask & target_dc_state) 287 break; 288 289 target_dc_state = states[i + 1]; 290 } 291 292 return target_dc_state; 293 } 294 295 /** 296 * intel_display_power_set_target_dc_state - Set target dc state. 297 * @dev_priv: i915 device 298 * @state: state which needs to be set as target_dc_state. 299 * 300 * This function set the "DC off" power well target_dc_state, 301 * based upon this target_dc_stste, "DC off" power well will 302 * enable desired DC state. 303 */ 304 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 305 u32 state) 306 { 307 struct i915_power_well *power_well; 308 bool dc_off_enabled; 309 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 310 311 mutex_lock(&power_domains->lock); 312 power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF); 313 314 if (drm_WARN_ON(&dev_priv->drm, !power_well)) 315 goto unlock; 316 317 state = sanitize_target_dc_state(dev_priv, state); 318 319 if (state == power_domains->target_dc_state) 320 goto unlock; 321 322 dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well); 323 /* 324 * If DC off power well is disabled, need to enable and disable the 325 * DC off power well to effect target DC state. 326 */ 327 if (!dc_off_enabled) 328 intel_power_well_enable(dev_priv, power_well); 329 330 power_domains->target_dc_state = state; 331 332 if (!dc_off_enabled) 333 intel_power_well_disable(dev_priv, power_well); 334 335 unlock: 336 mutex_unlock(&power_domains->lock); 337 } 338 339 static void __async_put_domains_mask(struct i915_power_domains *power_domains, 340 struct intel_power_domain_mask *mask) 341 { 342 bitmap_or(mask->bits, 343 power_domains->async_put_domains[0].bits, 344 power_domains->async_put_domains[1].bits, 345 POWER_DOMAIN_NUM); 346 } 347 348 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 349 350 static bool 351 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 352 { 353 struct drm_i915_private *i915 = container_of(power_domains, 354 struct drm_i915_private, 355 display.power.domains); 356 357 return !drm_WARN_ON(&i915->drm, 358 bitmap_intersects(power_domains->async_put_domains[0].bits, 359 power_domains->async_put_domains[1].bits, 360 POWER_DOMAIN_NUM)); 361 } 362 363 static bool 364 __async_put_domains_state_ok(struct i915_power_domains *power_domains) 365 { 366 struct drm_i915_private *i915 = container_of(power_domains, 367 struct drm_i915_private, 368 display.power.domains); 369 struct intel_power_domain_mask async_put_mask; 370 enum intel_display_power_domain domain; 371 bool err = false; 372 373 err |= !assert_async_put_domain_masks_disjoint(power_domains); 374 __async_put_domains_mask(power_domains, &async_put_mask); 375 err |= drm_WARN_ON(&i915->drm, 376 !!power_domains->async_put_wakeref != 377 !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)); 378 379 for_each_power_domain(domain, &async_put_mask) 380 err |= drm_WARN_ON(&i915->drm, 381 power_domains->domain_use_count[domain] != 1); 382 383 return !err; 384 } 385 386 static void print_power_domains(struct i915_power_domains *power_domains, 387 const char *prefix, struct intel_power_domain_mask *mask) 388 { 389 struct drm_i915_private *i915 = container_of(power_domains, 390 struct drm_i915_private, 391 display.power.domains); 392 enum intel_display_power_domain domain; 393 394 drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); 395 for_each_power_domain(domain, mask) 396 drm_dbg(&i915->drm, "%s use_count %d\n", 397 intel_display_power_domain_str(domain), 398 power_domains->domain_use_count[domain]); 399 } 400 401 static void 402 print_async_put_domains_state(struct i915_power_domains *power_domains) 403 { 404 struct drm_i915_private *i915 = container_of(power_domains, 405 struct drm_i915_private, 406 display.power.domains); 407 408 drm_dbg(&i915->drm, "async_put_wakeref: %s\n", 409 str_yes_no(power_domains->async_put_wakeref)); 410 411 print_power_domains(power_domains, "async_put_domains[0]", 412 &power_domains->async_put_domains[0]); 413 print_power_domains(power_domains, "async_put_domains[1]", 414 &power_domains->async_put_domains[1]); 415 } 416 417 static void 418 verify_async_put_domains_state(struct i915_power_domains *power_domains) 419 { 420 if (!__async_put_domains_state_ok(power_domains)) 421 print_async_put_domains_state(power_domains); 422 } 423 424 #else 425 426 static void 427 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 428 { 429 } 430 431 static void 432 verify_async_put_domains_state(struct i915_power_domains *power_domains) 433 { 434 } 435 436 #endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */ 437 438 static void async_put_domains_mask(struct i915_power_domains *power_domains, 439 struct intel_power_domain_mask *mask) 440 441 { 442 assert_async_put_domain_masks_disjoint(power_domains); 443 444 __async_put_domains_mask(power_domains, mask); 445 } 446 447 static void 448 async_put_domains_clear_domain(struct i915_power_domains *power_domains, 449 enum intel_display_power_domain domain) 450 { 451 assert_async_put_domain_masks_disjoint(power_domains); 452 453 clear_bit(domain, power_domains->async_put_domains[0].bits); 454 clear_bit(domain, power_domains->async_put_domains[1].bits); 455 } 456 457 static void 458 cancel_async_put_work(struct i915_power_domains *power_domains, bool sync) 459 { 460 if (sync) 461 cancel_delayed_work_sync(&power_domains->async_put_work); 462 else 463 cancel_delayed_work(&power_domains->async_put_work); 464 465 power_domains->async_put_next_delay = 0; 466 } 467 468 static bool 469 intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv, 470 enum intel_display_power_domain domain) 471 { 472 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 473 struct intel_power_domain_mask async_put_mask; 474 bool ret = false; 475 476 async_put_domains_mask(power_domains, &async_put_mask); 477 if (!test_bit(domain, async_put_mask.bits)) 478 goto out_verify; 479 480 async_put_domains_clear_domain(power_domains, domain); 481 482 ret = true; 483 484 async_put_domains_mask(power_domains, &async_put_mask); 485 if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)) 486 goto out_verify; 487 488 cancel_async_put_work(power_domains, false); 489 intel_runtime_pm_put_raw(&dev_priv->runtime_pm, 490 fetch_and_zero(&power_domains->async_put_wakeref)); 491 out_verify: 492 verify_async_put_domains_state(power_domains); 493 494 return ret; 495 } 496 497 static void 498 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 499 enum intel_display_power_domain domain) 500 { 501 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 502 struct i915_power_well *power_well; 503 504 if (intel_display_power_grab_async_put_ref(dev_priv, domain)) 505 return; 506 507 for_each_power_domain_well(dev_priv, power_well, domain) 508 intel_power_well_get(dev_priv, power_well); 509 510 power_domains->domain_use_count[domain]++; 511 } 512 513 /** 514 * intel_display_power_get - grab a power domain reference 515 * @dev_priv: i915 device instance 516 * @domain: power domain to reference 517 * 518 * This function grabs a power domain reference for @domain and ensures that the 519 * power domain and all its parents are powered up. Therefore users should only 520 * grab a reference to the innermost power domain they need. 521 * 522 * Any power domain reference obtained by this function must have a symmetric 523 * call to intel_display_power_put() to release the reference again. 524 */ 525 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 526 enum intel_display_power_domain domain) 527 { 528 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 529 intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 530 531 mutex_lock(&power_domains->lock); 532 __intel_display_power_get_domain(dev_priv, domain); 533 mutex_unlock(&power_domains->lock); 534 535 return wakeref; 536 } 537 538 /** 539 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 540 * @dev_priv: i915 device instance 541 * @domain: power domain to reference 542 * 543 * This function grabs a power domain reference for @domain and ensures that the 544 * power domain and all its parents are powered up. Therefore users should only 545 * grab a reference to the innermost power domain they need. 546 * 547 * Any power domain reference obtained by this function must have a symmetric 548 * call to intel_display_power_put() to release the reference again. 549 */ 550 intel_wakeref_t 551 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 552 enum intel_display_power_domain domain) 553 { 554 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 555 intel_wakeref_t wakeref; 556 bool is_enabled; 557 558 wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm); 559 if (!wakeref) 560 return false; 561 562 mutex_lock(&power_domains->lock); 563 564 if (__intel_display_power_is_enabled(dev_priv, domain)) { 565 __intel_display_power_get_domain(dev_priv, domain); 566 is_enabled = true; 567 } else { 568 is_enabled = false; 569 } 570 571 mutex_unlock(&power_domains->lock); 572 573 if (!is_enabled) { 574 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 575 wakeref = 0; 576 } 577 578 return wakeref; 579 } 580 581 static void 582 __intel_display_power_put_domain(struct drm_i915_private *dev_priv, 583 enum intel_display_power_domain domain) 584 { 585 struct i915_power_domains *power_domains; 586 struct i915_power_well *power_well; 587 const char *name = intel_display_power_domain_str(domain); 588 struct intel_power_domain_mask async_put_mask; 589 590 power_domains = &dev_priv->display.power.domains; 591 592 drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain], 593 "Use count on domain %s is already zero\n", 594 name); 595 async_put_domains_mask(power_domains, &async_put_mask); 596 drm_WARN(&dev_priv->drm, 597 test_bit(domain, async_put_mask.bits), 598 "Async disabling of domain %s is pending\n", 599 name); 600 601 power_domains->domain_use_count[domain]--; 602 603 for_each_power_domain_well_reverse(dev_priv, power_well, domain) 604 intel_power_well_put(dev_priv, power_well); 605 } 606 607 static void __intel_display_power_put(struct drm_i915_private *dev_priv, 608 enum intel_display_power_domain domain) 609 { 610 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 611 612 mutex_lock(&power_domains->lock); 613 __intel_display_power_put_domain(dev_priv, domain); 614 mutex_unlock(&power_domains->lock); 615 } 616 617 static void 618 queue_async_put_domains_work(struct i915_power_domains *power_domains, 619 intel_wakeref_t wakeref, 620 int delay_ms) 621 { 622 struct drm_i915_private *i915 = container_of(power_domains, 623 struct drm_i915_private, 624 display.power.domains); 625 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref); 626 power_domains->async_put_wakeref = wakeref; 627 drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq, 628 &power_domains->async_put_work, 629 msecs_to_jiffies(delay_ms))); 630 } 631 632 static void 633 release_async_put_domains(struct i915_power_domains *power_domains, 634 struct intel_power_domain_mask *mask) 635 { 636 struct drm_i915_private *dev_priv = 637 container_of(power_domains, struct drm_i915_private, 638 display.power.domains); 639 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 640 enum intel_display_power_domain domain; 641 intel_wakeref_t wakeref; 642 643 wakeref = intel_runtime_pm_get_noresume(rpm); 644 645 for_each_power_domain(domain, mask) { 646 /* Clear before put, so put's sanity check is happy. */ 647 async_put_domains_clear_domain(power_domains, domain); 648 __intel_display_power_put_domain(dev_priv, domain); 649 } 650 651 intel_runtime_pm_put(rpm, wakeref); 652 } 653 654 static void 655 intel_display_power_put_async_work(struct work_struct *work) 656 { 657 struct drm_i915_private *dev_priv = 658 container_of(work, struct drm_i915_private, 659 display.power.domains.async_put_work.work); 660 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 661 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 662 intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm); 663 intel_wakeref_t old_work_wakeref = 0; 664 665 mutex_lock(&power_domains->lock); 666 667 /* 668 * Bail out if all the domain refs pending to be released were grabbed 669 * by subsequent gets or a flush_work. 670 */ 671 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 672 if (!old_work_wakeref) 673 goto out_verify; 674 675 release_async_put_domains(power_domains, 676 &power_domains->async_put_domains[0]); 677 678 /* 679 * Cancel the work that got queued after this one got dequeued, 680 * since here we released the corresponding async-put reference. 681 */ 682 cancel_async_put_work(power_domains, false); 683 684 /* Requeue the work if more domains were async put meanwhile. */ 685 if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) { 686 bitmap_copy(power_domains->async_put_domains[0].bits, 687 power_domains->async_put_domains[1].bits, 688 POWER_DOMAIN_NUM); 689 bitmap_zero(power_domains->async_put_domains[1].bits, 690 POWER_DOMAIN_NUM); 691 queue_async_put_domains_work(power_domains, 692 fetch_and_zero(&new_work_wakeref), 693 power_domains->async_put_next_delay); 694 power_domains->async_put_next_delay = 0; 695 } 696 697 out_verify: 698 verify_async_put_domains_state(power_domains); 699 700 mutex_unlock(&power_domains->lock); 701 702 if (old_work_wakeref) 703 intel_runtime_pm_put_raw(rpm, old_work_wakeref); 704 if (new_work_wakeref) 705 intel_runtime_pm_put_raw(rpm, new_work_wakeref); 706 } 707 708 /** 709 * __intel_display_power_put_async - release a power domain reference asynchronously 710 * @i915: i915 device instance 711 * @domain: power domain to reference 712 * @wakeref: wakeref acquired for the reference that is being released 713 * @delay_ms: delay of powering down the power domain 714 * 715 * This function drops the power domain reference obtained by 716 * intel_display_power_get*() and schedules a work to power down the 717 * corresponding hardware block if this is the last reference. 718 * The power down is delayed by @delay_ms if this is >= 0, or by a default 719 * 100 ms otherwise. 720 */ 721 void __intel_display_power_put_async(struct drm_i915_private *i915, 722 enum intel_display_power_domain domain, 723 intel_wakeref_t wakeref, 724 int delay_ms) 725 { 726 struct i915_power_domains *power_domains = &i915->display.power.domains; 727 struct intel_runtime_pm *rpm = &i915->runtime_pm; 728 intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm); 729 730 delay_ms = delay_ms >= 0 ? delay_ms : 100; 731 732 mutex_lock(&power_domains->lock); 733 734 if (power_domains->domain_use_count[domain] > 1) { 735 __intel_display_power_put_domain(i915, domain); 736 737 goto out_verify; 738 } 739 740 drm_WARN_ON(&i915->drm, power_domains->domain_use_count[domain] != 1); 741 742 /* Let a pending work requeue itself or queue a new one. */ 743 if (power_domains->async_put_wakeref) { 744 set_bit(domain, power_domains->async_put_domains[1].bits); 745 power_domains->async_put_next_delay = max(power_domains->async_put_next_delay, 746 delay_ms); 747 } else { 748 set_bit(domain, power_domains->async_put_domains[0].bits); 749 queue_async_put_domains_work(power_domains, 750 fetch_and_zero(&work_wakeref), 751 delay_ms); 752 } 753 754 out_verify: 755 verify_async_put_domains_state(power_domains); 756 757 mutex_unlock(&power_domains->lock); 758 759 if (work_wakeref) 760 intel_runtime_pm_put_raw(rpm, work_wakeref); 761 762 intel_runtime_pm_put(rpm, wakeref); 763 } 764 765 /** 766 * intel_display_power_flush_work - flushes the async display power disabling work 767 * @i915: i915 device instance 768 * 769 * Flushes any pending work that was scheduled by a preceding 770 * intel_display_power_put_async() call, completing the disabling of the 771 * corresponding power domains. 772 * 773 * Note that the work handler function may still be running after this 774 * function returns; to ensure that the work handler isn't running use 775 * intel_display_power_flush_work_sync() instead. 776 */ 777 void intel_display_power_flush_work(struct drm_i915_private *i915) 778 { 779 struct i915_power_domains *power_domains = &i915->display.power.domains; 780 struct intel_power_domain_mask async_put_mask; 781 intel_wakeref_t work_wakeref; 782 783 mutex_lock(&power_domains->lock); 784 785 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 786 if (!work_wakeref) 787 goto out_verify; 788 789 async_put_domains_mask(power_domains, &async_put_mask); 790 release_async_put_domains(power_domains, &async_put_mask); 791 cancel_async_put_work(power_domains, false); 792 793 out_verify: 794 verify_async_put_domains_state(power_domains); 795 796 mutex_unlock(&power_domains->lock); 797 798 if (work_wakeref) 799 intel_runtime_pm_put_raw(&i915->runtime_pm, work_wakeref); 800 } 801 802 /** 803 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work 804 * @i915: i915 device instance 805 * 806 * Like intel_display_power_flush_work(), but also ensure that the work 807 * handler function is not running any more when this function returns. 808 */ 809 static void 810 intel_display_power_flush_work_sync(struct drm_i915_private *i915) 811 { 812 struct i915_power_domains *power_domains = &i915->display.power.domains; 813 814 intel_display_power_flush_work(i915); 815 cancel_async_put_work(power_domains, true); 816 817 verify_async_put_domains_state(power_domains); 818 819 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref); 820 } 821 822 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 823 /** 824 * intel_display_power_put - release a power domain reference 825 * @dev_priv: i915 device instance 826 * @domain: power domain to reference 827 * @wakeref: wakeref acquired for the reference that is being released 828 * 829 * This function drops the power domain reference obtained by 830 * intel_display_power_get() and might power down the corresponding hardware 831 * block right away if this is the last reference. 832 */ 833 void intel_display_power_put(struct drm_i915_private *dev_priv, 834 enum intel_display_power_domain domain, 835 intel_wakeref_t wakeref) 836 { 837 __intel_display_power_put(dev_priv, domain); 838 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 839 } 840 #else 841 /** 842 * intel_display_power_put_unchecked - release an unchecked power domain reference 843 * @dev_priv: i915 device instance 844 * @domain: power domain to reference 845 * 846 * This function drops the power domain reference obtained by 847 * intel_display_power_get() and might power down the corresponding hardware 848 * block right away if this is the last reference. 849 * 850 * This function is only for the power domain code's internal use to suppress wakeref 851 * tracking when the correspondig debug kconfig option is disabled, should not 852 * be used otherwise. 853 */ 854 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 855 enum intel_display_power_domain domain) 856 { 857 __intel_display_power_put(dev_priv, domain); 858 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); 859 } 860 #endif 861 862 void 863 intel_display_power_get_in_set(struct drm_i915_private *i915, 864 struct intel_display_power_domain_set *power_domain_set, 865 enum intel_display_power_domain domain) 866 { 867 intel_wakeref_t __maybe_unused wf; 868 869 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits)); 870 871 wf = intel_display_power_get(i915, domain); 872 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 873 power_domain_set->wakerefs[domain] = wf; 874 #endif 875 set_bit(domain, power_domain_set->mask.bits); 876 } 877 878 bool 879 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, 880 struct intel_display_power_domain_set *power_domain_set, 881 enum intel_display_power_domain domain) 882 { 883 intel_wakeref_t wf; 884 885 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits)); 886 887 wf = intel_display_power_get_if_enabled(i915, domain); 888 if (!wf) 889 return false; 890 891 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 892 power_domain_set->wakerefs[domain] = wf; 893 #endif 894 set_bit(domain, power_domain_set->mask.bits); 895 896 return true; 897 } 898 899 void 900 intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 901 struct intel_display_power_domain_set *power_domain_set, 902 struct intel_power_domain_mask *mask) 903 { 904 enum intel_display_power_domain domain; 905 906 drm_WARN_ON(&i915->drm, 907 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM)); 908 909 for_each_power_domain(domain, mask) { 910 intel_wakeref_t __maybe_unused wf = -1; 911 912 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 913 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]); 914 #endif 915 intel_display_power_put(i915, domain, wf); 916 clear_bit(domain, power_domain_set->mask.bits); 917 } 918 } 919 920 static int 921 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 922 int disable_power_well) 923 { 924 if (disable_power_well >= 0) 925 return !!disable_power_well; 926 927 return 1; 928 } 929 930 static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, 931 int enable_dc) 932 { 933 u32 mask; 934 int requested_dc; 935 int max_dc; 936 937 if (!HAS_DISPLAY(dev_priv)) 938 return 0; 939 940 if (DISPLAY_VER(dev_priv) >= 20) 941 max_dc = 2; 942 else if (IS_DG2(dev_priv)) 943 max_dc = 1; 944 else if (IS_DG1(dev_priv)) 945 max_dc = 3; 946 else if (DISPLAY_VER(dev_priv) >= 12) 947 max_dc = 4; 948 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 949 max_dc = 1; 950 else if (DISPLAY_VER(dev_priv) >= 9) 951 max_dc = 2; 952 else 953 max_dc = 0; 954 955 /* 956 * DC9 has a separate HW flow from the rest of the DC states, 957 * not depending on the DMC firmware. It's needed by system 958 * suspend/resume, so allow it unconditionally. 959 */ 960 mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || 961 DISPLAY_VER(dev_priv) >= 11 ? 962 DC_STATE_EN_DC9 : 0; 963 964 if (!dev_priv->display.params.disable_power_well) 965 max_dc = 0; 966 967 if (enable_dc >= 0 && enable_dc <= max_dc) { 968 requested_dc = enable_dc; 969 } else if (enable_dc == -1) { 970 requested_dc = max_dc; 971 } else if (enable_dc > max_dc && enable_dc <= 4) { 972 drm_dbg_kms(&dev_priv->drm, 973 "Adjusting requested max DC state (%d->%d)\n", 974 enable_dc, max_dc); 975 requested_dc = max_dc; 976 } else { 977 drm_err(&dev_priv->drm, 978 "Unexpected value for enable_dc (%d)\n", enable_dc); 979 requested_dc = max_dc; 980 } 981 982 switch (requested_dc) { 983 case 4: 984 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6; 985 break; 986 case 3: 987 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5; 988 break; 989 case 2: 990 mask |= DC_STATE_EN_UPTO_DC6; 991 break; 992 case 1: 993 mask |= DC_STATE_EN_UPTO_DC5; 994 break; 995 } 996 997 drm_dbg_kms(&dev_priv->drm, "Allowed DC state mask %02x\n", mask); 998 999 return mask; 1000 } 1001 1002 /** 1003 * intel_power_domains_init - initializes the power domain structures 1004 * @dev_priv: i915 device instance 1005 * 1006 * Initializes the power domain structures for @dev_priv depending upon the 1007 * supported platform. 1008 */ 1009 int intel_power_domains_init(struct drm_i915_private *dev_priv) 1010 { 1011 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1012 1013 dev_priv->display.params.disable_power_well = 1014 sanitize_disable_power_well_option(dev_priv, 1015 dev_priv->display.params.disable_power_well); 1016 power_domains->allowed_dc_mask = 1017 get_allowed_dc_mask(dev_priv, dev_priv->display.params.enable_dc); 1018 1019 power_domains->target_dc_state = 1020 sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 1021 1022 mutex_init(&power_domains->lock); 1023 1024 INIT_DELAYED_WORK(&power_domains->async_put_work, 1025 intel_display_power_put_async_work); 1026 1027 return intel_display_power_map_init(power_domains); 1028 } 1029 1030 /** 1031 * intel_power_domains_cleanup - clean up power domains resources 1032 * @dev_priv: i915 device instance 1033 * 1034 * Release any resources acquired by intel_power_domains_init() 1035 */ 1036 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv) 1037 { 1038 intel_display_power_map_cleanup(&dev_priv->display.power.domains); 1039 } 1040 1041 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 1042 { 1043 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1044 struct i915_power_well *power_well; 1045 1046 mutex_lock(&power_domains->lock); 1047 for_each_power_well(dev_priv, power_well) 1048 intel_power_well_sync_hw(dev_priv, power_well); 1049 mutex_unlock(&power_domains->lock); 1050 } 1051 1052 static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv, 1053 enum dbuf_slice slice, bool enable) 1054 { 1055 i915_reg_t reg = DBUF_CTL_S(slice); 1056 bool state; 1057 1058 intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST, 1059 enable ? DBUF_POWER_REQUEST : 0); 1060 intel_de_posting_read(dev_priv, reg); 1061 udelay(10); 1062 1063 state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE; 1064 drm_WARN(&dev_priv->drm, enable != state, 1065 "DBuf slice %d power %s timeout!\n", 1066 slice, str_enable_disable(enable)); 1067 } 1068 1069 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 1070 u8 req_slices) 1071 { 1072 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1073 u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask; 1074 enum dbuf_slice slice; 1075 1076 drm_WARN(&dev_priv->drm, req_slices & ~slice_mask, 1077 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n", 1078 req_slices, slice_mask); 1079 1080 drm_dbg_kms(&dev_priv->drm, "Updating dbuf slices to 0x%x\n", 1081 req_slices); 1082 1083 /* 1084 * Might be running this in parallel to gen9_dc_off_power_well_enable 1085 * being called from intel_dp_detect for instance, 1086 * which causes assertion triggered by race condition, 1087 * as gen9_assert_dbuf_enabled might preempt this when registers 1088 * were already updated, while dev_priv was not. 1089 */ 1090 mutex_lock(&power_domains->lock); 1091 1092 for_each_dbuf_slice(dev_priv, slice) 1093 gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice)); 1094 1095 dev_priv->display.dbuf.enabled_slices = req_slices; 1096 1097 mutex_unlock(&power_domains->lock); 1098 } 1099 1100 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) 1101 { 1102 u8 slices_mask; 1103 1104 dev_priv->display.dbuf.enabled_slices = 1105 intel_enabled_dbuf_slices_mask(dev_priv); 1106 1107 slices_mask = BIT(DBUF_S1) | dev_priv->display.dbuf.enabled_slices; 1108 1109 if (DISPLAY_VER(dev_priv) >= 14) 1110 intel_pmdemand_program_dbuf(dev_priv, slices_mask); 1111 1112 /* 1113 * Just power up at least 1 slice, we will 1114 * figure out later which slices we have and what we need. 1115 */ 1116 gen9_dbuf_slices_update(dev_priv, slices_mask); 1117 } 1118 1119 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) 1120 { 1121 gen9_dbuf_slices_update(dev_priv, 0); 1122 1123 if (DISPLAY_VER(dev_priv) >= 14) 1124 intel_pmdemand_program_dbuf(dev_priv, 0); 1125 } 1126 1127 static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) 1128 { 1129 enum dbuf_slice slice; 1130 1131 if (IS_ALDERLAKE_P(dev_priv)) 1132 return; 1133 1134 for_each_dbuf_slice(dev_priv, slice) 1135 intel_de_rmw(dev_priv, DBUF_CTL_S(slice), 1136 DBUF_TRACKER_STATE_SERVICE_MASK, 1137 DBUF_TRACKER_STATE_SERVICE(8)); 1138 } 1139 1140 static void icl_mbus_init(struct drm_i915_private *dev_priv) 1141 { 1142 unsigned long abox_regs = DISPLAY_INFO(dev_priv)->abox_mask; 1143 u32 mask, val, i; 1144 1145 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 1146 return; 1147 1148 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | 1149 MBUS_ABOX_BT_CREDIT_POOL2_MASK | 1150 MBUS_ABOX_B_CREDIT_MASK | 1151 MBUS_ABOX_BW_CREDIT_MASK; 1152 val = MBUS_ABOX_BT_CREDIT_POOL1(16) | 1153 MBUS_ABOX_BT_CREDIT_POOL2(16) | 1154 MBUS_ABOX_B_CREDIT(1) | 1155 MBUS_ABOX_BW_CREDIT(1); 1156 1157 /* 1158 * gen12 platforms that use abox1 and abox2 for pixel data reads still 1159 * expect us to program the abox_ctl0 register as well, even though 1160 * we don't have to program other instance-0 registers like BW_BUDDY. 1161 */ 1162 if (DISPLAY_VER(dev_priv) == 12) 1163 abox_regs |= BIT(0); 1164 1165 for_each_set_bit(i, &abox_regs, sizeof(abox_regs)) 1166 intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val); 1167 } 1168 1169 static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) 1170 { 1171 u32 val = intel_de_read(dev_priv, LCPLL_CTL); 1172 1173 /* 1174 * The LCPLL register should be turned on by the BIOS. For now 1175 * let's just check its state and print errors in case 1176 * something is wrong. Don't even try to turn it on. 1177 */ 1178 1179 if (val & LCPLL_CD_SOURCE_FCLK) 1180 drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n"); 1181 1182 if (val & LCPLL_PLL_DISABLE) 1183 drm_err(&dev_priv->drm, "LCPLL is disabled\n"); 1184 1185 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC) 1186 drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n"); 1187 } 1188 1189 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) 1190 { 1191 struct intel_crtc *crtc; 1192 1193 for_each_intel_crtc(&dev_priv->drm, crtc) 1194 I915_STATE_WARN(dev_priv, crtc->active, 1195 "CRTC for pipe %c enabled\n", 1196 pipe_name(crtc->pipe)); 1197 1198 I915_STATE_WARN(dev_priv, intel_de_read(dev_priv, HSW_PWR_WELL_CTL2), 1199 "Display power well on\n"); 1200 I915_STATE_WARN(dev_priv, 1201 intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE, 1202 "SPLL enabled\n"); 1203 I915_STATE_WARN(dev_priv, 1204 intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, 1205 "WRPLL1 enabled\n"); 1206 I915_STATE_WARN(dev_priv, 1207 intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, 1208 "WRPLL2 enabled\n"); 1209 I915_STATE_WARN(dev_priv, 1210 intel_de_read(dev_priv, PP_STATUS(dev_priv, 0)) & PP_ON, 1211 "Panel power on\n"); 1212 I915_STATE_WARN(dev_priv, 1213 intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 1214 "CPU PWM1 enabled\n"); 1215 if (IS_HASWELL(dev_priv)) 1216 I915_STATE_WARN(dev_priv, 1217 intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 1218 "CPU PWM2 enabled\n"); 1219 I915_STATE_WARN(dev_priv, 1220 intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, 1221 "PCH PWM1 enabled\n"); 1222 I915_STATE_WARN(dev_priv, 1223 (intel_de_read(dev_priv, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 1224 "Utility pin enabled in PWM mode\n"); 1225 I915_STATE_WARN(dev_priv, 1226 intel_de_read(dev_priv, PCH_GTC_CTL) & PCH_GTC_ENABLE, 1227 "PCH GTC enabled\n"); 1228 1229 /* 1230 * In theory we can still leave IRQs enabled, as long as only the HPD 1231 * interrupts remain enabled. We used to check for that, but since it's 1232 * gen-specific and since we only disable LCPLL after we fully disable 1233 * the interrupts, the check below should be enough. 1234 */ 1235 I915_STATE_WARN(dev_priv, intel_irqs_enabled(dev_priv), 1236 "IRQs enabled\n"); 1237 } 1238 1239 static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv) 1240 { 1241 if (IS_HASWELL(dev_priv)) 1242 return intel_de_read(dev_priv, D_COMP_HSW); 1243 else 1244 return intel_de_read(dev_priv, D_COMP_BDW); 1245 } 1246 1247 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val) 1248 { 1249 if (IS_HASWELL(dev_priv)) { 1250 if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val)) 1251 drm_dbg_kms(&dev_priv->drm, 1252 "Failed to write to D_COMP\n"); 1253 } else { 1254 intel_de_write(dev_priv, D_COMP_BDW, val); 1255 intel_de_posting_read(dev_priv, D_COMP_BDW); 1256 } 1257 } 1258 1259 /* 1260 * This function implements pieces of two sequences from BSpec: 1261 * - Sequence for display software to disable LCPLL 1262 * - Sequence for display software to allow package C8+ 1263 * The steps implemented here are just the steps that actually touch the LCPLL 1264 * register. Callers should take care of disabling all the display engine 1265 * functions, doing the mode unset, fixing interrupts, etc. 1266 */ 1267 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, 1268 bool switch_to_fclk, bool allow_power_down) 1269 { 1270 u32 val; 1271 1272 assert_can_disable_lcpll(dev_priv); 1273 1274 val = intel_de_read(dev_priv, LCPLL_CTL); 1275 1276 if (switch_to_fclk) { 1277 val |= LCPLL_CD_SOURCE_FCLK; 1278 intel_de_write(dev_priv, LCPLL_CTL, val); 1279 1280 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 1281 LCPLL_CD_SOURCE_FCLK_DONE, 1)) 1282 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 1283 1284 val = intel_de_read(dev_priv, LCPLL_CTL); 1285 } 1286 1287 val |= LCPLL_PLL_DISABLE; 1288 intel_de_write(dev_priv, LCPLL_CTL, val); 1289 intel_de_posting_read(dev_priv, LCPLL_CTL); 1290 1291 if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) 1292 drm_err(&dev_priv->drm, "LCPLL still locked\n"); 1293 1294 val = hsw_read_dcomp(dev_priv); 1295 val |= D_COMP_COMP_DISABLE; 1296 hsw_write_dcomp(dev_priv, val); 1297 ndelay(100); 1298 1299 if (wait_for((hsw_read_dcomp(dev_priv) & 1300 D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) 1301 drm_err(&dev_priv->drm, "D_COMP RCOMP still in progress\n"); 1302 1303 if (allow_power_down) { 1304 intel_de_rmw(dev_priv, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); 1305 intel_de_posting_read(dev_priv, LCPLL_CTL); 1306 } 1307 } 1308 1309 /* 1310 * Fully restores LCPLL, disallowing power down and switching back to LCPLL 1311 * source. 1312 */ 1313 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) 1314 { 1315 u32 val; 1316 1317 val = intel_de_read(dev_priv, LCPLL_CTL); 1318 1319 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | 1320 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) 1321 return; 1322 1323 /* 1324 * Make sure we're not on PC8 state before disabling PC8, otherwise 1325 * we'll hang the machine. To prevent PC8 state, just enable force_wake. 1326 */ 1327 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); 1328 1329 if (val & LCPLL_POWER_DOWN_ALLOW) { 1330 val &= ~LCPLL_POWER_DOWN_ALLOW; 1331 intel_de_write(dev_priv, LCPLL_CTL, val); 1332 intel_de_posting_read(dev_priv, LCPLL_CTL); 1333 } 1334 1335 val = hsw_read_dcomp(dev_priv); 1336 val |= D_COMP_COMP_FORCE; 1337 val &= ~D_COMP_COMP_DISABLE; 1338 hsw_write_dcomp(dev_priv, val); 1339 1340 val = intel_de_read(dev_priv, LCPLL_CTL); 1341 val &= ~LCPLL_PLL_DISABLE; 1342 intel_de_write(dev_priv, LCPLL_CTL, val); 1343 1344 if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) 1345 drm_err(&dev_priv->drm, "LCPLL not locked yet\n"); 1346 1347 if (val & LCPLL_CD_SOURCE_FCLK) { 1348 intel_de_rmw(dev_priv, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); 1349 1350 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 1351 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 1352 drm_err(&dev_priv->drm, 1353 "Switching back to LCPLL failed\n"); 1354 } 1355 1356 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); 1357 1358 intel_update_cdclk(dev_priv); 1359 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 1360 } 1361 1362 /* 1363 * Package states C8 and deeper are really deep PC states that can only be 1364 * reached when all the devices on the system allow it, so even if the graphics 1365 * device allows PC8+, it doesn't mean the system will actually get to these 1366 * states. Our driver only allows PC8+ when going into runtime PM. 1367 * 1368 * The requirements for PC8+ are that all the outputs are disabled, the power 1369 * well is disabled and most interrupts are disabled, and these are also 1370 * requirements for runtime PM. When these conditions are met, we manually do 1371 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk 1372 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard 1373 * hang the machine. 1374 * 1375 * When we really reach PC8 or deeper states (not just when we allow it) we lose 1376 * the state of some registers, so when we come back from PC8+ we need to 1377 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't 1378 * need to take care of the registers kept by RC6. Notice that this happens even 1379 * if we don't put the device in PCI D3 state (which is what currently happens 1380 * because of the runtime PM support). 1381 * 1382 * For more, read "Display Sequences for Package C8" on the hardware 1383 * documentation. 1384 */ 1385 static void hsw_enable_pc8(struct drm_i915_private *dev_priv) 1386 { 1387 drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n"); 1388 1389 if (HAS_PCH_LPT_LP(dev_priv)) 1390 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1391 PCH_LP_PARTITION_LEVEL_DISABLE, 0); 1392 1393 lpt_disable_clkout_dp(dev_priv); 1394 hsw_disable_lcpll(dev_priv, true, true); 1395 } 1396 1397 static void hsw_disable_pc8(struct drm_i915_private *dev_priv) 1398 { 1399 drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n"); 1400 1401 hsw_restore_lcpll(dev_priv); 1402 intel_init_pch_refclk(dev_priv); 1403 1404 /* Many display registers don't survive PC8+ */ 1405 intel_clock_gating_init(dev_priv); 1406 } 1407 1408 static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, 1409 bool enable) 1410 { 1411 i915_reg_t reg; 1412 u32 reset_bits; 1413 1414 if (IS_IVYBRIDGE(dev_priv)) { 1415 reg = GEN7_MSG_CTL; 1416 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK; 1417 } else { 1418 reg = HSW_NDE_RSTWRN_OPT; 1419 reset_bits = RESET_PCH_HANDSHAKE_ENABLE; 1420 } 1421 1422 if (DISPLAY_VER(dev_priv) >= 14) 1423 reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; 1424 1425 intel_de_rmw(dev_priv, reg, reset_bits, enable ? reset_bits : 0); 1426 } 1427 1428 static void skl_display_core_init(struct drm_i915_private *dev_priv, 1429 bool resume) 1430 { 1431 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1432 struct i915_power_well *well; 1433 1434 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 1435 1436 /* enable PCH reset handshake */ 1437 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); 1438 1439 if (!HAS_DISPLAY(dev_priv)) 1440 return; 1441 1442 /* enable PG1 and Misc I/O */ 1443 mutex_lock(&power_domains->lock); 1444 1445 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1446 intel_power_well_enable(dev_priv, well); 1447 1448 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 1449 intel_power_well_enable(dev_priv, well); 1450 1451 mutex_unlock(&power_domains->lock); 1452 1453 intel_cdclk_init_hw(dev_priv); 1454 1455 gen9_dbuf_enable(dev_priv); 1456 1457 if (resume) 1458 intel_dmc_load_program(dev_priv); 1459 } 1460 1461 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 1462 { 1463 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1464 struct i915_power_well *well; 1465 1466 if (!HAS_DISPLAY(dev_priv)) 1467 return; 1468 1469 gen9_disable_dc_states(dev_priv); 1470 /* TODO: disable DMC program */ 1471 1472 gen9_dbuf_disable(dev_priv); 1473 1474 intel_cdclk_uninit_hw(dev_priv); 1475 1476 /* The spec doesn't call for removing the reset handshake flag */ 1477 /* disable PG1 and Misc I/O */ 1478 1479 mutex_lock(&power_domains->lock); 1480 1481 /* 1482 * BSpec says to keep the MISC IO power well enabled here, only 1483 * remove our request for power well 1. 1484 * Note that even though the driver's request is removed power well 1 1485 * may stay enabled after this due to DMC's own request on it. 1486 */ 1487 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1488 intel_power_well_disable(dev_priv, well); 1489 1490 mutex_unlock(&power_domains->lock); 1491 1492 usleep_range(10, 30); /* 10 us delay per Bspec */ 1493 } 1494 1495 static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume) 1496 { 1497 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1498 struct i915_power_well *well; 1499 1500 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 1501 1502 /* 1503 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 1504 * or else the reset will hang because there is no PCH to respond. 1505 * Move the handshake programming to initialization sequence. 1506 * Previously was left up to BIOS. 1507 */ 1508 intel_pch_reset_handshake(dev_priv, false); 1509 1510 if (!HAS_DISPLAY(dev_priv)) 1511 return; 1512 1513 /* Enable PG1 */ 1514 mutex_lock(&power_domains->lock); 1515 1516 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1517 intel_power_well_enable(dev_priv, well); 1518 1519 mutex_unlock(&power_domains->lock); 1520 1521 intel_cdclk_init_hw(dev_priv); 1522 1523 gen9_dbuf_enable(dev_priv); 1524 1525 if (resume) 1526 intel_dmc_load_program(dev_priv); 1527 } 1528 1529 static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 1530 { 1531 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1532 struct i915_power_well *well; 1533 1534 if (!HAS_DISPLAY(dev_priv)) 1535 return; 1536 1537 gen9_disable_dc_states(dev_priv); 1538 /* TODO: disable DMC program */ 1539 1540 gen9_dbuf_disable(dev_priv); 1541 1542 intel_cdclk_uninit_hw(dev_priv); 1543 1544 /* The spec doesn't call for removing the reset handshake flag */ 1545 1546 /* 1547 * Disable PW1 (PG1). 1548 * Note that even though the driver's request is removed power well 1 1549 * may stay enabled after this due to DMC's own request on it. 1550 */ 1551 mutex_lock(&power_domains->lock); 1552 1553 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1554 intel_power_well_disable(dev_priv, well); 1555 1556 mutex_unlock(&power_domains->lock); 1557 1558 usleep_range(10, 30); /* 10 us delay per Bspec */ 1559 } 1560 1561 struct buddy_page_mask { 1562 u32 page_mask; 1563 u8 type; 1564 u8 num_channels; 1565 }; 1566 1567 static const struct buddy_page_mask tgl_buddy_page_masks[] = { 1568 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF }, 1569 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF }, 1570 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C }, 1571 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C }, 1572 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F }, 1573 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E }, 1574 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 }, 1575 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 }, 1576 {} 1577 }; 1578 1579 static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = { 1580 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 }, 1581 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 }, 1582 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 }, 1583 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 }, 1584 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 }, 1585 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 }, 1586 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 }, 1587 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 }, 1588 {} 1589 }; 1590 1591 static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) 1592 { 1593 enum intel_dram_type type = dev_priv->dram_info.type; 1594 u8 num_channels = dev_priv->dram_info.num_channels; 1595 const struct buddy_page_mask *table; 1596 unsigned long abox_mask = DISPLAY_INFO(dev_priv)->abox_mask; 1597 int config, i; 1598 1599 /* BW_BUDDY registers are not used on dgpu's beyond DG1 */ 1600 if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv)) 1601 return; 1602 1603 if (IS_ALDERLAKE_S(dev_priv) || 1604 (IS_ROCKETLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))) 1605 /* Wa_1409767108 */ 1606 table = wa_1409767108_buddy_page_masks; 1607 else 1608 table = tgl_buddy_page_masks; 1609 1610 for (config = 0; table[config].page_mask != 0; config++) 1611 if (table[config].num_channels == num_channels && 1612 table[config].type == type) 1613 break; 1614 1615 if (table[config].page_mask == 0) { 1616 drm_dbg(&dev_priv->drm, 1617 "Unknown memory configuration; disabling address buddy logic.\n"); 1618 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) 1619 intel_de_write(dev_priv, BW_BUDDY_CTL(i), 1620 BW_BUDDY_DISABLE); 1621 } else { 1622 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) { 1623 intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), 1624 table[config].page_mask); 1625 1626 /* Wa_22010178259:tgl,dg1,rkl,adl-s */ 1627 if (DISPLAY_VER(dev_priv) == 12) 1628 intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), 1629 BW_BUDDY_TLB_REQ_TIMER_MASK, 1630 BW_BUDDY_TLB_REQ_TIMER(0x8)); 1631 } 1632 } 1633 } 1634 1635 static void icl_display_core_init(struct drm_i915_private *dev_priv, 1636 bool resume) 1637 { 1638 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1639 struct i915_power_well *well; 1640 1641 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 1642 1643 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ 1644 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && 1645 INTEL_PCH_TYPE(dev_priv) < PCH_DG1) 1646 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, 1647 PCH_DPMGUNIT_CLOCK_GATE_DISABLE); 1648 1649 /* 1. Enable PCH reset handshake. */ 1650 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); 1651 1652 if (!HAS_DISPLAY(dev_priv)) 1653 return; 1654 1655 /* 2. Initialize all combo phys */ 1656 intel_combo_phy_init(dev_priv); 1657 1658 /* 1659 * 3. Enable Power Well 1 (PG1). 1660 * The AUX IO power wells will be enabled on demand. 1661 */ 1662 mutex_lock(&power_domains->lock); 1663 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1664 intel_power_well_enable(dev_priv, well); 1665 mutex_unlock(&power_domains->lock); 1666 1667 if (DISPLAY_VER(dev_priv) == 14) 1668 intel_de_rmw(dev_priv, DC_STATE_EN, 1669 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0); 1670 1671 /* 4. Enable CDCLK. */ 1672 intel_cdclk_init_hw(dev_priv); 1673 1674 if (DISPLAY_VER(dev_priv) >= 12) 1675 gen12_dbuf_slices_config(dev_priv); 1676 1677 /* 5. Enable DBUF. */ 1678 gen9_dbuf_enable(dev_priv); 1679 1680 /* 6. Setup MBUS. */ 1681 icl_mbus_init(dev_priv); 1682 1683 /* 7. Program arbiter BW_BUDDY registers */ 1684 if (DISPLAY_VER(dev_priv) >= 12) 1685 tgl_bw_buddy_init(dev_priv); 1686 1687 /* 8. Ensure PHYs have completed calibration and adaptation */ 1688 if (IS_DG2(dev_priv)) 1689 intel_snps_phy_wait_for_calibration(dev_priv); 1690 1691 /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ 1692 if (DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 1)) 1693 intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); 1694 1695 if (resume) 1696 intel_dmc_load_program(dev_priv); 1697 1698 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */ 1699 if (IS_DISPLAY_IP_RANGE(dev_priv, IP_VER(12, 0), IP_VER(13, 0))) 1700 intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0, 1701 DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | 1702 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR); 1703 1704 /* Wa_14011503030:xelpd */ 1705 if (DISPLAY_VER(dev_priv) == 13) 1706 intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); 1707 1708 /* Wa_15013987218 */ 1709 if (DISPLAY_VER(dev_priv) == 20) { 1710 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1711 0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE); 1712 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1713 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0); 1714 } 1715 } 1716 1717 static void icl_display_core_uninit(struct drm_i915_private *dev_priv) 1718 { 1719 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1720 struct i915_power_well *well; 1721 1722 if (!HAS_DISPLAY(dev_priv)) 1723 return; 1724 1725 gen9_disable_dc_states(dev_priv); 1726 intel_dmc_disable_program(dev_priv); 1727 1728 /* 1. Disable all display engine functions -> aready done */ 1729 1730 /* 2. Disable DBUF */ 1731 gen9_dbuf_disable(dev_priv); 1732 1733 /* 3. Disable CD clock */ 1734 intel_cdclk_uninit_hw(dev_priv); 1735 1736 if (DISPLAY_VER(dev_priv) == 14) 1737 intel_de_rmw(dev_priv, DC_STATE_EN, 0, 1738 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH); 1739 1740 /* 1741 * 4. Disable Power Well 1 (PG1). 1742 * The AUX IO power wells are toggled on demand, so they are already 1743 * disabled at this point. 1744 */ 1745 mutex_lock(&power_domains->lock); 1746 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1747 intel_power_well_disable(dev_priv, well); 1748 mutex_unlock(&power_domains->lock); 1749 1750 /* 5. */ 1751 intel_combo_phy_uninit(dev_priv); 1752 } 1753 1754 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 1755 { 1756 struct i915_power_well *cmn_bc = 1757 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1758 struct i915_power_well *cmn_d = 1759 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); 1760 1761 /* 1762 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 1763 * workaround never ever read DISPLAY_PHY_CONTROL, and 1764 * instead maintain a shadow copy ourselves. Use the actual 1765 * power well state and lane status to reconstruct the 1766 * expected initial value. 1767 */ 1768 dev_priv->display.power.chv_phy_control = 1769 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 1770 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 1771 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 1772 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 1773 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 1774 1775 /* 1776 * If all lanes are disabled we leave the override disabled 1777 * with all power down bits cleared to match the state we 1778 * would use after disabling the port. Otherwise enable the 1779 * override and set the lane powerdown bits accding to the 1780 * current lane status. 1781 */ 1782 if (intel_power_well_is_enabled(dev_priv, cmn_bc)) { 1783 u32 status = intel_de_read(dev_priv, DPLL(dev_priv, PIPE_A)); 1784 unsigned int mask; 1785 1786 mask = status & DPLL_PORTB_READY_MASK; 1787 if (mask == 0xf) 1788 mask = 0x0; 1789 else 1790 dev_priv->display.power.chv_phy_control |= 1791 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 1792 1793 dev_priv->display.power.chv_phy_control |= 1794 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 1795 1796 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 1797 if (mask == 0xf) 1798 mask = 0x0; 1799 else 1800 dev_priv->display.power.chv_phy_control |= 1801 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 1802 1803 dev_priv->display.power.chv_phy_control |= 1804 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 1805 1806 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 1807 1808 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false; 1809 } else { 1810 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true; 1811 } 1812 1813 if (intel_power_well_is_enabled(dev_priv, cmn_d)) { 1814 u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS); 1815 unsigned int mask; 1816 1817 mask = status & DPLL_PORTD_READY_MASK; 1818 1819 if (mask == 0xf) 1820 mask = 0x0; 1821 else 1822 dev_priv->display.power.chv_phy_control |= 1823 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 1824 1825 dev_priv->display.power.chv_phy_control |= 1826 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 1827 1828 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 1829 1830 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false; 1831 } else { 1832 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true; 1833 } 1834 1835 drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n", 1836 dev_priv->display.power.chv_phy_control); 1837 1838 /* Defer application of initial phy_control to enabling the powerwell */ 1839 } 1840 1841 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 1842 { 1843 struct i915_power_well *cmn = 1844 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1845 struct i915_power_well *disp2d = 1846 lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D); 1847 1848 /* If the display might be already active skip this */ 1849 if (intel_power_well_is_enabled(dev_priv, cmn) && 1850 intel_power_well_is_enabled(dev_priv, disp2d) && 1851 intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST) 1852 return; 1853 1854 drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n"); 1855 1856 /* cmnlane needs DPLL registers */ 1857 intel_power_well_enable(dev_priv, disp2d); 1858 1859 /* 1860 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 1861 * Need to assert and de-assert PHY SB reset by gating the 1862 * common lane power, then un-gating it. 1863 * Simply ungating isn't enough to reset the PHY enough to get 1864 * ports and lanes running. 1865 */ 1866 intel_power_well_disable(dev_priv, cmn); 1867 } 1868 1869 static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0) 1870 { 1871 bool ret; 1872 1873 vlv_punit_get(dev_priv); 1874 ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; 1875 vlv_punit_put(dev_priv); 1876 1877 return ret; 1878 } 1879 1880 static void assert_ved_power_gated(struct drm_i915_private *dev_priv) 1881 { 1882 drm_WARN(&dev_priv->drm, 1883 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0), 1884 "VED not power gated\n"); 1885 } 1886 1887 static void assert_isp_power_gated(struct drm_i915_private *dev_priv) 1888 { 1889 static const struct pci_device_id isp_ids[] = { 1890 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)}, 1891 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)}, 1892 {} 1893 }; 1894 1895 drm_WARN(&dev_priv->drm, !pci_dev_present(isp_ids) && 1896 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0), 1897 "ISP not power gated\n"); 1898 } 1899 1900 static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); 1901 1902 /** 1903 * intel_power_domains_init_hw - initialize hardware power domain state 1904 * @i915: i915 device instance 1905 * @resume: Called from resume code paths or not 1906 * 1907 * This function initializes the hardware power domain state and enables all 1908 * power wells belonging to the INIT power domain. Power wells in other 1909 * domains (and not in the INIT domain) are referenced or disabled by 1910 * intel_modeset_readout_hw_state(). After that the reference count of each 1911 * power well must match its HW enabled state, see 1912 * intel_power_domains_verify_state(). 1913 * 1914 * It will return with power domains disabled (to be enabled later by 1915 * intel_power_domains_enable()) and must be paired with 1916 * intel_power_domains_driver_remove(). 1917 */ 1918 void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) 1919 { 1920 struct i915_power_domains *power_domains = &i915->display.power.domains; 1921 1922 power_domains->initializing = true; 1923 1924 if (DISPLAY_VER(i915) >= 11) { 1925 icl_display_core_init(i915, resume); 1926 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 1927 bxt_display_core_init(i915, resume); 1928 } else if (DISPLAY_VER(i915) == 9) { 1929 skl_display_core_init(i915, resume); 1930 } else if (IS_CHERRYVIEW(i915)) { 1931 mutex_lock(&power_domains->lock); 1932 chv_phy_control_init(i915); 1933 mutex_unlock(&power_domains->lock); 1934 assert_isp_power_gated(i915); 1935 } else if (IS_VALLEYVIEW(i915)) { 1936 mutex_lock(&power_domains->lock); 1937 vlv_cmnlane_wa(i915); 1938 mutex_unlock(&power_domains->lock); 1939 assert_ved_power_gated(i915); 1940 assert_isp_power_gated(i915); 1941 } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) { 1942 hsw_assert_cdclk(i915); 1943 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); 1944 } else if (IS_IVYBRIDGE(i915)) { 1945 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); 1946 } 1947 1948 /* 1949 * Keep all power wells enabled for any dependent HW access during 1950 * initialization and to make sure we keep BIOS enabled display HW 1951 * resources powered until display HW readout is complete. We drop 1952 * this reference in intel_power_domains_enable(). 1953 */ 1954 drm_WARN_ON(&i915->drm, power_domains->init_wakeref); 1955 power_domains->init_wakeref = 1956 intel_display_power_get(i915, POWER_DOMAIN_INIT); 1957 1958 /* Disable power support if the user asked so. */ 1959 if (!i915->display.params.disable_power_well) { 1960 drm_WARN_ON(&i915->drm, power_domains->disable_wakeref); 1961 i915->display.power.domains.disable_wakeref = intel_display_power_get(i915, 1962 POWER_DOMAIN_INIT); 1963 } 1964 intel_power_domains_sync_hw(i915); 1965 1966 power_domains->initializing = false; 1967 } 1968 1969 /** 1970 * intel_power_domains_driver_remove - deinitialize hw power domain state 1971 * @i915: i915 device instance 1972 * 1973 * De-initializes the display power domain HW state. It also ensures that the 1974 * device stays powered up so that the driver can be reloaded. 1975 * 1976 * It must be called with power domains already disabled (after a call to 1977 * intel_power_domains_disable()) and must be paired with 1978 * intel_power_domains_init_hw(). 1979 */ 1980 void intel_power_domains_driver_remove(struct drm_i915_private *i915) 1981 { 1982 intel_wakeref_t wakeref __maybe_unused = 1983 fetch_and_zero(&i915->display.power.domains.init_wakeref); 1984 1985 /* Remove the refcount we took to keep power well support disabled. */ 1986 if (!i915->display.params.disable_power_well) 1987 intel_display_power_put(i915, POWER_DOMAIN_INIT, 1988 fetch_and_zero(&i915->display.power.domains.disable_wakeref)); 1989 1990 intel_display_power_flush_work_sync(i915); 1991 1992 intel_power_domains_verify_state(i915); 1993 1994 /* Keep the power well enabled, but cancel its rpm wakeref. */ 1995 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1996 } 1997 1998 /** 1999 * intel_power_domains_sanitize_state - sanitize power domains state 2000 * @i915: i915 device instance 2001 * 2002 * Sanitize the power domains state during driver loading and system resume. 2003 * The function will disable all display power wells that BIOS has enabled 2004 * without a user for it (any user for a power well has taken a reference 2005 * on it by the time this function is called, after the state of all the 2006 * pipe, encoder, etc. HW resources have been sanitized). 2007 */ 2008 void intel_power_domains_sanitize_state(struct drm_i915_private *i915) 2009 { 2010 struct i915_power_domains *power_domains = &i915->display.power.domains; 2011 struct i915_power_well *power_well; 2012 2013 mutex_lock(&power_domains->lock); 2014 2015 for_each_power_well_reverse(i915, power_well) { 2016 if (power_well->desc->always_on || power_well->count || 2017 !intel_power_well_is_enabled(i915, power_well)) 2018 continue; 2019 2020 drm_dbg_kms(&i915->drm, 2021 "BIOS left unused %s power well enabled, disabling it\n", 2022 intel_power_well_name(power_well)); 2023 intel_power_well_disable(i915, power_well); 2024 } 2025 2026 mutex_unlock(&power_domains->lock); 2027 } 2028 2029 /** 2030 * intel_power_domains_enable - enable toggling of display power wells 2031 * @i915: i915 device instance 2032 * 2033 * Enable the ondemand enabling/disabling of the display power wells. Note that 2034 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled 2035 * only at specific points of the display modeset sequence, thus they are not 2036 * affected by the intel_power_domains_enable()/disable() calls. The purpose 2037 * of these function is to keep the rest of power wells enabled until the end 2038 * of display HW readout (which will acquire the power references reflecting 2039 * the current HW state). 2040 */ 2041 void intel_power_domains_enable(struct drm_i915_private *i915) 2042 { 2043 intel_wakeref_t wakeref __maybe_unused = 2044 fetch_and_zero(&i915->display.power.domains.init_wakeref); 2045 2046 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 2047 intel_power_domains_verify_state(i915); 2048 } 2049 2050 /** 2051 * intel_power_domains_disable - disable toggling of display power wells 2052 * @i915: i915 device instance 2053 * 2054 * Disable the ondemand enabling/disabling of the display power wells. See 2055 * intel_power_domains_enable() for which power wells this call controls. 2056 */ 2057 void intel_power_domains_disable(struct drm_i915_private *i915) 2058 { 2059 struct i915_power_domains *power_domains = &i915->display.power.domains; 2060 2061 drm_WARN_ON(&i915->drm, power_domains->init_wakeref); 2062 power_domains->init_wakeref = 2063 intel_display_power_get(i915, POWER_DOMAIN_INIT); 2064 2065 intel_power_domains_verify_state(i915); 2066 } 2067 2068 /** 2069 * intel_power_domains_suspend - suspend power domain state 2070 * @i915: i915 device instance 2071 * @s2idle: specifies whether we go to idle, or deeper sleep 2072 * 2073 * This function prepares the hardware power domain state before entering 2074 * system suspend. 2075 * 2076 * It must be called with power domains already disabled (after a call to 2077 * intel_power_domains_disable()) and paired with intel_power_domains_resume(). 2078 */ 2079 void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle) 2080 { 2081 struct i915_power_domains *power_domains = &i915->display.power.domains; 2082 intel_wakeref_t wakeref __maybe_unused = 2083 fetch_and_zero(&power_domains->init_wakeref); 2084 2085 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 2086 2087 /* 2088 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 2089 * support don't manually deinit the power domains. This also means the 2090 * DMC firmware will stay active, it will power down any HW 2091 * resources as required and also enable deeper system power states 2092 * that would be blocked if the firmware was inactive. 2093 */ 2094 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle && 2095 intel_dmc_has_payload(i915)) { 2096 intel_display_power_flush_work(i915); 2097 intel_power_domains_verify_state(i915); 2098 return; 2099 } 2100 2101 /* 2102 * Even if power well support was disabled we still want to disable 2103 * power wells if power domains must be deinitialized for suspend. 2104 */ 2105 if (!i915->display.params.disable_power_well) 2106 intel_display_power_put(i915, POWER_DOMAIN_INIT, 2107 fetch_and_zero(&i915->display.power.domains.disable_wakeref)); 2108 2109 intel_display_power_flush_work(i915); 2110 intel_power_domains_verify_state(i915); 2111 2112 if (DISPLAY_VER(i915) >= 11) 2113 icl_display_core_uninit(i915); 2114 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 2115 bxt_display_core_uninit(i915); 2116 else if (DISPLAY_VER(i915) == 9) 2117 skl_display_core_uninit(i915); 2118 2119 power_domains->display_core_suspended = true; 2120 } 2121 2122 /** 2123 * intel_power_domains_resume - resume power domain state 2124 * @i915: i915 device instance 2125 * 2126 * This function resume the hardware power domain state during system resume. 2127 * 2128 * It will return with power domain support disabled (to be enabled later by 2129 * intel_power_domains_enable()) and must be paired with 2130 * intel_power_domains_suspend(). 2131 */ 2132 void intel_power_domains_resume(struct drm_i915_private *i915) 2133 { 2134 struct i915_power_domains *power_domains = &i915->display.power.domains; 2135 2136 if (power_domains->display_core_suspended) { 2137 intel_power_domains_init_hw(i915, true); 2138 power_domains->display_core_suspended = false; 2139 } else { 2140 drm_WARN_ON(&i915->drm, power_domains->init_wakeref); 2141 power_domains->init_wakeref = 2142 intel_display_power_get(i915, POWER_DOMAIN_INIT); 2143 } 2144 2145 intel_power_domains_verify_state(i915); 2146 } 2147 2148 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 2149 2150 static void intel_power_domains_dump_info(struct drm_i915_private *i915) 2151 { 2152 struct i915_power_domains *power_domains = &i915->display.power.domains; 2153 struct i915_power_well *power_well; 2154 2155 for_each_power_well(i915, power_well) { 2156 enum intel_display_power_domain domain; 2157 2158 drm_dbg(&i915->drm, "%-25s %d\n", 2159 intel_power_well_name(power_well), intel_power_well_refcount(power_well)); 2160 2161 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2162 drm_dbg(&i915->drm, " %-23s %d\n", 2163 intel_display_power_domain_str(domain), 2164 power_domains->domain_use_count[domain]); 2165 } 2166 } 2167 2168 /** 2169 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 2170 * @i915: i915 device instance 2171 * 2172 * Verify if the reference count of each power well matches its HW enabled 2173 * state and the total refcount of the domains it belongs to. This must be 2174 * called after modeset HW state sanitization, which is responsible for 2175 * acquiring reference counts for any power wells in use and disabling the 2176 * ones left on by BIOS but not required by any active output. 2177 */ 2178 static void intel_power_domains_verify_state(struct drm_i915_private *i915) 2179 { 2180 struct i915_power_domains *power_domains = &i915->display.power.domains; 2181 struct i915_power_well *power_well; 2182 bool dump_domain_info; 2183 2184 mutex_lock(&power_domains->lock); 2185 2186 verify_async_put_domains_state(power_domains); 2187 2188 dump_domain_info = false; 2189 for_each_power_well(i915, power_well) { 2190 enum intel_display_power_domain domain; 2191 int domains_count; 2192 bool enabled; 2193 2194 enabled = intel_power_well_is_enabled(i915, power_well); 2195 if ((intel_power_well_refcount(power_well) || 2196 intel_power_well_is_always_on(power_well)) != 2197 enabled) 2198 drm_err(&i915->drm, 2199 "power well %s state mismatch (refcount %d/enabled %d)", 2200 intel_power_well_name(power_well), 2201 intel_power_well_refcount(power_well), enabled); 2202 2203 domains_count = 0; 2204 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2205 domains_count += power_domains->domain_use_count[domain]; 2206 2207 if (intel_power_well_refcount(power_well) != domains_count) { 2208 drm_err(&i915->drm, 2209 "power well %s refcount/domain refcount mismatch " 2210 "(refcount %d/domains refcount %d)\n", 2211 intel_power_well_name(power_well), 2212 intel_power_well_refcount(power_well), 2213 domains_count); 2214 dump_domain_info = true; 2215 } 2216 } 2217 2218 if (dump_domain_info) { 2219 static bool dumped; 2220 2221 if (!dumped) { 2222 intel_power_domains_dump_info(i915); 2223 dumped = true; 2224 } 2225 } 2226 2227 mutex_unlock(&power_domains->lock); 2228 } 2229 2230 #else 2231 2232 static void intel_power_domains_verify_state(struct drm_i915_private *i915) 2233 { 2234 } 2235 2236 #endif 2237 2238 void intel_display_power_suspend_late(struct drm_i915_private *i915) 2239 { 2240 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || 2241 IS_BROXTON(i915)) { 2242 bxt_enable_dc9(i915); 2243 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2244 hsw_enable_pc8(i915); 2245 } 2246 2247 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2248 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) 2249 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); 2250 } 2251 2252 void intel_display_power_resume_early(struct drm_i915_private *i915) 2253 { 2254 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || 2255 IS_BROXTON(i915)) { 2256 gen9_sanitize_dc_state(i915); 2257 bxt_disable_dc9(i915); 2258 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2259 hsw_disable_pc8(i915); 2260 } 2261 2262 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2263 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) 2264 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); 2265 } 2266 2267 void intel_display_power_suspend(struct drm_i915_private *i915) 2268 { 2269 if (DISPLAY_VER(i915) >= 11) { 2270 icl_display_core_uninit(i915); 2271 bxt_enable_dc9(i915); 2272 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 2273 bxt_display_core_uninit(i915); 2274 bxt_enable_dc9(i915); 2275 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2276 hsw_enable_pc8(i915); 2277 } 2278 } 2279 2280 void intel_display_power_resume(struct drm_i915_private *i915) 2281 { 2282 struct i915_power_domains *power_domains = &i915->display.power.domains; 2283 2284 if (DISPLAY_VER(i915) >= 11) { 2285 bxt_disable_dc9(i915); 2286 icl_display_core_init(i915, true); 2287 if (intel_dmc_has_payload(i915)) { 2288 if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 2289 skl_enable_dc6(i915); 2290 else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 2291 gen9_enable_dc5(i915); 2292 } 2293 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 2294 bxt_disable_dc9(i915); 2295 bxt_display_core_init(i915, true); 2296 if (intel_dmc_has_payload(i915) && 2297 (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) 2298 gen9_enable_dc5(i915); 2299 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2300 hsw_disable_pc8(i915); 2301 } 2302 } 2303 2304 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m) 2305 { 2306 struct i915_power_domains *power_domains = &i915->display.power.domains; 2307 int i; 2308 2309 mutex_lock(&power_domains->lock); 2310 2311 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); 2312 for (i = 0; i < power_domains->power_well_count; i++) { 2313 struct i915_power_well *power_well; 2314 enum intel_display_power_domain power_domain; 2315 2316 power_well = &power_domains->power_wells[i]; 2317 seq_printf(m, "%-25s %d\n", intel_power_well_name(power_well), 2318 intel_power_well_refcount(power_well)); 2319 2320 for_each_power_domain(power_domain, intel_power_well_domains(power_well)) 2321 seq_printf(m, " %-23s %d\n", 2322 intel_display_power_domain_str(power_domain), 2323 power_domains->domain_use_count[power_domain]); 2324 } 2325 2326 mutex_unlock(&power_domains->lock); 2327 } 2328 2329 struct intel_ddi_port_domains { 2330 enum port port_start; 2331 enum port port_end; 2332 enum aux_ch aux_ch_start; 2333 enum aux_ch aux_ch_end; 2334 2335 enum intel_display_power_domain ddi_lanes; 2336 enum intel_display_power_domain ddi_io; 2337 enum intel_display_power_domain aux_io; 2338 enum intel_display_power_domain aux_legacy_usbc; 2339 enum intel_display_power_domain aux_tbt; 2340 }; 2341 2342 static const struct intel_ddi_port_domains 2343 i9xx_port_domains[] = { 2344 { 2345 .port_start = PORT_A, 2346 .port_end = PORT_F, 2347 .aux_ch_start = AUX_CH_A, 2348 .aux_ch_end = AUX_CH_F, 2349 2350 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2351 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2352 .aux_io = POWER_DOMAIN_AUX_IO_A, 2353 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2354 .aux_tbt = POWER_DOMAIN_INVALID, 2355 }, 2356 }; 2357 2358 static const struct intel_ddi_port_domains 2359 d11_port_domains[] = { 2360 { 2361 .port_start = PORT_A, 2362 .port_end = PORT_B, 2363 .aux_ch_start = AUX_CH_A, 2364 .aux_ch_end = AUX_CH_B, 2365 2366 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2367 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2368 .aux_io = POWER_DOMAIN_AUX_IO_A, 2369 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2370 .aux_tbt = POWER_DOMAIN_INVALID, 2371 }, { 2372 .port_start = PORT_C, 2373 .port_end = PORT_F, 2374 .aux_ch_start = AUX_CH_C, 2375 .aux_ch_end = AUX_CH_F, 2376 2377 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C, 2378 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C, 2379 .aux_io = POWER_DOMAIN_AUX_IO_C, 2380 .aux_legacy_usbc = POWER_DOMAIN_AUX_C, 2381 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2382 }, 2383 }; 2384 2385 static const struct intel_ddi_port_domains 2386 d12_port_domains[] = { 2387 { 2388 .port_start = PORT_A, 2389 .port_end = PORT_C, 2390 .aux_ch_start = AUX_CH_A, 2391 .aux_ch_end = AUX_CH_C, 2392 2393 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2394 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2395 .aux_io = POWER_DOMAIN_AUX_IO_A, 2396 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2397 .aux_tbt = POWER_DOMAIN_INVALID, 2398 }, { 2399 .port_start = PORT_TC1, 2400 .port_end = PORT_TC6, 2401 .aux_ch_start = AUX_CH_USBC1, 2402 .aux_ch_end = AUX_CH_USBC6, 2403 2404 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2405 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2406 .aux_io = POWER_DOMAIN_INVALID, 2407 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2408 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2409 }, 2410 }; 2411 2412 static const struct intel_ddi_port_domains 2413 d13_port_domains[] = { 2414 { 2415 .port_start = PORT_A, 2416 .port_end = PORT_C, 2417 .aux_ch_start = AUX_CH_A, 2418 .aux_ch_end = AUX_CH_C, 2419 2420 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2421 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2422 .aux_io = POWER_DOMAIN_AUX_IO_A, 2423 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2424 .aux_tbt = POWER_DOMAIN_INVALID, 2425 }, { 2426 .port_start = PORT_TC1, 2427 .port_end = PORT_TC4, 2428 .aux_ch_start = AUX_CH_USBC1, 2429 .aux_ch_end = AUX_CH_USBC4, 2430 2431 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2432 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2433 .aux_io = POWER_DOMAIN_INVALID, 2434 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2435 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2436 }, { 2437 .port_start = PORT_D_XELPD, 2438 .port_end = PORT_E_XELPD, 2439 .aux_ch_start = AUX_CH_D_XELPD, 2440 .aux_ch_end = AUX_CH_E_XELPD, 2441 2442 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D, 2443 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D, 2444 .aux_io = POWER_DOMAIN_AUX_IO_D, 2445 .aux_legacy_usbc = POWER_DOMAIN_AUX_D, 2446 .aux_tbt = POWER_DOMAIN_INVALID, 2447 }, 2448 }; 2449 2450 static void 2451 intel_port_domains_for_platform(struct drm_i915_private *i915, 2452 const struct intel_ddi_port_domains **domains, 2453 int *domains_size) 2454 { 2455 if (DISPLAY_VER(i915) >= 13) { 2456 *domains = d13_port_domains; 2457 *domains_size = ARRAY_SIZE(d13_port_domains); 2458 } else if (DISPLAY_VER(i915) >= 12) { 2459 *domains = d12_port_domains; 2460 *domains_size = ARRAY_SIZE(d12_port_domains); 2461 } else if (DISPLAY_VER(i915) >= 11) { 2462 *domains = d11_port_domains; 2463 *domains_size = ARRAY_SIZE(d11_port_domains); 2464 } else { 2465 *domains = i9xx_port_domains; 2466 *domains_size = ARRAY_SIZE(i9xx_port_domains); 2467 } 2468 } 2469 2470 static const struct intel_ddi_port_domains * 2471 intel_port_domains_for_port(struct drm_i915_private *i915, enum port port) 2472 { 2473 const struct intel_ddi_port_domains *domains; 2474 int domains_size; 2475 int i; 2476 2477 intel_port_domains_for_platform(i915, &domains, &domains_size); 2478 for (i = 0; i < domains_size; i++) 2479 if (port >= domains[i].port_start && port <= domains[i].port_end) 2480 return &domains[i]; 2481 2482 return NULL; 2483 } 2484 2485 enum intel_display_power_domain 2486 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port) 2487 { 2488 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port); 2489 2490 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) 2491 return POWER_DOMAIN_PORT_DDI_IO_A; 2492 2493 return domains->ddi_io + (int)(port - domains->port_start); 2494 } 2495 2496 enum intel_display_power_domain 2497 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port) 2498 { 2499 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port); 2500 2501 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) 2502 return POWER_DOMAIN_PORT_DDI_LANES_A; 2503 2504 return domains->ddi_lanes + (int)(port - domains->port_start); 2505 } 2506 2507 static const struct intel_ddi_port_domains * 2508 intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch) 2509 { 2510 const struct intel_ddi_port_domains *domains; 2511 int domains_size; 2512 int i; 2513 2514 intel_port_domains_for_platform(i915, &domains, &domains_size); 2515 for (i = 0; i < domains_size; i++) 2516 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end) 2517 return &domains[i]; 2518 2519 return NULL; 2520 } 2521 2522 enum intel_display_power_domain 2523 intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2524 { 2525 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch); 2526 2527 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) 2528 return POWER_DOMAIN_AUX_IO_A; 2529 2530 return domains->aux_io + (int)(aux_ch - domains->aux_ch_start); 2531 } 2532 2533 enum intel_display_power_domain 2534 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2535 { 2536 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch); 2537 2538 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) 2539 return POWER_DOMAIN_AUX_A; 2540 2541 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start); 2542 } 2543 2544 enum intel_display_power_domain 2545 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2546 { 2547 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch); 2548 2549 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) 2550 return POWER_DOMAIN_AUX_TBT1; 2551 2552 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start); 2553 } 2554