1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/iopoll.h> 7 #include <linux/string_helpers.h> 8 9 #include <drm/drm_print.h> 10 #include <drm/intel/intel_pcode_regs.h> 11 12 #include "intel_backlight_regs.h" 13 #include "intel_cdclk.h" 14 #include "intel_clock_gating.h" 15 #include "intel_combo_phy.h" 16 #include "intel_de.h" 17 #include "intel_display_power.h" 18 #include "intel_display_power_map.h" 19 #include "intel_display_power_well.h" 20 #include "intel_display_regs.h" 21 #include "intel_display_rpm.h" 22 #include "intel_display_types.h" 23 #include "intel_display_utils.h" 24 #include "intel_display_wa.h" 25 #include "intel_dmc.h" 26 #include "intel_dram.h" 27 #include "intel_mchbar_regs.h" 28 #include "intel_parent.h" 29 #include "intel_pch_refclk.h" 30 #include "intel_pmdemand.h" 31 #include "intel_pps_regs.h" 32 #include "intel_snps_phy.h" 33 #include "intel_step.h" 34 #include "skl_watermark.h" 35 #include "skl_watermark_regs.h" 36 #include "vlv_sideband.h" 37 38 #define for_each_power_domain_well(__display, __power_well, __domain) \ 39 for_each_power_well((__display), __power_well) \ 40 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 41 42 #define for_each_power_domain_well_reverse(__display, __power_well, __domain) \ 43 for_each_power_well_reverse((__display), __power_well) \ 44 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 45 46 static const char * 47 intel_display_power_domain_str(enum intel_display_power_domain domain) 48 { 49 switch (domain) { 50 case POWER_DOMAIN_DISPLAY_CORE: 51 return "DISPLAY_CORE"; 52 case POWER_DOMAIN_PIPE_A: 53 return "PIPE_A"; 54 case POWER_DOMAIN_PIPE_B: 55 return "PIPE_B"; 56 case POWER_DOMAIN_PIPE_C: 57 return "PIPE_C"; 58 case POWER_DOMAIN_PIPE_D: 59 return "PIPE_D"; 60 case POWER_DOMAIN_PIPE_PANEL_FITTER_A: 61 return "PIPE_PANEL_FITTER_A"; 62 case POWER_DOMAIN_PIPE_PANEL_FITTER_B: 63 return "PIPE_PANEL_FITTER_B"; 64 case POWER_DOMAIN_PIPE_PANEL_FITTER_C: 65 return "PIPE_PANEL_FITTER_C"; 66 case POWER_DOMAIN_PIPE_PANEL_FITTER_D: 67 return "PIPE_PANEL_FITTER_D"; 68 case POWER_DOMAIN_TRANSCODER_A: 69 return "TRANSCODER_A"; 70 case POWER_DOMAIN_TRANSCODER_B: 71 return "TRANSCODER_B"; 72 case POWER_DOMAIN_TRANSCODER_C: 73 return "TRANSCODER_C"; 74 case POWER_DOMAIN_TRANSCODER_D: 75 return "TRANSCODER_D"; 76 case POWER_DOMAIN_TRANSCODER_EDP: 77 return "TRANSCODER_EDP"; 78 case POWER_DOMAIN_TRANSCODER_DSI_A: 79 return "TRANSCODER_DSI_A"; 80 case POWER_DOMAIN_TRANSCODER_DSI_C: 81 return "TRANSCODER_DSI_C"; 82 case POWER_DOMAIN_TRANSCODER_VDSC_PW2: 83 return "TRANSCODER_VDSC_PW2"; 84 case POWER_DOMAIN_PORT_DDI_LANES_A: 85 return "PORT_DDI_LANES_A"; 86 case POWER_DOMAIN_PORT_DDI_LANES_B: 87 return "PORT_DDI_LANES_B"; 88 case POWER_DOMAIN_PORT_DDI_LANES_C: 89 return "PORT_DDI_LANES_C"; 90 case POWER_DOMAIN_PORT_DDI_LANES_D: 91 return "PORT_DDI_LANES_D"; 92 case POWER_DOMAIN_PORT_DDI_LANES_E: 93 return "PORT_DDI_LANES_E"; 94 case POWER_DOMAIN_PORT_DDI_LANES_F: 95 return "PORT_DDI_LANES_F"; 96 case POWER_DOMAIN_PORT_DDI_LANES_TC1: 97 return "PORT_DDI_LANES_TC1"; 98 case POWER_DOMAIN_PORT_DDI_LANES_TC2: 99 return "PORT_DDI_LANES_TC2"; 100 case POWER_DOMAIN_PORT_DDI_LANES_TC3: 101 return "PORT_DDI_LANES_TC3"; 102 case POWER_DOMAIN_PORT_DDI_LANES_TC4: 103 return "PORT_DDI_LANES_TC4"; 104 case POWER_DOMAIN_PORT_DDI_LANES_TC5: 105 return "PORT_DDI_LANES_TC5"; 106 case POWER_DOMAIN_PORT_DDI_LANES_TC6: 107 return "PORT_DDI_LANES_TC6"; 108 case POWER_DOMAIN_PORT_DDI_IO_A: 109 return "PORT_DDI_IO_A"; 110 case POWER_DOMAIN_PORT_DDI_IO_B: 111 return "PORT_DDI_IO_B"; 112 case POWER_DOMAIN_PORT_DDI_IO_C: 113 return "PORT_DDI_IO_C"; 114 case POWER_DOMAIN_PORT_DDI_IO_D: 115 return "PORT_DDI_IO_D"; 116 case POWER_DOMAIN_PORT_DDI_IO_E: 117 return "PORT_DDI_IO_E"; 118 case POWER_DOMAIN_PORT_DDI_IO_F: 119 return "PORT_DDI_IO_F"; 120 case POWER_DOMAIN_PORT_DDI_IO_TC1: 121 return "PORT_DDI_IO_TC1"; 122 case POWER_DOMAIN_PORT_DDI_IO_TC2: 123 return "PORT_DDI_IO_TC2"; 124 case POWER_DOMAIN_PORT_DDI_IO_TC3: 125 return "PORT_DDI_IO_TC3"; 126 case POWER_DOMAIN_PORT_DDI_IO_TC4: 127 return "PORT_DDI_IO_TC4"; 128 case POWER_DOMAIN_PORT_DDI_IO_TC5: 129 return "PORT_DDI_IO_TC5"; 130 case POWER_DOMAIN_PORT_DDI_IO_TC6: 131 return "PORT_DDI_IO_TC6"; 132 case POWER_DOMAIN_PORT_DSI: 133 return "PORT_DSI"; 134 case POWER_DOMAIN_PORT_CRT: 135 return "PORT_CRT"; 136 case POWER_DOMAIN_PORT_OTHER: 137 return "PORT_OTHER"; 138 case POWER_DOMAIN_VGA: 139 return "VGA"; 140 case POWER_DOMAIN_AUDIO_MMIO: 141 return "AUDIO_MMIO"; 142 case POWER_DOMAIN_AUDIO_PLAYBACK: 143 return "AUDIO_PLAYBACK"; 144 case POWER_DOMAIN_AUX_IO_A: 145 return "AUX_IO_A"; 146 case POWER_DOMAIN_AUX_IO_B: 147 return "AUX_IO_B"; 148 case POWER_DOMAIN_AUX_IO_C: 149 return "AUX_IO_C"; 150 case POWER_DOMAIN_AUX_IO_D: 151 return "AUX_IO_D"; 152 case POWER_DOMAIN_AUX_IO_E: 153 return "AUX_IO_E"; 154 case POWER_DOMAIN_AUX_IO_F: 155 return "AUX_IO_F"; 156 case POWER_DOMAIN_AUX_A: 157 return "AUX_A"; 158 case POWER_DOMAIN_AUX_B: 159 return "AUX_B"; 160 case POWER_DOMAIN_AUX_C: 161 return "AUX_C"; 162 case POWER_DOMAIN_AUX_D: 163 return "AUX_D"; 164 case POWER_DOMAIN_AUX_E: 165 return "AUX_E"; 166 case POWER_DOMAIN_AUX_F: 167 return "AUX_F"; 168 case POWER_DOMAIN_AUX_USBC1: 169 return "AUX_USBC1"; 170 case POWER_DOMAIN_AUX_USBC2: 171 return "AUX_USBC2"; 172 case POWER_DOMAIN_AUX_USBC3: 173 return "AUX_USBC3"; 174 case POWER_DOMAIN_AUX_USBC4: 175 return "AUX_USBC4"; 176 case POWER_DOMAIN_AUX_USBC5: 177 return "AUX_USBC5"; 178 case POWER_DOMAIN_AUX_USBC6: 179 return "AUX_USBC6"; 180 case POWER_DOMAIN_AUX_TBT1: 181 return "AUX_TBT1"; 182 case POWER_DOMAIN_AUX_TBT2: 183 return "AUX_TBT2"; 184 case POWER_DOMAIN_AUX_TBT3: 185 return "AUX_TBT3"; 186 case POWER_DOMAIN_AUX_TBT4: 187 return "AUX_TBT4"; 188 case POWER_DOMAIN_AUX_TBT5: 189 return "AUX_TBT5"; 190 case POWER_DOMAIN_AUX_TBT6: 191 return "AUX_TBT6"; 192 case POWER_DOMAIN_GMBUS: 193 return "GMBUS"; 194 case POWER_DOMAIN_INIT: 195 return "INIT"; 196 case POWER_DOMAIN_GT_IRQ: 197 return "GT_IRQ"; 198 case POWER_DOMAIN_DC_OFF: 199 return "DC_OFF"; 200 case POWER_DOMAIN_TC_COLD_OFF: 201 return "TC_COLD_OFF"; 202 default: 203 MISSING_CASE(domain); 204 return "?"; 205 } 206 } 207 208 static bool __intel_display_power_is_enabled(struct intel_display *display, 209 enum intel_display_power_domain domain) 210 { 211 struct i915_power_well *power_well; 212 bool is_enabled; 213 214 if (intel_display_rpm_suspended(display)) 215 return false; 216 217 is_enabled = true; 218 219 for_each_power_domain_well_reverse(display, power_well, domain) { 220 if (intel_power_well_is_always_on(power_well)) 221 continue; 222 223 if (!intel_power_well_is_enabled_cached(power_well)) { 224 is_enabled = false; 225 break; 226 } 227 } 228 229 return is_enabled; 230 } 231 232 /** 233 * intel_display_power_is_enabled - check for a power domain 234 * @display: display device instance 235 * @domain: power domain to check 236 * 237 * This function can be used to check the hw power domain state. It is mostly 238 * used in hardware state readout functions. Everywhere else code should rely 239 * upon explicit power domain reference counting to ensure that the hardware 240 * block is powered up before accessing it. 241 * 242 * Callers must hold the relevant modesetting locks to ensure that concurrent 243 * threads can't disable the power well while the caller tries to read a few 244 * registers. 245 * 246 * Returns: 247 * True when the power domain is enabled, false otherwise. 248 */ 249 bool intel_display_power_is_enabled(struct intel_display *display, 250 enum intel_display_power_domain domain) 251 { 252 struct i915_power_domains *power_domains = &display->power.domains; 253 bool ret; 254 255 mutex_lock(&power_domains->lock); 256 ret = __intel_display_power_is_enabled(display, domain); 257 mutex_unlock(&power_domains->lock); 258 259 return ret; 260 } 261 262 static u32 263 sanitize_target_dc_state(struct intel_display *display, 264 u32 target_dc_state) 265 { 266 struct i915_power_domains *power_domains = &display->power.domains; 267 static const u32 states[] = { 268 DC_STATE_EN_UPTO_DC6, 269 DC_STATE_EN_UPTO_DC5, 270 DC_STATE_EN_DC3CO, 271 DC_STATE_DISABLE, 272 }; 273 int i; 274 275 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { 276 if (target_dc_state != states[i]) 277 continue; 278 279 if (power_domains->allowed_dc_mask & target_dc_state) 280 break; 281 282 target_dc_state = states[i + 1]; 283 } 284 285 return target_dc_state; 286 } 287 288 /** 289 * intel_display_power_set_target_dc_state - Set target dc state. 290 * @display: display device 291 * @state: state which needs to be set as target_dc_state. 292 * 293 * This function set the "DC off" power well target_dc_state, 294 * based upon this target_dc_stste, "DC off" power well will 295 * enable desired DC state. 296 */ 297 void intel_display_power_set_target_dc_state(struct intel_display *display, 298 u32 state) 299 { 300 struct i915_power_well *power_well; 301 bool dc_off_enabled; 302 struct i915_power_domains *power_domains = &display->power.domains; 303 304 mutex_lock(&power_domains->lock); 305 power_well = lookup_power_well(display, SKL_DISP_DC_OFF); 306 307 if (drm_WARN_ON(display->drm, !power_well)) 308 goto unlock; 309 310 state = sanitize_target_dc_state(display, state); 311 312 if (state == power_domains->target_dc_state) 313 goto unlock; 314 315 dc_off_enabled = intel_power_well_is_enabled(display, power_well); 316 /* 317 * If DC off power well is disabled, need to enable and disable the 318 * DC off power well to effect target DC state. 319 */ 320 if (!dc_off_enabled) 321 intel_power_well_enable(display, power_well); 322 323 power_domains->target_dc_state = state; 324 325 if (!dc_off_enabled) 326 intel_power_well_disable(display, power_well); 327 328 unlock: 329 mutex_unlock(&power_domains->lock); 330 } 331 332 /** 333 * intel_display_power_get_current_dc_state - Set target dc state. 334 * @display: display device 335 * 336 * This function set the "DC off" power well target_dc_state, 337 * based upon this target_dc_stste, "DC off" power well will 338 * enable desired DC state. 339 */ 340 u32 intel_display_power_get_current_dc_state(struct intel_display *display) 341 { 342 struct i915_power_well *power_well; 343 struct i915_power_domains *power_domains = &display->power.domains; 344 u32 current_dc_state = DC_STATE_DISABLE; 345 346 mutex_lock(&power_domains->lock); 347 power_well = lookup_power_well(display, SKL_DISP_DC_OFF); 348 349 if (drm_WARN_ON(display->drm, !power_well)) 350 goto unlock; 351 352 current_dc_state = intel_power_well_is_enabled(display, power_well) ? 353 DC_STATE_DISABLE : power_domains->target_dc_state; 354 355 unlock: 356 mutex_unlock(&power_domains->lock); 357 358 return current_dc_state; 359 } 360 361 static void __async_put_domains_mask(struct i915_power_domains *power_domains, 362 struct intel_power_domain_mask *mask) 363 { 364 bitmap_or(mask->bits, 365 power_domains->async_put_domains[0].bits, 366 power_domains->async_put_domains[1].bits, 367 POWER_DOMAIN_NUM); 368 } 369 370 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 371 372 static bool 373 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 374 { 375 struct intel_display *display = container_of(power_domains, 376 struct intel_display, 377 power.domains); 378 379 return !drm_WARN_ON(display->drm, 380 bitmap_intersects(power_domains->async_put_domains[0].bits, 381 power_domains->async_put_domains[1].bits, 382 POWER_DOMAIN_NUM)); 383 } 384 385 static bool 386 __async_put_domains_state_ok(struct i915_power_domains *power_domains) 387 { 388 struct intel_display *display = container_of(power_domains, 389 struct intel_display, 390 power.domains); 391 struct intel_power_domain_mask async_put_mask; 392 enum intel_display_power_domain domain; 393 bool err = false; 394 395 err |= !assert_async_put_domain_masks_disjoint(power_domains); 396 __async_put_domains_mask(power_domains, &async_put_mask); 397 err |= drm_WARN_ON(display->drm, 398 !!power_domains->async_put_wakeref != 399 !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)); 400 401 for_each_power_domain(domain, &async_put_mask) 402 err |= drm_WARN_ON(display->drm, 403 power_domains->domain_use_count[domain] != 1); 404 405 return !err; 406 } 407 408 static void print_power_domains(struct i915_power_domains *power_domains, 409 const char *prefix, struct intel_power_domain_mask *mask) 410 { 411 struct intel_display *display = container_of(power_domains, 412 struct intel_display, 413 power.domains); 414 enum intel_display_power_domain domain; 415 416 drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); 417 for_each_power_domain(domain, mask) 418 drm_dbg_kms(display->drm, "%s use_count %d\n", 419 intel_display_power_domain_str(domain), 420 power_domains->domain_use_count[domain]); 421 } 422 423 static void 424 print_async_put_domains_state(struct i915_power_domains *power_domains) 425 { 426 struct intel_display *display = container_of(power_domains, 427 struct intel_display, 428 power.domains); 429 430 drm_dbg_kms(display->drm, "async_put_wakeref: %s\n", 431 str_yes_no(power_domains->async_put_wakeref)); 432 433 print_power_domains(power_domains, "async_put_domains[0]", 434 &power_domains->async_put_domains[0]); 435 print_power_domains(power_domains, "async_put_domains[1]", 436 &power_domains->async_put_domains[1]); 437 } 438 439 static void 440 verify_async_put_domains_state(struct i915_power_domains *power_domains) 441 { 442 if (!__async_put_domains_state_ok(power_domains)) 443 print_async_put_domains_state(power_domains); 444 } 445 446 #else 447 448 static void 449 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 450 { 451 } 452 453 static void 454 verify_async_put_domains_state(struct i915_power_domains *power_domains) 455 { 456 } 457 458 #endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */ 459 460 static void async_put_domains_mask(struct i915_power_domains *power_domains, 461 struct intel_power_domain_mask *mask) 462 463 { 464 assert_async_put_domain_masks_disjoint(power_domains); 465 466 __async_put_domains_mask(power_domains, mask); 467 } 468 469 static void 470 async_put_domains_clear_domain(struct i915_power_domains *power_domains, 471 enum intel_display_power_domain domain) 472 { 473 assert_async_put_domain_masks_disjoint(power_domains); 474 475 clear_bit(domain, power_domains->async_put_domains[0].bits); 476 clear_bit(domain, power_domains->async_put_domains[1].bits); 477 } 478 479 static void 480 cancel_async_put_work(struct i915_power_domains *power_domains, bool sync) 481 { 482 if (sync) 483 cancel_delayed_work_sync(&power_domains->async_put_work); 484 else 485 cancel_delayed_work(&power_domains->async_put_work); 486 487 power_domains->async_put_next_delay = 0; 488 } 489 490 static bool 491 intel_display_power_grab_async_put_ref(struct intel_display *display, 492 enum intel_display_power_domain domain) 493 { 494 struct i915_power_domains *power_domains = &display->power.domains; 495 struct intel_power_domain_mask async_put_mask; 496 bool ret = false; 497 498 async_put_domains_mask(power_domains, &async_put_mask); 499 if (!test_bit(domain, async_put_mask.bits)) 500 goto out_verify; 501 502 async_put_domains_clear_domain(power_domains, domain); 503 504 ret = true; 505 506 async_put_domains_mask(power_domains, &async_put_mask); 507 if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)) 508 goto out_verify; 509 510 cancel_async_put_work(power_domains, false); 511 intel_display_rpm_put_raw(display, 512 fetch_and_zero(&power_domains->async_put_wakeref)); 513 out_verify: 514 verify_async_put_domains_state(power_domains); 515 516 return ret; 517 } 518 519 static void 520 __intel_display_power_get_domain(struct intel_display *display, 521 enum intel_display_power_domain domain) 522 { 523 struct i915_power_domains *power_domains = &display->power.domains; 524 struct i915_power_well *power_well; 525 526 if (intel_display_power_grab_async_put_ref(display, domain)) 527 return; 528 529 for_each_power_domain_well(display, power_well, domain) 530 intel_power_well_get(display, power_well); 531 532 power_domains->domain_use_count[domain]++; 533 } 534 535 /** 536 * intel_display_power_get - grab a power domain reference 537 * @display: display device instance 538 * @domain: power domain to reference 539 * 540 * This function grabs a power domain reference for @domain and ensures that the 541 * power domain and all its parents are powered up. Therefore users should only 542 * grab a reference to the innermost power domain they need. 543 * 544 * Any power domain reference obtained by this function must have a symmetric 545 * call to intel_display_power_put() to release the reference again. 546 */ 547 struct ref_tracker *intel_display_power_get(struct intel_display *display, 548 enum intel_display_power_domain domain) 549 { 550 struct i915_power_domains *power_domains = &display->power.domains; 551 struct ref_tracker *wakeref; 552 553 wakeref = intel_display_rpm_get(display); 554 555 mutex_lock(&power_domains->lock); 556 __intel_display_power_get_domain(display, domain); 557 mutex_unlock(&power_domains->lock); 558 559 return wakeref; 560 } 561 562 /** 563 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 564 * @display: display device instance 565 * @domain: power domain to reference 566 * 567 * This function grabs a power domain reference for @domain and ensures that the 568 * power domain and all its parents are powered up. Therefore users should only 569 * grab a reference to the innermost power domain they need. 570 * 571 * Any power domain reference obtained by this function must have a symmetric 572 * call to intel_display_power_put() to release the reference again. 573 */ 574 struct ref_tracker * 575 intel_display_power_get_if_enabled(struct intel_display *display, 576 enum intel_display_power_domain domain) 577 { 578 struct i915_power_domains *power_domains = &display->power.domains; 579 struct ref_tracker *wakeref; 580 bool is_enabled; 581 582 wakeref = intel_display_rpm_get_if_in_use(display); 583 if (!wakeref) 584 return NULL; 585 586 mutex_lock(&power_domains->lock); 587 588 if (__intel_display_power_is_enabled(display, domain)) { 589 __intel_display_power_get_domain(display, domain); 590 is_enabled = true; 591 } else { 592 is_enabled = false; 593 } 594 595 mutex_unlock(&power_domains->lock); 596 597 if (!is_enabled) { 598 intel_display_rpm_put(display, wakeref); 599 wakeref = NULL; 600 } 601 602 return wakeref; 603 } 604 605 static void 606 __intel_display_power_put_domain(struct intel_display *display, 607 enum intel_display_power_domain domain) 608 { 609 struct i915_power_domains *power_domains = &display->power.domains; 610 struct i915_power_well *power_well; 611 const char *name = intel_display_power_domain_str(domain); 612 struct intel_power_domain_mask async_put_mask; 613 614 drm_WARN(display->drm, !power_domains->domain_use_count[domain], 615 "Use count on domain %s is already zero\n", 616 name); 617 async_put_domains_mask(power_domains, &async_put_mask); 618 drm_WARN(display->drm, 619 test_bit(domain, async_put_mask.bits), 620 "Async disabling of domain %s is pending\n", 621 name); 622 623 power_domains->domain_use_count[domain]--; 624 625 for_each_power_domain_well_reverse(display, power_well, domain) 626 intel_power_well_put(display, power_well); 627 } 628 629 static void __intel_display_power_put(struct intel_display *display, 630 enum intel_display_power_domain domain) 631 { 632 struct i915_power_domains *power_domains = &display->power.domains; 633 634 mutex_lock(&power_domains->lock); 635 __intel_display_power_put_domain(display, domain); 636 mutex_unlock(&power_domains->lock); 637 } 638 639 static void 640 queue_async_put_domains_work(struct i915_power_domains *power_domains, 641 struct ref_tracker *wakeref, 642 int delay_ms) 643 { 644 struct intel_display *display = container_of(power_domains, 645 struct intel_display, 646 power.domains); 647 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); 648 power_domains->async_put_wakeref = wakeref; 649 drm_WARN_ON(display->drm, !queue_delayed_work(system_dfl_wq, 650 &power_domains->async_put_work, 651 msecs_to_jiffies(delay_ms))); 652 } 653 654 static void 655 release_async_put_domains(struct i915_power_domains *power_domains, 656 struct intel_power_domain_mask *mask) 657 { 658 struct intel_display *display = container_of(power_domains, 659 struct intel_display, 660 power.domains); 661 enum intel_display_power_domain domain; 662 struct ref_tracker *wakeref; 663 664 wakeref = intel_display_rpm_get_noresume(display); 665 666 for_each_power_domain(domain, mask) { 667 /* Clear before put, so put's sanity check is happy. */ 668 async_put_domains_clear_domain(power_domains, domain); 669 __intel_display_power_put_domain(display, domain); 670 } 671 672 intel_display_rpm_put(display, wakeref); 673 } 674 675 static void 676 intel_display_power_put_async_work(struct work_struct *work) 677 { 678 struct intel_display *display = container_of(work, struct intel_display, 679 power.domains.async_put_work.work); 680 struct i915_power_domains *power_domains = &display->power.domains; 681 struct ref_tracker *new_work_wakeref, *old_work_wakeref = NULL; 682 683 new_work_wakeref = intel_display_rpm_get_raw(display); 684 685 mutex_lock(&power_domains->lock); 686 687 /* 688 * Bail out if all the domain refs pending to be released were grabbed 689 * by subsequent gets or a flush_work. 690 */ 691 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 692 if (!old_work_wakeref) 693 goto out_verify; 694 695 release_async_put_domains(power_domains, 696 &power_domains->async_put_domains[0]); 697 698 /* 699 * Cancel the work that got queued after this one got dequeued, 700 * since here we released the corresponding async-put reference. 701 */ 702 cancel_async_put_work(power_domains, false); 703 704 /* Requeue the work if more domains were async put meanwhile. */ 705 if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) { 706 bitmap_copy(power_domains->async_put_domains[0].bits, 707 power_domains->async_put_domains[1].bits, 708 POWER_DOMAIN_NUM); 709 bitmap_zero(power_domains->async_put_domains[1].bits, 710 POWER_DOMAIN_NUM); 711 queue_async_put_domains_work(power_domains, 712 fetch_and_zero(&new_work_wakeref), 713 power_domains->async_put_next_delay); 714 power_domains->async_put_next_delay = 0; 715 } 716 717 out_verify: 718 verify_async_put_domains_state(power_domains); 719 720 mutex_unlock(&power_domains->lock); 721 722 if (old_work_wakeref) 723 intel_display_rpm_put_raw(display, old_work_wakeref); 724 if (new_work_wakeref) 725 intel_display_rpm_put_raw(display, new_work_wakeref); 726 } 727 728 /** 729 * __intel_display_power_put_async - release a power domain reference asynchronously 730 * @display: display device instance 731 * @domain: power domain to reference 732 * @wakeref: wakeref acquired for the reference that is being released 733 * @delay_ms: delay of powering down the power domain 734 * 735 * This function drops the power domain reference obtained by 736 * intel_display_power_get*() and schedules a work to power down the 737 * corresponding hardware block if this is the last reference. 738 * The power down is delayed by @delay_ms if this is >= 0, or by a default 739 * 100 ms otherwise. 740 */ 741 void __intel_display_power_put_async(struct intel_display *display, 742 enum intel_display_power_domain domain, 743 struct ref_tracker *wakeref, 744 int delay_ms) 745 { 746 struct i915_power_domains *power_domains = &display->power.domains; 747 struct ref_tracker *work_wakeref; 748 749 work_wakeref = intel_display_rpm_get_raw(display); 750 751 delay_ms = delay_ms >= 0 ? delay_ms : 100; 752 753 mutex_lock(&power_domains->lock); 754 755 if (power_domains->domain_use_count[domain] > 1) { 756 __intel_display_power_put_domain(display, domain); 757 758 goto out_verify; 759 } 760 761 drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1); 762 763 /* Let a pending work requeue itself or queue a new one. */ 764 if (power_domains->async_put_wakeref) { 765 set_bit(domain, power_domains->async_put_domains[1].bits); 766 power_domains->async_put_next_delay = max(power_domains->async_put_next_delay, 767 delay_ms); 768 } else { 769 set_bit(domain, power_domains->async_put_domains[0].bits); 770 queue_async_put_domains_work(power_domains, 771 fetch_and_zero(&work_wakeref), 772 delay_ms); 773 } 774 775 out_verify: 776 verify_async_put_domains_state(power_domains); 777 778 mutex_unlock(&power_domains->lock); 779 780 if (work_wakeref) 781 intel_display_rpm_put_raw(display, work_wakeref); 782 783 intel_display_rpm_put(display, wakeref); 784 } 785 786 /** 787 * intel_display_power_flush_work - flushes the async display power disabling work 788 * @display: display device instance 789 * 790 * Flushes any pending work that was scheduled by a preceding 791 * intel_display_power_put_async() call, completing the disabling of the 792 * corresponding power domains. 793 * 794 * Note that the work handler function may still be running after this 795 * function returns; to ensure that the work handler isn't running use 796 * intel_display_power_flush_work_sync() instead. 797 */ 798 void intel_display_power_flush_work(struct intel_display *display) 799 { 800 struct i915_power_domains *power_domains = &display->power.domains; 801 struct intel_power_domain_mask async_put_mask; 802 struct ref_tracker *work_wakeref; 803 804 mutex_lock(&power_domains->lock); 805 806 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 807 if (!work_wakeref) 808 goto out_verify; 809 810 async_put_domains_mask(power_domains, &async_put_mask); 811 release_async_put_domains(power_domains, &async_put_mask); 812 cancel_async_put_work(power_domains, false); 813 814 out_verify: 815 verify_async_put_domains_state(power_domains); 816 817 mutex_unlock(&power_domains->lock); 818 819 if (work_wakeref) 820 intel_display_rpm_put_raw(display, work_wakeref); 821 } 822 823 /** 824 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work 825 * @display: display device instance 826 * 827 * Like intel_display_power_flush_work(), but also ensure that the work 828 * handler function is not running any more when this function returns. 829 */ 830 static void 831 intel_display_power_flush_work_sync(struct intel_display *display) 832 { 833 struct i915_power_domains *power_domains = &display->power.domains; 834 835 intel_display_power_flush_work(display); 836 cancel_async_put_work(power_domains, true); 837 838 verify_async_put_domains_state(power_domains); 839 840 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); 841 } 842 843 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 844 /** 845 * intel_display_power_put - release a power domain reference 846 * @display: display device instance 847 * @domain: power domain to reference 848 * @wakeref: wakeref acquired for the reference that is being released 849 * 850 * This function drops the power domain reference obtained by 851 * intel_display_power_get() and might power down the corresponding hardware 852 * block right away if this is the last reference. 853 */ 854 void intel_display_power_put(struct intel_display *display, 855 enum intel_display_power_domain domain, 856 struct ref_tracker *wakeref) 857 { 858 __intel_display_power_put(display, domain); 859 intel_display_rpm_put(display, wakeref); 860 } 861 #else 862 /** 863 * intel_display_power_put_unchecked - release an unchecked power domain reference 864 * @display: display device instance 865 * @domain: power domain to reference 866 * 867 * This function drops the power domain reference obtained by 868 * intel_display_power_get() and might power down the corresponding hardware 869 * block right away if this is the last reference. 870 * 871 * This function is only for the power domain code's internal use to suppress wakeref 872 * tracking when the corresponding debug kconfig option is disabled, should not 873 * be used otherwise. 874 */ 875 void intel_display_power_put_unchecked(struct intel_display *display, 876 enum intel_display_power_domain domain) 877 { 878 __intel_display_power_put(display, domain); 879 intel_display_rpm_put_unchecked(display); 880 } 881 #endif 882 883 void 884 intel_display_power_get_in_set(struct intel_display *display, 885 struct intel_display_power_domain_set *power_domain_set, 886 enum intel_display_power_domain domain) 887 { 888 struct ref_tracker *__maybe_unused wf; 889 890 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); 891 892 wf = intel_display_power_get(display, domain); 893 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 894 power_domain_set->wakerefs[domain] = wf; 895 #endif 896 set_bit(domain, power_domain_set->mask.bits); 897 } 898 899 bool 900 intel_display_power_get_in_set_if_enabled(struct intel_display *display, 901 struct intel_display_power_domain_set *power_domain_set, 902 enum intel_display_power_domain domain) 903 { 904 struct ref_tracker *wf; 905 906 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); 907 908 wf = intel_display_power_get_if_enabled(display, domain); 909 if (!wf) 910 return false; 911 912 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 913 power_domain_set->wakerefs[domain] = wf; 914 #endif 915 set_bit(domain, power_domain_set->mask.bits); 916 917 return true; 918 } 919 920 void 921 intel_display_power_put_mask_in_set(struct intel_display *display, 922 struct intel_display_power_domain_set *power_domain_set, 923 struct intel_power_domain_mask *mask) 924 { 925 enum intel_display_power_domain domain; 926 927 drm_WARN_ON(display->drm, 928 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM)); 929 930 for_each_power_domain(domain, mask) { 931 struct ref_tracker *__maybe_unused wf = INTEL_WAKEREF_DEF; 932 933 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 934 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]); 935 #endif 936 intel_display_power_put(display, domain, wf); 937 clear_bit(domain, power_domain_set->mask.bits); 938 } 939 } 940 941 static int 942 sanitize_disable_power_well_option(int disable_power_well) 943 { 944 if (disable_power_well >= 0) 945 return !!disable_power_well; 946 947 return 1; 948 } 949 950 static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc) 951 { 952 u32 mask; 953 int requested_dc; 954 int max_dc; 955 956 if (!HAS_DISPLAY(display)) 957 return 0; 958 959 if (DISPLAY_VER(display) >= 20) 960 max_dc = 2; 961 else if (display->platform.dg2) 962 max_dc = 1; 963 else if (display->platform.dg1) 964 max_dc = 3; 965 else if (DISPLAY_VER(display) >= 12) 966 max_dc = 4; 967 else if (display->platform.geminilake || display->platform.broxton) 968 max_dc = 1; 969 else if (DISPLAY_VER(display) >= 9) 970 max_dc = 2; 971 else 972 max_dc = 0; 973 974 /* 975 * DC9 has a separate HW flow from the rest of the DC states, 976 * not depending on the DMC firmware. It's needed by system 977 * suspend/resume, so allow it unconditionally. 978 */ 979 mask = display->platform.geminilake || display->platform.broxton || 980 DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0; 981 982 if (!display->params.disable_power_well) 983 max_dc = 0; 984 985 if (enable_dc >= 0 && enable_dc <= max_dc) { 986 requested_dc = enable_dc; 987 } else if (enable_dc == -1) { 988 requested_dc = max_dc; 989 } else if (enable_dc > max_dc && enable_dc <= 4) { 990 drm_dbg_kms(display->drm, 991 "Adjusting requested max DC state (%d->%d)\n", 992 enable_dc, max_dc); 993 requested_dc = max_dc; 994 } else { 995 drm_err(display->drm, 996 "Unexpected value for enable_dc (%d)\n", enable_dc); 997 requested_dc = max_dc; 998 } 999 1000 switch (requested_dc) { 1001 case 4: 1002 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6; 1003 break; 1004 case 3: 1005 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5; 1006 break; 1007 case 2: 1008 mask |= DC_STATE_EN_UPTO_DC6; 1009 break; 1010 case 1: 1011 mask |= DC_STATE_EN_UPTO_DC5; 1012 break; 1013 } 1014 1015 drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask); 1016 1017 return mask; 1018 } 1019 1020 /** 1021 * intel_power_domains_init - initializes the power domain structures 1022 * @display: display device instance 1023 * 1024 * Initializes the power domain structures for @display depending upon the 1025 * supported platform. 1026 */ 1027 int intel_power_domains_init(struct intel_display *display) 1028 { 1029 struct i915_power_domains *power_domains = &display->power.domains; 1030 1031 display->params.disable_power_well = 1032 sanitize_disable_power_well_option(display->params.disable_power_well); 1033 power_domains->allowed_dc_mask = 1034 get_allowed_dc_mask(display, display->params.enable_dc); 1035 1036 power_domains->target_dc_state = 1037 sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1038 1039 mutex_init(&power_domains->lock); 1040 1041 INIT_DELAYED_WORK(&power_domains->async_put_work, 1042 intel_display_power_put_async_work); 1043 1044 return intel_display_power_map_init(power_domains); 1045 } 1046 1047 /** 1048 * intel_power_domains_cleanup - clean up power domains resources 1049 * @display: display device instance 1050 * 1051 * Release any resources acquired by intel_power_domains_init() 1052 */ 1053 void intel_power_domains_cleanup(struct intel_display *display) 1054 { 1055 intel_display_power_map_cleanup(&display->power.domains); 1056 } 1057 1058 static void intel_power_domains_sync_hw(struct intel_display *display) 1059 { 1060 struct i915_power_domains *power_domains = &display->power.domains; 1061 struct i915_power_well *power_well; 1062 1063 mutex_lock(&power_domains->lock); 1064 for_each_power_well(display, power_well) 1065 intel_power_well_sync_hw(display, power_well); 1066 mutex_unlock(&power_domains->lock); 1067 } 1068 1069 static void gen9_dbuf_slice_set(struct intel_display *display, 1070 enum dbuf_slice slice, bool enable) 1071 { 1072 i915_reg_t reg = DBUF_CTL_S(slice); 1073 bool state; 1074 1075 intel_de_rmw(display, reg, DBUF_POWER_REQUEST, 1076 enable ? DBUF_POWER_REQUEST : 0); 1077 intel_de_posting_read(display, reg); 1078 udelay(10); 1079 1080 state = intel_de_read(display, reg) & DBUF_POWER_STATE; 1081 drm_WARN(display->drm, enable != state, 1082 "DBuf slice %d power %s timeout!\n", 1083 slice, str_enable_disable(enable)); 1084 } 1085 1086 void gen9_dbuf_slices_update(struct intel_display *display, 1087 u8 req_slices) 1088 { 1089 struct i915_power_domains *power_domains = &display->power.domains; 1090 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; 1091 enum dbuf_slice slice; 1092 1093 drm_WARN(display->drm, req_slices & ~slice_mask, 1094 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n", 1095 req_slices, slice_mask); 1096 1097 drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n", 1098 req_slices); 1099 1100 /* 1101 * Might be running this in parallel to gen9_dc_off_power_well_enable 1102 * being called from intel_dp_detect for instance, 1103 * which causes assertion triggered by race condition, 1104 * as gen9_assert_dbuf_enabled might preempt this when registers 1105 * were already updated, while dev_priv was not. 1106 */ 1107 mutex_lock(&power_domains->lock); 1108 1109 for_each_dbuf_slice(display, slice) 1110 gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice)); 1111 1112 display->dbuf.enabled_slices = req_slices; 1113 1114 mutex_unlock(&power_domains->lock); 1115 } 1116 1117 static void gen9_dbuf_enable(struct intel_display *display) 1118 { 1119 u8 slices_mask; 1120 1121 display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(display); 1122 1123 slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices; 1124 1125 if (DISPLAY_VER(display) >= 14) 1126 intel_pmdemand_program_dbuf(display, slices_mask); 1127 1128 /* 1129 * Just power up at least 1 slice, we will 1130 * figure out later which slices we have and what we need. 1131 */ 1132 gen9_dbuf_slices_update(display, slices_mask); 1133 } 1134 1135 static void gen9_dbuf_disable(struct intel_display *display) 1136 { 1137 gen9_dbuf_slices_update(display, 0); 1138 1139 if (DISPLAY_VER(display) >= 14) 1140 intel_pmdemand_program_dbuf(display, 0); 1141 } 1142 1143 static void gen12_dbuf_slices_config(struct intel_display *display) 1144 { 1145 enum dbuf_slice slice; 1146 1147 for_each_dbuf_slice(display, slice) 1148 intel_de_rmw(display, DBUF_CTL_S(slice), 1149 DBUF_TRACKER_STATE_SERVICE_MASK, 1150 DBUF_TRACKER_STATE_SERVICE(8)); 1151 } 1152 1153 static void icl_mbus_init(struct intel_display *display) 1154 { 1155 unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask; 1156 u32 mask, val, i; 1157 1158 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1159 return; 1160 1161 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | 1162 MBUS_ABOX_BT_CREDIT_POOL2_MASK | 1163 MBUS_ABOX_B_CREDIT_MASK | 1164 MBUS_ABOX_BW_CREDIT_MASK; 1165 val = MBUS_ABOX_BT_CREDIT_POOL1(16) | 1166 MBUS_ABOX_BT_CREDIT_POOL2(16) | 1167 MBUS_ABOX_B_CREDIT(1) | 1168 MBUS_ABOX_BW_CREDIT(1); 1169 1170 /* 1171 * gen12 platforms that use abox1 and abox2 for pixel data reads still 1172 * expect us to program the abox_ctl0 register as well, even though 1173 * we don't have to program other instance-0 registers like BW_BUDDY. 1174 */ 1175 if (DISPLAY_VER(display) == 12) 1176 abox_regs |= BIT(0); 1177 1178 for_each_set_bit(i, &abox_regs, BITS_PER_TYPE(abox_regs)) 1179 intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val); 1180 } 1181 1182 static void hsw_assert_cdclk(struct intel_display *display) 1183 { 1184 u32 val = intel_de_read(display, LCPLL_CTL); 1185 1186 /* 1187 * The LCPLL register should be turned on by the BIOS. For now 1188 * let's just check its state and print errors in case 1189 * something is wrong. Don't even try to turn it on. 1190 */ 1191 1192 if (val & LCPLL_CD_SOURCE_FCLK) 1193 drm_err(display->drm, "CDCLK source is not LCPLL\n"); 1194 1195 if (val & LCPLL_PLL_DISABLE) 1196 drm_err(display->drm, "LCPLL is disabled\n"); 1197 1198 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC) 1199 drm_err(display->drm, "LCPLL not using non-SSC reference\n"); 1200 } 1201 1202 static void assert_can_disable_lcpll(struct intel_display *display) 1203 { 1204 struct intel_crtc *crtc; 1205 1206 for_each_intel_crtc(display->drm, crtc) 1207 INTEL_DISPLAY_STATE_WARN(display, crtc->active, 1208 "CRTC for pipe %c enabled\n", 1209 pipe_name(crtc->pipe)); 1210 1211 INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2), 1212 "Display power well on\n"); 1213 INTEL_DISPLAY_STATE_WARN(display, 1214 intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE, 1215 "SPLL enabled\n"); 1216 INTEL_DISPLAY_STATE_WARN(display, 1217 intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, 1218 "WRPLL1 enabled\n"); 1219 INTEL_DISPLAY_STATE_WARN(display, 1220 intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, 1221 "WRPLL2 enabled\n"); 1222 INTEL_DISPLAY_STATE_WARN(display, 1223 intel_de_read(display, PP_STATUS(display, 0)) & PP_ON, 1224 "Panel power on\n"); 1225 INTEL_DISPLAY_STATE_WARN(display, 1226 intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 1227 "CPU PWM1 enabled\n"); 1228 if (display->platform.haswell) 1229 INTEL_DISPLAY_STATE_WARN(display, 1230 intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 1231 "CPU PWM2 enabled\n"); 1232 INTEL_DISPLAY_STATE_WARN(display, 1233 intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, 1234 "PCH PWM1 enabled\n"); 1235 INTEL_DISPLAY_STATE_WARN(display, 1236 (intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 1237 "Utility pin enabled in PWM mode\n"); 1238 INTEL_DISPLAY_STATE_WARN(display, 1239 intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE, 1240 "PCH GTC enabled\n"); 1241 1242 /* 1243 * In theory we can still leave IRQs enabled, as long as only the HPD 1244 * interrupts remain enabled. We used to check for that, but since it's 1245 * gen-specific and since we only disable LCPLL after we fully disable 1246 * the interrupts, the check below should be enough. 1247 */ 1248 INTEL_DISPLAY_STATE_WARN(display, intel_parent_irq_enabled(display), 1249 "IRQs enabled\n"); 1250 } 1251 1252 static u32 hsw_read_dcomp(struct intel_display *display) 1253 { 1254 if (display->platform.haswell) 1255 return intel_de_read(display, D_COMP_HSW); 1256 else 1257 return intel_de_read(display, D_COMP_BDW); 1258 } 1259 1260 static void hsw_write_dcomp(struct intel_display *display, u32 val) 1261 { 1262 if (display->platform.haswell) { 1263 if (intel_parent_pcode_write(display, GEN6_PCODE_WRITE_D_COMP, val)) 1264 drm_dbg_kms(display->drm, "Failed to write to D_COMP\n"); 1265 } else { 1266 intel_de_write(display, D_COMP_BDW, val); 1267 intel_de_posting_read(display, D_COMP_BDW); 1268 } 1269 } 1270 1271 /* 1272 * This function implements pieces of two sequences from BSpec: 1273 * - Sequence for display software to disable LCPLL 1274 * - Sequence for display software to allow package C8+ 1275 * The steps implemented here are just the steps that actually touch the LCPLL 1276 * register. Callers should take care of disabling all the display engine 1277 * functions, doing the mode unset, fixing interrupts, etc. 1278 */ 1279 static void hsw_disable_lcpll(struct intel_display *display, 1280 bool switch_to_fclk, bool allow_power_down) 1281 { 1282 u32 val; 1283 int ret; 1284 1285 assert_can_disable_lcpll(display); 1286 1287 val = intel_de_read(display, LCPLL_CTL); 1288 1289 if (switch_to_fclk) { 1290 val |= LCPLL_CD_SOURCE_FCLK; 1291 intel_de_write(display, LCPLL_CTL, val); 1292 1293 ret = intel_de_wait_for_set_us(display, LCPLL_CTL, 1294 LCPLL_CD_SOURCE_FCLK_DONE, 1); 1295 if (ret) 1296 drm_err(display->drm, "Switching to FCLK failed\n"); 1297 1298 val = intel_de_read(display, LCPLL_CTL); 1299 } 1300 1301 val |= LCPLL_PLL_DISABLE; 1302 intel_de_write(display, LCPLL_CTL, val); 1303 intel_de_posting_read(display, LCPLL_CTL); 1304 1305 if (intel_de_wait_for_clear_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) 1306 drm_err(display->drm, "LCPLL still locked\n"); 1307 1308 val = hsw_read_dcomp(display); 1309 val |= D_COMP_COMP_DISABLE; 1310 hsw_write_dcomp(display, val); 1311 ndelay(100); 1312 1313 ret = poll_timeout_us(val = hsw_read_dcomp(display), 1314 (val & D_COMP_RCOMP_IN_PROGRESS) == 0, 1315 100, 1000, false); 1316 if (ret) 1317 drm_err(display->drm, "D_COMP RCOMP still in progress\n"); 1318 1319 if (allow_power_down) { 1320 intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); 1321 intel_de_posting_read(display, LCPLL_CTL); 1322 } 1323 } 1324 1325 /* 1326 * Fully restores LCPLL, disallowing power down and switching back to LCPLL 1327 * source. 1328 */ 1329 static void hsw_restore_lcpll(struct intel_display *display) 1330 { 1331 u32 val; 1332 int ret; 1333 1334 val = intel_de_read(display, LCPLL_CTL); 1335 1336 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | 1337 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) 1338 return; 1339 1340 /* 1341 * Make sure we're not on PC8 state before disabling 1342 * PC8, otherwise we'll hang the machine. 1343 */ 1344 intel_parent_pc8_block(display); 1345 1346 if (val & LCPLL_POWER_DOWN_ALLOW) { 1347 val &= ~LCPLL_POWER_DOWN_ALLOW; 1348 intel_de_write(display, LCPLL_CTL, val); 1349 intel_de_posting_read(display, LCPLL_CTL); 1350 } 1351 1352 val = hsw_read_dcomp(display); 1353 val |= D_COMP_COMP_FORCE; 1354 val &= ~D_COMP_COMP_DISABLE; 1355 hsw_write_dcomp(display, val); 1356 1357 val = intel_de_read(display, LCPLL_CTL); 1358 val &= ~LCPLL_PLL_DISABLE; 1359 intel_de_write(display, LCPLL_CTL, val); 1360 1361 if (intel_de_wait_for_set_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) 1362 drm_err(display->drm, "LCPLL not locked yet\n"); 1363 1364 if (val & LCPLL_CD_SOURCE_FCLK) { 1365 intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); 1366 1367 ret = intel_de_wait_for_clear_us(display, LCPLL_CTL, 1368 LCPLL_CD_SOURCE_FCLK_DONE, 1); 1369 if (ret) 1370 drm_err(display->drm, 1371 "Switching back to LCPLL failed\n"); 1372 } 1373 1374 intel_parent_pc8_unblock(display); 1375 1376 intel_update_cdclk(display); 1377 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1378 } 1379 1380 /* 1381 * Package states C8 and deeper are really deep PC states that can only be 1382 * reached when all the devices on the system allow it, so even if the graphics 1383 * device allows PC8+, it doesn't mean the system will actually get to these 1384 * states. Our driver only allows PC8+ when going into runtime PM. 1385 * 1386 * The requirements for PC8+ are that all the outputs are disabled, the power 1387 * well is disabled and most interrupts are disabled, and these are also 1388 * requirements for runtime PM. When these conditions are met, we manually do 1389 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk 1390 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard 1391 * hang the machine. 1392 * 1393 * When we really reach PC8 or deeper states (not just when we allow it) we lose 1394 * the state of some registers, so when we come back from PC8+ we need to 1395 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't 1396 * need to take care of the registers kept by RC6. Notice that this happens even 1397 * if we don't put the device in PCI D3 state (which is what currently happens 1398 * because of the runtime PM support). 1399 * 1400 * For more, read "Display Sequences for Package C8" on the hardware 1401 * documentation. 1402 */ 1403 static void hsw_enable_pc8(struct intel_display *display) 1404 { 1405 drm_dbg_kms(display->drm, "Enabling package C8+\n"); 1406 1407 if (HAS_PCH_LPT_LP(display)) 1408 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1409 PCH_LP_PARTITION_LEVEL_DISABLE, 0); 1410 1411 lpt_disable_clkout_dp(display); 1412 hsw_disable_lcpll(display, true, true); 1413 } 1414 1415 static void hsw_disable_pc8(struct intel_display *display) 1416 { 1417 drm_dbg_kms(display->drm, "Disabling package C8+\n"); 1418 1419 hsw_restore_lcpll(display); 1420 intel_init_pch_refclk(display); 1421 1422 /* Many display registers don't survive PC8+ */ 1423 #ifdef I915 /* FIXME */ 1424 intel_clock_gating_init(display->drm); 1425 #endif 1426 } 1427 1428 static void intel_pch_reset_handshake(struct intel_display *display, 1429 bool enable) 1430 { 1431 i915_reg_t reg; 1432 u32 reset_bits; 1433 1434 if (DISPLAY_VER(display) >= 35) 1435 return; 1436 1437 if (display->platform.ivybridge) { 1438 reg = GEN7_MSG_CTL; 1439 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK; 1440 } else { 1441 reg = HSW_NDE_RSTWRN_OPT; 1442 reset_bits = RESET_PCH_HANDSHAKE_ENABLE; 1443 } 1444 1445 if (DISPLAY_VER(display) >= 14) 1446 reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; 1447 1448 intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0); 1449 } 1450 1451 static void skl_display_core_init(struct intel_display *display, 1452 bool resume) 1453 { 1454 struct i915_power_domains *power_domains = &display->power.domains; 1455 struct i915_power_well *well; 1456 1457 gen9_set_dc_state(display, DC_STATE_DISABLE); 1458 1459 /* enable PCH reset handshake */ 1460 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); 1461 1462 if (!HAS_DISPLAY(display)) 1463 return; 1464 1465 /* enable PG1 and Misc I/O */ 1466 mutex_lock(&power_domains->lock); 1467 1468 well = lookup_power_well(display, SKL_DISP_PW_1); 1469 intel_power_well_enable(display, well); 1470 1471 well = lookup_power_well(display, SKL_DISP_PW_MISC_IO); 1472 intel_power_well_enable(display, well); 1473 1474 mutex_unlock(&power_domains->lock); 1475 1476 intel_cdclk_init_hw(display); 1477 1478 gen9_dbuf_enable(display); 1479 1480 if (resume) 1481 intel_dmc_load_program(display); 1482 } 1483 1484 static void skl_display_core_uninit(struct intel_display *display) 1485 { 1486 struct i915_power_domains *power_domains = &display->power.domains; 1487 struct i915_power_well *well; 1488 1489 if (!HAS_DISPLAY(display)) 1490 return; 1491 1492 gen9_disable_dc_states(display); 1493 /* TODO: disable DMC program */ 1494 1495 gen9_dbuf_disable(display); 1496 1497 intel_cdclk_uninit_hw(display); 1498 1499 /* The spec doesn't call for removing the reset handshake flag */ 1500 /* disable PG1 and Misc I/O */ 1501 1502 mutex_lock(&power_domains->lock); 1503 1504 /* 1505 * BSpec says to keep the MISC IO power well enabled here, only 1506 * remove our request for power well 1. 1507 * Note that even though the driver's request is removed power well 1 1508 * may stay enabled after this due to DMC's own request on it. 1509 */ 1510 well = lookup_power_well(display, SKL_DISP_PW_1); 1511 intel_power_well_disable(display, well); 1512 1513 mutex_unlock(&power_domains->lock); 1514 1515 usleep_range(10, 30); /* 10 us delay per Bspec */ 1516 } 1517 1518 static void bxt_display_core_init(struct intel_display *display, bool resume) 1519 { 1520 struct i915_power_domains *power_domains = &display->power.domains; 1521 struct i915_power_well *well; 1522 1523 gen9_set_dc_state(display, DC_STATE_DISABLE); 1524 1525 /* 1526 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 1527 * or else the reset will hang because there is no PCH to respond. 1528 * Move the handshake programming to initialization sequence. 1529 * Previously was left up to BIOS. 1530 */ 1531 intel_pch_reset_handshake(display, false); 1532 1533 if (!HAS_DISPLAY(display)) 1534 return; 1535 1536 /* Enable PG1 */ 1537 mutex_lock(&power_domains->lock); 1538 1539 well = lookup_power_well(display, SKL_DISP_PW_1); 1540 intel_power_well_enable(display, well); 1541 1542 mutex_unlock(&power_domains->lock); 1543 1544 intel_cdclk_init_hw(display); 1545 1546 gen9_dbuf_enable(display); 1547 1548 if (resume) 1549 intel_dmc_load_program(display); 1550 } 1551 1552 static void bxt_display_core_uninit(struct intel_display *display) 1553 { 1554 struct i915_power_domains *power_domains = &display->power.domains; 1555 struct i915_power_well *well; 1556 1557 if (!HAS_DISPLAY(display)) 1558 return; 1559 1560 gen9_disable_dc_states(display); 1561 /* TODO: disable DMC program */ 1562 1563 gen9_dbuf_disable(display); 1564 1565 intel_cdclk_uninit_hw(display); 1566 1567 /* The spec doesn't call for removing the reset handshake flag */ 1568 1569 /* 1570 * Disable PW1 (PG1). 1571 * Note that even though the driver's request is removed power well 1 1572 * may stay enabled after this due to DMC's own request on it. 1573 */ 1574 mutex_lock(&power_domains->lock); 1575 1576 well = lookup_power_well(display, SKL_DISP_PW_1); 1577 intel_power_well_disable(display, well); 1578 1579 mutex_unlock(&power_domains->lock); 1580 1581 usleep_range(10, 30); /* 10 us delay per Bspec */ 1582 } 1583 1584 struct buddy_page_mask { 1585 u32 page_mask; 1586 u8 type; 1587 u8 num_channels; 1588 }; 1589 1590 static const struct buddy_page_mask tgl_buddy_page_masks[] = { 1591 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF }, 1592 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF }, 1593 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C }, 1594 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C }, 1595 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F }, 1596 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E }, 1597 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 }, 1598 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 }, 1599 {} 1600 }; 1601 1602 static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = { 1603 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 }, 1604 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 }, 1605 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 }, 1606 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 }, 1607 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 }, 1608 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 }, 1609 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 }, 1610 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 }, 1611 {} 1612 }; 1613 1614 static void tgl_bw_buddy_init(struct intel_display *display) 1615 { 1616 const struct dram_info *dram_info = intel_dram_info(display); 1617 const struct buddy_page_mask *table; 1618 unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; 1619 int config, i; 1620 1621 /* BW_BUDDY registers are not used on dgpu's beyond DG1 */ 1622 if (display->platform.dgfx && !display->platform.dg1) 1623 return; 1624 1625 if (intel_display_wa(display, INTEL_DISPLAY_WA_1409767108)) 1626 /* Wa_1409767108 */ 1627 table = wa_1409767108_buddy_page_masks; 1628 else 1629 table = tgl_buddy_page_masks; 1630 1631 for (config = 0; table[config].page_mask != 0; config++) 1632 if (table[config].num_channels == dram_info->num_channels && 1633 table[config].type == dram_info->type) 1634 break; 1635 1636 if (table[config].page_mask == 0) { 1637 drm_dbg_kms(display->drm, 1638 "Unknown memory configuration; disabling address buddy logic.\n"); 1639 for_each_set_bit(i, &abox_mask, BITS_PER_TYPE(abox_mask)) 1640 intel_de_write(display, BW_BUDDY_CTL(i), 1641 BW_BUDDY_DISABLE); 1642 } else { 1643 for_each_set_bit(i, &abox_mask, BITS_PER_TYPE(abox_mask)) { 1644 intel_de_write(display, BW_BUDDY_PAGE_MASK(i), 1645 table[config].page_mask); 1646 1647 /* Wa_22010178259:tgl,dg1,rkl,adl-s */ 1648 if (intel_display_wa(display, INTEL_DISPLAY_WA_22010178259)) 1649 intel_de_rmw(display, BW_BUDDY_CTL(i), 1650 BW_BUDDY_TLB_REQ_TIMER_MASK, 1651 BW_BUDDY_TLB_REQ_TIMER(0x8)); 1652 } 1653 } 1654 } 1655 1656 static void icl_display_core_init(struct intel_display *display, 1657 bool resume) 1658 { 1659 struct i915_power_domains *power_domains = &display->power.domains; 1660 struct i915_power_well *well; 1661 1662 gen9_set_dc_state(display, DC_STATE_DISABLE); 1663 1664 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ 1665 if (intel_display_wa(display, INTEL_DISPLAY_WA_14011294188)) 1666 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0, 1667 PCH_DPMGUNIT_CLOCK_GATE_DISABLE); 1668 1669 /* 1. Enable PCH reset handshake. */ 1670 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); 1671 1672 if (!HAS_DISPLAY(display)) 1673 return; 1674 1675 /* 2. Initialize all combo phys */ 1676 intel_combo_phy_init(display); 1677 1678 /* 1679 * 3. Enable Power Well 1 (PG1). 1680 * The AUX IO power wells will be enabled on demand. 1681 */ 1682 mutex_lock(&power_domains->lock); 1683 well = lookup_power_well(display, SKL_DISP_PW_1); 1684 intel_power_well_enable(display, well); 1685 mutex_unlock(&power_domains->lock); 1686 1687 if (DISPLAY_VER(display) == 14) 1688 intel_de_rmw(display, DC_STATE_EN, 1689 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0); 1690 1691 /* 4. Enable CDCLK. */ 1692 intel_cdclk_init_hw(display); 1693 1694 if (DISPLAY_VER(display) == 12 || display->platform.dg2) 1695 gen12_dbuf_slices_config(display); 1696 1697 /* 5. Enable DBUF. */ 1698 gen9_dbuf_enable(display); 1699 1700 /* 6. Setup MBUS. */ 1701 icl_mbus_init(display); 1702 1703 /* 7. Program arbiter BW_BUDDY registers */ 1704 if (DISPLAY_VER(display) >= 12) 1705 tgl_bw_buddy_init(display); 1706 1707 /* 8. Ensure PHYs have completed calibration and adaptation */ 1708 if (display->platform.dg2) 1709 intel_snps_phy_wait_for_calibration(display); 1710 1711 /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ 1712 if (DISPLAY_VERx100(display) == 1401) 1713 intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); 1714 1715 if (resume) 1716 intel_dmc_load_program(display); 1717 1718 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */ 1719 if (intel_display_wa(display, INTEL_DISPLAY_WA_14011508470)) 1720 intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0, 1721 DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | 1722 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR); 1723 1724 /* Wa_14011503030:xelpd */ 1725 if (intel_display_wa(display, INTEL_DISPLAY_WA_14011503030)) 1726 intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); 1727 1728 /* Wa_15013987218 */ 1729 if (intel_display_wa(display, INTEL_DISPLAY_WA_15013987218)) { 1730 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1731 0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE); 1732 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1733 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0); 1734 } 1735 } 1736 1737 static void icl_display_core_uninit(struct intel_display *display) 1738 { 1739 struct i915_power_domains *power_domains = &display->power.domains; 1740 struct i915_power_well *well; 1741 1742 if (!HAS_DISPLAY(display)) 1743 return; 1744 1745 gen9_disable_dc_states(display); 1746 intel_dmc_disable_program(display); 1747 1748 /* 1. Disable all display engine functions -> already done */ 1749 1750 /* 2. Disable DBUF */ 1751 gen9_dbuf_disable(display); 1752 1753 /* 3. Disable CD clock */ 1754 intel_cdclk_uninit_hw(display); 1755 1756 if (DISPLAY_VER(display) == 14) 1757 intel_de_rmw(display, DC_STATE_EN, 0, 1758 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH); 1759 1760 /* 1761 * 4. Disable Power Well 1 (PG1). 1762 * The AUX IO power wells are toggled on demand, so they are already 1763 * disabled at this point. 1764 */ 1765 mutex_lock(&power_domains->lock); 1766 well = lookup_power_well(display, SKL_DISP_PW_1); 1767 intel_power_well_disable(display, well); 1768 mutex_unlock(&power_domains->lock); 1769 1770 /* 5. */ 1771 intel_combo_phy_uninit(display); 1772 } 1773 1774 static void chv_phy_control_init(struct intel_display *display) 1775 { 1776 struct i915_power_well *cmn_bc = 1777 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1778 struct i915_power_well *cmn_d = 1779 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1780 1781 /* 1782 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 1783 * workaround never ever read DISPLAY_PHY_CONTROL, and 1784 * instead maintain a shadow copy ourselves. Use the actual 1785 * power well state and lane status to reconstruct the 1786 * expected initial value. 1787 */ 1788 display->power.chv_phy_control = 1789 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 1790 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 1791 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 1792 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 1793 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 1794 1795 /* 1796 * If all lanes are disabled we leave the override disabled 1797 * with all power down bits cleared to match the state we 1798 * would use after disabling the port. Otherwise enable the 1799 * override and set the lane powerdown bits accding to the 1800 * current lane status. 1801 */ 1802 if (intel_power_well_is_enabled(display, cmn_bc)) { 1803 u32 status = intel_de_read(display, DPLL(display, PIPE_A)); 1804 unsigned int mask; 1805 1806 mask = status & DPLL_PORTB_READY_MASK; 1807 if (mask == 0xf) 1808 mask = 0x0; 1809 else 1810 display->power.chv_phy_control |= 1811 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 1812 1813 display->power.chv_phy_control |= 1814 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 1815 1816 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 1817 if (mask == 0xf) 1818 mask = 0x0; 1819 else 1820 display->power.chv_phy_control |= 1821 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 1822 1823 display->power.chv_phy_control |= 1824 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 1825 1826 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 1827 1828 display->power.chv_phy_assert[DPIO_PHY0] = false; 1829 } else { 1830 display->power.chv_phy_assert[DPIO_PHY0] = true; 1831 } 1832 1833 if (intel_power_well_is_enabled(display, cmn_d)) { 1834 u32 status = intel_de_read(display, DPIO_PHY_STATUS); 1835 unsigned int mask; 1836 1837 mask = status & DPLL_PORTD_READY_MASK; 1838 1839 if (mask == 0xf) 1840 mask = 0x0; 1841 else 1842 display->power.chv_phy_control |= 1843 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 1844 1845 display->power.chv_phy_control |= 1846 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 1847 1848 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 1849 1850 display->power.chv_phy_assert[DPIO_PHY1] = false; 1851 } else { 1852 display->power.chv_phy_assert[DPIO_PHY1] = true; 1853 } 1854 1855 drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n", 1856 display->power.chv_phy_control); 1857 1858 /* Defer application of initial phy_control to enabling the powerwell */ 1859 } 1860 1861 static void vlv_cmnlane_wa(struct intel_display *display) 1862 { 1863 struct i915_power_well *cmn = 1864 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1865 struct i915_power_well *disp2d = 1866 lookup_power_well(display, VLV_DISP_PW_DISP2D); 1867 1868 /* If the display might be already active skip this */ 1869 if (intel_power_well_is_enabled(display, cmn) && 1870 intel_power_well_is_enabled(display, disp2d) && 1871 intel_de_read(display, DPIO_CTL) & DPIO_CMNRST) 1872 return; 1873 1874 drm_dbg_kms(display->drm, "toggling display PHY side reset\n"); 1875 1876 /* cmnlane needs DPLL registers */ 1877 intel_power_well_enable(display, disp2d); 1878 1879 /* 1880 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 1881 * Need to assert and de-assert PHY SB reset by gating the 1882 * common lane power, then un-gating it. 1883 * Simply ungating isn't enough to reset the PHY enough to get 1884 * ports and lanes running. 1885 */ 1886 intel_power_well_disable(display, cmn); 1887 } 1888 1889 static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0) 1890 { 1891 bool ret; 1892 1893 vlv_punit_get(display->drm); 1894 ret = (vlv_punit_read(display->drm, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; 1895 vlv_punit_put(display->drm); 1896 1897 return ret; 1898 } 1899 1900 static void assert_ved_power_gated(struct intel_display *display) 1901 { 1902 drm_WARN(display->drm, 1903 !vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0), 1904 "VED not power gated\n"); 1905 } 1906 1907 static void assert_isp_power_gated(struct intel_display *display) 1908 { 1909 static const struct pci_device_id isp_ids[] = { 1910 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)}, 1911 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)}, 1912 {} 1913 }; 1914 1915 drm_WARN(display->drm, !pci_dev_present(isp_ids) && 1916 !vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0), 1917 "ISP not power gated\n"); 1918 } 1919 1920 static void intel_power_domains_verify_state(struct intel_display *display); 1921 1922 /** 1923 * intel_power_domains_init_hw - initialize hardware power domain state 1924 * @display: display device instance 1925 * @resume: Called from resume code paths or not 1926 * 1927 * This function initializes the hardware power domain state and enables all 1928 * power wells belonging to the INIT power domain. Power wells in other 1929 * domains (and not in the INIT domain) are referenced or disabled by 1930 * intel_modeset_readout_hw_state(). After that the reference count of each 1931 * power well must match its HW enabled state, see 1932 * intel_power_domains_verify_state(). 1933 * 1934 * It will return with power domains disabled (to be enabled later by 1935 * intel_power_domains_enable()) and must be paired with 1936 * intel_power_domains_driver_remove(). 1937 */ 1938 void intel_power_domains_init_hw(struct intel_display *display, bool resume) 1939 { 1940 struct i915_power_domains *power_domains = &display->power.domains; 1941 1942 power_domains->initializing = true; 1943 1944 if (DISPLAY_VER(display) >= 11) { 1945 icl_display_core_init(display, resume); 1946 } else if (display->platform.geminilake || display->platform.broxton) { 1947 bxt_display_core_init(display, resume); 1948 } else if (DISPLAY_VER(display) == 9) { 1949 skl_display_core_init(display, resume); 1950 } else if (display->platform.cherryview) { 1951 mutex_lock(&power_domains->lock); 1952 chv_phy_control_init(display); 1953 mutex_unlock(&power_domains->lock); 1954 assert_isp_power_gated(display); 1955 } else if (display->platform.valleyview) { 1956 mutex_lock(&power_domains->lock); 1957 vlv_cmnlane_wa(display); 1958 mutex_unlock(&power_domains->lock); 1959 assert_ved_power_gated(display); 1960 assert_isp_power_gated(display); 1961 } else if (display->platform.broadwell || display->platform.haswell) { 1962 hsw_assert_cdclk(display); 1963 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); 1964 } else if (display->platform.ivybridge) { 1965 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); 1966 } 1967 1968 /* 1969 * Keep all power wells enabled for any dependent HW access during 1970 * initialization and to make sure we keep BIOS enabled display HW 1971 * resources powered until display HW readout is complete. We drop 1972 * this reference in intel_power_domains_enable(). 1973 */ 1974 drm_WARN_ON(display->drm, power_domains->init_wakeref); 1975 power_domains->init_wakeref = 1976 intel_display_power_get(display, POWER_DOMAIN_INIT); 1977 1978 /* Disable power support if the user asked so. */ 1979 if (!display->params.disable_power_well) { 1980 drm_WARN_ON(display->drm, power_domains->disable_wakeref); 1981 display->power.domains.disable_wakeref = intel_display_power_get(display, 1982 POWER_DOMAIN_INIT); 1983 } 1984 intel_power_domains_sync_hw(display); 1985 1986 power_domains->initializing = false; 1987 } 1988 1989 /** 1990 * intel_power_domains_driver_remove - deinitialize hw power domain state 1991 * @display: display device instance 1992 * 1993 * De-initializes the display power domain HW state. It also ensures that the 1994 * device stays powered up so that the driver can be reloaded. 1995 * 1996 * It must be called with power domains already disabled (after a call to 1997 * intel_power_domains_disable()) and must be paired with 1998 * intel_power_domains_init_hw(). 1999 */ 2000 void intel_power_domains_driver_remove(struct intel_display *display) 2001 { 2002 struct ref_tracker *wakeref __maybe_unused = 2003 fetch_and_zero(&display->power.domains.init_wakeref); 2004 2005 /* Remove the refcount we took to keep power well support disabled. */ 2006 if (!display->params.disable_power_well) 2007 intel_display_power_put(display, POWER_DOMAIN_INIT, 2008 fetch_and_zero(&display->power.domains.disable_wakeref)); 2009 2010 intel_display_power_flush_work_sync(display); 2011 2012 intel_power_domains_verify_state(display); 2013 2014 /* Keep the power well enabled, but cancel its rpm wakeref. */ 2015 intel_display_rpm_put(display, wakeref); 2016 } 2017 2018 /** 2019 * intel_power_domains_sanitize_state - sanitize power domains state 2020 * @display: display device instance 2021 * 2022 * Sanitize the power domains state during driver loading and system resume. 2023 * The function will disable all display power wells that BIOS has enabled 2024 * without a user for it (any user for a power well has taken a reference 2025 * on it by the time this function is called, after the state of all the 2026 * pipe, encoder, etc. HW resources have been sanitized). 2027 */ 2028 void intel_power_domains_sanitize_state(struct intel_display *display) 2029 { 2030 struct i915_power_domains *power_domains = &display->power.domains; 2031 struct i915_power_well *power_well; 2032 2033 mutex_lock(&power_domains->lock); 2034 2035 for_each_power_well_reverse(display, power_well) { 2036 if (power_well->desc->always_on || power_well->count || 2037 !intel_power_well_is_enabled(display, power_well)) 2038 continue; 2039 2040 drm_dbg_kms(display->drm, 2041 "BIOS left unused %s power well enabled, disabling it\n", 2042 intel_power_well_name(power_well)); 2043 intel_power_well_disable(display, power_well); 2044 } 2045 2046 mutex_unlock(&power_domains->lock); 2047 } 2048 2049 /** 2050 * intel_power_domains_enable - enable toggling of display power wells 2051 * @display: display device instance 2052 * 2053 * Enable the ondemand enabling/disabling of the display power wells. Note that 2054 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled 2055 * only at specific points of the display modeset sequence, thus they are not 2056 * affected by the intel_power_domains_enable()/disable() calls. The purpose 2057 * of these function is to keep the rest of power wells enabled until the end 2058 * of display HW readout (which will acquire the power references reflecting 2059 * the current HW state). 2060 */ 2061 void intel_power_domains_enable(struct intel_display *display) 2062 { 2063 struct ref_tracker *wakeref __maybe_unused = 2064 fetch_and_zero(&display->power.domains.init_wakeref); 2065 2066 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 2067 intel_power_domains_verify_state(display); 2068 } 2069 2070 /** 2071 * intel_power_domains_disable - disable toggling of display power wells 2072 * @display: display device instance 2073 * 2074 * Disable the ondemand enabling/disabling of the display power wells. See 2075 * intel_power_domains_enable() for which power wells this call controls. 2076 */ 2077 void intel_power_domains_disable(struct intel_display *display) 2078 { 2079 struct i915_power_domains *power_domains = &display->power.domains; 2080 2081 drm_WARN_ON(display->drm, power_domains->init_wakeref); 2082 power_domains->init_wakeref = 2083 intel_display_power_get(display, POWER_DOMAIN_INIT); 2084 2085 intel_power_domains_verify_state(display); 2086 } 2087 2088 /** 2089 * intel_power_domains_suspend - suspend power domain state 2090 * @display: display device instance 2091 * @s2idle: specifies whether we go to idle, or deeper sleep 2092 * 2093 * This function prepares the hardware power domain state before entering 2094 * system suspend. 2095 * 2096 * It must be called with power domains already disabled (after a call to 2097 * intel_power_domains_disable()) and paired with intel_power_domains_resume(). 2098 */ 2099 void intel_power_domains_suspend(struct intel_display *display, bool s2idle) 2100 { 2101 struct i915_power_domains *power_domains = &display->power.domains; 2102 struct ref_tracker *wakeref __maybe_unused = 2103 fetch_and_zero(&power_domains->init_wakeref); 2104 2105 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 2106 2107 /* 2108 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 2109 * support don't manually deinit the power domains. This also means the 2110 * DMC firmware will stay active, it will power down any HW 2111 * resources as required and also enable deeper system power states 2112 * that would be blocked if the firmware was inactive. 2113 */ 2114 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle && 2115 intel_dmc_has_payload(display)) { 2116 intel_display_power_flush_work(display); 2117 intel_power_domains_verify_state(display); 2118 return; 2119 } 2120 2121 /* 2122 * Even if power well support was disabled we still want to disable 2123 * power wells if power domains must be deinitialized for suspend. 2124 */ 2125 if (!display->params.disable_power_well) 2126 intel_display_power_put(display, POWER_DOMAIN_INIT, 2127 fetch_and_zero(&display->power.domains.disable_wakeref)); 2128 2129 intel_display_power_flush_work(display); 2130 intel_power_domains_verify_state(display); 2131 2132 if (DISPLAY_VER(display) >= 11) 2133 icl_display_core_uninit(display); 2134 else if (display->platform.geminilake || display->platform.broxton) 2135 bxt_display_core_uninit(display); 2136 else if (DISPLAY_VER(display) == 9) 2137 skl_display_core_uninit(display); 2138 2139 power_domains->display_core_suspended = true; 2140 } 2141 2142 /** 2143 * intel_power_domains_resume - resume power domain state 2144 * @display: display device instance 2145 * 2146 * This function resume the hardware power domain state during system resume. 2147 * 2148 * It will return with power domain support disabled (to be enabled later by 2149 * intel_power_domains_enable()) and must be paired with 2150 * intel_power_domains_suspend(). 2151 */ 2152 void intel_power_domains_resume(struct intel_display *display) 2153 { 2154 struct i915_power_domains *power_domains = &display->power.domains; 2155 2156 if (power_domains->display_core_suspended) { 2157 intel_power_domains_init_hw(display, true); 2158 power_domains->display_core_suspended = false; 2159 } else { 2160 drm_WARN_ON(display->drm, power_domains->init_wakeref); 2161 power_domains->init_wakeref = 2162 intel_display_power_get(display, POWER_DOMAIN_INIT); 2163 } 2164 } 2165 2166 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 2167 2168 static void intel_power_domains_dump_info(struct intel_display *display) 2169 { 2170 struct i915_power_domains *power_domains = &display->power.domains; 2171 struct i915_power_well *power_well; 2172 2173 for_each_power_well(display, power_well) { 2174 enum intel_display_power_domain domain; 2175 2176 drm_dbg_kms(display->drm, "%-25s %d\n", 2177 intel_power_well_name(power_well), intel_power_well_refcount(power_well)); 2178 2179 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2180 drm_dbg_kms(display->drm, " %-23s %d\n", 2181 intel_display_power_domain_str(domain), 2182 power_domains->domain_use_count[domain]); 2183 } 2184 } 2185 2186 /** 2187 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 2188 * @display: display device instance 2189 * 2190 * Verify if the reference count of each power well matches its HW enabled 2191 * state and the total refcount of the domains it belongs to. This must be 2192 * called after modeset HW state sanitization, which is responsible for 2193 * acquiring reference counts for any power wells in use and disabling the 2194 * ones left on by BIOS but not required by any active output. 2195 */ 2196 static void intel_power_domains_verify_state(struct intel_display *display) 2197 { 2198 struct i915_power_domains *power_domains = &display->power.domains; 2199 struct i915_power_well *power_well; 2200 bool dump_domain_info; 2201 2202 mutex_lock(&power_domains->lock); 2203 2204 verify_async_put_domains_state(power_domains); 2205 2206 dump_domain_info = false; 2207 for_each_power_well(display, power_well) { 2208 enum intel_display_power_domain domain; 2209 int domains_count; 2210 bool enabled; 2211 2212 enabled = intel_power_well_is_enabled(display, power_well); 2213 if ((intel_power_well_refcount(power_well) || 2214 intel_power_well_is_always_on(power_well)) != 2215 enabled) 2216 drm_err(display->drm, 2217 "power well %s state mismatch (refcount %d/enabled %d)", 2218 intel_power_well_name(power_well), 2219 intel_power_well_refcount(power_well), enabled); 2220 2221 domains_count = 0; 2222 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2223 domains_count += power_domains->domain_use_count[domain]; 2224 2225 if (intel_power_well_refcount(power_well) != domains_count) { 2226 drm_err(display->drm, 2227 "power well %s refcount/domain refcount mismatch " 2228 "(refcount %d/domains refcount %d)\n", 2229 intel_power_well_name(power_well), 2230 intel_power_well_refcount(power_well), 2231 domains_count); 2232 dump_domain_info = true; 2233 } 2234 } 2235 2236 if (dump_domain_info) { 2237 static bool dumped; 2238 2239 if (!dumped) { 2240 intel_power_domains_dump_info(display); 2241 dumped = true; 2242 } 2243 } 2244 2245 mutex_unlock(&power_domains->lock); 2246 } 2247 2248 #else 2249 2250 static void intel_power_domains_verify_state(struct intel_display *display) 2251 { 2252 } 2253 2254 #endif 2255 2256 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle) 2257 { 2258 intel_power_domains_suspend(display, s2idle); 2259 2260 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || 2261 display->platform.broxton) { 2262 bxt_enable_dc9(display); 2263 } else if (display->platform.haswell || display->platform.broadwell) { 2264 hsw_enable_pc8(display); 2265 } 2266 2267 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2268 if (intel_display_wa(display, INTEL_DISPLAY_WA_14010685332)) 2269 intel_de_rmw(display, SOUTH_CHICKEN1, 2270 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); 2271 } 2272 2273 void intel_display_power_resume_early(struct intel_display *display) 2274 { 2275 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || 2276 display->platform.broxton) { 2277 gen9_sanitize_dc_state(display); 2278 bxt_disable_dc9(display); 2279 } else if (display->platform.haswell || display->platform.broadwell) { 2280 hsw_disable_pc8(display); 2281 } 2282 2283 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2284 if (intel_display_wa(display, INTEL_DISPLAY_WA_14010685332)) 2285 intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); 2286 2287 intel_power_domains_resume(display); 2288 } 2289 2290 void intel_display_power_suspend(struct intel_display *display) 2291 { 2292 if (DISPLAY_VER(display) >= 11) { 2293 icl_display_core_uninit(display); 2294 bxt_enable_dc9(display); 2295 } else if (display->platform.geminilake || display->platform.broxton) { 2296 bxt_display_core_uninit(display); 2297 bxt_enable_dc9(display); 2298 } else if (display->platform.haswell || display->platform.broadwell) { 2299 hsw_enable_pc8(display); 2300 } 2301 } 2302 2303 void intel_display_power_resume(struct intel_display *display) 2304 { 2305 struct i915_power_domains *power_domains = &display->power.domains; 2306 2307 if (DISPLAY_VER(display) >= 11) { 2308 bxt_disable_dc9(display); 2309 icl_display_core_init(display, true); 2310 if (intel_dmc_has_payload(display)) { 2311 if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 2312 skl_enable_dc6(display); 2313 else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 2314 gen9_enable_dc5(display); 2315 } 2316 } else if (display->platform.geminilake || display->platform.broxton) { 2317 bxt_disable_dc9(display); 2318 bxt_display_core_init(display, true); 2319 if (intel_dmc_has_payload(display) && 2320 (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) 2321 gen9_enable_dc5(display); 2322 } else if (display->platform.haswell || display->platform.broadwell) { 2323 hsw_disable_pc8(display); 2324 } 2325 } 2326 2327 void intel_display_power_debug(struct intel_display *display, struct seq_file *m) 2328 { 2329 struct i915_power_domains *power_domains = &display->power.domains; 2330 int i; 2331 2332 mutex_lock(&power_domains->lock); 2333 2334 seq_printf(m, "Runtime power status: %s\n", 2335 str_enabled_disabled(!power_domains->init_wakeref)); 2336 2337 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); 2338 for (i = 0; i < power_domains->power_well_count; i++) { 2339 struct i915_power_well *power_well; 2340 enum intel_display_power_domain power_domain; 2341 2342 power_well = &power_domains->power_wells[i]; 2343 seq_printf(m, "%-25s %d\n", intel_power_well_name(power_well), 2344 intel_power_well_refcount(power_well)); 2345 2346 for_each_power_domain(power_domain, intel_power_well_domains(power_well)) 2347 seq_printf(m, " %-23s %d\n", 2348 intel_display_power_domain_str(power_domain), 2349 power_domains->domain_use_count[power_domain]); 2350 } 2351 2352 mutex_unlock(&power_domains->lock); 2353 } 2354 2355 struct intel_ddi_port_domains { 2356 enum port port_start; 2357 enum port port_end; 2358 enum aux_ch aux_ch_start; 2359 enum aux_ch aux_ch_end; 2360 2361 enum intel_display_power_domain ddi_lanes; 2362 enum intel_display_power_domain ddi_io; 2363 enum intel_display_power_domain aux_io; 2364 enum intel_display_power_domain aux_legacy_usbc; 2365 enum intel_display_power_domain aux_tbt; 2366 }; 2367 2368 static const struct intel_ddi_port_domains 2369 i9xx_port_domains[] = { 2370 { 2371 .port_start = PORT_A, 2372 .port_end = PORT_F, 2373 .aux_ch_start = AUX_CH_A, 2374 .aux_ch_end = AUX_CH_F, 2375 2376 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2377 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2378 .aux_io = POWER_DOMAIN_AUX_IO_A, 2379 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2380 .aux_tbt = POWER_DOMAIN_INVALID, 2381 }, 2382 }; 2383 2384 static const struct intel_ddi_port_domains 2385 d11_port_domains[] = { 2386 { 2387 .port_start = PORT_A, 2388 .port_end = PORT_B, 2389 .aux_ch_start = AUX_CH_A, 2390 .aux_ch_end = AUX_CH_B, 2391 2392 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2393 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2394 .aux_io = POWER_DOMAIN_AUX_IO_A, 2395 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2396 .aux_tbt = POWER_DOMAIN_INVALID, 2397 }, { 2398 .port_start = PORT_C, 2399 .port_end = PORT_F, 2400 .aux_ch_start = AUX_CH_C, 2401 .aux_ch_end = AUX_CH_F, 2402 2403 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C, 2404 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C, 2405 .aux_io = POWER_DOMAIN_AUX_IO_C, 2406 .aux_legacy_usbc = POWER_DOMAIN_AUX_C, 2407 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2408 }, 2409 }; 2410 2411 static const struct intel_ddi_port_domains 2412 d12_port_domains[] = { 2413 { 2414 .port_start = PORT_A, 2415 .port_end = PORT_C, 2416 .aux_ch_start = AUX_CH_A, 2417 .aux_ch_end = AUX_CH_C, 2418 2419 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2420 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2421 .aux_io = POWER_DOMAIN_AUX_IO_A, 2422 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2423 .aux_tbt = POWER_DOMAIN_INVALID, 2424 }, { 2425 .port_start = PORT_TC1, 2426 .port_end = PORT_TC6, 2427 .aux_ch_start = AUX_CH_USBC1, 2428 .aux_ch_end = AUX_CH_USBC6, 2429 2430 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2431 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2432 .aux_io = POWER_DOMAIN_INVALID, 2433 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2434 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2435 }, 2436 }; 2437 2438 static const struct intel_ddi_port_domains 2439 d13_port_domains[] = { 2440 { 2441 .port_start = PORT_A, 2442 .port_end = PORT_C, 2443 .aux_ch_start = AUX_CH_A, 2444 .aux_ch_end = AUX_CH_C, 2445 2446 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2447 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2448 .aux_io = POWER_DOMAIN_AUX_IO_A, 2449 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2450 .aux_tbt = POWER_DOMAIN_INVALID, 2451 }, { 2452 .port_start = PORT_TC1, 2453 .port_end = PORT_TC4, 2454 .aux_ch_start = AUX_CH_USBC1, 2455 .aux_ch_end = AUX_CH_USBC4, 2456 2457 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2458 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2459 .aux_io = POWER_DOMAIN_INVALID, 2460 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2461 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2462 }, { 2463 .port_start = PORT_D_XELPD, 2464 .port_end = PORT_E_XELPD, 2465 .aux_ch_start = AUX_CH_D_XELPD, 2466 .aux_ch_end = AUX_CH_E_XELPD, 2467 2468 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D, 2469 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D, 2470 .aux_io = POWER_DOMAIN_AUX_IO_D, 2471 .aux_legacy_usbc = POWER_DOMAIN_AUX_D, 2472 .aux_tbt = POWER_DOMAIN_INVALID, 2473 }, 2474 }; 2475 2476 static void 2477 intel_port_domains_for_platform(struct intel_display *display, 2478 const struct intel_ddi_port_domains **domains, 2479 int *domains_size) 2480 { 2481 if (DISPLAY_VER(display) >= 13) { 2482 *domains = d13_port_domains; 2483 *domains_size = ARRAY_SIZE(d13_port_domains); 2484 } else if (DISPLAY_VER(display) >= 12) { 2485 *domains = d12_port_domains; 2486 *domains_size = ARRAY_SIZE(d12_port_domains); 2487 } else if (DISPLAY_VER(display) >= 11) { 2488 *domains = d11_port_domains; 2489 *domains_size = ARRAY_SIZE(d11_port_domains); 2490 } else { 2491 *domains = i9xx_port_domains; 2492 *domains_size = ARRAY_SIZE(i9xx_port_domains); 2493 } 2494 } 2495 2496 static const struct intel_ddi_port_domains * 2497 intel_port_domains_for_port(struct intel_display *display, enum port port) 2498 { 2499 const struct intel_ddi_port_domains *domains; 2500 int domains_size; 2501 int i; 2502 2503 intel_port_domains_for_platform(display, &domains, &domains_size); 2504 for (i = 0; i < domains_size; i++) 2505 if (port >= domains[i].port_start && port <= domains[i].port_end) 2506 return &domains[i]; 2507 2508 return NULL; 2509 } 2510 2511 enum intel_display_power_domain 2512 intel_display_power_ddi_io_domain(struct intel_display *display, enum port port) 2513 { 2514 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); 2515 2516 if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) 2517 return POWER_DOMAIN_PORT_DDI_IO_A; 2518 2519 return domains->ddi_io + (int)(port - domains->port_start); 2520 } 2521 2522 enum intel_display_power_domain 2523 intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port) 2524 { 2525 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); 2526 2527 if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) 2528 return POWER_DOMAIN_PORT_DDI_LANES_A; 2529 2530 return domains->ddi_lanes + (int)(port - domains->port_start); 2531 } 2532 2533 static const struct intel_ddi_port_domains * 2534 intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch) 2535 { 2536 const struct intel_ddi_port_domains *domains; 2537 int domains_size; 2538 int i; 2539 2540 intel_port_domains_for_platform(display, &domains, &domains_size); 2541 for (i = 0; i < domains_size; i++) 2542 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end) 2543 return &domains[i]; 2544 2545 return NULL; 2546 } 2547 2548 enum intel_display_power_domain 2549 intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch) 2550 { 2551 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2552 2553 if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) 2554 return POWER_DOMAIN_AUX_IO_A; 2555 2556 return domains->aux_io + (int)(aux_ch - domains->aux_ch_start); 2557 } 2558 2559 enum intel_display_power_domain 2560 intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch) 2561 { 2562 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2563 2564 if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) 2565 return POWER_DOMAIN_AUX_A; 2566 2567 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start); 2568 } 2569 2570 enum intel_display_power_domain 2571 intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch) 2572 { 2573 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2574 2575 if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) 2576 return POWER_DOMAIN_AUX_TBT1; 2577 2578 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start); 2579 } 2580