1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/iopoll.h> 7 #include <linux/string_helpers.h> 8 9 #include <drm/drm_print.h> 10 #include <drm/intel/intel_pcode_regs.h> 11 #include <drm/intel/step.h> 12 13 #include "intel_backlight_regs.h" 14 #include "intel_cdclk.h" 15 #include "intel_clock_gating.h" 16 #include "intel_combo_phy.h" 17 #include "intel_crtc.h" 18 #include "intel_de.h" 19 #include "intel_display.h" 20 #include "intel_display_power.h" 21 #include "intel_display_power_map.h" 22 #include "intel_display_power_well.h" 23 #include "intel_display_regs.h" 24 #include "intel_display_rpm.h" 25 #include "intel_display_types.h" 26 #include "intel_display_utils.h" 27 #include "intel_display_wa.h" 28 #include "intel_dmc.h" 29 #include "intel_dram.h" 30 #include "intel_mchbar.h" 31 #include "intel_parent.h" 32 #include "intel_pch_refclk.h" 33 #include "intel_pmdemand.h" 34 #include "intel_pps_regs.h" 35 #include "intel_psr.h" 36 #include "intel_psr_regs.h" 37 #include "intel_snps_phy.h" 38 #include "skl_watermark.h" 39 #include "skl_watermark_regs.h" 40 #include "vlv_sideband.h" 41 42 #define for_each_power_domain_well(__display, __power_well, __domain) \ 43 for_each_power_well((__display), __power_well) \ 44 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 45 46 #define for_each_power_domain_well_reverse(__display, __power_well, __domain) \ 47 for_each_power_well_reverse((__display), __power_well) \ 48 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 49 50 static const char * 51 intel_display_power_domain_str(enum intel_display_power_domain domain) 52 { 53 switch (domain) { 54 case POWER_DOMAIN_DISPLAY_CORE: 55 return "DISPLAY_CORE"; 56 case POWER_DOMAIN_PIPE_A: 57 return "PIPE_A"; 58 case POWER_DOMAIN_PIPE_B: 59 return "PIPE_B"; 60 case POWER_DOMAIN_PIPE_C: 61 return "PIPE_C"; 62 case POWER_DOMAIN_PIPE_D: 63 return "PIPE_D"; 64 case POWER_DOMAIN_PIPE_PANEL_FITTER_A: 65 return "PIPE_PANEL_FITTER_A"; 66 case POWER_DOMAIN_PIPE_PANEL_FITTER_B: 67 return "PIPE_PANEL_FITTER_B"; 68 case POWER_DOMAIN_PIPE_PANEL_FITTER_C: 69 return "PIPE_PANEL_FITTER_C"; 70 case POWER_DOMAIN_PIPE_PANEL_FITTER_D: 71 return "PIPE_PANEL_FITTER_D"; 72 case POWER_DOMAIN_TRANSCODER_A: 73 return "TRANSCODER_A"; 74 case POWER_DOMAIN_TRANSCODER_B: 75 return "TRANSCODER_B"; 76 case POWER_DOMAIN_TRANSCODER_C: 77 return "TRANSCODER_C"; 78 case POWER_DOMAIN_TRANSCODER_D: 79 return "TRANSCODER_D"; 80 case POWER_DOMAIN_TRANSCODER_EDP: 81 return "TRANSCODER_EDP"; 82 case POWER_DOMAIN_TRANSCODER_DSI_A: 83 return "TRANSCODER_DSI_A"; 84 case POWER_DOMAIN_TRANSCODER_DSI_C: 85 return "TRANSCODER_DSI_C"; 86 case POWER_DOMAIN_TRANSCODER_VDSC_PW2: 87 return "TRANSCODER_VDSC_PW2"; 88 case POWER_DOMAIN_PORT_DDI_LANES_A: 89 return "PORT_DDI_LANES_A"; 90 case POWER_DOMAIN_PORT_DDI_LANES_B: 91 return "PORT_DDI_LANES_B"; 92 case POWER_DOMAIN_PORT_DDI_LANES_C: 93 return "PORT_DDI_LANES_C"; 94 case POWER_DOMAIN_PORT_DDI_LANES_D: 95 return "PORT_DDI_LANES_D"; 96 case POWER_DOMAIN_PORT_DDI_LANES_E: 97 return "PORT_DDI_LANES_E"; 98 case POWER_DOMAIN_PORT_DDI_LANES_F: 99 return "PORT_DDI_LANES_F"; 100 case POWER_DOMAIN_PORT_DDI_LANES_TC1: 101 return "PORT_DDI_LANES_TC1"; 102 case POWER_DOMAIN_PORT_DDI_LANES_TC2: 103 return "PORT_DDI_LANES_TC2"; 104 case POWER_DOMAIN_PORT_DDI_LANES_TC3: 105 return "PORT_DDI_LANES_TC3"; 106 case POWER_DOMAIN_PORT_DDI_LANES_TC4: 107 return "PORT_DDI_LANES_TC4"; 108 case POWER_DOMAIN_PORT_DDI_LANES_TC5: 109 return "PORT_DDI_LANES_TC5"; 110 case POWER_DOMAIN_PORT_DDI_LANES_TC6: 111 return "PORT_DDI_LANES_TC6"; 112 case POWER_DOMAIN_PORT_DDI_IO_A: 113 return "PORT_DDI_IO_A"; 114 case POWER_DOMAIN_PORT_DDI_IO_B: 115 return "PORT_DDI_IO_B"; 116 case POWER_DOMAIN_PORT_DDI_IO_C: 117 return "PORT_DDI_IO_C"; 118 case POWER_DOMAIN_PORT_DDI_IO_D: 119 return "PORT_DDI_IO_D"; 120 case POWER_DOMAIN_PORT_DDI_IO_E: 121 return "PORT_DDI_IO_E"; 122 case POWER_DOMAIN_PORT_DDI_IO_F: 123 return "PORT_DDI_IO_F"; 124 case POWER_DOMAIN_PORT_DDI_IO_TC1: 125 return "PORT_DDI_IO_TC1"; 126 case POWER_DOMAIN_PORT_DDI_IO_TC2: 127 return "PORT_DDI_IO_TC2"; 128 case POWER_DOMAIN_PORT_DDI_IO_TC3: 129 return "PORT_DDI_IO_TC3"; 130 case POWER_DOMAIN_PORT_DDI_IO_TC4: 131 return "PORT_DDI_IO_TC4"; 132 case POWER_DOMAIN_PORT_DDI_IO_TC5: 133 return "PORT_DDI_IO_TC5"; 134 case POWER_DOMAIN_PORT_DDI_IO_TC6: 135 return "PORT_DDI_IO_TC6"; 136 case POWER_DOMAIN_PORT_DSI: 137 return "PORT_DSI"; 138 case POWER_DOMAIN_PORT_CRT: 139 return "PORT_CRT"; 140 case POWER_DOMAIN_PORT_OTHER: 141 return "PORT_OTHER"; 142 case POWER_DOMAIN_VGA: 143 return "VGA"; 144 case POWER_DOMAIN_AUDIO_MMIO: 145 return "AUDIO_MMIO"; 146 case POWER_DOMAIN_AUDIO_PLAYBACK: 147 return "AUDIO_PLAYBACK"; 148 case POWER_DOMAIN_AUX_IO_A: 149 return "AUX_IO_A"; 150 case POWER_DOMAIN_AUX_IO_B: 151 return "AUX_IO_B"; 152 case POWER_DOMAIN_AUX_IO_C: 153 return "AUX_IO_C"; 154 case POWER_DOMAIN_AUX_IO_D: 155 return "AUX_IO_D"; 156 case POWER_DOMAIN_AUX_IO_E: 157 return "AUX_IO_E"; 158 case POWER_DOMAIN_AUX_IO_F: 159 return "AUX_IO_F"; 160 case POWER_DOMAIN_AUX_A: 161 return "AUX_A"; 162 case POWER_DOMAIN_AUX_B: 163 return "AUX_B"; 164 case POWER_DOMAIN_AUX_C: 165 return "AUX_C"; 166 case POWER_DOMAIN_AUX_D: 167 return "AUX_D"; 168 case POWER_DOMAIN_AUX_E: 169 return "AUX_E"; 170 case POWER_DOMAIN_AUX_F: 171 return "AUX_F"; 172 case POWER_DOMAIN_AUX_USBC1: 173 return "AUX_USBC1"; 174 case POWER_DOMAIN_AUX_USBC2: 175 return "AUX_USBC2"; 176 case POWER_DOMAIN_AUX_USBC3: 177 return "AUX_USBC3"; 178 case POWER_DOMAIN_AUX_USBC4: 179 return "AUX_USBC4"; 180 case POWER_DOMAIN_AUX_USBC5: 181 return "AUX_USBC5"; 182 case POWER_DOMAIN_AUX_USBC6: 183 return "AUX_USBC6"; 184 case POWER_DOMAIN_AUX_TBT1: 185 return "AUX_TBT1"; 186 case POWER_DOMAIN_AUX_TBT2: 187 return "AUX_TBT2"; 188 case POWER_DOMAIN_AUX_TBT3: 189 return "AUX_TBT3"; 190 case POWER_DOMAIN_AUX_TBT4: 191 return "AUX_TBT4"; 192 case POWER_DOMAIN_AUX_TBT5: 193 return "AUX_TBT5"; 194 case POWER_DOMAIN_AUX_TBT6: 195 return "AUX_TBT6"; 196 case POWER_DOMAIN_GMBUS: 197 return "GMBUS"; 198 case POWER_DOMAIN_INIT: 199 return "INIT"; 200 case POWER_DOMAIN_GT_IRQ: 201 return "GT_IRQ"; 202 case POWER_DOMAIN_DC_OFF: 203 return "DC_OFF"; 204 case POWER_DOMAIN_TC_COLD_OFF: 205 return "TC_COLD_OFF"; 206 default: 207 MISSING_CASE(domain); 208 return "?"; 209 } 210 } 211 212 static bool __intel_display_power_is_enabled(struct intel_display *display, 213 enum intel_display_power_domain domain) 214 { 215 struct i915_power_well *power_well; 216 bool is_enabled; 217 218 if (intel_display_rpm_suspended(display)) 219 return false; 220 221 is_enabled = true; 222 223 for_each_power_domain_well_reverse(display, power_well, domain) { 224 if (intel_power_well_is_always_on(power_well)) 225 continue; 226 227 if (!intel_power_well_is_enabled_cached(power_well)) { 228 is_enabled = false; 229 break; 230 } 231 } 232 233 return is_enabled; 234 } 235 236 /** 237 * intel_display_power_is_enabled - check for a power domain 238 * @display: display device instance 239 * @domain: power domain to check 240 * 241 * This function can be used to check the hw power domain state. It is mostly 242 * used in hardware state readout functions. Everywhere else code should rely 243 * upon explicit power domain reference counting to ensure that the hardware 244 * block is powered up before accessing it. 245 * 246 * Callers must hold the relevant modesetting locks to ensure that concurrent 247 * threads can't disable the power well while the caller tries to read a few 248 * registers. 249 * 250 * Returns: 251 * True when the power domain is enabled, false otherwise. 252 */ 253 bool intel_display_power_is_enabled(struct intel_display *display, 254 enum intel_display_power_domain domain) 255 { 256 struct i915_power_domains *power_domains = &display->power.domains; 257 bool ret; 258 259 mutex_lock(&power_domains->lock); 260 ret = __intel_display_power_is_enabled(display, domain); 261 mutex_unlock(&power_domains->lock); 262 263 return ret; 264 } 265 266 static u32 267 sanitize_target_dc_state(struct intel_display *display, 268 u32 target_dc_state) 269 { 270 struct i915_power_domains *power_domains = &display->power.domains; 271 static const u32 states[] = { 272 DC_STATE_EN_UPTO_DC6, 273 DC_STATE_EN_UPTO_DC5, 274 DC_STATE_EN_UPTO_DC3CO, 275 DC_STATE_DISABLE, 276 }; 277 int i; 278 279 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { 280 if (target_dc_state != states[i]) 281 continue; 282 283 if (power_domains->allowed_dc_mask & target_dc_state) 284 break; 285 286 target_dc_state = states[i + 1]; 287 } 288 289 return target_dc_state; 290 } 291 292 bool intel_display_power_get_and_reset_dc3co_to_dc6(struct intel_display *display) 293 { 294 struct i915_power_domains *power_domains = &display->power.domains; 295 bool ret; 296 297 mutex_lock(&power_domains->lock); 298 ret = power_domains->dc3co_to_dc6; 299 power_domains->dc3co_to_dc6 = false; 300 mutex_unlock(&power_domains->lock); 301 302 return ret; 303 } 304 305 /** 306 * intel_display_power_set_target_dc_state - Set target dc state. 307 * @display: display device 308 * @state: state which needs to be set as target_dc_state. 309 * 310 * This function set the "DC off" power well target_dc_state, 311 * based upon this target_dc_stste, "DC off" power well will 312 * enable desired DC state. 313 */ 314 void intel_display_power_set_target_dc_state(struct intel_display *display, 315 u32 state) 316 { 317 struct i915_power_well *power_well; 318 bool dc_off_enabled; 319 struct i915_power_domains *power_domains = &display->power.domains; 320 u32 old_target_dc_state; 321 322 mutex_lock(&power_domains->lock); 323 power_well = lookup_power_well(display, SKL_DISP_DC_OFF); 324 325 if (drm_WARN_ON(display->drm, !power_well)) 326 goto unlock; 327 328 state = sanitize_target_dc_state(display, state); 329 330 if (state == power_domains->target_dc_state) 331 goto unlock; 332 333 dc_off_enabled = intel_power_well_is_enabled(display, power_well); 334 /* 335 * If DC off power well is disabled, need to enable and disable the 336 * DC off power well to effect target DC state. 337 */ 338 if (!dc_off_enabled) 339 intel_power_well_enable(display, power_well); 340 341 old_target_dc_state = power_domains->target_dc_state; 342 power_domains->target_dc_state = state; 343 344 /* 345 * CMTG must be restored explicitly after DC6 exit. The dc3co_to_dc6 346 * flag helps CMTG determine whether restoration is required. 347 */ 348 if (old_target_dc_state == DC_STATE_EN_UPTO_DC3CO && 349 power_domains->target_dc_state == DC_STATE_EN_UPTO_DC6) 350 power_domains->dc3co_to_dc6 = true; 351 352 if (!dc_off_enabled) 353 intel_power_well_disable(display, power_well); 354 355 unlock: 356 mutex_unlock(&power_domains->lock); 357 } 358 359 /** 360 * intel_display_power_get_current_dc_state - Set target dc state. 361 * @display: display device 362 * 363 * This function set the "DC off" power well target_dc_state, 364 * based upon this target_dc_stste, "DC off" power well will 365 * enable desired DC state. 366 */ 367 u32 intel_display_power_get_current_dc_state(struct intel_display *display) 368 { 369 struct i915_power_well *power_well; 370 struct i915_power_domains *power_domains = &display->power.domains; 371 u32 current_dc_state = DC_STATE_DISABLE; 372 373 mutex_lock(&power_domains->lock); 374 power_well = lookup_power_well(display, SKL_DISP_DC_OFF); 375 376 if (drm_WARN_ON(display->drm, !power_well)) 377 goto unlock; 378 379 current_dc_state = intel_power_well_is_enabled(display, power_well) ? 380 DC_STATE_DISABLE : power_domains->target_dc_state; 381 382 unlock: 383 mutex_unlock(&power_domains->lock); 384 385 return current_dc_state; 386 } 387 388 bool intel_display_power_dc3co_supported(struct intel_display *display) 389 { 390 struct i915_power_domains *power_domains = &display->power.domains; 391 392 if (!HAS_DC3CO(display)) 393 return false; 394 395 return (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO; 396 } 397 398 bool intel_display_power_dc3co_allowed(struct intel_display *display) 399 { 400 struct intel_dc3co_state *dc3co = &display->power.dc3co; 401 bool allowed; 402 403 if (!intel_display_power_dc3co_supported(display)) 404 return false; 405 406 mutex_lock(&dc3co->lock); 407 allowed = dc3co->allowed; 408 mutex_unlock(&dc3co->lock); 409 410 return allowed; 411 } 412 413 void intel_display_power_dc3co_update(struct intel_display *display, u32 trigger) 414 { 415 struct intel_dc3co_state *dc3co = &display->power.dc3co; 416 417 if (!intel_display_power_dc3co_supported(display)) 418 return; 419 420 mutex_lock(&dc3co->lock); 421 dc3co->trigger = trigger; 422 dc3co->allowed = !!trigger; 423 mutex_unlock(&dc3co->lock); 424 } 425 426 static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp, 427 const struct intel_crtc_state *crtc_state) 428 { 429 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 430 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 431 enum port port = dig_port->base.port; 432 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 433 434 /* Need to follow 1:1 mapping because of CMTG restriction */ 435 if (DISPLAY_VER(to_intel_display(crtc_state)) == 35) 436 return num_pipes == 1 && 437 ((pipe == PIPE_A && port == PORT_A) || 438 (pipe == PIPE_B && port == PORT_B)); 439 else 440 return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B; 441 } 442 443 void intel_display_power_dc3co_compute(struct intel_atomic_state *state) 444 { 445 struct intel_display *display = to_intel_display(state); 446 struct intel_crtc *crtc; 447 struct intel_crtc_state *crtc_state; 448 struct intel_encoder *encoder; 449 struct intel_dp *intel_dp; 450 u8 active_pipes = 0; 451 enum pipe pipe; 452 u32 trigger = DC3CO_TRIGGER_NONE; 453 454 if (!intel_display_power_dc3co_supported(display)) 455 return; 456 457 for_each_intel_crtc(display, crtc) 458 active_pipes |= crtc->active ? BIT(crtc->pipe) : 0; 459 460 active_pipes = intel_calc_active_pipes(state, active_pipes); 461 462 if (hweight8(active_pipes) != 1) 463 goto done; 464 465 pipe = ffs(active_pipes) - 1; 466 crtc = intel_crtc_for_pipe(display, pipe); 467 468 crtc_state = to_intel_crtc_state(crtc->base.state); 469 470 for_each_intel_encoder_mask(display->drm, encoder, 471 crtc_state->uapi.encoder_mask) { 472 if (encoder->type != INTEL_OUTPUT_EDP) 473 goto done; 474 475 intel_dp = enc_to_intel_dp(encoder); 476 477 if (!intel_dc3co_port_pipe_compatible(intel_dp, crtc_state)) 478 goto done; 479 480 if (intel_psr2_in_deep_sleep(intel_dp)) 481 goto done; 482 } 483 484 if (crtc_state->has_lobf) 485 trigger |= DC3CO_TRIGGER_LOBF; 486 if (crtc_state->has_panel_replay && intel_dp->as_sdp_supported) 487 trigger |= DC3CO_TRIGGER_PANEL_REPLAY; 488 if (crtc_state->has_sel_update) 489 trigger |= DC3CO_TRIGGER_PSR2; 490 491 done: 492 intel_display_power_dc3co_update(display, trigger); 493 } 494 495 /* 496 * Select the target DC state for this commit and return the async-put delay 497 * to use when releasing the DC_OFF reference. 498 * 499 * Picks DC_STATE_EN_UPTO_DC3CO when DC3CO can be enabled 500 * otherwise falls back to default DC state of DC_STATE_EN_UPTO_DC6. 501 * The chosen target is programmed via intel_display_power_set_target_dc_state(). 502 * 503 * Returns the async-put delay (in ms) to use when releasing the DC_OFF 504 * reference: DC3CO_PUT_ASYNC_DELAY_MS when DC3CO was selected, otherwise 505 * DC6_PUT_ASYNC_DELAY_MS. 506 */ 507 int intel_display_power_select_target_dc_state(struct intel_atomic_state *state) 508 { 509 struct intel_display *display = to_intel_display(state); 510 u32 target_dc_state; 511 512 if (!intel_display_power_dc3co_supported(display)) 513 return DC6_PUT_ASYNC_DELAY_MS; 514 515 if (intel_display_power_dc3co_allowed(display)) 516 target_dc_state = DC_STATE_EN_UPTO_DC3CO; 517 else 518 target_dc_state = DC_STATE_EN_UPTO_DC6; 519 520 intel_display_power_set_target_dc_state(display, target_dc_state); 521 522 return target_dc_state == DC_STATE_EN_UPTO_DC3CO ? 523 DC3CO_PUT_ASYNC_DELAY_MS : DC6_PUT_ASYNC_DELAY_MS; 524 } 525 526 static void __async_put_domains_mask(struct i915_power_domains *power_domains, 527 struct intel_power_domain_mask *mask) 528 { 529 bitmap_or(mask->bits, 530 power_domains->async_put_domains[0].bits, 531 power_domains->async_put_domains[1].bits, 532 POWER_DOMAIN_NUM); 533 } 534 535 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 536 537 static bool 538 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 539 { 540 struct intel_display *display = container_of(power_domains, 541 struct intel_display, 542 power.domains); 543 544 return !drm_WARN_ON(display->drm, 545 bitmap_intersects(power_domains->async_put_domains[0].bits, 546 power_domains->async_put_domains[1].bits, 547 POWER_DOMAIN_NUM)); 548 } 549 550 static bool 551 __async_put_domains_state_ok(struct i915_power_domains *power_domains) 552 { 553 struct intel_display *display = container_of(power_domains, 554 struct intel_display, 555 power.domains); 556 struct intel_power_domain_mask async_put_mask; 557 enum intel_display_power_domain domain; 558 bool err = false; 559 560 err |= !assert_async_put_domain_masks_disjoint(power_domains); 561 __async_put_domains_mask(power_domains, &async_put_mask); 562 err |= drm_WARN_ON(display->drm, 563 !!power_domains->async_put_wakeref != 564 !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)); 565 566 for_each_power_domain(domain, &async_put_mask) 567 err |= drm_WARN_ON(display->drm, 568 power_domains->domain_use_count[domain] != 1); 569 570 return !err; 571 } 572 573 static void print_power_domains(struct i915_power_domains *power_domains, 574 const char *prefix, struct intel_power_domain_mask *mask) 575 { 576 struct intel_display *display = container_of(power_domains, 577 struct intel_display, 578 power.domains); 579 enum intel_display_power_domain domain; 580 581 drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); 582 for_each_power_domain(domain, mask) 583 drm_dbg_kms(display->drm, "%s use_count %d\n", 584 intel_display_power_domain_str(domain), 585 power_domains->domain_use_count[domain]); 586 } 587 588 static void 589 print_async_put_domains_state(struct i915_power_domains *power_domains) 590 { 591 struct intel_display *display = container_of(power_domains, 592 struct intel_display, 593 power.domains); 594 595 drm_dbg_kms(display->drm, "async_put_wakeref: %s\n", 596 str_yes_no(power_domains->async_put_wakeref)); 597 598 print_power_domains(power_domains, "async_put_domains[0]", 599 &power_domains->async_put_domains[0]); 600 print_power_domains(power_domains, "async_put_domains[1]", 601 &power_domains->async_put_domains[1]); 602 } 603 604 static void 605 verify_async_put_domains_state(struct i915_power_domains *power_domains) 606 { 607 if (!__async_put_domains_state_ok(power_domains)) 608 print_async_put_domains_state(power_domains); 609 } 610 611 #else 612 613 static void 614 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 615 { 616 } 617 618 static void 619 verify_async_put_domains_state(struct i915_power_domains *power_domains) 620 { 621 } 622 623 #endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */ 624 625 static void async_put_domains_mask(struct i915_power_domains *power_domains, 626 struct intel_power_domain_mask *mask) 627 628 { 629 assert_async_put_domain_masks_disjoint(power_domains); 630 631 __async_put_domains_mask(power_domains, mask); 632 } 633 634 static void 635 async_put_domains_clear_domain(struct i915_power_domains *power_domains, 636 enum intel_display_power_domain domain) 637 { 638 assert_async_put_domain_masks_disjoint(power_domains); 639 640 clear_bit(domain, power_domains->async_put_domains[0].bits); 641 clear_bit(domain, power_domains->async_put_domains[1].bits); 642 } 643 644 static void 645 cancel_async_put_work(struct i915_power_domains *power_domains, bool sync) 646 { 647 if (sync) 648 cancel_delayed_work_sync(&power_domains->async_put_work); 649 else 650 cancel_delayed_work(&power_domains->async_put_work); 651 652 power_domains->async_put_next_delay = 0; 653 } 654 655 static bool 656 intel_display_power_grab_async_put_ref(struct intel_display *display, 657 enum intel_display_power_domain domain) 658 { 659 struct i915_power_domains *power_domains = &display->power.domains; 660 struct intel_power_domain_mask async_put_mask; 661 bool ret = false; 662 663 async_put_domains_mask(power_domains, &async_put_mask); 664 if (!test_bit(domain, async_put_mask.bits)) 665 goto out_verify; 666 667 async_put_domains_clear_domain(power_domains, domain); 668 669 ret = true; 670 671 async_put_domains_mask(power_domains, &async_put_mask); 672 if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)) 673 goto out_verify; 674 675 cancel_async_put_work(power_domains, false); 676 intel_display_rpm_put_raw(display, 677 fetch_and_zero(&power_domains->async_put_wakeref)); 678 out_verify: 679 verify_async_put_domains_state(power_domains); 680 681 return ret; 682 } 683 684 static void 685 __intel_display_power_get_domain(struct intel_display *display, 686 enum intel_display_power_domain domain) 687 { 688 struct i915_power_domains *power_domains = &display->power.domains; 689 struct i915_power_well *power_well; 690 691 if (intel_display_power_grab_async_put_ref(display, domain)) 692 return; 693 694 for_each_power_domain_well(display, power_well, domain) 695 intel_power_well_get(display, power_well); 696 697 power_domains->domain_use_count[domain]++; 698 } 699 700 /** 701 * intel_display_power_get - grab a power domain reference 702 * @display: display device instance 703 * @domain: power domain to reference 704 * 705 * This function grabs a power domain reference for @domain and ensures that the 706 * power domain and all its parents are powered up. Therefore users should only 707 * grab a reference to the innermost power domain they need. 708 * 709 * Any power domain reference obtained by this function must have a symmetric 710 * call to intel_display_power_put() to release the reference again. 711 */ 712 struct ref_tracker *intel_display_power_get(struct intel_display *display, 713 enum intel_display_power_domain domain) 714 { 715 struct i915_power_domains *power_domains = &display->power.domains; 716 struct ref_tracker *wakeref; 717 718 wakeref = intel_display_rpm_get(display); 719 720 mutex_lock(&power_domains->lock); 721 __intel_display_power_get_domain(display, domain); 722 mutex_unlock(&power_domains->lock); 723 724 return wakeref; 725 } 726 727 /** 728 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 729 * @display: display device instance 730 * @domain: power domain to reference 731 * 732 * This function grabs a power domain reference for @domain and ensures that the 733 * power domain and all its parents are powered up. Therefore users should only 734 * grab a reference to the innermost power domain they need. 735 * 736 * Any power domain reference obtained by this function must have a symmetric 737 * call to intel_display_power_put() to release the reference again. 738 */ 739 struct ref_tracker * 740 intel_display_power_get_if_enabled(struct intel_display *display, 741 enum intel_display_power_domain domain) 742 { 743 struct i915_power_domains *power_domains = &display->power.domains; 744 struct ref_tracker *wakeref; 745 bool is_enabled; 746 747 wakeref = intel_display_rpm_get_if_in_use(display); 748 if (!wakeref) 749 return NULL; 750 751 mutex_lock(&power_domains->lock); 752 753 if (__intel_display_power_is_enabled(display, domain)) { 754 __intel_display_power_get_domain(display, domain); 755 is_enabled = true; 756 } else { 757 is_enabled = false; 758 } 759 760 mutex_unlock(&power_domains->lock); 761 762 if (!is_enabled) { 763 intel_display_rpm_put(display, wakeref); 764 wakeref = NULL; 765 } 766 767 return wakeref; 768 } 769 770 static void 771 __intel_display_power_put_domain(struct intel_display *display, 772 enum intel_display_power_domain domain) 773 { 774 struct i915_power_domains *power_domains = &display->power.domains; 775 struct i915_power_well *power_well; 776 const char *name = intel_display_power_domain_str(domain); 777 struct intel_power_domain_mask async_put_mask; 778 779 drm_WARN(display->drm, !power_domains->domain_use_count[domain], 780 "Use count on domain %s is already zero\n", 781 name); 782 async_put_domains_mask(power_domains, &async_put_mask); 783 drm_WARN(display->drm, 784 test_bit(domain, async_put_mask.bits), 785 "Async disabling of domain %s is pending\n", 786 name); 787 788 power_domains->domain_use_count[domain]--; 789 790 for_each_power_domain_well_reverse(display, power_well, domain) 791 intel_power_well_put(display, power_well); 792 } 793 794 static void __intel_display_power_put(struct intel_display *display, 795 enum intel_display_power_domain domain) 796 { 797 struct i915_power_domains *power_domains = &display->power.domains; 798 799 mutex_lock(&power_domains->lock); 800 __intel_display_power_put_domain(display, domain); 801 mutex_unlock(&power_domains->lock); 802 } 803 804 static void 805 queue_async_put_domains_work(struct i915_power_domains *power_domains, 806 struct ref_tracker *wakeref, 807 int delay_ms) 808 { 809 struct intel_display *display = container_of(power_domains, 810 struct intel_display, 811 power.domains); 812 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); 813 power_domains->async_put_wakeref = wakeref; 814 drm_WARN_ON(display->drm, !queue_delayed_work(system_dfl_wq, 815 &power_domains->async_put_work, 816 msecs_to_jiffies(delay_ms))); 817 } 818 819 static void 820 release_async_put_domains(struct i915_power_domains *power_domains, 821 struct intel_power_domain_mask *mask) 822 { 823 struct intel_display *display = container_of(power_domains, 824 struct intel_display, 825 power.domains); 826 enum intel_display_power_domain domain; 827 struct ref_tracker *wakeref; 828 829 wakeref = intel_display_rpm_get_noresume(display); 830 831 for_each_power_domain(domain, mask) { 832 /* Clear before put, so put's sanity check is happy. */ 833 async_put_domains_clear_domain(power_domains, domain); 834 __intel_display_power_put_domain(display, domain); 835 } 836 837 intel_display_rpm_put(display, wakeref); 838 } 839 840 static void 841 intel_display_power_put_async_work(struct work_struct *work) 842 { 843 struct intel_display *display = container_of(work, struct intel_display, 844 power.domains.async_put_work.work); 845 struct i915_power_domains *power_domains = &display->power.domains; 846 struct ref_tracker *new_work_wakeref, *old_work_wakeref = NULL; 847 848 new_work_wakeref = intel_display_rpm_get_raw(display); 849 850 mutex_lock(&power_domains->lock); 851 852 /* 853 * Bail out if all the domain refs pending to be released were grabbed 854 * by subsequent gets or a flush_work. 855 */ 856 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 857 if (!old_work_wakeref) 858 goto out_verify; 859 860 release_async_put_domains(power_domains, 861 &power_domains->async_put_domains[0]); 862 863 /* 864 * Cancel the work that got queued after this one got dequeued, 865 * since here we released the corresponding async-put reference. 866 */ 867 cancel_async_put_work(power_domains, false); 868 869 /* Requeue the work if more domains were async put meanwhile. */ 870 if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) { 871 bitmap_copy(power_domains->async_put_domains[0].bits, 872 power_domains->async_put_domains[1].bits, 873 POWER_DOMAIN_NUM); 874 bitmap_zero(power_domains->async_put_domains[1].bits, 875 POWER_DOMAIN_NUM); 876 queue_async_put_domains_work(power_domains, 877 fetch_and_zero(&new_work_wakeref), 878 power_domains->async_put_next_delay); 879 power_domains->async_put_next_delay = 0; 880 } 881 882 out_verify: 883 verify_async_put_domains_state(power_domains); 884 885 mutex_unlock(&power_domains->lock); 886 887 if (old_work_wakeref) 888 intel_display_rpm_put_raw(display, old_work_wakeref); 889 if (new_work_wakeref) 890 intel_display_rpm_put_raw(display, new_work_wakeref); 891 } 892 893 /** 894 * __intel_display_power_put_async - release a power domain reference asynchronously 895 * @display: display device instance 896 * @domain: power domain to reference 897 * @wakeref: wakeref acquired for the reference that is being released 898 * @delay_ms: delay of powering down the power domain 899 * 900 * This function drops the power domain reference obtained by 901 * intel_display_power_get*() and schedules a work to power down the 902 * corresponding hardware block if this is the last reference. 903 * The power down is delayed by @delay_ms if this is >= 0, or by a default 904 * 100 ms otherwise. 905 */ 906 void __intel_display_power_put_async(struct intel_display *display, 907 enum intel_display_power_domain domain, 908 struct ref_tracker *wakeref, 909 int delay_ms) 910 { 911 struct i915_power_domains *power_domains = &display->power.domains; 912 struct ref_tracker *work_wakeref; 913 914 work_wakeref = intel_display_rpm_get_raw(display); 915 916 delay_ms = delay_ms >= 0 ? delay_ms : 100; 917 918 mutex_lock(&power_domains->lock); 919 920 if (power_domains->domain_use_count[domain] > 1) { 921 __intel_display_power_put_domain(display, domain); 922 923 goto out_verify; 924 } 925 926 drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1); 927 928 /* Let a pending work requeue itself or queue a new one. */ 929 if (power_domains->async_put_wakeref) { 930 set_bit(domain, power_domains->async_put_domains[1].bits); 931 power_domains->async_put_next_delay = max(power_domains->async_put_next_delay, 932 delay_ms); 933 } else { 934 set_bit(domain, power_domains->async_put_domains[0].bits); 935 queue_async_put_domains_work(power_domains, 936 fetch_and_zero(&work_wakeref), 937 delay_ms); 938 } 939 940 out_verify: 941 verify_async_put_domains_state(power_domains); 942 943 mutex_unlock(&power_domains->lock); 944 945 if (work_wakeref) 946 intel_display_rpm_put_raw(display, work_wakeref); 947 948 intel_display_rpm_put(display, wakeref); 949 } 950 951 /** 952 * intel_display_power_flush_work - flushes the async display power disabling work 953 * @display: display device instance 954 * 955 * Flushes any pending work that was scheduled by a preceding 956 * intel_display_power_put_async() call, completing the disabling of the 957 * corresponding power domains. 958 * 959 * Note that the work handler function may still be running after this 960 * function returns; to ensure that the work handler isn't running use 961 * intel_display_power_flush_work_sync() instead. 962 */ 963 void intel_display_power_flush_work(struct intel_display *display) 964 { 965 struct i915_power_domains *power_domains = &display->power.domains; 966 struct intel_power_domain_mask async_put_mask; 967 struct ref_tracker *work_wakeref; 968 969 mutex_lock(&power_domains->lock); 970 971 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); 972 if (!work_wakeref) 973 goto out_verify; 974 975 async_put_domains_mask(power_domains, &async_put_mask); 976 release_async_put_domains(power_domains, &async_put_mask); 977 cancel_async_put_work(power_domains, false); 978 979 out_verify: 980 verify_async_put_domains_state(power_domains); 981 982 mutex_unlock(&power_domains->lock); 983 984 if (work_wakeref) 985 intel_display_rpm_put_raw(display, work_wakeref); 986 } 987 988 /** 989 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work 990 * @display: display device instance 991 * 992 * Like intel_display_power_flush_work(), but also ensure that the work 993 * handler function is not running any more when this function returns. 994 */ 995 static void 996 intel_display_power_flush_work_sync(struct intel_display *display) 997 { 998 struct i915_power_domains *power_domains = &display->power.domains; 999 1000 intel_display_power_flush_work(display); 1001 cancel_async_put_work(power_domains, true); 1002 1003 verify_async_put_domains_state(power_domains); 1004 1005 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); 1006 } 1007 1008 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 1009 /** 1010 * intel_display_power_put - release a power domain reference 1011 * @display: display device instance 1012 * @domain: power domain to reference 1013 * @wakeref: wakeref acquired for the reference that is being released 1014 * 1015 * This function drops the power domain reference obtained by 1016 * intel_display_power_get() and might power down the corresponding hardware 1017 * block right away if this is the last reference. 1018 */ 1019 void intel_display_power_put(struct intel_display *display, 1020 enum intel_display_power_domain domain, 1021 struct ref_tracker *wakeref) 1022 { 1023 __intel_display_power_put(display, domain); 1024 intel_display_rpm_put(display, wakeref); 1025 } 1026 #else 1027 /** 1028 * intel_display_power_put_unchecked - release an unchecked power domain reference 1029 * @display: display device instance 1030 * @domain: power domain to reference 1031 * 1032 * This function drops the power domain reference obtained by 1033 * intel_display_power_get() and might power down the corresponding hardware 1034 * block right away if this is the last reference. 1035 * 1036 * This function is only for the power domain code's internal use to suppress wakeref 1037 * tracking when the corresponding debug kconfig option is disabled, should not 1038 * be used otherwise. 1039 */ 1040 void intel_display_power_put_unchecked(struct intel_display *display, 1041 enum intel_display_power_domain domain) 1042 { 1043 __intel_display_power_put(display, domain); 1044 intel_display_rpm_put_unchecked(display); 1045 } 1046 #endif 1047 1048 void 1049 intel_display_power_get_in_set(struct intel_display *display, 1050 struct intel_display_power_domain_set *power_domain_set, 1051 enum intel_display_power_domain domain) 1052 { 1053 struct ref_tracker *__maybe_unused wf; 1054 1055 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); 1056 1057 wf = intel_display_power_get(display, domain); 1058 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 1059 power_domain_set->wakerefs[domain] = wf; 1060 #endif 1061 set_bit(domain, power_domain_set->mask.bits); 1062 } 1063 1064 bool 1065 intel_display_power_get_in_set_if_enabled(struct intel_display *display, 1066 struct intel_display_power_domain_set *power_domain_set, 1067 enum intel_display_power_domain domain) 1068 { 1069 struct ref_tracker *wf; 1070 1071 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); 1072 1073 wf = intel_display_power_get_if_enabled(display, domain); 1074 if (!wf) 1075 return false; 1076 1077 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 1078 power_domain_set->wakerefs[domain] = wf; 1079 #endif 1080 set_bit(domain, power_domain_set->mask.bits); 1081 1082 return true; 1083 } 1084 1085 void 1086 intel_display_power_put_mask_in_set(struct intel_display *display, 1087 struct intel_display_power_domain_set *power_domain_set, 1088 struct intel_power_domain_mask *mask) 1089 { 1090 enum intel_display_power_domain domain; 1091 1092 drm_WARN_ON(display->drm, 1093 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM)); 1094 1095 for_each_power_domain(domain, mask) { 1096 struct ref_tracker *__maybe_unused wf = INTEL_WAKEREF_DEF; 1097 1098 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 1099 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]); 1100 #endif 1101 intel_display_power_put(display, domain, wf); 1102 clear_bit(domain, power_domain_set->mask.bits); 1103 } 1104 } 1105 1106 static int 1107 sanitize_disable_power_well_option(int disable_power_well) 1108 { 1109 if (disable_power_well >= 0) 1110 return !!disable_power_well; 1111 1112 return 1; 1113 } 1114 1115 static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc) 1116 { 1117 u32 mask; 1118 int requested_dc; 1119 int max_dc; 1120 1121 if (!HAS_DISPLAY(display)) 1122 return 0; 1123 1124 if (DISPLAY_VER(display) >= 35) 1125 max_dc = 4; 1126 else if (DISPLAY_VER(display) >= 20) 1127 max_dc = 2; 1128 else if (display->platform.dg2) 1129 max_dc = 1; 1130 else if (display->platform.dg1) 1131 max_dc = 3; 1132 else if (DISPLAY_VER(display) >= 12) 1133 max_dc = 4; 1134 else if (display->platform.geminilake || display->platform.broxton) 1135 max_dc = 1; 1136 else if (DISPLAY_VER(display) >= 9) 1137 max_dc = 2; 1138 else 1139 max_dc = 0; 1140 1141 /* 1142 * DC9 has a separate HW flow from the rest of the DC states, 1143 * not depending on the DMC firmware. It's needed by system 1144 * suspend/resume, so allow it unconditionally. 1145 */ 1146 mask = display->platform.geminilake || display->platform.broxton || 1147 DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0; 1148 1149 if (!display->params.disable_power_well) 1150 max_dc = 0; 1151 1152 if (enable_dc >= 0 && enable_dc <= max_dc) { 1153 requested_dc = enable_dc; 1154 } else if (enable_dc == -1) { 1155 requested_dc = max_dc; 1156 } else if (enable_dc > max_dc && enable_dc <= 4) { 1157 drm_dbg_kms(display->drm, 1158 "Adjusting requested max DC state (%d->%d)\n", 1159 enable_dc, max_dc); 1160 requested_dc = max_dc; 1161 } else { 1162 drm_err(display->drm, 1163 "Unexpected value for enable_dc (%d)\n", enable_dc); 1164 requested_dc = max_dc; 1165 } 1166 1167 switch (requested_dc) { 1168 case 4: 1169 mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6; 1170 break; 1171 case 3: 1172 mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC5; 1173 break; 1174 case 2: 1175 mask |= DC_STATE_EN_UPTO_DC6; 1176 break; 1177 case 1: 1178 mask |= DC_STATE_EN_UPTO_DC5; 1179 break; 1180 } 1181 1182 drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask); 1183 1184 return mask; 1185 } 1186 1187 /** 1188 * intel_display_power_init - initializes the power domain structures 1189 * @display: display device instance 1190 * 1191 * Initializes the power domain structures for @display depending upon the 1192 * supported platform. 1193 */ 1194 int intel_display_power_init(struct intel_display *display) 1195 { 1196 struct i915_power_domains *power_domains = &display->power.domains; 1197 1198 display->params.disable_power_well = 1199 sanitize_disable_power_well_option(display->params.disable_power_well); 1200 power_domains->allowed_dc_mask = 1201 get_allowed_dc_mask(display, display->params.enable_dc); 1202 1203 power_domains->target_dc_state = 1204 sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1205 1206 mutex_init(&power_domains->lock); 1207 mutex_init(&display->power.dc3co.lock); 1208 1209 INIT_DELAYED_WORK(&power_domains->async_put_work, 1210 intel_display_power_put_async_work); 1211 1212 return intel_display_power_map_init(power_domains); 1213 } 1214 1215 /** 1216 * intel_display_power_cleanup - clean up power domains resources 1217 * @display: display device instance 1218 * 1219 * Release any resources acquired by intel_display_power_init() 1220 */ 1221 void intel_display_power_cleanup(struct intel_display *display) 1222 { 1223 intel_display_power_map_cleanup(&display->power.domains); 1224 } 1225 1226 static void intel_power_domains_sync_hw(struct intel_display *display) 1227 { 1228 struct i915_power_domains *power_domains = &display->power.domains; 1229 struct i915_power_well *power_well; 1230 1231 mutex_lock(&power_domains->lock); 1232 for_each_power_well(display, power_well) 1233 intel_power_well_sync_hw(display, power_well); 1234 mutex_unlock(&power_domains->lock); 1235 } 1236 1237 static void gen9_dbuf_slice_set(struct intel_display *display, 1238 enum dbuf_slice slice, bool enable) 1239 { 1240 intel_reg_t reg = DBUF_CTL_S(slice); 1241 bool state; 1242 1243 intel_de_rmw(display, reg, DBUF_POWER_REQUEST, 1244 enable ? DBUF_POWER_REQUEST : 0); 1245 intel_de_posting_read(display, reg); 1246 udelay(10); 1247 1248 state = intel_de_read(display, reg) & DBUF_POWER_STATE; 1249 drm_WARN(display->drm, enable != state, 1250 "DBuf slice %d power %s timeout!\n", 1251 slice, str_enable_disable(enable)); 1252 } 1253 1254 void gen9_dbuf_slices_update(struct intel_display *display, 1255 u8 req_slices) 1256 { 1257 struct i915_power_domains *power_domains = &display->power.domains; 1258 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; 1259 enum dbuf_slice slice; 1260 1261 drm_WARN(display->drm, req_slices & ~slice_mask, 1262 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n", 1263 req_slices, slice_mask); 1264 1265 drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n", 1266 req_slices); 1267 1268 /* 1269 * Might be running this in parallel to gen9_dc_off_power_well_enable 1270 * being called from intel_dp_detect for instance, 1271 * which causes assertion triggered by race condition, 1272 * as gen9_assert_dbuf_enabled might preempt this when registers 1273 * were already updated, while dev_priv was not. 1274 */ 1275 mutex_lock(&power_domains->lock); 1276 1277 for_each_dbuf_slice(display, slice) 1278 gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice)); 1279 1280 display->dbuf.enabled_slices = req_slices; 1281 1282 mutex_unlock(&power_domains->lock); 1283 } 1284 1285 static void gen9_dbuf_enable(struct intel_display *display) 1286 { 1287 u8 slices_mask; 1288 1289 display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(display); 1290 1291 slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices; 1292 1293 if (HAS_PMDEMAND(display)) 1294 intel_pmdemand_program_dbuf(display, slices_mask); 1295 1296 /* 1297 * Just power up at least 1 slice, we will 1298 * figure out later which slices we have and what we need. 1299 */ 1300 gen9_dbuf_slices_update(display, slices_mask); 1301 } 1302 1303 static void gen9_dbuf_disable(struct intel_display *display) 1304 { 1305 gen9_dbuf_slices_update(display, 0); 1306 1307 if (HAS_PMDEMAND(display)) 1308 intel_pmdemand_program_dbuf(display, 0); 1309 } 1310 1311 static void gen12_dbuf_slices_config(struct intel_display *display) 1312 { 1313 enum dbuf_slice slice; 1314 1315 for_each_dbuf_slice(display, slice) 1316 intel_de_rmw(display, DBUF_CTL_S(slice), 1317 DBUF_TRACKER_STATE_SERVICE_MASK, 1318 DBUF_TRACKER_STATE_SERVICE(8)); 1319 } 1320 1321 static void icl_mbus_init(struct intel_display *display) 1322 { 1323 unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask; 1324 u32 mask, val, i; 1325 1326 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1327 return; 1328 1329 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | 1330 MBUS_ABOX_BT_CREDIT_POOL2_MASK | 1331 MBUS_ABOX_B_CREDIT_MASK | 1332 MBUS_ABOX_BW_CREDIT_MASK; 1333 val = MBUS_ABOX_BT_CREDIT_POOL1(16) | 1334 MBUS_ABOX_BT_CREDIT_POOL2(16) | 1335 MBUS_ABOX_B_CREDIT(1) | 1336 MBUS_ABOX_BW_CREDIT(1); 1337 1338 /* 1339 * gen12 platforms that use abox1 and abox2 for pixel data reads still 1340 * expect us to program the abox_ctl0 register as well, even though 1341 * we don't have to program other instance-0 registers like BW_BUDDY. 1342 */ 1343 if (DISPLAY_VER(display) == 12) 1344 abox_regs |= BIT(0); 1345 1346 for_each_set_bit(i, &abox_regs, BITS_PER_TYPE(abox_regs)) 1347 intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val); 1348 } 1349 1350 static void hsw_assert_cdclk(struct intel_display *display) 1351 { 1352 u32 val = intel_de_read(display, LCPLL_CTL); 1353 1354 /* 1355 * The LCPLL register should be turned on by the BIOS. For now 1356 * let's just check its state and print errors in case 1357 * something is wrong. Don't even try to turn it on. 1358 */ 1359 1360 if (val & LCPLL_CD_SOURCE_FCLK) 1361 drm_err(display->drm, "CDCLK source is not LCPLL\n"); 1362 1363 if (val & LCPLL_PLL_DISABLE) 1364 drm_err(display->drm, "LCPLL is disabled\n"); 1365 1366 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC) 1367 drm_err(display->drm, "LCPLL not using non-SSC reference\n"); 1368 } 1369 1370 static void assert_can_disable_lcpll(struct intel_display *display) 1371 { 1372 struct intel_crtc *crtc; 1373 1374 for_each_intel_crtc(display, crtc) 1375 INTEL_DISPLAY_STATE_WARN(display, crtc->active, 1376 "CRTC for pipe %c enabled\n", 1377 pipe_name(crtc->pipe)); 1378 1379 INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2), 1380 "Display power well on\n"); 1381 INTEL_DISPLAY_STATE_WARN(display, 1382 intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE, 1383 "SPLL enabled\n"); 1384 INTEL_DISPLAY_STATE_WARN(display, 1385 intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, 1386 "WRPLL1 enabled\n"); 1387 INTEL_DISPLAY_STATE_WARN(display, 1388 intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, 1389 "WRPLL2 enabled\n"); 1390 INTEL_DISPLAY_STATE_WARN(display, 1391 intel_de_read(display, PP_STATUS(display, 0)) & PP_ON, 1392 "Panel power on\n"); 1393 INTEL_DISPLAY_STATE_WARN(display, 1394 intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 1395 "CPU PWM1 enabled\n"); 1396 if (display->platform.haswell) 1397 INTEL_DISPLAY_STATE_WARN(display, 1398 intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 1399 "CPU PWM2 enabled\n"); 1400 INTEL_DISPLAY_STATE_WARN(display, 1401 intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, 1402 "PCH PWM1 enabled\n"); 1403 INTEL_DISPLAY_STATE_WARN(display, 1404 (intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 1405 "Utility pin enabled in PWM mode\n"); 1406 INTEL_DISPLAY_STATE_WARN(display, 1407 intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE, 1408 "PCH GTC enabled\n"); 1409 1410 /* 1411 * In theory we can still leave IRQs enabled, as long as only the HPD 1412 * interrupts remain enabled. We used to check for that, but since it's 1413 * gen-specific and since we only disable LCPLL after we fully disable 1414 * the interrupts, the check below should be enough. 1415 */ 1416 INTEL_DISPLAY_STATE_WARN(display, intel_parent_irq_enabled(display), 1417 "IRQs enabled\n"); 1418 } 1419 1420 static u32 hsw_read_dcomp(struct intel_display *display) 1421 { 1422 if (display->platform.haswell) 1423 return intel_mchbar_read(display, D_COMP_HSW); 1424 else 1425 return intel_de_read(display, D_COMP_BDW); 1426 } 1427 1428 static void hsw_write_dcomp(struct intel_display *display, u32 val) 1429 { 1430 if (display->platform.haswell) { 1431 if (intel_parent_pcode_write(display, GEN6_PCODE_WRITE_D_COMP, val)) 1432 drm_dbg_kms(display->drm, "Failed to write to D_COMP\n"); 1433 } else { 1434 intel_de_write(display, D_COMP_BDW, val); 1435 intel_de_posting_read(display, D_COMP_BDW); 1436 } 1437 } 1438 1439 /* 1440 * This function implements pieces of two sequences from BSpec: 1441 * - Sequence for display software to disable LCPLL 1442 * - Sequence for display software to allow package C8+ 1443 * The steps implemented here are just the steps that actually touch the LCPLL 1444 * register. Callers should take care of disabling all the display engine 1445 * functions, doing the mode unset, fixing interrupts, etc. 1446 */ 1447 static void hsw_disable_lcpll(struct intel_display *display, 1448 bool switch_to_fclk, bool allow_power_down) 1449 { 1450 u32 val; 1451 int ret; 1452 1453 assert_can_disable_lcpll(display); 1454 1455 val = intel_de_read(display, LCPLL_CTL); 1456 1457 if (switch_to_fclk) { 1458 val |= LCPLL_CD_SOURCE_FCLK; 1459 intel_de_write(display, LCPLL_CTL, val); 1460 1461 ret = intel_de_wait_for_set_us(display, LCPLL_CTL, 1462 LCPLL_CD_SOURCE_FCLK_DONE, 1); 1463 if (ret) 1464 drm_err(display->drm, "Switching to FCLK failed\n"); 1465 1466 val = intel_de_read(display, LCPLL_CTL); 1467 } 1468 1469 val |= LCPLL_PLL_DISABLE; 1470 intel_de_write(display, LCPLL_CTL, val); 1471 intel_de_posting_read(display, LCPLL_CTL); 1472 1473 if (intel_de_wait_for_clear_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) 1474 drm_err(display->drm, "LCPLL still locked\n"); 1475 1476 val = hsw_read_dcomp(display); 1477 val |= D_COMP_COMP_DISABLE; 1478 hsw_write_dcomp(display, val); 1479 ndelay(100); 1480 1481 ret = poll_timeout_us(val = hsw_read_dcomp(display), 1482 (val & D_COMP_RCOMP_IN_PROGRESS) == 0, 1483 100, 1000, false); 1484 if (ret) 1485 drm_err(display->drm, "D_COMP RCOMP still in progress\n"); 1486 1487 if (allow_power_down) { 1488 intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); 1489 intel_de_posting_read(display, LCPLL_CTL); 1490 } 1491 } 1492 1493 /* 1494 * Fully restores LCPLL, disallowing power down and switching back to LCPLL 1495 * source. 1496 */ 1497 static void hsw_restore_lcpll(struct intel_display *display) 1498 { 1499 u32 val; 1500 int ret; 1501 1502 val = intel_de_read(display, LCPLL_CTL); 1503 1504 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | 1505 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) 1506 return; 1507 1508 /* 1509 * Make sure we're not on PC8 state before disabling 1510 * PC8, otherwise we'll hang the machine. 1511 */ 1512 intel_parent_pc8_block(display); 1513 1514 if (val & LCPLL_POWER_DOWN_ALLOW) { 1515 val &= ~LCPLL_POWER_DOWN_ALLOW; 1516 intel_de_write(display, LCPLL_CTL, val); 1517 intel_de_posting_read(display, LCPLL_CTL); 1518 } 1519 1520 val = hsw_read_dcomp(display); 1521 val |= D_COMP_COMP_FORCE; 1522 val &= ~D_COMP_COMP_DISABLE; 1523 hsw_write_dcomp(display, val); 1524 1525 val = intel_de_read(display, LCPLL_CTL); 1526 val &= ~LCPLL_PLL_DISABLE; 1527 intel_de_write(display, LCPLL_CTL, val); 1528 1529 if (intel_de_wait_for_set_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) 1530 drm_err(display->drm, "LCPLL not locked yet\n"); 1531 1532 if (val & LCPLL_CD_SOURCE_FCLK) { 1533 intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); 1534 1535 ret = intel_de_wait_for_clear_us(display, LCPLL_CTL, 1536 LCPLL_CD_SOURCE_FCLK_DONE, 1); 1537 if (ret) 1538 drm_err(display->drm, 1539 "Switching back to LCPLL failed\n"); 1540 } 1541 1542 intel_parent_pc8_unblock(display); 1543 1544 intel_update_cdclk(display); 1545 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1546 } 1547 1548 /* 1549 * Package states C8 and deeper are really deep PC states that can only be 1550 * reached when all the devices on the system allow it, so even if the graphics 1551 * device allows PC8+, it doesn't mean the system will actually get to these 1552 * states. Our driver only allows PC8+ when going into runtime PM. 1553 * 1554 * The requirements for PC8+ are that all the outputs are disabled, the power 1555 * well is disabled and most interrupts are disabled, and these are also 1556 * requirements for runtime PM. When these conditions are met, we manually do 1557 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk 1558 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard 1559 * hang the machine. 1560 * 1561 * When we really reach PC8 or deeper states (not just when we allow it) we lose 1562 * the state of some registers, so when we come back from PC8+ we need to 1563 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't 1564 * need to take care of the registers kept by RC6. Notice that this happens even 1565 * if we don't put the device in PCI D3 state (which is what currently happens 1566 * because of the runtime PM support). 1567 * 1568 * For more, read "Display Sequences for Package C8" on the hardware 1569 * documentation. 1570 */ 1571 static void hsw_enable_pc8(struct intel_display *display) 1572 { 1573 drm_dbg_kms(display->drm, "Enabling package C8+\n"); 1574 1575 if (HAS_PCH_LPT_LP(display)) 1576 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1577 PCH_LP_PARTITION_LEVEL_DISABLE, 0); 1578 1579 lpt_disable_clkout_dp(display); 1580 hsw_disable_lcpll(display, true, true); 1581 } 1582 1583 static void hsw_disable_pc8(struct intel_display *display) 1584 { 1585 drm_dbg_kms(display->drm, "Disabling package C8+\n"); 1586 1587 hsw_restore_lcpll(display); 1588 intel_init_pch_refclk(display); 1589 1590 /* Many display registers don't survive PC8+ */ 1591 intel_clock_gating_init(display->drm); 1592 } 1593 1594 static void intel_pch_reset_handshake(struct intel_display *display, 1595 bool enable) 1596 { 1597 intel_reg_t reg; 1598 u32 reset_bits; 1599 1600 if (DISPLAY_VER(display) >= 35) 1601 return; 1602 1603 if (display->platform.ivybridge) { 1604 reg = GEN7_MSG_CTL; 1605 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK; 1606 } else { 1607 reg = HSW_NDE_RSTWRN_OPT; 1608 reset_bits = RESET_PCH_HANDSHAKE_ENABLE; 1609 } 1610 1611 if (DISPLAY_VER(display) >= 14) 1612 reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; 1613 1614 intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0); 1615 } 1616 1617 static void skl_display_core_init(struct intel_display *display, 1618 bool resume) 1619 { 1620 struct i915_power_domains *power_domains = &display->power.domains; 1621 struct i915_power_well *well; 1622 1623 gen9_set_dc_state(display, DC_STATE_DISABLE); 1624 1625 /* enable PCH reset handshake */ 1626 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); 1627 1628 if (!HAS_DISPLAY(display)) 1629 return; 1630 1631 /* enable PG1 and Misc I/O */ 1632 mutex_lock(&power_domains->lock); 1633 1634 well = lookup_power_well(display, SKL_DISP_PW_1); 1635 intel_power_well_enable(display, well); 1636 1637 well = lookup_power_well(display, SKL_DISP_PW_MISC_IO); 1638 intel_power_well_enable(display, well); 1639 1640 mutex_unlock(&power_domains->lock); 1641 1642 intel_cdclk_init_hw(display); 1643 1644 gen9_dbuf_enable(display); 1645 1646 if (resume) 1647 intel_dmc_load_program(display); 1648 } 1649 1650 static void skl_display_core_uninit(struct intel_display *display) 1651 { 1652 struct i915_power_domains *power_domains = &display->power.domains; 1653 struct i915_power_well *well; 1654 1655 if (!HAS_DISPLAY(display)) 1656 return; 1657 1658 gen9_disable_dc_states(display); 1659 /* TODO: disable DMC program */ 1660 1661 gen9_dbuf_disable(display); 1662 1663 intel_cdclk_uninit_hw(display); 1664 1665 /* The spec doesn't call for removing the reset handshake flag */ 1666 /* disable PG1 and Misc I/O */ 1667 1668 mutex_lock(&power_domains->lock); 1669 1670 /* 1671 * BSpec says to keep the MISC IO power well enabled here, only 1672 * remove our request for power well 1. 1673 * Note that even though the driver's request is removed power well 1 1674 * may stay enabled after this due to DMC's own request on it. 1675 */ 1676 well = lookup_power_well(display, SKL_DISP_PW_1); 1677 intel_power_well_disable(display, well); 1678 1679 mutex_unlock(&power_domains->lock); 1680 1681 usleep_range(10, 30); /* 10 us delay per Bspec */ 1682 } 1683 1684 static void bxt_display_core_init(struct intel_display *display, bool resume) 1685 { 1686 struct i915_power_domains *power_domains = &display->power.domains; 1687 struct i915_power_well *well; 1688 1689 gen9_set_dc_state(display, DC_STATE_DISABLE); 1690 1691 /* 1692 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 1693 * or else the reset will hang because there is no PCH to respond. 1694 * Move the handshake programming to initialization sequence. 1695 * Previously was left up to BIOS. 1696 */ 1697 intel_pch_reset_handshake(display, false); 1698 1699 if (!HAS_DISPLAY(display)) 1700 return; 1701 1702 /* Enable PG1 */ 1703 mutex_lock(&power_domains->lock); 1704 1705 well = lookup_power_well(display, SKL_DISP_PW_1); 1706 intel_power_well_enable(display, well); 1707 1708 mutex_unlock(&power_domains->lock); 1709 1710 intel_cdclk_init_hw(display); 1711 1712 gen9_dbuf_enable(display); 1713 1714 if (resume) 1715 intel_dmc_load_program(display); 1716 } 1717 1718 static void bxt_display_core_uninit(struct intel_display *display) 1719 { 1720 struct i915_power_domains *power_domains = &display->power.domains; 1721 struct i915_power_well *well; 1722 1723 if (!HAS_DISPLAY(display)) 1724 return; 1725 1726 gen9_disable_dc_states(display); 1727 /* TODO: disable DMC program */ 1728 1729 gen9_dbuf_disable(display); 1730 1731 intel_cdclk_uninit_hw(display); 1732 1733 /* The spec doesn't call for removing the reset handshake flag */ 1734 1735 /* 1736 * Disable PW1 (PG1). 1737 * Note that even though the driver's request is removed power well 1 1738 * may stay enabled after this due to DMC's own request on it. 1739 */ 1740 mutex_lock(&power_domains->lock); 1741 1742 well = lookup_power_well(display, SKL_DISP_PW_1); 1743 intel_power_well_disable(display, well); 1744 1745 mutex_unlock(&power_domains->lock); 1746 1747 usleep_range(10, 30); /* 10 us delay per Bspec */ 1748 } 1749 1750 struct buddy_page_mask { 1751 u32 page_mask; 1752 u8 type; 1753 u8 num_channels; 1754 }; 1755 1756 static const struct buddy_page_mask tgl_buddy_page_masks[] = { 1757 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF }, 1758 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF }, 1759 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C }, 1760 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C }, 1761 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F }, 1762 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E }, 1763 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 }, 1764 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 }, 1765 {} 1766 }; 1767 1768 static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = { 1769 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 }, 1770 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 }, 1771 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 }, 1772 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 }, 1773 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 }, 1774 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 }, 1775 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 }, 1776 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 }, 1777 {} 1778 }; 1779 1780 static void tgl_bw_buddy_init(struct intel_display *display) 1781 { 1782 const struct dram_info *dram_info = intel_dram_info(display); 1783 const struct buddy_page_mask *table; 1784 unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; 1785 int config, i; 1786 1787 /* BW_BUDDY registers are not used on dgpu's beyond DG1 */ 1788 if (display->platform.dgfx && !display->platform.dg1) 1789 return; 1790 1791 if (intel_display_wa(display, INTEL_DISPLAY_WA_1409767108)) 1792 /* Wa_1409767108 */ 1793 table = wa_1409767108_buddy_page_masks; 1794 else 1795 table = tgl_buddy_page_masks; 1796 1797 for (config = 0; table[config].page_mask != 0; config++) 1798 if (table[config].num_channels == dram_info->num_channels && 1799 table[config].type == dram_info->type) 1800 break; 1801 1802 if (table[config].page_mask == 0) { 1803 drm_dbg_kms(display->drm, 1804 "Unknown memory configuration; disabling address buddy logic.\n"); 1805 1806 if (DISPLAY_VER(display) < 20) { 1807 for_each_set_bit(i, &abox_mask, BITS_PER_TYPE(abox_mask)) 1808 intel_de_write(display, BW_BUDDY_CTL(i), 1809 BW_BUDDY_DISABLE); 1810 } 1811 } else { 1812 for_each_set_bit(i, &abox_mask, BITS_PER_TYPE(abox_mask)) { 1813 intel_de_write(display, BW_BUDDY_PAGE_MASK(i), 1814 table[config].page_mask); 1815 1816 /* Wa_22010178259:tgl,dg1,rkl,adl-s */ 1817 if (intel_display_wa(display, INTEL_DISPLAY_WA_22010178259)) 1818 intel_de_rmw(display, BW_BUDDY_CTL(i), 1819 BW_BUDDY_TLB_REQ_TIMER_MASK, 1820 BW_BUDDY_TLB_REQ_TIMER(0x8)); 1821 } 1822 } 1823 } 1824 1825 static void icl_display_core_init(struct intel_display *display, 1826 bool resume) 1827 { 1828 struct i915_power_domains *power_domains = &display->power.domains; 1829 struct i915_power_well *well; 1830 1831 gen9_set_dc_state(display, DC_STATE_DISABLE); 1832 1833 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ 1834 if (intel_display_wa(display, INTEL_DISPLAY_WA_14011294188)) 1835 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0, 1836 PCH_DPMGUNIT_CLOCK_GATE_DISABLE); 1837 1838 /* 1. Enable PCH reset handshake. */ 1839 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); 1840 1841 if (!HAS_DISPLAY(display)) 1842 return; 1843 1844 /* 2. Initialize all combo phys */ 1845 intel_combo_phy_init(display); 1846 1847 /* 1848 * 3. Enable Power Well 1 (PG1). 1849 * The AUX IO power wells will be enabled on demand. 1850 */ 1851 mutex_lock(&power_domains->lock); 1852 well = lookup_power_well(display, SKL_DISP_PW_1); 1853 intel_power_well_enable(display, well); 1854 mutex_unlock(&power_domains->lock); 1855 1856 if (DISPLAY_VER(display) == 14) 1857 intel_de_rmw(display, DC_STATE_EN, 1858 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0); 1859 1860 /* 4. Enable CDCLK. */ 1861 intel_cdclk_init_hw(display); 1862 1863 if (DISPLAY_VER(display) == 12 || display->platform.dg2) 1864 gen12_dbuf_slices_config(display); 1865 1866 /* 5. Enable DBUF. */ 1867 gen9_dbuf_enable(display); 1868 1869 /* 6. Setup MBUS. */ 1870 icl_mbus_init(display); 1871 1872 /* 7. Program arbiter BW_BUDDY registers */ 1873 if (DISPLAY_VER(display) >= 12) 1874 tgl_bw_buddy_init(display); 1875 1876 /* 8. Ensure PHYs have completed calibration and adaptation */ 1877 if (display->platform.dg2) 1878 intel_snps_phy_wait_for_calibration(display); 1879 1880 /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ 1881 if (DISPLAY_VERx100(display) == 1401) 1882 intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); 1883 1884 if (resume) 1885 intel_dmc_load_program(display); 1886 1887 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */ 1888 if (intel_display_wa(display, INTEL_DISPLAY_WA_14011508470)) 1889 intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0, 1890 DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | 1891 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR); 1892 1893 /* Wa_14011503030:xelpd */ 1894 if (intel_display_wa(display, INTEL_DISPLAY_WA_14011503030)) 1895 intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); 1896 1897 /* Wa_15013987218 */ 1898 if (intel_display_wa(display, INTEL_DISPLAY_WA_15013987218)) { 1899 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1900 0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE); 1901 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1902 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0); 1903 } 1904 } 1905 1906 static void icl_display_core_uninit(struct intel_display *display) 1907 { 1908 struct i915_power_domains *power_domains = &display->power.domains; 1909 struct i915_power_well *well; 1910 1911 if (!HAS_DISPLAY(display)) 1912 return; 1913 1914 gen9_disable_dc_states(display); 1915 intel_dmc_disable_program(display); 1916 1917 /* 1. Disable all display engine functions -> already done */ 1918 1919 /* 2. Disable DBUF */ 1920 gen9_dbuf_disable(display); 1921 1922 /* 3. Disable CD clock */ 1923 intel_cdclk_uninit_hw(display); 1924 1925 if (DISPLAY_VER(display) == 14) 1926 intel_de_rmw(display, DC_STATE_EN, 0, 1927 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH); 1928 1929 /* 1930 * 4. Disable Power Well 1 (PG1). 1931 * The AUX IO power wells are toggled on demand, so they are already 1932 * disabled at this point. 1933 */ 1934 mutex_lock(&power_domains->lock); 1935 well = lookup_power_well(display, SKL_DISP_PW_1); 1936 intel_power_well_disable(display, well); 1937 mutex_unlock(&power_domains->lock); 1938 1939 /* 5. */ 1940 intel_combo_phy_uninit(display); 1941 } 1942 1943 static void chv_phy_control_init(struct intel_display *display) 1944 { 1945 struct i915_power_well *cmn_bc = 1946 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1947 struct i915_power_well *cmn_d = 1948 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1949 1950 /* 1951 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 1952 * workaround never ever read DISPLAY_PHY_CONTROL, and 1953 * instead maintain a shadow copy ourselves. Use the actual 1954 * power well state and lane status to reconstruct the 1955 * expected initial value. 1956 */ 1957 display->power.chv_phy_control = 1958 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 1959 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 1960 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 1961 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 1962 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 1963 1964 /* 1965 * If all lanes are disabled we leave the override disabled 1966 * with all power down bits cleared to match the state we 1967 * would use after disabling the port. Otherwise enable the 1968 * override and set the lane powerdown bits accding to the 1969 * current lane status. 1970 */ 1971 if (intel_power_well_is_enabled(display, cmn_bc)) { 1972 u32 status = intel_de_read(display, DPLL(display, PIPE_A)); 1973 unsigned int mask; 1974 1975 mask = status & DPLL_PORTB_READY_MASK; 1976 if (mask == 0xf) 1977 mask = 0x0; 1978 else 1979 display->power.chv_phy_control |= 1980 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 1981 1982 display->power.chv_phy_control |= 1983 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 1984 1985 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 1986 if (mask == 0xf) 1987 mask = 0x0; 1988 else 1989 display->power.chv_phy_control |= 1990 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 1991 1992 display->power.chv_phy_control |= 1993 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 1994 1995 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 1996 1997 display->power.chv_phy_assert[DPIO_PHY0] = false; 1998 } else { 1999 display->power.chv_phy_assert[DPIO_PHY0] = true; 2000 } 2001 2002 if (intel_power_well_is_enabled(display, cmn_d)) { 2003 u32 status = intel_de_read(display, DPIO_PHY_STATUS); 2004 unsigned int mask; 2005 2006 mask = status & DPLL_PORTD_READY_MASK; 2007 2008 if (mask == 0xf) 2009 mask = 0x0; 2010 else 2011 display->power.chv_phy_control |= 2012 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 2013 2014 display->power.chv_phy_control |= 2015 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 2016 2017 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 2018 2019 display->power.chv_phy_assert[DPIO_PHY1] = false; 2020 } else { 2021 display->power.chv_phy_assert[DPIO_PHY1] = true; 2022 } 2023 2024 drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n", 2025 display->power.chv_phy_control); 2026 2027 /* Defer application of initial phy_control to enabling the powerwell */ 2028 } 2029 2030 static void vlv_cmnlane_wa(struct intel_display *display) 2031 { 2032 struct i915_power_well *cmn = 2033 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 2034 struct i915_power_well *disp2d = 2035 lookup_power_well(display, VLV_DISP_PW_DISP2D); 2036 2037 /* If the display might be already active skip this */ 2038 if (intel_power_well_is_enabled(display, cmn) && 2039 intel_power_well_is_enabled(display, disp2d) && 2040 intel_de_read(display, DPIO_CTL) & DPIO_CMNRST) 2041 return; 2042 2043 drm_dbg_kms(display->drm, "toggling display PHY side reset\n"); 2044 2045 /* cmnlane needs DPLL registers */ 2046 intel_power_well_enable(display, disp2d); 2047 2048 /* 2049 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 2050 * Need to assert and de-assert PHY SB reset by gating the 2051 * common lane power, then un-gating it. 2052 * Simply ungating isn't enough to reset the PHY enough to get 2053 * ports and lanes running. 2054 */ 2055 intel_power_well_disable(display, cmn); 2056 } 2057 2058 static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0) 2059 { 2060 bool ret; 2061 2062 vlv_punit_get(display); 2063 ret = (vlv_punit_read(display, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; 2064 vlv_punit_put(display); 2065 2066 return ret; 2067 } 2068 2069 static void assert_ved_power_gated(struct intel_display *display) 2070 { 2071 drm_WARN(display->drm, 2072 !vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0), 2073 "VED not power gated\n"); 2074 } 2075 2076 static void assert_isp_power_gated(struct intel_display *display) 2077 { 2078 static const struct pci_device_id isp_ids[] = { 2079 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)}, 2080 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)}, 2081 {} 2082 }; 2083 2084 drm_WARN(display->drm, !pci_dev_present(isp_ids) && 2085 !vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0), 2086 "ISP not power gated\n"); 2087 } 2088 2089 static void intel_power_domains_verify_state(struct intel_display *display); 2090 2091 static void __intel_display_power_init_hw(struct intel_display *display, bool resume) 2092 { 2093 struct i915_power_domains *power_domains = &display->power.domains; 2094 2095 power_domains->initializing = true; 2096 2097 if (DISPLAY_VER(display) >= 11) { 2098 icl_display_core_init(display, resume); 2099 } else if (display->platform.geminilake || display->platform.broxton) { 2100 bxt_display_core_init(display, resume); 2101 } else if (DISPLAY_VER(display) == 9) { 2102 skl_display_core_init(display, resume); 2103 } else if (display->platform.cherryview) { 2104 mutex_lock(&power_domains->lock); 2105 chv_phy_control_init(display); 2106 mutex_unlock(&power_domains->lock); 2107 assert_isp_power_gated(display); 2108 } else if (display->platform.valleyview) { 2109 mutex_lock(&power_domains->lock); 2110 vlv_cmnlane_wa(display); 2111 mutex_unlock(&power_domains->lock); 2112 assert_ved_power_gated(display); 2113 assert_isp_power_gated(display); 2114 } else if (display->platform.broadwell || display->platform.haswell) { 2115 hsw_assert_cdclk(display); 2116 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); 2117 } else if (display->platform.ivybridge) { 2118 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); 2119 } 2120 2121 /* 2122 * Keep all power wells enabled for any dependent HW access during 2123 * initialization and to make sure we keep BIOS enabled display HW 2124 * resources powered until display HW readout is complete. We drop 2125 * this reference in intel_display_power_enable(). 2126 */ 2127 drm_WARN_ON(display->drm, power_domains->init_wakeref); 2128 power_domains->init_wakeref = 2129 intel_display_power_get(display, POWER_DOMAIN_INIT); 2130 2131 /* Disable power support if the user asked so. */ 2132 if (!display->params.disable_power_well) { 2133 drm_WARN_ON(display->drm, power_domains->disable_wakeref); 2134 display->power.domains.disable_wakeref = intel_display_power_get(display, 2135 POWER_DOMAIN_INIT); 2136 } 2137 intel_power_domains_sync_hw(display); 2138 2139 power_domains->initializing = false; 2140 } 2141 2142 /** 2143 * intel_display_power_init_hw - initialize hardware power domain state 2144 * @display: display device instance 2145 * 2146 * This function initializes the hardware power domain state and enables all 2147 * power wells belonging to the INIT power domain. Power wells in other 2148 * domains (and not in the INIT domain) are referenced or disabled by 2149 * intel_modeset_readout_hw_state(). After that the reference count of each 2150 * power well must match its HW enabled state, see 2151 * intel_power_domains_verify_state(). 2152 * 2153 * It will return with power domains disabled (to be enabled later by 2154 * intel_display_power_enable()) and must be paired with 2155 * intel_display_power_driver_remove(). 2156 */ 2157 void intel_display_power_init_hw(struct intel_display *display) 2158 { 2159 __intel_display_power_init_hw(display, false); 2160 } 2161 2162 /** 2163 * intel_display_power_driver_remove - deinitialize hw power domain state 2164 * @display: display device instance 2165 * 2166 * De-initializes the display power domain HW state. It also ensures that the 2167 * device stays powered up so that the driver can be reloaded. 2168 * 2169 * It must be called with power domains already disabled (after a call to 2170 * intel_display_power_disable()) and must be paired with 2171 * intel_display_power_init_hw(). 2172 */ 2173 void intel_display_power_driver_remove(struct intel_display *display) 2174 { 2175 struct ref_tracker *wakeref __maybe_unused = 2176 fetch_and_zero(&display->power.domains.init_wakeref); 2177 2178 /* Remove the refcount we took to keep power well support disabled. */ 2179 if (!display->params.disable_power_well) 2180 intel_display_power_put(display, POWER_DOMAIN_INIT, 2181 fetch_and_zero(&display->power.domains.disable_wakeref)); 2182 2183 intel_display_power_flush_work_sync(display); 2184 2185 intel_power_domains_verify_state(display); 2186 2187 /* Keep the power well enabled, but cancel its rpm wakeref. */ 2188 intel_display_rpm_put(display, wakeref); 2189 } 2190 2191 /** 2192 * intel_display_power_sanitize_state - sanitize power domains state 2193 * @display: display device instance 2194 * 2195 * Sanitize the power domains state during driver loading and system resume. 2196 * The function will disable all display power wells that BIOS has enabled 2197 * without a user for it (any user for a power well has taken a reference 2198 * on it by the time this function is called, after the state of all the 2199 * pipe, encoder, etc. HW resources have been sanitized). 2200 */ 2201 void intel_display_power_sanitize_state(struct intel_display *display) 2202 { 2203 struct i915_power_domains *power_domains = &display->power.domains; 2204 struct i915_power_well *power_well; 2205 2206 mutex_lock(&power_domains->lock); 2207 2208 for_each_power_well_reverse(display, power_well) { 2209 if (power_well->desc->always_on || power_well->count || 2210 !intel_power_well_is_enabled(display, power_well)) 2211 continue; 2212 2213 drm_dbg_kms(display->drm, 2214 "BIOS left unused %s power well enabled, disabling it\n", 2215 intel_power_well_name(power_well)); 2216 intel_power_well_disable(display, power_well); 2217 } 2218 2219 mutex_unlock(&power_domains->lock); 2220 } 2221 2222 /** 2223 * intel_display_power_enable - enable toggling of display power wells 2224 * @display: display device instance 2225 * 2226 * Enable the ondemand enabling/disabling of the display power wells. Note that 2227 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled 2228 * only at specific points of the display modeset sequence, thus they are not 2229 * affected by the intel_display_power_enable()/disable() calls. The purpose 2230 * of these function is to keep the rest of power wells enabled until the end 2231 * of display HW readout (which will acquire the power references reflecting 2232 * the current HW state). 2233 */ 2234 void intel_display_power_enable(struct intel_display *display) 2235 { 2236 struct ref_tracker *wakeref __maybe_unused = 2237 fetch_and_zero(&display->power.domains.init_wakeref); 2238 2239 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 2240 intel_power_domains_verify_state(display); 2241 } 2242 2243 /** 2244 * intel_display_power_disable - disable toggling of display power wells 2245 * @display: display device instance 2246 * 2247 * Disable the ondemand enabling/disabling of the display power wells. See 2248 * intel_display_power_enable() for which power wells this call controls. 2249 */ 2250 void intel_display_power_disable(struct intel_display *display) 2251 { 2252 struct i915_power_domains *power_domains = &display->power.domains; 2253 2254 drm_WARN_ON(display->drm, power_domains->init_wakeref); 2255 power_domains->init_wakeref = 2256 intel_display_power_get(display, POWER_DOMAIN_INIT); 2257 2258 intel_power_domains_verify_state(display); 2259 } 2260 2261 /** 2262 * intel_power_domains_suspend - suspend power domain state 2263 * @display: display device instance 2264 * @s2idle: specifies whether we go to idle, or deeper sleep 2265 * 2266 * This function prepares the hardware power domain state before entering 2267 * system suspend. 2268 * 2269 * It must be called with power domains already disabled (after a call to 2270 * intel_display_power_disable()) and paired with intel_power_domains_resume(). 2271 */ 2272 static void intel_power_domains_suspend(struct intel_display *display, bool s2idle) 2273 { 2274 struct i915_power_domains *power_domains = &display->power.domains; 2275 struct ref_tracker *wakeref __maybe_unused = 2276 fetch_and_zero(&power_domains->init_wakeref); 2277 2278 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 2279 2280 /* 2281 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 2282 * support don't manually deinit the power domains. This also means the 2283 * DMC firmware will stay active, it will power down any HW 2284 * resources as required and also enable deeper system power states 2285 * that would be blocked if the firmware was inactive. 2286 */ 2287 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle && 2288 intel_dmc_has_payload(display)) { 2289 intel_display_power_flush_work(display); 2290 intel_power_domains_verify_state(display); 2291 return; 2292 } 2293 2294 /* 2295 * Even if power well support was disabled we still want to disable 2296 * power wells if power domains must be deinitialized for suspend. 2297 */ 2298 if (!display->params.disable_power_well) 2299 intel_display_power_put(display, POWER_DOMAIN_INIT, 2300 fetch_and_zero(&display->power.domains.disable_wakeref)); 2301 2302 intel_display_power_flush_work(display); 2303 intel_power_domains_verify_state(display); 2304 2305 if (DISPLAY_VER(display) >= 11) 2306 icl_display_core_uninit(display); 2307 else if (display->platform.geminilake || display->platform.broxton) 2308 bxt_display_core_uninit(display); 2309 else if (DISPLAY_VER(display) == 9) 2310 skl_display_core_uninit(display); 2311 2312 power_domains->display_core_suspended = true; 2313 } 2314 2315 /** 2316 * intel_power_domains_resume - resume power domain state 2317 * @display: display device instance 2318 * 2319 * This function resume the hardware power domain state during system resume. 2320 * 2321 * It will return with power domain support disabled (to be enabled later by 2322 * intel_display_power_enable()) and must be paired with 2323 * intel_power_domains_suspend(). 2324 */ 2325 static void intel_power_domains_resume(struct intel_display *display) 2326 { 2327 struct i915_power_domains *power_domains = &display->power.domains; 2328 2329 if (power_domains->display_core_suspended) { 2330 __intel_display_power_init_hw(display, true); 2331 power_domains->display_core_suspended = false; 2332 } else { 2333 drm_WARN_ON(display->drm, power_domains->init_wakeref); 2334 power_domains->init_wakeref = 2335 intel_display_power_get(display, POWER_DOMAIN_INIT); 2336 } 2337 } 2338 2339 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 2340 2341 static void intel_power_domains_dump_info(struct intel_display *display) 2342 { 2343 struct i915_power_domains *power_domains = &display->power.domains; 2344 struct i915_power_well *power_well; 2345 2346 for_each_power_well(display, power_well) { 2347 enum intel_display_power_domain domain; 2348 2349 drm_dbg_kms(display->drm, "%-25s %d\n", 2350 intel_power_well_name(power_well), intel_power_well_refcount(power_well)); 2351 2352 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2353 drm_dbg_kms(display->drm, " %-23s %d\n", 2354 intel_display_power_domain_str(domain), 2355 power_domains->domain_use_count[domain]); 2356 } 2357 } 2358 2359 /** 2360 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 2361 * @display: display device instance 2362 * 2363 * Verify if the reference count of each power well matches its HW enabled 2364 * state and the total refcount of the domains it belongs to. This must be 2365 * called after modeset HW state sanitization, which is responsible for 2366 * acquiring reference counts for any power wells in use and disabling the 2367 * ones left on by BIOS but not required by any active output. 2368 */ 2369 static void intel_power_domains_verify_state(struct intel_display *display) 2370 { 2371 struct i915_power_domains *power_domains = &display->power.domains; 2372 struct i915_power_well *power_well; 2373 bool dump_domain_info; 2374 2375 mutex_lock(&power_domains->lock); 2376 2377 verify_async_put_domains_state(power_domains); 2378 2379 dump_domain_info = false; 2380 for_each_power_well(display, power_well) { 2381 enum intel_display_power_domain domain; 2382 int domains_count; 2383 bool enabled; 2384 2385 enabled = intel_power_well_is_enabled(display, power_well); 2386 if ((intel_power_well_refcount(power_well) || 2387 intel_power_well_is_always_on(power_well)) != 2388 enabled) 2389 drm_err(display->drm, 2390 "power well %s state mismatch (refcount %d/enabled %d)", 2391 intel_power_well_name(power_well), 2392 intel_power_well_refcount(power_well), enabled); 2393 2394 domains_count = 0; 2395 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2396 domains_count += power_domains->domain_use_count[domain]; 2397 2398 if (intel_power_well_refcount(power_well) != domains_count) { 2399 drm_err(display->drm, 2400 "power well %s refcount/domain refcount mismatch " 2401 "(refcount %d/domains refcount %d)\n", 2402 intel_power_well_name(power_well), 2403 intel_power_well_refcount(power_well), 2404 domains_count); 2405 dump_domain_info = true; 2406 } 2407 } 2408 2409 if (dump_domain_info) { 2410 static bool dumped; 2411 2412 if (!dumped) { 2413 intel_power_domains_dump_info(display); 2414 dumped = true; 2415 } 2416 } 2417 2418 mutex_unlock(&power_domains->lock); 2419 } 2420 2421 #else 2422 2423 static void intel_power_domains_verify_state(struct intel_display *display) 2424 { 2425 } 2426 2427 #endif 2428 2429 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle) 2430 { 2431 intel_power_domains_suspend(display, s2idle); 2432 2433 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || 2434 display->platform.broxton) { 2435 bxt_enable_dc9(display); 2436 } else if (display->platform.haswell || display->platform.broadwell) { 2437 hsw_enable_pc8(display); 2438 } 2439 2440 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2441 if (intel_display_wa(display, INTEL_DISPLAY_WA_14010685332)) 2442 intel_de_rmw(display, SOUTH_CHICKEN1, 2443 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); 2444 } 2445 2446 void intel_display_power_resume_early(struct intel_display *display) 2447 { 2448 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || 2449 display->platform.broxton) { 2450 gen9_sanitize_dc_state(display); 2451 bxt_disable_dc9(display); 2452 } else if (display->platform.haswell || display->platform.broadwell) { 2453 hsw_disable_pc8(display); 2454 } 2455 2456 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2457 if (intel_display_wa(display, INTEL_DISPLAY_WA_14010685332)) 2458 intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); 2459 2460 intel_power_domains_resume(display); 2461 } 2462 2463 void intel_display_power_runtime_suspend(struct intel_display *display) 2464 { 2465 if (DISPLAY_VER(display) >= 11) { 2466 icl_display_core_uninit(display); 2467 bxt_enable_dc9(display); 2468 } else if (display->platform.geminilake || display->platform.broxton) { 2469 bxt_display_core_uninit(display); 2470 bxt_enable_dc9(display); 2471 } else if (display->platform.haswell || display->platform.broadwell) { 2472 hsw_enable_pc8(display); 2473 } 2474 } 2475 2476 void intel_display_power_runtime_resume(struct intel_display *display) 2477 { 2478 struct i915_power_domains *power_domains = &display->power.domains; 2479 2480 if (DISPLAY_VER(display) >= 11) { 2481 bxt_disable_dc9(display); 2482 icl_display_core_init(display, true); 2483 if (intel_dmc_has_payload(display)) { 2484 if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 2485 skl_enable_dc6(display); 2486 else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 2487 gen9_enable_dc5(display); 2488 } 2489 } else if (display->platform.geminilake || display->platform.broxton) { 2490 bxt_disable_dc9(display); 2491 bxt_display_core_init(display, true); 2492 if (intel_dmc_has_payload(display) && 2493 (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) 2494 gen9_enable_dc5(display); 2495 } else if (display->platform.haswell || display->platform.broadwell) { 2496 hsw_disable_pc8(display); 2497 } 2498 } 2499 2500 void intel_display_power_debug(struct intel_display *display, struct seq_file *m) 2501 { 2502 struct i915_power_domains *power_domains = &display->power.domains; 2503 int i; 2504 2505 mutex_lock(&power_domains->lock); 2506 2507 seq_printf(m, "Runtime power status: %s\n", 2508 str_enabled_disabled(!power_domains->init_wakeref)); 2509 2510 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); 2511 for (i = 0; i < power_domains->power_well_count; i++) { 2512 struct i915_power_well *power_well; 2513 enum intel_display_power_domain power_domain; 2514 2515 power_well = &power_domains->power_wells[i]; 2516 seq_printf(m, "%-25s %d\n", intel_power_well_name(power_well), 2517 intel_power_well_refcount(power_well)); 2518 2519 for_each_power_domain(power_domain, intel_power_well_domains(power_well)) 2520 seq_printf(m, " %-23s %d\n", 2521 intel_display_power_domain_str(power_domain), 2522 power_domains->domain_use_count[power_domain]); 2523 } 2524 2525 mutex_unlock(&power_domains->lock); 2526 } 2527 2528 struct intel_ddi_port_domains { 2529 enum port port_start; 2530 enum port port_end; 2531 enum aux_ch aux_ch_start; 2532 enum aux_ch aux_ch_end; 2533 2534 enum intel_display_power_domain ddi_lanes; 2535 enum intel_display_power_domain ddi_io; 2536 enum intel_display_power_domain aux_io; 2537 enum intel_display_power_domain aux_legacy_usbc; 2538 enum intel_display_power_domain aux_tbt; 2539 }; 2540 2541 static const struct intel_ddi_port_domains 2542 i9xx_port_domains[] = { 2543 { 2544 .port_start = PORT_A, 2545 .port_end = PORT_F, 2546 .aux_ch_start = AUX_CH_A, 2547 .aux_ch_end = AUX_CH_F, 2548 2549 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2550 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2551 .aux_io = POWER_DOMAIN_AUX_IO_A, 2552 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2553 .aux_tbt = POWER_DOMAIN_INVALID, 2554 }, 2555 }; 2556 2557 static const struct intel_ddi_port_domains 2558 d11_port_domains[] = { 2559 { 2560 .port_start = PORT_A, 2561 .port_end = PORT_B, 2562 .aux_ch_start = AUX_CH_A, 2563 .aux_ch_end = AUX_CH_B, 2564 2565 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2566 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2567 .aux_io = POWER_DOMAIN_AUX_IO_A, 2568 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2569 .aux_tbt = POWER_DOMAIN_INVALID, 2570 }, { 2571 .port_start = PORT_C, 2572 .port_end = PORT_F, 2573 .aux_ch_start = AUX_CH_C, 2574 .aux_ch_end = AUX_CH_F, 2575 2576 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C, 2577 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C, 2578 .aux_io = POWER_DOMAIN_AUX_IO_C, 2579 .aux_legacy_usbc = POWER_DOMAIN_AUX_C, 2580 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2581 }, 2582 }; 2583 2584 static const struct intel_ddi_port_domains 2585 d12_port_domains[] = { 2586 { 2587 .port_start = PORT_A, 2588 .port_end = PORT_C, 2589 .aux_ch_start = AUX_CH_A, 2590 .aux_ch_end = AUX_CH_C, 2591 2592 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2593 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2594 .aux_io = POWER_DOMAIN_AUX_IO_A, 2595 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2596 .aux_tbt = POWER_DOMAIN_INVALID, 2597 }, { 2598 .port_start = PORT_TC1, 2599 .port_end = PORT_TC6, 2600 .aux_ch_start = AUX_CH_USBC1, 2601 .aux_ch_end = AUX_CH_USBC6, 2602 2603 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2604 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2605 .aux_io = POWER_DOMAIN_INVALID, 2606 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2607 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2608 }, 2609 }; 2610 2611 static const struct intel_ddi_port_domains 2612 d13_port_domains[] = { 2613 { 2614 .port_start = PORT_A, 2615 .port_end = PORT_C, 2616 .aux_ch_start = AUX_CH_A, 2617 .aux_ch_end = AUX_CH_C, 2618 2619 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A, 2620 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A, 2621 .aux_io = POWER_DOMAIN_AUX_IO_A, 2622 .aux_legacy_usbc = POWER_DOMAIN_AUX_A, 2623 .aux_tbt = POWER_DOMAIN_INVALID, 2624 }, { 2625 .port_start = PORT_TC1, 2626 .port_end = PORT_TC4, 2627 .aux_ch_start = AUX_CH_USBC1, 2628 .aux_ch_end = AUX_CH_USBC4, 2629 2630 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1, 2631 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1, 2632 .aux_io = POWER_DOMAIN_INVALID, 2633 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1, 2634 .aux_tbt = POWER_DOMAIN_AUX_TBT1, 2635 }, { 2636 .port_start = PORT_D_XELPD, 2637 .port_end = PORT_E_XELPD, 2638 .aux_ch_start = AUX_CH_D_XELPD, 2639 .aux_ch_end = AUX_CH_E_XELPD, 2640 2641 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D, 2642 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D, 2643 .aux_io = POWER_DOMAIN_AUX_IO_D, 2644 .aux_legacy_usbc = POWER_DOMAIN_AUX_D, 2645 .aux_tbt = POWER_DOMAIN_INVALID, 2646 }, 2647 }; 2648 2649 static void 2650 intel_port_domains_for_platform(struct intel_display *display, 2651 const struct intel_ddi_port_domains **domains, 2652 int *domains_size) 2653 { 2654 if (DISPLAY_VER(display) >= 13) { 2655 *domains = d13_port_domains; 2656 *domains_size = ARRAY_SIZE(d13_port_domains); 2657 } else if (DISPLAY_VER(display) >= 12) { 2658 *domains = d12_port_domains; 2659 *domains_size = ARRAY_SIZE(d12_port_domains); 2660 } else if (DISPLAY_VER(display) >= 11) { 2661 *domains = d11_port_domains; 2662 *domains_size = ARRAY_SIZE(d11_port_domains); 2663 } else { 2664 *domains = i9xx_port_domains; 2665 *domains_size = ARRAY_SIZE(i9xx_port_domains); 2666 } 2667 } 2668 2669 static const struct intel_ddi_port_domains * 2670 intel_port_domains_for_port(struct intel_display *display, enum port port) 2671 { 2672 const struct intel_ddi_port_domains *domains; 2673 int domains_size; 2674 int i; 2675 2676 intel_port_domains_for_platform(display, &domains, &domains_size); 2677 for (i = 0; i < domains_size; i++) 2678 if (port >= domains[i].port_start && port <= domains[i].port_end) 2679 return &domains[i]; 2680 2681 return NULL; 2682 } 2683 2684 enum intel_display_power_domain 2685 intel_display_power_ddi_io_domain(struct intel_display *display, enum port port) 2686 { 2687 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); 2688 2689 if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) 2690 return POWER_DOMAIN_PORT_DDI_IO_A; 2691 2692 return domains->ddi_io + (int)(port - domains->port_start); 2693 } 2694 2695 enum intel_display_power_domain 2696 intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port) 2697 { 2698 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); 2699 2700 if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) 2701 return POWER_DOMAIN_PORT_DDI_LANES_A; 2702 2703 return domains->ddi_lanes + (int)(port - domains->port_start); 2704 } 2705 2706 static const struct intel_ddi_port_domains * 2707 intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch) 2708 { 2709 const struct intel_ddi_port_domains *domains; 2710 int domains_size; 2711 int i; 2712 2713 intel_port_domains_for_platform(display, &domains, &domains_size); 2714 for (i = 0; i < domains_size; i++) 2715 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end) 2716 return &domains[i]; 2717 2718 return NULL; 2719 } 2720 2721 enum intel_display_power_domain 2722 intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch) 2723 { 2724 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2725 2726 if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) 2727 return POWER_DOMAIN_AUX_IO_A; 2728 2729 return domains->aux_io + (int)(aux_ch - domains->aux_ch_start); 2730 } 2731 2732 enum intel_display_power_domain 2733 intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch) 2734 { 2735 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2736 2737 if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) 2738 return POWER_DOMAIN_AUX_A; 2739 2740 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start); 2741 } 2742 2743 enum intel_display_power_domain 2744 intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch) 2745 { 2746 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2747 2748 if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) 2749 return POWER_DOMAIN_AUX_TBT1; 2750 2751 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start); 2752 } 2753