1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/log2.h> 7 #include <linux/math64.h> 8 #include "i915_reg.h" 9 #include "intel_cx0_phy.h" 10 #include "intel_cx0_phy_regs.h" 11 #include "intel_ddi.h" 12 #include "intel_ddi_buf_trans.h" 13 #include "intel_de.h" 14 #include "intel_display_types.h" 15 #include "intel_dp.h" 16 #include "intel_hdmi.h" 17 #include "intel_panel.h" 18 #include "intel_psr.h" 19 #include "intel_tc.h" 20 21 #define MB_WRITE_COMMITTED true 22 #define MB_WRITE_UNCOMMITTED false 23 24 #define for_each_cx0_lane_in_mask(__lane_mask, __lane) \ 25 for ((__lane) = 0; (__lane) < 2; (__lane)++) \ 26 for_each_if((__lane_mask) & BIT(__lane)) 27 28 #define INTEL_CX0_LANE0 BIT(0) 29 #define INTEL_CX0_LANE1 BIT(1) 30 #define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0) 31 32 bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy) 33 { 34 if (IS_METEORLAKE(i915) && (phy < PHY_C)) 35 return true; 36 37 return false; 38 } 39 40 static int lane_mask_to_lane(u8 lane_mask) 41 { 42 if (WARN_ON((lane_mask & ~INTEL_CX0_BOTH_LANES) || 43 hweight8(lane_mask) != 1)) 44 return 0; 45 46 return ilog2(lane_mask); 47 } 48 49 static void 50 assert_dc_off(struct drm_i915_private *i915) 51 { 52 bool enabled; 53 54 enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF); 55 drm_WARN_ON(&i915->drm, !enabled); 56 } 57 58 /* 59 * Prepare HW for CX0 phy transactions. 60 * 61 * It is required that PSR and DC5/6 are disabled before any CX0 message 62 * bus transaction is executed. 63 */ 64 static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder) 65 { 66 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 67 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 68 69 intel_psr_pause(intel_dp); 70 return intel_display_power_get(i915, POWER_DOMAIN_DC_OFF); 71 } 72 73 static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref) 74 { 75 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 76 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 77 78 intel_psr_resume(intel_dp); 79 intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref); 80 } 81 82 static void intel_clear_response_ready_flag(struct drm_i915_private *i915, 83 enum port port, int lane) 84 { 85 intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane), 86 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET); 87 } 88 89 static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane) 90 { 91 enum phy phy = intel_port_to_phy(i915, port); 92 93 intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), 94 XELPDP_PORT_M2P_TRANSACTION_RESET); 95 96 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), 97 XELPDP_PORT_M2P_TRANSACTION_RESET, 98 XELPDP_MSGBUS_TIMEOUT_SLOW)) { 99 drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy)); 100 return; 101 } 102 103 intel_clear_response_ready_flag(i915, port, lane); 104 } 105 106 static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port, 107 int command, int lane, u32 *val) 108 { 109 enum phy phy = intel_port_to_phy(i915, port); 110 111 if (__intel_de_wait_for_register(i915, 112 XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane), 113 XELPDP_PORT_P2M_RESPONSE_READY, 114 XELPDP_PORT_P2M_RESPONSE_READY, 115 XELPDP_MSGBUS_TIMEOUT_FAST_US, 116 XELPDP_MSGBUS_TIMEOUT_SLOW, val)) { 117 drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", 118 phy_name(phy), *val); 119 return -ETIMEDOUT; 120 } 121 122 if (*val & XELPDP_PORT_P2M_ERROR_SET) { 123 drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy), 124 command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val); 125 intel_cx0_bus_reset(i915, port, lane); 126 return -EINVAL; 127 } 128 129 if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) { 130 drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy), 131 command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val); 132 intel_cx0_bus_reset(i915, port, lane); 133 return -EINVAL; 134 } 135 136 return 0; 137 } 138 139 static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port, 140 int lane, u16 addr) 141 { 142 enum phy phy = intel_port_to_phy(i915, port); 143 int ack; 144 u32 val; 145 146 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), 147 XELPDP_PORT_M2P_TRANSACTION_PENDING, 148 XELPDP_MSGBUS_TIMEOUT_SLOW)) { 149 drm_dbg_kms(&i915->drm, 150 "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy)); 151 intel_cx0_bus_reset(i915, port, lane); 152 return -ETIMEDOUT; 153 } 154 155 intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), 156 XELPDP_PORT_M2P_TRANSACTION_PENDING | 157 XELPDP_PORT_M2P_COMMAND_READ | 158 XELPDP_PORT_M2P_ADDRESS(addr)); 159 160 ack = intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_READ_ACK, lane, &val); 161 if (ack < 0) { 162 intel_cx0_bus_reset(i915, port, lane); 163 return ack; 164 } 165 166 intel_clear_response_ready_flag(i915, port, lane); 167 168 return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val); 169 } 170 171 static u8 __intel_cx0_read(struct drm_i915_private *i915, enum port port, 172 int lane, u16 addr) 173 { 174 enum phy phy = intel_port_to_phy(i915, port); 175 int i, status; 176 177 assert_dc_off(i915); 178 179 /* 3 tries is assumed to be enough to read successfully */ 180 for (i = 0; i < 3; i++) { 181 status = __intel_cx0_read_once(i915, port, lane, addr); 182 183 if (status >= 0) 184 return status; 185 } 186 187 drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n", 188 phy_name(phy), addr, i); 189 190 return 0; 191 } 192 193 static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port, 194 u8 lane_mask, u16 addr) 195 { 196 int lane = lane_mask_to_lane(lane_mask); 197 198 return __intel_cx0_read(i915, port, lane, addr); 199 } 200 201 static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port, 202 int lane, u16 addr, u8 data, bool committed) 203 { 204 enum phy phy = intel_port_to_phy(i915, port); 205 u32 val; 206 207 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), 208 XELPDP_PORT_M2P_TRANSACTION_PENDING, 209 XELPDP_MSGBUS_TIMEOUT_SLOW)) { 210 drm_dbg_kms(&i915->drm, 211 "PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy)); 212 intel_cx0_bus_reset(i915, port, lane); 213 return -ETIMEDOUT; 214 } 215 216 intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), 217 XELPDP_PORT_M2P_TRANSACTION_PENDING | 218 (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED : 219 XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) | 220 XELPDP_PORT_M2P_DATA(data) | 221 XELPDP_PORT_M2P_ADDRESS(addr)); 222 223 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), 224 XELPDP_PORT_M2P_TRANSACTION_PENDING, 225 XELPDP_MSGBUS_TIMEOUT_SLOW)) { 226 drm_dbg_kms(&i915->drm, 227 "PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy)); 228 intel_cx0_bus_reset(i915, port, lane); 229 return -ETIMEDOUT; 230 } 231 232 if (committed) { 233 if (intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val) < 0) { 234 intel_cx0_bus_reset(i915, port, lane); 235 return -EINVAL; 236 } 237 } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) & 238 XELPDP_PORT_P2M_ERROR_SET)) { 239 drm_dbg_kms(&i915->drm, 240 "PHY %c Error occurred during write command.\n", phy_name(phy)); 241 intel_cx0_bus_reset(i915, port, lane); 242 return -EINVAL; 243 } 244 245 intel_clear_response_ready_flag(i915, port, lane); 246 247 return 0; 248 } 249 250 static void __intel_cx0_write(struct drm_i915_private *i915, enum port port, 251 int lane, u16 addr, u8 data, bool committed) 252 { 253 enum phy phy = intel_port_to_phy(i915, port); 254 int i, status; 255 256 assert_dc_off(i915); 257 258 /* 3 tries is assumed to be enough to write successfully */ 259 for (i = 0; i < 3; i++) { 260 status = __intel_cx0_write_once(i915, port, lane, addr, data, committed); 261 262 if (status == 0) 263 return; 264 } 265 266 drm_err_once(&i915->drm, 267 "PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i); 268 } 269 270 static void intel_cx0_write(struct drm_i915_private *i915, enum port port, 271 u8 lane_mask, u16 addr, u8 data, bool committed) 272 { 273 int lane; 274 275 for_each_cx0_lane_in_mask(lane_mask, lane) 276 __intel_cx0_write(i915, port, lane, addr, data, committed); 277 } 278 279 static void intel_c20_sram_write(struct drm_i915_private *i915, enum port port, 280 int lane, u16 addr, u16 data) 281 { 282 assert_dc_off(i915); 283 284 intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0); 285 intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0); 286 287 intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, data >> 8, 0); 288 intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1); 289 } 290 291 static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port port, 292 int lane, u16 addr) 293 { 294 u16 val; 295 296 assert_dc_off(i915); 297 298 intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0); 299 intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1); 300 301 val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H); 302 val <<= 8; 303 val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L); 304 305 return val; 306 } 307 308 static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port, 309 int lane, u16 addr, u8 clear, u8 set, bool committed) 310 { 311 u8 old, val; 312 313 old = __intel_cx0_read(i915, port, lane, addr); 314 val = (old & ~clear) | set; 315 316 if (val != old) 317 __intel_cx0_write(i915, port, lane, addr, val, committed); 318 } 319 320 static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port, 321 u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed) 322 { 323 u8 lane; 324 325 for_each_cx0_lane_in_mask(lane_mask, lane) 326 __intel_cx0_rmw(i915, port, lane, addr, clear, set, committed); 327 } 328 329 static u8 intel_c10_get_tx_vboost_lvl(const struct intel_crtc_state *crtc_state) 330 { 331 if (intel_crtc_has_dp_encoder(crtc_state)) { 332 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 333 (crtc_state->port_clock == 540000 || 334 crtc_state->port_clock == 810000)) 335 return 5; 336 else 337 return 4; 338 } else { 339 return 5; 340 } 341 } 342 343 static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state) 344 { 345 if (intel_crtc_has_dp_encoder(crtc_state)) { 346 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 347 (crtc_state->port_clock == 540000 || 348 crtc_state->port_clock == 810000)) 349 return 5; 350 else 351 return 2; 352 } else { 353 return 6; 354 } 355 } 356 357 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, 358 const struct intel_crtc_state *crtc_state) 359 { 360 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 361 const struct intel_ddi_buf_trans *trans; 362 enum phy phy = intel_port_to_phy(i915, encoder->port); 363 intel_wakeref_t wakeref; 364 int n_entries, ln; 365 366 wakeref = intel_cx0_phy_transaction_begin(encoder); 367 368 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 369 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) { 370 intel_cx0_phy_transaction_end(encoder, wakeref); 371 return; 372 } 373 374 if (intel_is_c10phy(i915, phy)) { 375 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), 376 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); 377 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CMN(3), 378 C10_CMN3_TXVBOOST_MASK, 379 C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)), 380 MB_WRITE_UNCOMMITTED); 381 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_TX(1), 382 C10_TX1_TERMCTL_MASK, 383 C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)), 384 MB_WRITE_COMMITTED); 385 } 386 387 for (ln = 0; ln < crtc_state->lane_count; ln++) { 388 int level = intel_ddi_level(encoder, crtc_state, ln); 389 int lane, tx; 390 391 lane = ln / 2; 392 tx = ln % 2; 393 394 intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 0), 395 C10_PHY_OVRD_LEVEL_MASK, 396 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor), 397 MB_WRITE_COMMITTED); 398 intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 1), 399 C10_PHY_OVRD_LEVEL_MASK, 400 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing), 401 MB_WRITE_COMMITTED); 402 intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 2), 403 C10_PHY_OVRD_LEVEL_MASK, 404 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor), 405 MB_WRITE_COMMITTED); 406 } 407 408 /* Write Override enables in 0xD71 */ 409 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD, 410 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2, 411 MB_WRITE_COMMITTED); 412 413 if (intel_is_c10phy(i915, phy)) 414 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), 415 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); 416 417 intel_cx0_phy_transaction_end(encoder, wakeref); 418 } 419 420 /* 421 * Basic DP link rates with 38.4 MHz reference clock. 422 * Note: The tables below are with SSC. In non-ssc 423 * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be 424 * programmed 0. 425 */ 426 427 static const struct intel_c10pll_state mtl_c10_dp_rbr = { 428 .clock = 162000, 429 .tx = 0x10, 430 .cmn = 0x21, 431 .pll[0] = 0xB4, 432 .pll[1] = 0, 433 .pll[2] = 0x30, 434 .pll[3] = 0x1, 435 .pll[4] = 0x26, 436 .pll[5] = 0x0C, 437 .pll[6] = 0x98, 438 .pll[7] = 0x46, 439 .pll[8] = 0x1, 440 .pll[9] = 0x1, 441 .pll[10] = 0, 442 .pll[11] = 0, 443 .pll[12] = 0xC0, 444 .pll[13] = 0, 445 .pll[14] = 0, 446 .pll[15] = 0x2, 447 .pll[16] = 0x84, 448 .pll[17] = 0x4F, 449 .pll[18] = 0xE5, 450 .pll[19] = 0x23, 451 }; 452 453 static const struct intel_c10pll_state mtl_c10_edp_r216 = { 454 .clock = 216000, 455 .tx = 0x10, 456 .cmn = 0x21, 457 .pll[0] = 0x4, 458 .pll[1] = 0, 459 .pll[2] = 0xA2, 460 .pll[3] = 0x1, 461 .pll[4] = 0x33, 462 .pll[5] = 0x10, 463 .pll[6] = 0x75, 464 .pll[7] = 0xB3, 465 .pll[8] = 0x1, 466 .pll[9] = 0x1, 467 .pll[10] = 0, 468 .pll[11] = 0, 469 .pll[12] = 0, 470 .pll[13] = 0, 471 .pll[14] = 0, 472 .pll[15] = 0x2, 473 .pll[16] = 0x85, 474 .pll[17] = 0x0F, 475 .pll[18] = 0xE6, 476 .pll[19] = 0x23, 477 }; 478 479 static const struct intel_c10pll_state mtl_c10_edp_r243 = { 480 .clock = 243000, 481 .tx = 0x10, 482 .cmn = 0x21, 483 .pll[0] = 0x34, 484 .pll[1] = 0, 485 .pll[2] = 0xDA, 486 .pll[3] = 0x1, 487 .pll[4] = 0x39, 488 .pll[5] = 0x12, 489 .pll[6] = 0xE3, 490 .pll[7] = 0xE9, 491 .pll[8] = 0x1, 492 .pll[9] = 0x1, 493 .pll[10] = 0, 494 .pll[11] = 0, 495 .pll[12] = 0x20, 496 .pll[13] = 0, 497 .pll[14] = 0, 498 .pll[15] = 0x2, 499 .pll[16] = 0x85, 500 .pll[17] = 0x8F, 501 .pll[18] = 0xE6, 502 .pll[19] = 0x23, 503 }; 504 505 static const struct intel_c10pll_state mtl_c10_dp_hbr1 = { 506 .clock = 270000, 507 .tx = 0x10, 508 .cmn = 0x21, 509 .pll[0] = 0xF4, 510 .pll[1] = 0, 511 .pll[2] = 0xF8, 512 .pll[3] = 0x0, 513 .pll[4] = 0x20, 514 .pll[5] = 0x0A, 515 .pll[6] = 0x29, 516 .pll[7] = 0x10, 517 .pll[8] = 0x1, /* Verify */ 518 .pll[9] = 0x1, 519 .pll[10] = 0, 520 .pll[11] = 0, 521 .pll[12] = 0xA0, 522 .pll[13] = 0, 523 .pll[14] = 0, 524 .pll[15] = 0x1, 525 .pll[16] = 0x84, 526 .pll[17] = 0x4F, 527 .pll[18] = 0xE5, 528 .pll[19] = 0x23, 529 }; 530 531 static const struct intel_c10pll_state mtl_c10_edp_r324 = { 532 .clock = 324000, 533 .tx = 0x10, 534 .cmn = 0x21, 535 .pll[0] = 0xB4, 536 .pll[1] = 0, 537 .pll[2] = 0x30, 538 .pll[3] = 0x1, 539 .pll[4] = 0x26, 540 .pll[5] = 0x0C, 541 .pll[6] = 0x98, 542 .pll[7] = 0x46, 543 .pll[8] = 0x1, 544 .pll[9] = 0x1, 545 .pll[10] = 0, 546 .pll[11] = 0, 547 .pll[12] = 0xC0, 548 .pll[13] = 0, 549 .pll[14] = 0, 550 .pll[15] = 0x1, 551 .pll[16] = 0x85, 552 .pll[17] = 0x4F, 553 .pll[18] = 0xE6, 554 .pll[19] = 0x23, 555 }; 556 557 static const struct intel_c10pll_state mtl_c10_edp_r432 = { 558 .clock = 432000, 559 .tx = 0x10, 560 .cmn = 0x21, 561 .pll[0] = 0x4, 562 .pll[1] = 0, 563 .pll[2] = 0xA2, 564 .pll[3] = 0x1, 565 .pll[4] = 0x33, 566 .pll[5] = 0x10, 567 .pll[6] = 0x75, 568 .pll[7] = 0xB3, 569 .pll[8] = 0x1, 570 .pll[9] = 0x1, 571 .pll[10] = 0, 572 .pll[11] = 0, 573 .pll[12] = 0, 574 .pll[13] = 0, 575 .pll[14] = 0, 576 .pll[15] = 0x1, 577 .pll[16] = 0x85, 578 .pll[17] = 0x0F, 579 .pll[18] = 0xE6, 580 .pll[19] = 0x23, 581 }; 582 583 static const struct intel_c10pll_state mtl_c10_dp_hbr2 = { 584 .clock = 540000, 585 .tx = 0x10, 586 .cmn = 0x21, 587 .pll[0] = 0xF4, 588 .pll[1] = 0, 589 .pll[2] = 0xF8, 590 .pll[3] = 0, 591 .pll[4] = 0x20, 592 .pll[5] = 0x0A, 593 .pll[6] = 0x29, 594 .pll[7] = 0x10, 595 .pll[8] = 0x1, 596 .pll[9] = 0x1, 597 .pll[10] = 0, 598 .pll[11] = 0, 599 .pll[12] = 0xA0, 600 .pll[13] = 0, 601 .pll[14] = 0, 602 .pll[15] = 0, 603 .pll[16] = 0x84, 604 .pll[17] = 0x4F, 605 .pll[18] = 0xE5, 606 .pll[19] = 0x23, 607 }; 608 609 static const struct intel_c10pll_state mtl_c10_edp_r675 = { 610 .clock = 675000, 611 .tx = 0x10, 612 .cmn = 0x21, 613 .pll[0] = 0xB4, 614 .pll[1] = 0, 615 .pll[2] = 0x3E, 616 .pll[3] = 0x1, 617 .pll[4] = 0xA8, 618 .pll[5] = 0x0C, 619 .pll[6] = 0x33, 620 .pll[7] = 0x54, 621 .pll[8] = 0x1, 622 .pll[9] = 0x1, 623 .pll[10] = 0, 624 .pll[11] = 0, 625 .pll[12] = 0xC8, 626 .pll[13] = 0, 627 .pll[14] = 0, 628 .pll[15] = 0, 629 .pll[16] = 0x85, 630 .pll[17] = 0x8F, 631 .pll[18] = 0xE6, 632 .pll[19] = 0x23, 633 }; 634 635 static const struct intel_c10pll_state mtl_c10_dp_hbr3 = { 636 .clock = 810000, 637 .tx = 0x10, 638 .cmn = 0x21, 639 .pll[0] = 0x34, 640 .pll[1] = 0, 641 .pll[2] = 0x84, 642 .pll[3] = 0x1, 643 .pll[4] = 0x30, 644 .pll[5] = 0x0F, 645 .pll[6] = 0x3D, 646 .pll[7] = 0x98, 647 .pll[8] = 0x1, 648 .pll[9] = 0x1, 649 .pll[10] = 0, 650 .pll[11] = 0, 651 .pll[12] = 0xF0, 652 .pll[13] = 0, 653 .pll[14] = 0, 654 .pll[15] = 0, 655 .pll[16] = 0x84, 656 .pll[17] = 0x0F, 657 .pll[18] = 0xE5, 658 .pll[19] = 0x23, 659 }; 660 661 static const struct intel_c10pll_state * const mtl_c10_dp_tables[] = { 662 &mtl_c10_dp_rbr, 663 &mtl_c10_dp_hbr1, 664 &mtl_c10_dp_hbr2, 665 &mtl_c10_dp_hbr3, 666 NULL, 667 }; 668 669 static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = { 670 &mtl_c10_dp_rbr, 671 &mtl_c10_edp_r216, 672 &mtl_c10_edp_r243, 673 &mtl_c10_dp_hbr1, 674 &mtl_c10_edp_r324, 675 &mtl_c10_edp_r432, 676 &mtl_c10_dp_hbr2, 677 &mtl_c10_edp_r675, 678 &mtl_c10_dp_hbr3, 679 NULL, 680 }; 681 682 /* C20 basic DP 1.4 tables */ 683 static const struct intel_c20pll_state mtl_c20_dp_rbr = { 684 .link_bit_rate = 162000, 685 .clock = 162000, 686 .tx = { 0xbe88, /* tx cfg0 */ 687 0x5800, /* tx cfg1 */ 688 0x0000, /* tx cfg2 */ 689 }, 690 .cmn = {0x0500, /* cmn cfg0*/ 691 0x0005, /* cmn cfg1 */ 692 0x0000, /* cmn cfg2 */ 693 0x0000, /* cmn cfg3 */ 694 }, 695 .mpllb = { 0x50a8, /* mpllb cfg0 */ 696 0x2120, /* mpllb cfg1 */ 697 0xcd9a, /* mpllb cfg2 */ 698 0xbfc1, /* mpllb cfg3 */ 699 0x5ab8, /* mpllb cfg4 */ 700 0x4c34, /* mpllb cfg5 */ 701 0x2000, /* mpllb cfg6 */ 702 0x0001, /* mpllb cfg7 */ 703 0x6000, /* mpllb cfg8 */ 704 0x0000, /* mpllb cfg9 */ 705 0x0000, /* mpllb cfg10 */ 706 }, 707 }; 708 709 static const struct intel_c20pll_state mtl_c20_dp_hbr1 = { 710 .link_bit_rate = 270000, 711 .clock = 270000, 712 .tx = { 0xbe88, /* tx cfg0 */ 713 0x4800, /* tx cfg1 */ 714 0x0000, /* tx cfg2 */ 715 }, 716 .cmn = {0x0500, /* cmn cfg0*/ 717 0x0005, /* cmn cfg1 */ 718 0x0000, /* cmn cfg2 */ 719 0x0000, /* cmn cfg3 */ 720 }, 721 .mpllb = { 0x308c, /* mpllb cfg0 */ 722 0x2110, /* mpllb cfg1 */ 723 0xcc9c, /* mpllb cfg2 */ 724 0xbfc1, /* mpllb cfg3 */ 725 0x4b9a, /* mpllb cfg4 */ 726 0x3f81, /* mpllb cfg5 */ 727 0x2000, /* mpllb cfg6 */ 728 0x0001, /* mpllb cfg7 */ 729 0x5000, /* mpllb cfg8 */ 730 0x0000, /* mpllb cfg9 */ 731 0x0000, /* mpllb cfg10 */ 732 }, 733 }; 734 735 static const struct intel_c20pll_state mtl_c20_dp_hbr2 = { 736 .link_bit_rate = 540000, 737 .clock = 540000, 738 .tx = { 0xbe88, /* tx cfg0 */ 739 0x4800, /* tx cfg1 */ 740 0x0000, /* tx cfg2 */ 741 }, 742 .cmn = {0x0500, /* cmn cfg0*/ 743 0x0005, /* cmn cfg1 */ 744 0x0000, /* cmn cfg2 */ 745 0x0000, /* cmn cfg3 */ 746 }, 747 .mpllb = { 0x108c, /* mpllb cfg0 */ 748 0x2108, /* mpllb cfg1 */ 749 0xcc9c, /* mpllb cfg2 */ 750 0xbfc1, /* mpllb cfg3 */ 751 0x4b9a, /* mpllb cfg4 */ 752 0x3f81, /* mpllb cfg5 */ 753 0x2000, /* mpllb cfg6 */ 754 0x0001, /* mpllb cfg7 */ 755 0x5000, /* mpllb cfg8 */ 756 0x0000, /* mpllb cfg9 */ 757 0x0000, /* mpllb cfg10 */ 758 }, 759 }; 760 761 static const struct intel_c20pll_state mtl_c20_dp_hbr3 = { 762 .link_bit_rate = 810000, 763 .clock = 810000, 764 .tx = { 0xbe88, /* tx cfg0 */ 765 0x4800, /* tx cfg1 */ 766 0x0000, /* tx cfg2 */ 767 }, 768 .cmn = {0x0500, /* cmn cfg0*/ 769 0x0005, /* cmn cfg1 */ 770 0x0000, /* cmn cfg2 */ 771 0x0000, /* cmn cfg3 */ 772 }, 773 .mpllb = { 0x10d2, /* mpllb cfg0 */ 774 0x2108, /* mpllb cfg1 */ 775 0x8d98, /* mpllb cfg2 */ 776 0xbfc1, /* mpllb cfg3 */ 777 0x7166, /* mpllb cfg4 */ 778 0x5f42, /* mpllb cfg5 */ 779 0x2000, /* mpllb cfg6 */ 780 0x0001, /* mpllb cfg7 */ 781 0x7800, /* mpllb cfg8 */ 782 0x0000, /* mpllb cfg9 */ 783 0x0000, /* mpllb cfg10 */ 784 }, 785 }; 786 787 /* C20 basic DP 2.0 tables */ 788 static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = { 789 .link_bit_rate = 1000000, /* 10 Gbps */ 790 .clock = 312500, 791 .tx = { 0xbe21, /* tx cfg0 */ 792 0x4800, /* tx cfg1 */ 793 0x0000, /* tx cfg2 */ 794 }, 795 .cmn = {0x0500, /* cmn cfg0*/ 796 0x0005, /* cmn cfg1 */ 797 0x0000, /* cmn cfg2 */ 798 0x0000, /* cmn cfg3 */ 799 }, 800 .mplla = { 0x3104, /* mplla cfg0 */ 801 0xd105, /* mplla cfg1 */ 802 0xc025, /* mplla cfg2 */ 803 0xc025, /* mplla cfg3 */ 804 0x8c00, /* mplla cfg4 */ 805 0x759a, /* mplla cfg5 */ 806 0x4000, /* mplla cfg6 */ 807 0x0003, /* mplla cfg7 */ 808 0x3555, /* mplla cfg8 */ 809 0x0001, /* mplla cfg9 */ 810 }, 811 }; 812 813 static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = { 814 .link_bit_rate = 1350000, /* 13.5 Gbps */ 815 .clock = 421875, 816 .tx = { 0xbea0, /* tx cfg0 */ 817 0x4800, /* tx cfg1 */ 818 0x0000, /* tx cfg2 */ 819 }, 820 .cmn = {0x0500, /* cmn cfg0*/ 821 0x0005, /* cmn cfg1 */ 822 0x0000, /* cmn cfg2 */ 823 0x0000, /* cmn cfg3 */ 824 }, 825 .mpllb = { 0x015f, /* mpllb cfg0 */ 826 0x2205, /* mpllb cfg1 */ 827 0x1b17, /* mpllb cfg2 */ 828 0xffc1, /* mpllb cfg3 */ 829 0xe100, /* mpllb cfg4 */ 830 0xbd00, /* mpllb cfg5 */ 831 0x2000, /* mpllb cfg6 */ 832 0x0001, /* mpllb cfg7 */ 833 0x4800, /* mpllb cfg8 */ 834 0x0000, /* mpllb cfg9 */ 835 0x0000, /* mpllb cfg10 */ 836 }, 837 }; 838 839 static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = { 840 .link_bit_rate = 2000000, /* 20 Gbps */ 841 .clock = 625000, 842 .tx = { 0xbe20, /* tx cfg0 */ 843 0x4800, /* tx cfg1 */ 844 0x0000, /* tx cfg2 */ 845 }, 846 .cmn = {0x0500, /* cmn cfg0*/ 847 0x0005, /* cmn cfg1 */ 848 0x0000, /* cmn cfg2 */ 849 0x0000, /* cmn cfg3 */ 850 }, 851 .mplla = { 0x3104, /* mplla cfg0 */ 852 0xd105, /* mplla cfg1 */ 853 0xc025, /* mplla cfg2 */ 854 0xc025, /* mplla cfg3 */ 855 0xa6ab, /* mplla cfg4 */ 856 0x8c00, /* mplla cfg5 */ 857 0x4000, /* mplla cfg6 */ 858 0x0003, /* mplla cfg7 */ 859 0x3555, /* mplla cfg8 */ 860 0x0001, /* mplla cfg9 */ 861 }, 862 }; 863 864 static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = { 865 &mtl_c20_dp_rbr, 866 &mtl_c20_dp_hbr1, 867 &mtl_c20_dp_hbr2, 868 &mtl_c20_dp_hbr3, 869 &mtl_c20_dp_uhbr10, 870 &mtl_c20_dp_uhbr13_5, 871 &mtl_c20_dp_uhbr20, 872 NULL, 873 }; 874 875 /* 876 * HDMI link rates with 38.4 MHz reference clock. 877 */ 878 879 static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = { 880 .clock = 25200, 881 .tx = 0x10, 882 .cmn = 0x1, 883 .pll[0] = 0x4, 884 .pll[1] = 0, 885 .pll[2] = 0xB2, 886 .pll[3] = 0, 887 .pll[4] = 0, 888 .pll[5] = 0, 889 .pll[6] = 0, 890 .pll[7] = 0, 891 .pll[8] = 0x20, 892 .pll[9] = 0x1, 893 .pll[10] = 0, 894 .pll[11] = 0, 895 .pll[12] = 0, 896 .pll[13] = 0, 897 .pll[14] = 0, 898 .pll[15] = 0xD, 899 .pll[16] = 0x6, 900 .pll[17] = 0x8F, 901 .pll[18] = 0x84, 902 .pll[19] = 0x23, 903 }; 904 905 static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = { 906 .clock = 27000, 907 .tx = 0x10, 908 .cmn = 0x1, 909 .pll[0] = 0x34, 910 .pll[1] = 0, 911 .pll[2] = 0xC0, 912 .pll[3] = 0, 913 .pll[4] = 0, 914 .pll[5] = 0, 915 .pll[6] = 0, 916 .pll[7] = 0, 917 .pll[8] = 0x20, 918 .pll[9] = 0x1, 919 .pll[10] = 0, 920 .pll[11] = 0, 921 .pll[12] = 0x80, 922 .pll[13] = 0, 923 .pll[14] = 0, 924 .pll[15] = 0xD, 925 .pll[16] = 0x6, 926 .pll[17] = 0xCF, 927 .pll[18] = 0x84, 928 .pll[19] = 0x23, 929 }; 930 931 static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = { 932 .clock = 74250, 933 .tx = 0x10, 934 .cmn = 0x1, 935 .pll[0] = 0xF4, 936 .pll[1] = 0, 937 .pll[2] = 0x7A, 938 .pll[3] = 0, 939 .pll[4] = 0, 940 .pll[5] = 0, 941 .pll[6] = 0, 942 .pll[7] = 0, 943 .pll[8] = 0x20, 944 .pll[9] = 0x1, 945 .pll[10] = 0, 946 .pll[11] = 0, 947 .pll[12] = 0x58, 948 .pll[13] = 0, 949 .pll[14] = 0, 950 .pll[15] = 0xB, 951 .pll[16] = 0x6, 952 .pll[17] = 0xF, 953 .pll[18] = 0x85, 954 .pll[19] = 0x23, 955 }; 956 957 static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = { 958 .clock = 148500, 959 .tx = 0x10, 960 .cmn = 0x1, 961 .pll[0] = 0xF4, 962 .pll[1] = 0, 963 .pll[2] = 0x7A, 964 .pll[3] = 0, 965 .pll[4] = 0, 966 .pll[5] = 0, 967 .pll[6] = 0, 968 .pll[7] = 0, 969 .pll[8] = 0x20, 970 .pll[9] = 0x1, 971 .pll[10] = 0, 972 .pll[11] = 0, 973 .pll[12] = 0x58, 974 .pll[13] = 0, 975 .pll[14] = 0, 976 .pll[15] = 0xA, 977 .pll[16] = 0x6, 978 .pll[17] = 0xF, 979 .pll[18] = 0x85, 980 .pll[19] = 0x23, 981 }; 982 983 static const struct intel_c10pll_state mtl_c10_hdmi_594 = { 984 .clock = 594000, 985 .tx = 0x10, 986 .cmn = 0x1, 987 .pll[0] = 0xF4, 988 .pll[1] = 0, 989 .pll[2] = 0x7A, 990 .pll[3] = 0, 991 .pll[4] = 0, 992 .pll[5] = 0, 993 .pll[6] = 0, 994 .pll[7] = 0, 995 .pll[8] = 0x20, 996 .pll[9] = 0x1, 997 .pll[10] = 0, 998 .pll[11] = 0, 999 .pll[12] = 0x58, 1000 .pll[13] = 0, 1001 .pll[14] = 0, 1002 .pll[15] = 0x8, 1003 .pll[16] = 0x6, 1004 .pll[17] = 0xF, 1005 .pll[18] = 0x85, 1006 .pll[19] = 0x23, 1007 }; 1008 1009 /* Precomputed C10 HDMI PLL tables */ 1010 static const struct intel_c10pll_state mtl_c10_hdmi_27027 = { 1011 .clock = 27027, 1012 .tx = 0x10, 1013 .cmn = 0x1, 1014 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00, 1015 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1016 .pll[10] = 0xFF, .pll[11] = 0xCC, .pll[12] = 0x9C, .pll[13] = 0xCB, .pll[14] = 0xCC, 1017 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1018 }; 1019 1020 static const struct intel_c10pll_state mtl_c10_hdmi_28320 = { 1021 .clock = 28320, 1022 .tx = 0x10, 1023 .cmn = 0x1, 1024 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00, 1025 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1026 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00, 1027 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1028 }; 1029 1030 static const struct intel_c10pll_state mtl_c10_hdmi_30240 = { 1031 .clock = 30240, 1032 .tx = 0x10, 1033 .cmn = 0x1, 1034 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00, 1035 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1036 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00, 1037 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1038 }; 1039 1040 static const struct intel_c10pll_state mtl_c10_hdmi_31500 = { 1041 .clock = 31500, 1042 .tx = 0x10, 1043 .cmn = 0x1, 1044 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00, 1045 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1046 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xA0, .pll[13] = 0x00, .pll[14] = 0x00, 1047 .pll[15] = 0x0C, .pll[16] = 0x09, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1048 }; 1049 1050 static const struct intel_c10pll_state mtl_c10_hdmi_36000 = { 1051 .clock = 36000, 1052 .tx = 0x10, 1053 .cmn = 0x1, 1054 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00, 1055 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1056 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00, 1057 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1058 }; 1059 1060 static const struct intel_c10pll_state mtl_c10_hdmi_40000 = { 1061 .clock = 40000, 1062 .tx = 0x10, 1063 .cmn = 0x1, 1064 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00, 1065 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1066 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x55, .pll[13] = 0x55, .pll[14] = 0x55, 1067 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1068 }; 1069 1070 static const struct intel_c10pll_state mtl_c10_hdmi_49500 = { 1071 .clock = 49500, 1072 .tx = 0x10, 1073 .cmn = 0x1, 1074 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00, 1075 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1076 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00, 1077 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1078 }; 1079 1080 static const struct intel_c10pll_state mtl_c10_hdmi_50000 = { 1081 .clock = 50000, 1082 .tx = 0x10, 1083 .cmn = 0x1, 1084 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00, 1085 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1086 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x2A, .pll[13] = 0xA9, .pll[14] = 0xAA, 1087 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1088 }; 1089 1090 static const struct intel_c10pll_state mtl_c10_hdmi_57284 = { 1091 .clock = 57284, 1092 .tx = 0x10, 1093 .cmn = 0x1, 1094 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00, 1095 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1096 .pll[10] = 0xFF, .pll[11] = 0x77, .pll[12] = 0x57, .pll[13] = 0x77, .pll[14] = 0x77, 1097 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1098 }; 1099 1100 static const struct intel_c10pll_state mtl_c10_hdmi_58000 = { 1101 .clock = 58000, 1102 .tx = 0x10, 1103 .cmn = 0x1, 1104 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00, 1105 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1106 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xD5, .pll[13] = 0x55, .pll[14] = 0x55, 1107 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1108 }; 1109 1110 static const struct intel_c10pll_state mtl_c10_hdmi_65000 = { 1111 .clock = 65000, 1112 .tx = 0x10, 1113 .cmn = 0x1, 1114 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00, 1115 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1116 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xB5, .pll[13] = 0x55, .pll[14] = 0x55, 1117 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1118 }; 1119 1120 static const struct intel_c10pll_state mtl_c10_hdmi_71000 = { 1121 .clock = 71000, 1122 .tx = 0x10, 1123 .cmn = 0x1, 1124 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00, 1125 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1126 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55, 1127 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1128 }; 1129 1130 static const struct intel_c10pll_state mtl_c10_hdmi_74176 = { 1131 .clock = 74176, 1132 .tx = 0x10, 1133 .cmn = 0x1, 1134 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, 1135 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1136 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44, 1137 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1138 }; 1139 1140 static const struct intel_c10pll_state mtl_c10_hdmi_75000 = { 1141 .clock = 75000, 1142 .tx = 0x10, 1143 .cmn = 0x1, 1144 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00, 1145 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1146 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00, 1147 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1148 }; 1149 1150 static const struct intel_c10pll_state mtl_c10_hdmi_78750 = { 1151 .clock = 78750, 1152 .tx = 0x10, 1153 .cmn = 0x1, 1154 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00, 1155 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1156 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x08, .pll[13] = 0x00, .pll[14] = 0x00, 1157 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1158 }; 1159 1160 static const struct intel_c10pll_state mtl_c10_hdmi_85500 = { 1161 .clock = 85500, 1162 .tx = 0x10, 1163 .cmn = 0x1, 1164 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00, 1165 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1166 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x10, .pll[13] = 0x00, .pll[14] = 0x00, 1167 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1168 }; 1169 1170 static const struct intel_c10pll_state mtl_c10_hdmi_88750 = { 1171 .clock = 88750, 1172 .tx = 0x10, 1173 .cmn = 0x1, 1174 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00, 1175 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1176 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x72, .pll[13] = 0xA9, .pll[14] = 0xAA, 1177 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1178 }; 1179 1180 static const struct intel_c10pll_state mtl_c10_hdmi_106500 = { 1181 .clock = 106500, 1182 .tx = 0x10, 1183 .cmn = 0x1, 1184 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00, 1185 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1186 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xF0, .pll[13] = 0x00, .pll[14] = 0x00, 1187 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1188 }; 1189 1190 static const struct intel_c10pll_state mtl_c10_hdmi_108000 = { 1191 .clock = 108000, 1192 .tx = 0x10, 1193 .cmn = 0x1, 1194 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00, 1195 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1196 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x80, .pll[13] = 0x00, .pll[14] = 0x00, 1197 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1198 }; 1199 1200 static const struct intel_c10pll_state mtl_c10_hdmi_115500 = { 1201 .clock = 115500, 1202 .tx = 0x10, 1203 .cmn = 0x1, 1204 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00, 1205 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1206 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00, 1207 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1208 }; 1209 1210 static const struct intel_c10pll_state mtl_c10_hdmi_119000 = { 1211 .clock = 119000, 1212 .tx = 0x10, 1213 .cmn = 0x1, 1214 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00, 1215 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1216 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55, 1217 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1218 }; 1219 1220 static const struct intel_c10pll_state mtl_c10_hdmi_135000 = { 1221 .clock = 135000, 1222 .tx = 0x10, 1223 .cmn = 0x1, 1224 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00, 1225 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1226 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00, 1227 .pll[15] = 0x0A, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1228 }; 1229 1230 static const struct intel_c10pll_state mtl_c10_hdmi_138500 = { 1231 .clock = 138500, 1232 .tx = 0x10, 1233 .cmn = 0x1, 1234 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00, 1235 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1236 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x22, .pll[13] = 0xA9, .pll[14] = 0xAA, 1237 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1238 }; 1239 1240 static const struct intel_c10pll_state mtl_c10_hdmi_147160 = { 1241 .clock = 147160, 1242 .tx = 0x10, 1243 .cmn = 0x1, 1244 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00, 1245 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1246 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xA5, .pll[13] = 0x55, .pll[14] = 0x55, 1247 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1248 }; 1249 1250 static const struct intel_c10pll_state mtl_c10_hdmi_148352 = { 1251 .clock = 148352, 1252 .tx = 0x10, 1253 .cmn = 0x1, 1254 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, 1255 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1256 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44, 1257 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1258 }; 1259 1260 static const struct intel_c10pll_state mtl_c10_hdmi_154000 = { 1261 .clock = 154000, 1262 .tx = 0x10, 1263 .cmn = 0x1, 1264 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00, 1265 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1266 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x35, .pll[13] = 0x55, .pll[14] = 0x55, 1267 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1268 }; 1269 1270 static const struct intel_c10pll_state mtl_c10_hdmi_162000 = { 1271 .clock = 162000, 1272 .tx = 0x10, 1273 .cmn = 0x1, 1274 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00, 1275 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1276 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x60, .pll[13] = 0x00, .pll[14] = 0x00, 1277 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1278 }; 1279 1280 static const struct intel_c10pll_state mtl_c10_hdmi_167000 = { 1281 .clock = 167000, 1282 .tx = 0x10, 1283 .cmn = 0x1, 1284 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00, 1285 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1286 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0xFA, .pll[13] = 0xA9, .pll[14] = 0xAA, 1287 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1288 }; 1289 1290 static const struct intel_c10pll_state mtl_c10_hdmi_197802 = { 1291 .clock = 197802, 1292 .tx = 0x10, 1293 .cmn = 0x1, 1294 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00, 1295 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1296 .pll[10] = 0xFF, .pll[11] = 0x99, .pll[12] = 0x05, .pll[13] = 0x98, .pll[14] = 0x99, 1297 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1298 }; 1299 1300 static const struct intel_c10pll_state mtl_c10_hdmi_198000 = { 1301 .clock = 198000, 1302 .tx = 0x10, 1303 .cmn = 0x1, 1304 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00, 1305 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1306 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00, 1307 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1308 }; 1309 1310 static const struct intel_c10pll_state mtl_c10_hdmi_209800 = { 1311 .clock = 209800, 1312 .tx = 0x10, 1313 .cmn = 0x1, 1314 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00, 1315 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1316 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x45, .pll[13] = 0x55, .pll[14] = 0x55, 1317 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1318 }; 1319 1320 static const struct intel_c10pll_state mtl_c10_hdmi_241500 = { 1321 .clock = 241500, 1322 .tx = 0x10, 1323 .cmn = 0x1, 1324 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00, 1325 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1326 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xC8, .pll[13] = 0x00, .pll[14] = 0x00, 1327 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1328 }; 1329 1330 static const struct intel_c10pll_state mtl_c10_hdmi_262750 = { 1331 .clock = 262750, 1332 .tx = 0x10, 1333 .cmn = 0x1, 1334 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00, 1335 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1336 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x6C, .pll[13] = 0xA9, .pll[14] = 0xAA, 1337 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1338 }; 1339 1340 static const struct intel_c10pll_state mtl_c10_hdmi_268500 = { 1341 .clock = 268500, 1342 .tx = 0x10, 1343 .cmn = 0x1, 1344 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00, 1345 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1346 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xEC, .pll[13] = 0x00, .pll[14] = 0x00, 1347 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1348 }; 1349 1350 static const struct intel_c10pll_state mtl_c10_hdmi_296703 = { 1351 .clock = 296703, 1352 .tx = 0x10, 1353 .cmn = 0x1, 1354 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, 1355 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1356 .pll[10] = 0xFF, .pll[11] = 0x33, .pll[12] = 0x44, .pll[13] = 0x33, .pll[14] = 0x33, 1357 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1358 }; 1359 1360 static const struct intel_c10pll_state mtl_c10_hdmi_297000 = { 1361 .clock = 297000, 1362 .tx = 0x10, 1363 .cmn = 0x1, 1364 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, 1365 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1366 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x58, .pll[13] = 0x00, .pll[14] = 0x00, 1367 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1368 }; 1369 1370 static const struct intel_c10pll_state mtl_c10_hdmi_319750 = { 1371 .clock = 319750, 1372 .tx = 0x10, 1373 .cmn = 0x1, 1374 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00, 1375 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1376 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x44, .pll[13] = 0xA9, .pll[14] = 0xAA, 1377 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1378 }; 1379 1380 static const struct intel_c10pll_state mtl_c10_hdmi_497750 = { 1381 .clock = 497750, 1382 .tx = 0x10, 1383 .cmn = 0x1, 1384 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00, 1385 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1386 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x9F, .pll[13] = 0x55, .pll[14] = 0x55, 1387 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1388 }; 1389 1390 static const struct intel_c10pll_state mtl_c10_hdmi_592000 = { 1391 .clock = 592000, 1392 .tx = 0x10, 1393 .cmn = 0x1, 1394 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, 1395 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1396 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x15, .pll[13] = 0x55, .pll[14] = 0x55, 1397 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1398 }; 1399 1400 static const struct intel_c10pll_state mtl_c10_hdmi_593407 = { 1401 .clock = 593407, 1402 .tx = 0x10, 1403 .cmn = 0x1, 1404 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, 1405 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1406 .pll[10] = 0xFF, .pll[11] = 0x3B, .pll[12] = 0x44, .pll[13] = 0xBA, .pll[14] = 0xBB, 1407 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1408 }; 1409 1410 static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = { 1411 &mtl_c10_hdmi_25_2, /* Consolidated Table */ 1412 &mtl_c10_hdmi_27_0, /* Consolidated Table */ 1413 &mtl_c10_hdmi_27027, 1414 &mtl_c10_hdmi_28320, 1415 &mtl_c10_hdmi_30240, 1416 &mtl_c10_hdmi_31500, 1417 &mtl_c10_hdmi_36000, 1418 &mtl_c10_hdmi_40000, 1419 &mtl_c10_hdmi_49500, 1420 &mtl_c10_hdmi_50000, 1421 &mtl_c10_hdmi_57284, 1422 &mtl_c10_hdmi_58000, 1423 &mtl_c10_hdmi_65000, 1424 &mtl_c10_hdmi_71000, 1425 &mtl_c10_hdmi_74176, 1426 &mtl_c10_hdmi_74_25, /* Consolidated Table */ 1427 &mtl_c10_hdmi_75000, 1428 &mtl_c10_hdmi_78750, 1429 &mtl_c10_hdmi_85500, 1430 &mtl_c10_hdmi_88750, 1431 &mtl_c10_hdmi_106500, 1432 &mtl_c10_hdmi_108000, 1433 &mtl_c10_hdmi_115500, 1434 &mtl_c10_hdmi_119000, 1435 &mtl_c10_hdmi_135000, 1436 &mtl_c10_hdmi_138500, 1437 &mtl_c10_hdmi_147160, 1438 &mtl_c10_hdmi_148352, 1439 &mtl_c10_hdmi_148_5, /* Consolidated Table */ 1440 &mtl_c10_hdmi_154000, 1441 &mtl_c10_hdmi_162000, 1442 &mtl_c10_hdmi_167000, 1443 &mtl_c10_hdmi_197802, 1444 &mtl_c10_hdmi_198000, 1445 &mtl_c10_hdmi_209800, 1446 &mtl_c10_hdmi_241500, 1447 &mtl_c10_hdmi_262750, 1448 &mtl_c10_hdmi_268500, 1449 &mtl_c10_hdmi_296703, 1450 &mtl_c10_hdmi_297000, 1451 &mtl_c10_hdmi_319750, 1452 &mtl_c10_hdmi_497750, 1453 &mtl_c10_hdmi_592000, 1454 &mtl_c10_hdmi_593407, 1455 &mtl_c10_hdmi_594, /* Consolidated Table */ 1456 NULL, 1457 }; 1458 1459 static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = { 1460 .link_bit_rate = 25175, 1461 .clock = 25175, 1462 .tx = { 0xbe88, /* tx cfg0 */ 1463 0x9800, /* tx cfg1 */ 1464 0x0000, /* tx cfg2 */ 1465 }, 1466 .cmn = { 0x0500, /* cmn cfg0*/ 1467 0x0005, /* cmn cfg1 */ 1468 0x0000, /* cmn cfg2 */ 1469 0x0000, /* cmn cfg3 */ 1470 }, 1471 .mpllb = { 0xa0d2, /* mpllb cfg0 */ 1472 0x7d80, /* mpllb cfg1 */ 1473 0x0906, /* mpllb cfg2 */ 1474 0xbe40, /* mpllb cfg3 */ 1475 0x0000, /* mpllb cfg4 */ 1476 0x0000, /* mpllb cfg5 */ 1477 0x0200, /* mpllb cfg6 */ 1478 0x0001, /* mpllb cfg7 */ 1479 0x0000, /* mpllb cfg8 */ 1480 0x0000, /* mpllb cfg9 */ 1481 0x0001, /* mpllb cfg10 */ 1482 }, 1483 }; 1484 1485 static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = { 1486 .link_bit_rate = 27000, 1487 .clock = 27000, 1488 .tx = { 0xbe88, /* tx cfg0 */ 1489 0x9800, /* tx cfg1 */ 1490 0x0000, /* tx cfg2 */ 1491 }, 1492 .cmn = { 0x0500, /* cmn cfg0*/ 1493 0x0005, /* cmn cfg1 */ 1494 0x0000, /* cmn cfg2 */ 1495 0x0000, /* cmn cfg3 */ 1496 }, 1497 .mpllb = { 0xa0e0, /* mpllb cfg0 */ 1498 0x7d80, /* mpllb cfg1 */ 1499 0x0906, /* mpllb cfg2 */ 1500 0xbe40, /* mpllb cfg3 */ 1501 0x0000, /* mpllb cfg4 */ 1502 0x0000, /* mpllb cfg5 */ 1503 0x2200, /* mpllb cfg6 */ 1504 0x0001, /* mpllb cfg7 */ 1505 0x8000, /* mpllb cfg8 */ 1506 0x0000, /* mpllb cfg9 */ 1507 0x0001, /* mpllb cfg10 */ 1508 }, 1509 }; 1510 1511 static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = { 1512 .link_bit_rate = 74250, 1513 .clock = 74250, 1514 .tx = { 0xbe88, /* tx cfg0 */ 1515 0x9800, /* tx cfg1 */ 1516 0x0000, /* tx cfg2 */ 1517 }, 1518 .cmn = { 0x0500, /* cmn cfg0*/ 1519 0x0005, /* cmn cfg1 */ 1520 0x0000, /* cmn cfg2 */ 1521 0x0000, /* cmn cfg3 */ 1522 }, 1523 .mpllb = { 0x609a, /* mpllb cfg0 */ 1524 0x7d40, /* mpllb cfg1 */ 1525 0xca06, /* mpllb cfg2 */ 1526 0xbe40, /* mpllb cfg3 */ 1527 0x0000, /* mpllb cfg4 */ 1528 0x0000, /* mpllb cfg5 */ 1529 0x2200, /* mpllb cfg6 */ 1530 0x0001, /* mpllb cfg7 */ 1531 0x5800, /* mpllb cfg8 */ 1532 0x0000, /* mpllb cfg9 */ 1533 0x0001, /* mpllb cfg10 */ 1534 }, 1535 }; 1536 1537 static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = { 1538 .link_bit_rate = 148500, 1539 .clock = 148500, 1540 .tx = { 0xbe88, /* tx cfg0 */ 1541 0x9800, /* tx cfg1 */ 1542 0x0000, /* tx cfg2 */ 1543 }, 1544 .cmn = { 0x0500, /* cmn cfg0*/ 1545 0x0005, /* cmn cfg1 */ 1546 0x0000, /* cmn cfg2 */ 1547 0x0000, /* cmn cfg3 */ 1548 }, 1549 .mpllb = { 0x409a, /* mpllb cfg0 */ 1550 0x7d20, /* mpllb cfg1 */ 1551 0xca06, /* mpllb cfg2 */ 1552 0xbe40, /* mpllb cfg3 */ 1553 0x0000, /* mpllb cfg4 */ 1554 0x0000, /* mpllb cfg5 */ 1555 0x2200, /* mpllb cfg6 */ 1556 0x0001, /* mpllb cfg7 */ 1557 0x5800, /* mpllb cfg8 */ 1558 0x0000, /* mpllb cfg9 */ 1559 0x0001, /* mpllb cfg10 */ 1560 }, 1561 }; 1562 1563 static const struct intel_c20pll_state mtl_c20_hdmi_594 = { 1564 .link_bit_rate = 594000, 1565 .clock = 594000, 1566 .tx = { 0xbe88, /* tx cfg0 */ 1567 0x9800, /* tx cfg1 */ 1568 0x0000, /* tx cfg2 */ 1569 }, 1570 .cmn = { 0x0500, /* cmn cfg0*/ 1571 0x0005, /* cmn cfg1 */ 1572 0x0000, /* cmn cfg2 */ 1573 0x0000, /* cmn cfg3 */ 1574 }, 1575 .mpllb = { 0x009a, /* mpllb cfg0 */ 1576 0x7d08, /* mpllb cfg1 */ 1577 0xca06, /* mpllb cfg2 */ 1578 0xbe40, /* mpllb cfg3 */ 1579 0x0000, /* mpllb cfg4 */ 1580 0x0000, /* mpllb cfg5 */ 1581 0x2200, /* mpllb cfg6 */ 1582 0x0001, /* mpllb cfg7 */ 1583 0x5800, /* mpllb cfg8 */ 1584 0x0000, /* mpllb cfg9 */ 1585 0x0001, /* mpllb cfg10 */ 1586 }, 1587 }; 1588 1589 static const struct intel_c20pll_state mtl_c20_hdmi_300 = { 1590 .link_bit_rate = 3000000, 1591 .clock = 166670, 1592 .tx = { 0xbe98, /* tx cfg0 */ 1593 0x9800, /* tx cfg1 */ 1594 0x0000, /* tx cfg2 */ 1595 }, 1596 .cmn = { 0x0500, /* cmn cfg0*/ 1597 0x0005, /* cmn cfg1 */ 1598 0x0000, /* cmn cfg2 */ 1599 0x0000, /* cmn cfg3 */ 1600 }, 1601 .mpllb = { 0x209c, /* mpllb cfg0 */ 1602 0x7d10, /* mpllb cfg1 */ 1603 0xca06, /* mpllb cfg2 */ 1604 0xbe40, /* mpllb cfg3 */ 1605 0x0000, /* mpllb cfg4 */ 1606 0x0000, /* mpllb cfg5 */ 1607 0x2200, /* mpllb cfg6 */ 1608 0x0001, /* mpllb cfg7 */ 1609 0x2000, /* mpllb cfg8 */ 1610 0x0000, /* mpllb cfg9 */ 1611 0x0004, /* mpllb cfg10 */ 1612 }, 1613 }; 1614 1615 static const struct intel_c20pll_state mtl_c20_hdmi_600 = { 1616 .link_bit_rate = 6000000, 1617 .clock = 333330, 1618 .tx = { 0xbe98, /* tx cfg0 */ 1619 0x9800, /* tx cfg1 */ 1620 0x0000, /* tx cfg2 */ 1621 }, 1622 .cmn = { 0x0500, /* cmn cfg0*/ 1623 0x0005, /* cmn cfg1 */ 1624 0x0000, /* cmn cfg2 */ 1625 0x0000, /* cmn cfg3 */ 1626 }, 1627 .mpllb = { 0x009c, /* mpllb cfg0 */ 1628 0x7d08, /* mpllb cfg1 */ 1629 0xca06, /* mpllb cfg2 */ 1630 0xbe40, /* mpllb cfg3 */ 1631 0x0000, /* mpllb cfg4 */ 1632 0x0000, /* mpllb cfg5 */ 1633 0x2200, /* mpllb cfg6 */ 1634 0x0001, /* mpllb cfg7 */ 1635 0x2000, /* mpllb cfg8 */ 1636 0x0000, /* mpllb cfg9 */ 1637 0x0004, /* mpllb cfg10 */ 1638 }, 1639 }; 1640 1641 static const struct intel_c20pll_state mtl_c20_hdmi_800 = { 1642 .link_bit_rate = 8000000, 1643 .clock = 444440, 1644 .tx = { 0xbe98, /* tx cfg0 */ 1645 0x9800, /* tx cfg1 */ 1646 0x0000, /* tx cfg2 */ 1647 }, 1648 .cmn = { 0x0500, /* cmn cfg0*/ 1649 0x0005, /* cmn cfg1 */ 1650 0x0000, /* cmn cfg2 */ 1651 0x0000, /* cmn cfg3 */ 1652 }, 1653 .mpllb = { 0x00d0, /* mpllb cfg0 */ 1654 0x7d08, /* mpllb cfg1 */ 1655 0x4a06, /* mpllb cfg2 */ 1656 0xbe40, /* mpllb cfg3 */ 1657 0x0000, /* mpllb cfg4 */ 1658 0x0000, /* mpllb cfg5 */ 1659 0x2200, /* mpllb cfg6 */ 1660 0x0003, /* mpllb cfg7 */ 1661 0x2aaa, /* mpllb cfg8 */ 1662 0x0002, /* mpllb cfg9 */ 1663 0x0004, /* mpllb cfg10 */ 1664 }, 1665 }; 1666 1667 static const struct intel_c20pll_state mtl_c20_hdmi_1000 = { 1668 .link_bit_rate = 10000000, 1669 .clock = 555560, 1670 .tx = { 0xbe98, /* tx cfg0 */ 1671 0x9800, /* tx cfg1 */ 1672 0x0000, /* tx cfg2 */ 1673 }, 1674 .cmn = { 0x0500, /* cmn cfg0*/ 1675 0x0005, /* cmn cfg1 */ 1676 0x0000, /* cmn cfg2 */ 1677 0x0000, /* cmn cfg3 */ 1678 }, 1679 .mpllb = { 0x1104, /* mpllb cfg0 */ 1680 0x7d08, /* mpllb cfg1 */ 1681 0x0a06, /* mpllb cfg2 */ 1682 0xbe40, /* mpllb cfg3 */ 1683 0x0000, /* mpllb cfg4 */ 1684 0x0000, /* mpllb cfg5 */ 1685 0x2200, /* mpllb cfg6 */ 1686 0x0003, /* mpllb cfg7 */ 1687 0x3555, /* mpllb cfg8 */ 1688 0x0001, /* mpllb cfg9 */ 1689 0x0004, /* mpllb cfg10 */ 1690 }, 1691 }; 1692 1693 static const struct intel_c20pll_state mtl_c20_hdmi_1200 = { 1694 .link_bit_rate = 12000000, 1695 .clock = 666670, 1696 .tx = { 0xbe98, /* tx cfg0 */ 1697 0x9800, /* tx cfg1 */ 1698 0x0000, /* tx cfg2 */ 1699 }, 1700 .cmn = { 0x0500, /* cmn cfg0*/ 1701 0x0005, /* cmn cfg1 */ 1702 0x0000, /* cmn cfg2 */ 1703 0x0000, /* cmn cfg3 */ 1704 }, 1705 .mpllb = { 0x0138, /* mpllb cfg0 */ 1706 0x7d08, /* mpllb cfg1 */ 1707 0x5486, /* mpllb cfg2 */ 1708 0xfe40, /* mpllb cfg3 */ 1709 0x0000, /* mpllb cfg4 */ 1710 0x0000, /* mpllb cfg5 */ 1711 0x2200, /* mpllb cfg6 */ 1712 0x0001, /* mpllb cfg7 */ 1713 0x4000, /* mpllb cfg8 */ 1714 0x0000, /* mpllb cfg9 */ 1715 0x0004, /* mpllb cfg10 */ 1716 }, 1717 }; 1718 1719 static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = { 1720 &mtl_c20_hdmi_25_175, 1721 &mtl_c20_hdmi_27_0, 1722 &mtl_c20_hdmi_74_25, 1723 &mtl_c20_hdmi_148_5, 1724 &mtl_c20_hdmi_594, 1725 &mtl_c20_hdmi_300, 1726 &mtl_c20_hdmi_600, 1727 &mtl_c20_hdmi_800, 1728 &mtl_c20_hdmi_1000, 1729 &mtl_c20_hdmi_1200, 1730 NULL, 1731 }; 1732 1733 static int intel_c10_phy_check_hdmi_link_rate(int clock) 1734 { 1735 const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables; 1736 int i; 1737 1738 for (i = 0; tables[i]; i++) { 1739 if (clock == tables[i]->clock) 1740 return MODE_OK; 1741 } 1742 1743 return MODE_CLOCK_RANGE; 1744 } 1745 1746 static const struct intel_c10pll_state * const * 1747 intel_c10pll_tables_get(struct intel_crtc_state *crtc_state, 1748 struct intel_encoder *encoder) 1749 { 1750 if (intel_crtc_has_dp_encoder(crtc_state)) { 1751 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1752 return mtl_c10_edp_tables; 1753 else 1754 return mtl_c10_dp_tables; 1755 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1756 return mtl_c10_hdmi_tables; 1757 } 1758 1759 MISSING_CASE(encoder->type); 1760 return NULL; 1761 } 1762 1763 static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state, 1764 struct intel_encoder *encoder) 1765 { 1766 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1767 struct intel_cx0pll_state *pll_state = &crtc_state->cx0pll_state; 1768 int i; 1769 1770 if (intel_crtc_has_dp_encoder(crtc_state)) { 1771 if (intel_panel_use_ssc(i915)) { 1772 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1773 1774 pll_state->ssc_enabled = 1775 (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5); 1776 } 1777 } 1778 1779 if (pll_state->ssc_enabled) 1780 return; 1781 1782 drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); 1783 for (i = 4; i < 9; i++) 1784 pll_state->c10.pll[i] = 0; 1785 } 1786 1787 static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state, 1788 struct intel_encoder *encoder) 1789 { 1790 const struct intel_c10pll_state * const *tables; 1791 int i; 1792 1793 tables = intel_c10pll_tables_get(crtc_state, encoder); 1794 if (!tables) 1795 return -EINVAL; 1796 1797 for (i = 0; tables[i]; i++) { 1798 if (crtc_state->port_clock == tables[i]->clock) { 1799 crtc_state->cx0pll_state.c10 = *tables[i]; 1800 intel_c10pll_update_pll(crtc_state, encoder); 1801 1802 return 0; 1803 } 1804 } 1805 1806 return -EINVAL; 1807 } 1808 1809 void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, 1810 struct intel_c10pll_state *pll_state) 1811 { 1812 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1813 u8 lane = INTEL_CX0_LANE0; 1814 intel_wakeref_t wakeref; 1815 int i; 1816 1817 wakeref = intel_cx0_phy_transaction_begin(encoder); 1818 1819 /* 1820 * According to C10 VDR Register programming Sequence we need 1821 * to do this to read PHY internal registers from MsgBus. 1822 */ 1823 intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1), 1824 0, C10_VDR_CTRL_MSGBUS_ACCESS, 1825 MB_WRITE_COMMITTED); 1826 1827 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) 1828 pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane, 1829 PHY_C10_VDR_PLL(i)); 1830 1831 pll_state->cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0)); 1832 pll_state->tx = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0)); 1833 1834 intel_cx0_phy_transaction_end(encoder, wakeref); 1835 } 1836 1837 static void intel_c10_pll_program(struct drm_i915_private *i915, 1838 const struct intel_crtc_state *crtc_state, 1839 struct intel_encoder *encoder) 1840 { 1841 const struct intel_c10pll_state *pll_state = &crtc_state->cx0pll_state.c10; 1842 int i; 1843 1844 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), 1845 0, C10_VDR_CTRL_MSGBUS_ACCESS, 1846 MB_WRITE_COMMITTED); 1847 1848 /* Custom width needs to be programmed to 0 for both the phy lanes */ 1849 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH, 1850 C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10, 1851 MB_WRITE_COMMITTED); 1852 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), 1853 0, C10_VDR_CTRL_UPDATE_CFG, 1854 MB_WRITE_COMMITTED); 1855 1856 /* Program the pll values only for the master lane */ 1857 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) 1858 intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i), 1859 pll_state->pll[i], 1860 (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED); 1861 1862 intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED); 1863 intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED); 1864 1865 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1), 1866 0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, 1867 MB_WRITE_COMMITTED); 1868 } 1869 1870 void intel_c10pll_dump_hw_state(struct drm_i915_private *i915, 1871 const struct intel_c10pll_state *hw_state) 1872 { 1873 bool fracen; 1874 int i; 1875 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; 1876 unsigned int multiplier, tx_clk_div; 1877 1878 fracen = hw_state->pll[0] & C10_PLL0_FRACEN; 1879 drm_dbg_kms(&i915->drm, "c10pll_hw_state: fracen: %s, ", 1880 str_yes_no(fracen)); 1881 1882 if (fracen) { 1883 frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11]; 1884 frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13]; 1885 frac_den = hw_state->pll[10] << 8 | hw_state->pll[9]; 1886 drm_dbg_kms(&i915->drm, "quot: %u, rem: %u, den: %u,\n", 1887 frac_quot, frac_rem, frac_den); 1888 } 1889 1890 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 | 1891 hw_state->pll[2]) / 2 + 16; 1892 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]); 1893 drm_dbg_kms(&i915->drm, 1894 "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div); 1895 1896 drm_dbg_kms(&i915->drm, "c10pll_rawhw_state:"); 1897 drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn); 1898 1899 BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4); 1900 for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) 1901 drm_dbg_kms(&i915->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", 1902 i, hw_state->pll[i], i + 1, hw_state->pll[i + 1], 1903 i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); 1904 } 1905 1906 static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_state *pll_state) 1907 { 1908 u64 datarate; 1909 u64 mpll_tx_clk_div; 1910 u64 vco_freq_shift; 1911 u64 vco_freq; 1912 u64 multiplier; 1913 u64 mpll_multiplier; 1914 u64 mpll_fracn_quot; 1915 u64 mpll_fracn_rem; 1916 u8 mpllb_ana_freq_vco; 1917 u8 mpll_div_multiplier; 1918 1919 if (pixel_clock < 25175 || pixel_clock > 600000) 1920 return -EINVAL; 1921 1922 datarate = ((u64)pixel_clock * 1000) * 10; 1923 mpll_tx_clk_div = ilog2(div64_u64((u64)CLOCK_9999MHZ, (u64)datarate)); 1924 vco_freq_shift = ilog2(div64_u64((u64)CLOCK_4999MHZ * (u64)256, (u64)datarate)); 1925 vco_freq = (datarate << vco_freq_shift) >> 8; 1926 multiplier = div64_u64((vco_freq << 28), (REFCLK_38_4_MHZ >> 4)); 1927 mpll_multiplier = 2 * (multiplier >> 32); 1928 1929 mpll_fracn_quot = (multiplier >> 16) & 0xFFFF; 1930 mpll_fracn_rem = multiplier & 0xFFFF; 1931 1932 mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)), 1933 datarate), 255); 1934 1935 if (vco_freq <= DATARATE_3000000000) 1936 mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_3; 1937 else if (vco_freq <= DATARATE_3500000000) 1938 mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_2; 1939 else if (vco_freq <= DATARATE_4000000000) 1940 mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_1; 1941 else 1942 mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0; 1943 1944 pll_state->link_bit_rate = pixel_clock; 1945 pll_state->clock = pixel_clock; 1946 pll_state->tx[0] = 0xbe88; 1947 pll_state->tx[1] = 0x9800; 1948 pll_state->tx[2] = 0x0000; 1949 pll_state->cmn[0] = 0x0500; 1950 pll_state->cmn[1] = 0x0005; 1951 pll_state->cmn[2] = 0x0000; 1952 pll_state->cmn[3] = 0x0000; 1953 pll_state->mpllb[0] = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) | 1954 MPLL_MULTIPLIER(mpll_multiplier)); 1955 pll_state->mpllb[1] = (CAL_DAC_CODE(CAL_DAC_CODE_31) | 1956 WORD_CLK_DIV | 1957 MPLL_DIV_MULTIPLIER(mpll_div_multiplier)); 1958 pll_state->mpllb[2] = (MPLLB_ANA_FREQ_VCO(mpllb_ana_freq_vco) | 1959 CP_PROP(CP_PROP_20) | 1960 CP_INT(CP_INT_6)); 1961 pll_state->mpllb[3] = (V2I(V2I_2) | 1962 CP_PROP_GS(CP_PROP_GS_30) | 1963 CP_INT_GS(CP_INT_GS_28)); 1964 pll_state->mpllb[4] = 0x0000; 1965 pll_state->mpllb[5] = 0x0000; 1966 pll_state->mpllb[6] = (C20_MPLLB_FRACEN | SSC_UP_SPREAD); 1967 pll_state->mpllb[7] = MPLL_FRACN_DEN; 1968 pll_state->mpllb[8] = mpll_fracn_quot; 1969 pll_state->mpllb[9] = mpll_fracn_rem; 1970 pll_state->mpllb[10] = HDMI_DIV(HDMI_DIV_1); 1971 1972 return 0; 1973 } 1974 1975 static int intel_c20_phy_check_hdmi_link_rate(int clock) 1976 { 1977 const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables; 1978 int i; 1979 1980 for (i = 0; tables[i]; i++) { 1981 if (clock == tables[i]->link_bit_rate) 1982 return MODE_OK; 1983 } 1984 1985 if (clock >= 25175 && clock <= 594000) 1986 return MODE_OK; 1987 1988 return MODE_CLOCK_RANGE; 1989 } 1990 1991 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock) 1992 { 1993 struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi); 1994 struct drm_i915_private *i915 = intel_hdmi_to_i915(hdmi); 1995 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 1996 1997 if (intel_is_c10phy(i915, phy)) 1998 return intel_c10_phy_check_hdmi_link_rate(clock); 1999 return intel_c20_phy_check_hdmi_link_rate(clock); 2000 } 2001 2002 static const struct intel_c20pll_state * const * 2003 intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, 2004 struct intel_encoder *encoder) 2005 { 2006 if (intel_crtc_has_dp_encoder(crtc_state)) 2007 return mtl_c20_dp_tables; 2008 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2009 return mtl_c20_hdmi_tables; 2010 2011 MISSING_CASE(encoder->type); 2012 return NULL; 2013 } 2014 2015 static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state, 2016 struct intel_encoder *encoder) 2017 { 2018 const struct intel_c20pll_state * const *tables; 2019 int i; 2020 2021 /* try computed C20 HDMI tables before using consolidated tables */ 2022 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2023 if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock, 2024 &crtc_state->cx0pll_state.c20) == 0) 2025 return 0; 2026 } 2027 2028 tables = intel_c20_pll_tables_get(crtc_state, encoder); 2029 if (!tables) 2030 return -EINVAL; 2031 2032 for (i = 0; tables[i]; i++) { 2033 if (crtc_state->port_clock == tables[i]->link_bit_rate) { 2034 crtc_state->cx0pll_state.c20 = *tables[i]; 2035 return 0; 2036 } 2037 } 2038 2039 return -EINVAL; 2040 } 2041 2042 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, 2043 struct intel_encoder *encoder) 2044 { 2045 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2046 enum phy phy = intel_port_to_phy(i915, encoder->port); 2047 2048 if (intel_is_c10phy(i915, phy)) 2049 return intel_c10pll_calc_state(crtc_state, encoder); 2050 return intel_c20pll_calc_state(crtc_state, encoder); 2051 } 2052 2053 static bool intel_c20_use_mplla(u32 clock) 2054 { 2055 /* 10G and 20G rates use MPLLA */ 2056 if (clock == 312500 || clock == 625000) 2057 return true; 2058 2059 return false; 2060 } 2061 2062 void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, 2063 struct intel_c20pll_state *pll_state) 2064 { 2065 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2066 bool cntx; 2067 intel_wakeref_t wakeref; 2068 int i; 2069 2070 wakeref = intel_cx0_phy_transaction_begin(encoder); 2071 2072 /* 1. Read current context selection */ 2073 cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE; 2074 2075 /* Read Tx configuration */ 2076 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { 2077 if (cntx) 2078 pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, 2079 PHY_C20_B_TX_CNTX_CFG(i)); 2080 else 2081 pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, 2082 PHY_C20_A_TX_CNTX_CFG(i)); 2083 } 2084 2085 /* Read common configuration */ 2086 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { 2087 if (cntx) 2088 pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, 2089 PHY_C20_B_CMN_CNTX_CFG(i)); 2090 else 2091 pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, 2092 PHY_C20_A_CMN_CNTX_CFG(i)); 2093 } 2094 2095 if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { 2096 /* MPLLB configuration */ 2097 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { 2098 if (cntx) 2099 pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, 2100 PHY_C20_B_MPLLB_CNTX_CFG(i)); 2101 else 2102 pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, 2103 PHY_C20_A_MPLLB_CNTX_CFG(i)); 2104 } 2105 } else { 2106 /* MPLLA configuration */ 2107 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { 2108 if (cntx) 2109 pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, 2110 PHY_C20_B_MPLLA_CNTX_CFG(i)); 2111 else 2112 pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, 2113 PHY_C20_A_MPLLA_CNTX_CFG(i)); 2114 } 2115 } 2116 2117 intel_cx0_phy_transaction_end(encoder, wakeref); 2118 } 2119 2120 void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, 2121 const struct intel_c20pll_state *hw_state) 2122 { 2123 int i; 2124 2125 drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n"); 2126 drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", 2127 hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); 2128 drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", 2129 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); 2130 2131 if (intel_c20_use_mplla(hw_state->clock)) { 2132 for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) 2133 drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); 2134 } else { 2135 for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) 2136 drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); 2137 } 2138 } 2139 2140 static u8 intel_c20_get_dp_rate(u32 clock) 2141 { 2142 switch (clock) { 2143 case 162000: /* 1.62 Gbps DP1.4 */ 2144 return 0; 2145 case 270000: /* 2.7 Gbps DP1.4 */ 2146 return 1; 2147 case 540000: /* 5.4 Gbps DP 1.4 */ 2148 return 2; 2149 case 810000: /* 8.1 Gbps DP1.4 */ 2150 return 3; 2151 case 216000: /* 2.16 Gbps eDP */ 2152 return 4; 2153 case 243000: /* 2.43 Gbps eDP */ 2154 return 5; 2155 case 324000: /* 3.24 Gbps eDP */ 2156 return 6; 2157 case 432000: /* 4.32 Gbps eDP */ 2158 return 7; 2159 case 312500: /* 10 Gbps DP2.0 */ 2160 return 8; 2161 case 421875: /* 13.5 Gbps DP2.0 */ 2162 return 9; 2163 case 625000: /* 20 Gbps DP2.0*/ 2164 return 10; 2165 case 648000: /* 6.48 Gbps eDP*/ 2166 return 11; 2167 case 675000: /* 6.75 Gbps eDP*/ 2168 return 12; 2169 default: 2170 MISSING_CASE(clock); 2171 return 0; 2172 } 2173 } 2174 2175 static u8 intel_c20_get_hdmi_rate(u32 clock) 2176 { 2177 if (clock >= 25175 && clock <= 600000) 2178 return 0; 2179 2180 switch (clock) { 2181 case 166670: /* 3 Gbps */ 2182 case 333330: /* 6 Gbps */ 2183 case 666670: /* 12 Gbps */ 2184 return 1; 2185 case 444440: /* 8 Gbps */ 2186 return 2; 2187 case 555560: /* 10 Gbps */ 2188 return 3; 2189 default: 2190 MISSING_CASE(clock); 2191 return 0; 2192 } 2193 } 2194 2195 static bool is_dp2(u32 clock) 2196 { 2197 /* DP2.0 clock rates */ 2198 if (clock == 312500 || clock == 421875 || clock == 625000) 2199 return true; 2200 2201 return false; 2202 } 2203 2204 static bool is_hdmi_frl(u32 clock) 2205 { 2206 switch (clock) { 2207 case 166670: /* 3 Gbps */ 2208 case 333330: /* 6 Gbps */ 2209 case 444440: /* 8 Gbps */ 2210 case 555560: /* 10 Gbps */ 2211 case 666670: /* 12 Gbps */ 2212 return true; 2213 default: 2214 return false; 2215 } 2216 } 2217 2218 static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder) 2219 { 2220 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2221 2222 /* banks should not be cleared for DPALT/USB4/TBT modes */ 2223 /* TODO: optimize re-calibration in legacy mode */ 2224 return intel_tc_port_in_legacy_mode(intel_dig_port); 2225 } 2226 2227 static int intel_get_c20_custom_width(u32 clock, bool dp) 2228 { 2229 if (dp && is_dp2(clock)) 2230 return 2; 2231 else if (is_hdmi_frl(clock)) 2232 return 1; 2233 else 2234 return 0; 2235 } 2236 2237 static void intel_c20_pll_program(struct drm_i915_private *i915, 2238 const struct intel_crtc_state *crtc_state, 2239 struct intel_encoder *encoder) 2240 { 2241 const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20; 2242 bool dp = false; 2243 int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; 2244 bool cntx; 2245 int i; 2246 2247 if (intel_crtc_has_dp_encoder(crtc_state)) 2248 dp = true; 2249 2250 /* 1. Read current context selection */ 2251 cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0); 2252 2253 /* 2254 * 2. If there is a protocol switch from HDMI to DP or vice versa, clear 2255 * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA. 2256 * Protocol switch is only applicable for MPLLA 2257 */ 2258 if (intel_c20_protocol_switch_valid(encoder)) { 2259 for (i = 0; i < 4; i++) 2260 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0); 2261 usleep_range(4000, 4100); 2262 } 2263 2264 /* 3. Write SRAM configuration context. If A in use, write configuration to B context */ 2265 /* 3.1 Tx configuration */ 2266 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { 2267 if (cntx) 2268 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]); 2269 else 2270 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]); 2271 } 2272 2273 /* 3.2 common configuration */ 2274 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { 2275 if (cntx) 2276 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]); 2277 else 2278 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]); 2279 } 2280 2281 /* 3.3 mpllb or mplla configuration */ 2282 if (intel_c20_use_mplla(pll_state->clock)) { 2283 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { 2284 if (cntx) 2285 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, 2286 PHY_C20_A_MPLLA_CNTX_CFG(i), 2287 pll_state->mplla[i]); 2288 else 2289 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, 2290 PHY_C20_B_MPLLA_CNTX_CFG(i), 2291 pll_state->mplla[i]); 2292 } 2293 } else { 2294 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { 2295 if (cntx) 2296 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, 2297 PHY_C20_A_MPLLB_CNTX_CFG(i), 2298 pll_state->mpllb[i]); 2299 else 2300 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, 2301 PHY_C20_B_MPLLB_CNTX_CFG(i), 2302 pll_state->mpllb[i]); 2303 } 2304 } 2305 2306 /* 4. Program custom width to match the link protocol */ 2307 intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_WIDTH, 2308 PHY_C20_CUSTOM_WIDTH_MASK, 2309 PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(pll_state->clock, dp)), 2310 MB_WRITE_COMMITTED); 2311 2312 /* 5. For DP or 6. For HDMI */ 2313 if (dp) { 2314 intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, 2315 BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, 2316 BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(pll_state->clock)), 2317 MB_WRITE_COMMITTED); 2318 } else { 2319 intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, 2320 BIT(7) | PHY_C20_CUSTOM_SERDES_MASK, 2321 is_hdmi_frl(pll_state->clock) ? BIT(7) : 0, 2322 MB_WRITE_COMMITTED); 2323 2324 intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE, 2325 intel_c20_get_hdmi_rate(pll_state->clock), 2326 MB_WRITE_COMMITTED); 2327 } 2328 2329 /* 2330 * 7. Write Vendor specific registers to toggle context setting to load 2331 * the updated programming toggle context bit 2332 */ 2333 intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, 2334 BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); 2335 } 2336 2337 int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, 2338 const struct intel_c10pll_state *pll_state) 2339 { 2340 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; 2341 unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400; 2342 int tmpclk = 0; 2343 2344 if (pll_state->pll[0] & C10_PLL0_FRACEN) { 2345 frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; 2346 frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; 2347 frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; 2348 } 2349 2350 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | 2351 pll_state->pll[2]) / 2 + 16; 2352 2353 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]); 2354 hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); 2355 2356 tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + 2357 DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), 2358 10 << (tx_clk_div + 16)); 2359 tmpclk *= (hdmi_div ? 2 : 1); 2360 2361 return tmpclk; 2362 } 2363 2364 int intel_c20pll_calc_port_clock(struct intel_encoder *encoder, 2365 const struct intel_c20pll_state *pll_state) 2366 { 2367 unsigned int frac, frac_en, frac_quot, frac_rem, frac_den; 2368 unsigned int multiplier, refclk = 38400; 2369 unsigned int tx_clk_div; 2370 unsigned int ref_clk_mpllb_div; 2371 unsigned int fb_clk_div4_en; 2372 unsigned int ref, vco; 2373 unsigned int tx_rate_mult; 2374 unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); 2375 2376 if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { 2377 tx_rate_mult = 1; 2378 frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); 2379 frac_quot = pll_state->mpllb[8]; 2380 frac_rem = pll_state->mpllb[9]; 2381 frac_den = pll_state->mpllb[7]; 2382 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); 2383 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); 2384 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); 2385 fb_clk_div4_en = 0; 2386 } else { 2387 tx_rate_mult = 2; 2388 frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); 2389 frac_quot = pll_state->mplla[8]; 2390 frac_rem = pll_state->mplla[9]; 2391 frac_den = pll_state->mplla[7]; 2392 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); 2393 tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); 2394 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); 2395 fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); 2396 } 2397 2398 if (frac_en) 2399 frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den); 2400 else 2401 frac = 0; 2402 2403 ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div); 2404 vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10); 2405 2406 return vco << tx_rate_mult >> tx_clk_div >> tx_rate; 2407 } 2408 2409 static void intel_program_port_clock_ctl(struct intel_encoder *encoder, 2410 const struct intel_crtc_state *crtc_state, 2411 bool lane_reversal) 2412 { 2413 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2414 u32 val = 0; 2415 2416 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL, 2417 lane_reversal ? XELPDP_PORT_REVERSAL : 0); 2418 2419 if (lane_reversal) 2420 val |= XELPDP_LANE1_PHY_CLOCK_SELECT; 2421 2422 val |= XELPDP_FORWARD_CLOCK_UNGATE; 2423 2424 if (is_hdmi_frl(crtc_state->port_clock)) 2425 val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK); 2426 else 2427 val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK); 2428 2429 /* TODO: HDMI FRL */ 2430 /* DP2.0 10G and 20G rates enable MPLLA*/ 2431 if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) 2432 val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; 2433 else 2434 val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; 2435 2436 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2437 XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE | 2438 XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLB, val); 2439 } 2440 2441 static u32 intel_cx0_get_powerdown_update(u8 lane_mask) 2442 { 2443 u32 val = 0; 2444 int lane = 0; 2445 2446 for_each_cx0_lane_in_mask(lane_mask, lane) 2447 val |= XELPDP_LANE_POWERDOWN_UPDATE(lane); 2448 2449 return val; 2450 } 2451 2452 static u32 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state) 2453 { 2454 u32 val = 0; 2455 int lane = 0; 2456 2457 for_each_cx0_lane_in_mask(lane_mask, lane) 2458 val |= XELPDP_LANE_POWERDOWN_NEW_STATE(lane, state); 2459 2460 return val; 2461 } 2462 2463 static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915, 2464 enum port port, 2465 u8 lane_mask, u8 state) 2466 { 2467 enum phy phy = intel_port_to_phy(i915, port); 2468 int lane; 2469 2470 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), 2471 intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK), 2472 intel_cx0_get_powerdown_state(lane_mask, state)); 2473 2474 /* Wait for pending transactions.*/ 2475 for_each_cx0_lane_in_mask(lane_mask, lane) 2476 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), 2477 XELPDP_PORT_M2P_TRANSACTION_PENDING, 2478 XELPDP_MSGBUS_TIMEOUT_SLOW)) { 2479 drm_dbg_kms(&i915->drm, 2480 "PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n", 2481 phy_name(phy)); 2482 intel_cx0_bus_reset(i915, port, lane); 2483 } 2484 2485 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), 2486 intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES), 2487 intel_cx0_get_powerdown_update(lane_mask)); 2488 2489 /* Update Timeout Value */ 2490 if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port), 2491 intel_cx0_get_powerdown_update(lane_mask), 0, 2492 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL)) 2493 drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", 2494 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US); 2495 } 2496 2497 static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port) 2498 { 2499 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), 2500 XELPDP_POWER_STATE_READY_MASK, 2501 XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY)); 2502 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port), 2503 XELPDP_POWER_STATE_ACTIVE_MASK | 2504 XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, 2505 XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) | 2506 XELPDP_PLL_LANE_STAGGERING_DELAY(0)); 2507 } 2508 2509 static u32 intel_cx0_get_pclk_refclk_request(u8 lane_mask) 2510 { 2511 u32 val = 0; 2512 int lane = 0; 2513 2514 for_each_cx0_lane_in_mask(lane_mask, lane) 2515 val |= XELPDP_LANE_PCLK_REFCLK_REQUEST(lane); 2516 2517 return val; 2518 } 2519 2520 static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask) 2521 { 2522 u32 val = 0; 2523 int lane = 0; 2524 2525 for_each_cx0_lane_in_mask(lane_mask, lane) 2526 val |= XELPDP_LANE_PCLK_REFCLK_ACK(lane); 2527 2528 return val; 2529 } 2530 2531 static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, 2532 struct intel_encoder *encoder, 2533 bool lane_reversal) 2534 { 2535 enum port port = encoder->port; 2536 enum phy phy = intel_port_to_phy(i915, port); 2537 bool both_lanes = intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2; 2538 u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : 2539 INTEL_CX0_LANE0; 2540 u32 lane_pipe_reset = both_lanes ? 2541 XELPDP_LANE_PIPE_RESET(0) | 2542 XELPDP_LANE_PIPE_RESET(1) : 2543 XELPDP_LANE_PIPE_RESET(0); 2544 u32 lane_phy_current_status = both_lanes ? 2545 XELPDP_LANE_PHY_CURRENT_STATUS(0) | 2546 XELPDP_LANE_PHY_CURRENT_STATUS(1) : 2547 XELPDP_LANE_PHY_CURRENT_STATUS(0); 2548 2549 if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port), 2550 XELPDP_PORT_BUF_SOC_PHY_READY, 2551 XELPDP_PORT_BUF_SOC_PHY_READY, 2552 XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL)) 2553 drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n", 2554 phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US); 2555 2556 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), 2557 XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1), 2558 lane_pipe_reset); 2559 2560 if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port), 2561 lane_phy_current_status, lane_phy_current_status, 2562 XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL)) 2563 drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", 2564 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US); 2565 2566 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port), 2567 intel_cx0_get_pclk_refclk_request(both_lanes ? 2568 INTEL_CX0_BOTH_LANES : 2569 INTEL_CX0_LANE0), 2570 intel_cx0_get_pclk_refclk_request(lane_mask)); 2571 2572 if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port), 2573 intel_cx0_get_pclk_refclk_ack(both_lanes ? 2574 INTEL_CX0_BOTH_LANES : 2575 INTEL_CX0_LANE0), 2576 intel_cx0_get_pclk_refclk_ack(lane_mask), 2577 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL)) 2578 drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n", 2579 phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US); 2580 2581 intel_cx0_powerdown_change_sequence(i915, port, INTEL_CX0_BOTH_LANES, 2582 CX0_P2_STATE_RESET); 2583 intel_cx0_setup_powerdown(i915, port); 2584 2585 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0); 2586 2587 if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), lane_phy_current_status, 2588 XELPDP_PORT_RESET_END_TIMEOUT)) 2589 drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n", 2590 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT); 2591 } 2592 2593 static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, 2594 struct intel_encoder *encoder, int lane_count, 2595 bool lane_reversal) 2596 { 2597 u8 l0t1, l0t2, l1t1, l1t2; 2598 bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder)); 2599 enum port port = encoder->port; 2600 2601 if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) 2602 intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, 2603 PHY_C10_VDR_CONTROL(1), 0, 2604 C10_VDR_CTRL_MSGBUS_ACCESS, 2605 MB_WRITE_COMMITTED); 2606 2607 /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */ 2608 l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2)); 2609 l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2)); 2610 l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2)); 2611 l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2)); 2612 2613 l0t1 |= CONTROL2_DISABLE_SINGLE_TX; 2614 l0t2 |= CONTROL2_DISABLE_SINGLE_TX; 2615 l1t1 |= CONTROL2_DISABLE_SINGLE_TX; 2616 l1t2 |= CONTROL2_DISABLE_SINGLE_TX; 2617 2618 if (lane_reversal) { 2619 switch (lane_count) { 2620 case 4: 2621 l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX; 2622 fallthrough; 2623 case 3: 2624 l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX; 2625 fallthrough; 2626 case 2: 2627 l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX; 2628 fallthrough; 2629 case 1: 2630 l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX; 2631 break; 2632 default: 2633 MISSING_CASE(lane_count); 2634 } 2635 } else { 2636 switch (lane_count) { 2637 case 4: 2638 l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX; 2639 fallthrough; 2640 case 3: 2641 l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX; 2642 fallthrough; 2643 case 2: 2644 l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX; 2645 l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX; 2646 break; 2647 case 1: 2648 if (dp_alt_mode) 2649 l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX; 2650 else 2651 l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX; 2652 break; 2653 default: 2654 MISSING_CASE(lane_count); 2655 } 2656 } 2657 2658 /* disable MLs */ 2659 intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2), 2660 l0t1, MB_WRITE_COMMITTED); 2661 intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2), 2662 l0t2, MB_WRITE_COMMITTED); 2663 intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2), 2664 l1t1, MB_WRITE_COMMITTED); 2665 intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2), 2666 l1t2, MB_WRITE_COMMITTED); 2667 2668 if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) 2669 intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, 2670 PHY_C10_VDR_CONTROL(1), 0, 2671 C10_VDR_CTRL_UPDATE_CFG, 2672 MB_WRITE_COMMITTED); 2673 } 2674 2675 static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask) 2676 { 2677 u32 val = 0; 2678 int lane = 0; 2679 2680 for_each_cx0_lane_in_mask(lane_mask, lane) 2681 val |= XELPDP_LANE_PCLK_PLL_REQUEST(lane); 2682 2683 return val; 2684 } 2685 2686 static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask) 2687 { 2688 u32 val = 0; 2689 int lane = 0; 2690 2691 for_each_cx0_lane_in_mask(lane_mask, lane) 2692 val |= XELPDP_LANE_PCLK_PLL_ACK(lane); 2693 2694 return val; 2695 } 2696 2697 static void intel_cx0pll_enable(struct intel_encoder *encoder, 2698 const struct intel_crtc_state *crtc_state) 2699 { 2700 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2701 enum phy phy = intel_port_to_phy(i915, encoder->port); 2702 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2703 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2704 u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 : 2705 INTEL_CX0_LANE0; 2706 intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); 2707 2708 /* 2709 * 1. Program PORT_CLOCK_CTL REGISTER to configure 2710 * clock muxes, gating and SSC 2711 */ 2712 intel_program_port_clock_ctl(encoder, crtc_state, lane_reversal); 2713 2714 /* 2. Bring PHY out of reset. */ 2715 intel_cx0_phy_lane_reset(i915, encoder, lane_reversal); 2716 2717 /* 2718 * 3. Change Phy power state to Ready. 2719 * TODO: For DP alt mode use only one lane. 2720 */ 2721 intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES, 2722 CX0_P2_STATE_READY); 2723 2724 /* 4. Program PHY internal PLL internal registers. */ 2725 if (intel_is_c10phy(i915, phy)) 2726 intel_c10_pll_program(i915, crtc_state, encoder); 2727 else 2728 intel_c20_pll_program(i915, crtc_state, encoder); 2729 2730 /* 2731 * 5. Program the enabled and disabled owned PHY lane 2732 * transmitters over message bus 2733 */ 2734 intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal); 2735 2736 /* 2737 * 6. Follow the Display Voltage Frequency Switching - Sequence 2738 * Before Frequency Change. We handle this step in bxt_set_cdclk(). 2739 */ 2740 2741 /* 2742 * 7. Program DDI_CLK_VALFREQ to match intended DDI 2743 * clock frequency. 2744 */ 2745 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 2746 crtc_state->port_clock); 2747 2748 /* 2749 * 8. Set PORT_CLOCK_CTL register PCLK PLL Request 2750 * LN<Lane for maxPCLK> to "1" to enable PLL. 2751 */ 2752 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2753 intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES), 2754 intel_cx0_get_pclk_pll_request(maxpclk_lane)); 2755 2756 /* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */ 2757 if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2758 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES), 2759 intel_cx0_get_pclk_pll_ack(maxpclk_lane), 2760 XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL)) 2761 drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n", 2762 phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US); 2763 2764 /* 2765 * 10. Follow the Display Voltage Frequency Switching Sequence After 2766 * Frequency Change. We handle this step in bxt_set_cdclk(). 2767 */ 2768 2769 /* TODO: enable TBT-ALT mode */ 2770 intel_cx0_phy_transaction_end(encoder, wakeref); 2771 } 2772 2773 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder) 2774 { 2775 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2776 u32 clock; 2777 u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port)); 2778 2779 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val); 2780 2781 drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE)); 2782 drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST)); 2783 drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK)); 2784 2785 switch (clock) { 2786 case XELPDP_DDI_CLOCK_SELECT_TBT_162: 2787 return 162000; 2788 case XELPDP_DDI_CLOCK_SELECT_TBT_270: 2789 return 270000; 2790 case XELPDP_DDI_CLOCK_SELECT_TBT_540: 2791 return 540000; 2792 case XELPDP_DDI_CLOCK_SELECT_TBT_810: 2793 return 810000; 2794 default: 2795 MISSING_CASE(clock); 2796 return 162000; 2797 } 2798 } 2799 2800 static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock) 2801 { 2802 switch (clock) { 2803 case 162000: 2804 return XELPDP_DDI_CLOCK_SELECT_TBT_162; 2805 case 270000: 2806 return XELPDP_DDI_CLOCK_SELECT_TBT_270; 2807 case 540000: 2808 return XELPDP_DDI_CLOCK_SELECT_TBT_540; 2809 case 810000: 2810 return XELPDP_DDI_CLOCK_SELECT_TBT_810; 2811 default: 2812 MISSING_CASE(clock); 2813 return XELPDP_DDI_CLOCK_SELECT_TBT_162; 2814 } 2815 } 2816 2817 static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, 2818 const struct intel_crtc_state *crtc_state) 2819 { 2820 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2821 enum phy phy = intel_port_to_phy(i915, encoder->port); 2822 u32 val = 0; 2823 2824 /* 2825 * 1. Program PORT_CLOCK_CTL REGISTER to configure 2826 * clock muxes, gating and SSC 2827 */ 2828 val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock)); 2829 val |= XELPDP_FORWARD_CLOCK_UNGATE; 2830 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2831 XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val); 2832 2833 /* 2. Read back PORT_CLOCK_CTL REGISTER */ 2834 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port)); 2835 2836 /* 2837 * 3. Follow the Display Voltage Frequency Switching - Sequence 2838 * Before Frequency Change. We handle this step in bxt_set_cdclk(). 2839 */ 2840 2841 /* 2842 * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL. 2843 */ 2844 val |= XELPDP_TBT_CLOCK_REQUEST; 2845 intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val); 2846 2847 /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */ 2848 if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2849 XELPDP_TBT_CLOCK_ACK, 2850 XELPDP_TBT_CLOCK_ACK, 2851 100, 0, NULL)) 2852 drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n", 2853 encoder->base.base.id, encoder->base.name, phy_name(phy)); 2854 2855 /* 2856 * 6. Follow the Display Voltage Frequency Switching Sequence After 2857 * Frequency Change. We handle this step in bxt_set_cdclk(). 2858 */ 2859 2860 /* 2861 * 7. Program DDI_CLK_VALFREQ to match intended DDI 2862 * clock frequency. 2863 */ 2864 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 2865 crtc_state->port_clock); 2866 } 2867 2868 void intel_mtl_pll_enable(struct intel_encoder *encoder, 2869 const struct intel_crtc_state *crtc_state) 2870 { 2871 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2872 2873 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2874 intel_mtl_tbt_pll_enable(encoder, crtc_state); 2875 else 2876 intel_cx0pll_enable(encoder, crtc_state); 2877 } 2878 2879 static void intel_cx0pll_disable(struct intel_encoder *encoder) 2880 { 2881 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2882 enum phy phy = intel_port_to_phy(i915, encoder->port); 2883 bool is_c10 = intel_is_c10phy(i915, phy); 2884 intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); 2885 2886 /* 1. Change owned PHY lane power to Disable state. */ 2887 intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES, 2888 is_c10 ? CX0_P2PG_STATE_DISABLE : 2889 CX0_P4PG_STATE_DISABLE); 2890 2891 /* 2892 * 2. Follow the Display Voltage Frequency Switching Sequence Before 2893 * Frequency Change. We handle this step in bxt_set_cdclk(). 2894 */ 2895 2896 /* 2897 * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK> 2898 * to "0" to disable PLL. 2899 */ 2900 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2901 intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) | 2902 intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0); 2903 2904 /* 4. Program DDI_CLK_VALFREQ to 0. */ 2905 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); 2906 2907 /* 2908 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0". 2909 */ 2910 if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2911 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) | 2912 intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0, 2913 XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL)) 2914 drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n", 2915 phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US); 2916 2917 /* 2918 * 6. Follow the Display Voltage Frequency Switching Sequence After 2919 * Frequency Change. We handle this step in bxt_set_cdclk(). 2920 */ 2921 2922 /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */ 2923 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2924 XELPDP_DDI_CLOCK_SELECT_MASK, 0); 2925 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2926 XELPDP_FORWARD_CLOCK_UNGATE, 0); 2927 2928 intel_cx0_phy_transaction_end(encoder, wakeref); 2929 } 2930 2931 static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) 2932 { 2933 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2934 enum phy phy = intel_port_to_phy(i915, encoder->port); 2935 2936 /* 2937 * 1. Follow the Display Voltage Frequency Switching Sequence Before 2938 * Frequency Change. We handle this step in bxt_set_cdclk(). 2939 */ 2940 2941 /* 2942 * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL. 2943 */ 2944 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2945 XELPDP_TBT_CLOCK_REQUEST, 0); 2946 2947 /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ 2948 if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2949 XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL)) 2950 drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n", 2951 encoder->base.base.id, encoder->base.name, phy_name(phy)); 2952 2953 /* 2954 * 4. Follow the Display Voltage Frequency Switching Sequence After 2955 * Frequency Change. We handle this step in bxt_set_cdclk(). 2956 */ 2957 2958 /* 2959 * 5. Program PORT CLOCK CTRL register to disable and gate clocks 2960 */ 2961 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), 2962 XELPDP_DDI_CLOCK_SELECT_MASK | 2963 XELPDP_FORWARD_CLOCK_UNGATE, 0); 2964 2965 /* 6. Program DDI_CLK_VALFREQ to 0. */ 2966 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); 2967 } 2968 2969 void intel_mtl_pll_disable(struct intel_encoder *encoder) 2970 { 2971 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2972 2973 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2974 intel_mtl_tbt_pll_disable(encoder); 2975 else 2976 intel_cx0pll_disable(encoder); 2977 } 2978 2979 enum icl_port_dpll_id 2980 intel_mtl_port_pll_type(struct intel_encoder *encoder, 2981 const struct intel_crtc_state *crtc_state) 2982 { 2983 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2984 /* 2985 * TODO: Determine the PLL type from the SW state, once MTL PLL 2986 * handling is done via the standard shared DPLL framework. 2987 */ 2988 u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port)); 2989 u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val); 2990 2991 if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK || 2992 clock == XELPDP_DDI_CLOCK_SELECT_DIV18CLK) 2993 return ICL_PORT_DPLL_MG_PHY; 2994 else 2995 return ICL_PORT_DPLL_DEFAULT; 2996 } 2997 2998 void intel_c10pll_state_verify(struct intel_atomic_state *state, 2999 struct intel_crtc_state *new_crtc_state) 3000 { 3001 struct drm_i915_private *i915 = to_i915(state->base.dev); 3002 struct intel_c10pll_state mpllb_hw_state = { 0 }; 3003 struct intel_c10pll_state *mpllb_sw_state = &new_crtc_state->cx0pll_state.c10; 3004 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 3005 struct intel_encoder *encoder; 3006 enum phy phy; 3007 int i; 3008 3009 if (DISPLAY_VER(i915) < 14) 3010 return; 3011 3012 if (!new_crtc_state->hw.active) 3013 return; 3014 3015 /* intel_get_crtc_new_encoder() only works for modeset/fastset commits */ 3016 if (!intel_crtc_needs_modeset(new_crtc_state) && 3017 !intel_crtc_needs_fastset(new_crtc_state)) 3018 return; 3019 3020 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 3021 phy = intel_port_to_phy(i915, encoder->port); 3022 3023 if (!intel_is_c10phy(i915, phy)) 3024 return; 3025 3026 intel_c10pll_readout_hw_state(encoder, &mpllb_hw_state); 3027 3028 for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { 3029 u8 expected = mpllb_sw_state->pll[i]; 3030 3031 I915_STATE_WARN(i915, mpllb_hw_state.pll[i] != expected, 3032 "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", 3033 crtc->base.base.id, crtc->base.name, i, 3034 expected, mpllb_hw_state.pll[i]); 3035 } 3036 3037 I915_STATE_WARN(i915, mpllb_hw_state.tx != mpllb_sw_state->tx, 3038 "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", 3039 crtc->base.base.id, crtc->base.name, 3040 mpllb_sw_state->tx, mpllb_hw_state.tx); 3041 3042 I915_STATE_WARN(i915, mpllb_hw_state.cmn != mpllb_sw_state->cmn, 3043 "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", 3044 crtc->base.base.id, crtc->base.name, 3045 mpllb_sw_state->cmn, mpllb_hw_state.cmn); 3046 } 3047