1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/log2.h> 7 #include <linux/math64.h> 8 #include "i915_reg.h" 9 #include "intel_cx0_phy.h" 10 #include "intel_cx0_phy_regs.h" 11 #include "intel_ddi.h" 12 #include "intel_ddi_buf_trans.h" 13 #include "intel_de.h" 14 #include "intel_display_types.h" 15 #include "intel_dp.h" 16 #include "intel_hdmi.h" 17 #include "intel_panel.h" 18 #include "intel_psr.h" 19 #include "intel_tc.h" 20 21 #define MB_WRITE_COMMITTED true 22 #define MB_WRITE_UNCOMMITTED false 23 24 #define for_each_cx0_lane_in_mask(__lane_mask, __lane) \ 25 for ((__lane) = 0; (__lane) < 2; (__lane)++) \ 26 for_each_if((__lane_mask) & BIT(__lane)) 27 28 #define INTEL_CX0_LANE0 BIT(0) 29 #define INTEL_CX0_LANE1 BIT(1) 30 #define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0) 31 32 bool intel_encoder_is_c10phy(struct intel_encoder *encoder) 33 { 34 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 35 enum phy phy = intel_encoder_to_phy(encoder); 36 37 if (IS_PANTHERLAKE(i915) && phy == PHY_A) 38 return true; 39 40 if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C) 41 return true; 42 43 return false; 44 } 45 46 static int lane_mask_to_lane(u8 lane_mask) 47 { 48 if (WARN_ON((lane_mask & ~INTEL_CX0_BOTH_LANES) || 49 hweight8(lane_mask) != 1)) 50 return 0; 51 52 return ilog2(lane_mask); 53 } 54 55 static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder) 56 { 57 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 58 59 if (!intel_tc_port_in_dp_alt_mode(dig_port)) 60 return INTEL_CX0_BOTH_LANES; 61 62 /* 63 * In DP-alt with pin assignment D, only PHY lane 0 is owned 64 * by display and lane 1 is owned by USB. 65 */ 66 return intel_tc_port_max_lane_count(dig_port) > 2 67 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; 68 } 69 70 static void 71 assert_dc_off(struct intel_display *display) 72 { 73 struct drm_i915_private *i915 = to_i915(display->drm); 74 bool enabled; 75 76 enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF); 77 drm_WARN_ON(display->drm, !enabled); 78 } 79 80 static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder) 81 { 82 struct intel_display *display = to_intel_display(encoder); 83 int lane; 84 85 for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane) 86 intel_de_rmw(display, 87 XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane), 88 XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, 89 XELPDP_PORT_MSGBUS_TIMER_VAL); 90 } 91 92 /* 93 * Prepare HW for CX0 phy transactions. 94 * 95 * It is required that PSR and DC5/6 are disabled before any CX0 message 96 * bus transaction is executed. 97 * 98 * We also do the msgbus timer programming here to ensure that the timer 99 * is already programmed before any access to the msgbus. 100 */ 101 static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder) 102 { 103 intel_wakeref_t wakeref; 104 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 105 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 106 107 intel_psr_pause(intel_dp); 108 wakeref = intel_display_power_get(i915, POWER_DOMAIN_DC_OFF); 109 intel_cx0_program_msgbus_timer(encoder); 110 111 return wakeref; 112 } 113 114 static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref) 115 { 116 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 117 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 118 119 intel_psr_resume(intel_dp); 120 intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref); 121 } 122 123 static void intel_clear_response_ready_flag(struct intel_encoder *encoder, 124 int lane) 125 { 126 struct intel_display *display = to_intel_display(encoder); 127 128 intel_de_rmw(display, 129 XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane), 130 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET); 131 } 132 133 static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane) 134 { 135 struct intel_display *display = to_intel_display(encoder); 136 enum port port = encoder->port; 137 enum phy phy = intel_encoder_to_phy(encoder); 138 139 intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), 140 XELPDP_PORT_M2P_TRANSACTION_RESET); 141 142 if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), 143 XELPDP_PORT_M2P_TRANSACTION_RESET, 144 XELPDP_MSGBUS_TIMEOUT_SLOW)) { 145 drm_err_once(display->drm, 146 "Failed to bring PHY %c to idle.\n", 147 phy_name(phy)); 148 return; 149 } 150 151 intel_clear_response_ready_flag(encoder, lane); 152 } 153 154 static int intel_cx0_wait_for_ack(struct intel_encoder *encoder, 155 int command, int lane, u32 *val) 156 { 157 struct intel_display *display = to_intel_display(encoder); 158 enum port port = encoder->port; 159 enum phy phy = intel_encoder_to_phy(encoder); 160 161 if (intel_de_wait_custom(display, 162 XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane), 163 XELPDP_PORT_P2M_RESPONSE_READY, 164 XELPDP_PORT_P2M_RESPONSE_READY, 165 XELPDP_MSGBUS_TIMEOUT_FAST_US, 166 XELPDP_MSGBUS_TIMEOUT_SLOW, val)) { 167 drm_dbg_kms(display->drm, 168 "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", 169 phy_name(phy), *val); 170 171 if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) & 172 XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT)) 173 drm_dbg_kms(display->drm, 174 "PHY %c Hardware did not detect a timeout\n", 175 phy_name(phy)); 176 177 intel_cx0_bus_reset(encoder, lane); 178 return -ETIMEDOUT; 179 } 180 181 if (*val & XELPDP_PORT_P2M_ERROR_SET) { 182 drm_dbg_kms(display->drm, 183 "PHY %c Error occurred during %s command. Status: 0x%x\n", 184 phy_name(phy), 185 command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val); 186 intel_cx0_bus_reset(encoder, lane); 187 return -EINVAL; 188 } 189 190 if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) { 191 drm_dbg_kms(display->drm, 192 "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", 193 phy_name(phy), 194 command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val); 195 intel_cx0_bus_reset(encoder, lane); 196 return -EINVAL; 197 } 198 199 return 0; 200 } 201 202 static int __intel_cx0_read_once(struct intel_encoder *encoder, 203 int lane, u16 addr) 204 { 205 struct intel_display *display = to_intel_display(encoder); 206 enum port port = encoder->port; 207 enum phy phy = intel_encoder_to_phy(encoder); 208 int ack; 209 u32 val; 210 211 if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), 212 XELPDP_PORT_M2P_TRANSACTION_PENDING, 213 XELPDP_MSGBUS_TIMEOUT_SLOW)) { 214 drm_dbg_kms(display->drm, 215 "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy)); 216 intel_cx0_bus_reset(encoder, lane); 217 return -ETIMEDOUT; 218 } 219 220 intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), 221 XELPDP_PORT_M2P_TRANSACTION_PENDING | 222 XELPDP_PORT_M2P_COMMAND_READ | 223 XELPDP_PORT_M2P_ADDRESS(addr)); 224 225 ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_READ_ACK, lane, &val); 226 if (ack < 0) 227 return ack; 228 229 intel_clear_response_ready_flag(encoder, lane); 230 231 /* 232 * FIXME: Workaround to let HW to settle 233 * down and let the message bus to end up 234 * in a known state 235 */ 236 if (DISPLAY_VER(display) < 30) 237 intel_cx0_bus_reset(encoder, lane); 238 239 return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val); 240 } 241 242 static u8 __intel_cx0_read(struct intel_encoder *encoder, 243 int lane, u16 addr) 244 { 245 struct intel_display *display = to_intel_display(encoder); 246 enum phy phy = intel_encoder_to_phy(encoder); 247 int i, status; 248 249 assert_dc_off(display); 250 251 /* 3 tries is assumed to be enough to read successfully */ 252 for (i = 0; i < 3; i++) { 253 status = __intel_cx0_read_once(encoder, lane, addr); 254 255 if (status >= 0) 256 return status; 257 } 258 259 drm_err_once(display->drm, 260 "PHY %c Read %04x failed after %d retries.\n", 261 phy_name(phy), addr, i); 262 263 return 0; 264 } 265 266 static u8 intel_cx0_read(struct intel_encoder *encoder, 267 u8 lane_mask, u16 addr) 268 { 269 int lane = lane_mask_to_lane(lane_mask); 270 271 return __intel_cx0_read(encoder, lane, addr); 272 } 273 274 static int __intel_cx0_write_once(struct intel_encoder *encoder, 275 int lane, u16 addr, u8 data, bool committed) 276 { 277 struct intel_display *display = to_intel_display(encoder); 278 enum port port = encoder->port; 279 enum phy phy = intel_encoder_to_phy(encoder); 280 int ack; 281 u32 val; 282 283 if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), 284 XELPDP_PORT_M2P_TRANSACTION_PENDING, 285 XELPDP_MSGBUS_TIMEOUT_SLOW)) { 286 drm_dbg_kms(display->drm, 287 "PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy)); 288 intel_cx0_bus_reset(encoder, lane); 289 return -ETIMEDOUT; 290 } 291 292 intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), 293 XELPDP_PORT_M2P_TRANSACTION_PENDING | 294 (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED : 295 XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) | 296 XELPDP_PORT_M2P_DATA(data) | 297 XELPDP_PORT_M2P_ADDRESS(addr)); 298 299 if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), 300 XELPDP_PORT_M2P_TRANSACTION_PENDING, 301 XELPDP_MSGBUS_TIMEOUT_SLOW)) { 302 drm_dbg_kms(display->drm, 303 "PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy)); 304 intel_cx0_bus_reset(encoder, lane); 305 return -ETIMEDOUT; 306 } 307 308 if (committed) { 309 ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val); 310 if (ack < 0) 311 return ack; 312 } else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) & 313 XELPDP_PORT_P2M_ERROR_SET)) { 314 drm_dbg_kms(display->drm, 315 "PHY %c Error occurred during write command.\n", phy_name(phy)); 316 intel_cx0_bus_reset(encoder, lane); 317 return -EINVAL; 318 } 319 320 intel_clear_response_ready_flag(encoder, lane); 321 322 /* 323 * FIXME: Workaround to let HW to settle 324 * down and let the message bus to end up 325 * in a known state 326 */ 327 if (DISPLAY_VER(display) < 30) 328 intel_cx0_bus_reset(encoder, lane); 329 330 return 0; 331 } 332 333 static void __intel_cx0_write(struct intel_encoder *encoder, 334 int lane, u16 addr, u8 data, bool committed) 335 { 336 struct intel_display *display = to_intel_display(encoder); 337 enum phy phy = intel_encoder_to_phy(encoder); 338 int i, status; 339 340 assert_dc_off(display); 341 342 /* 3 tries is assumed to be enough to write successfully */ 343 for (i = 0; i < 3; i++) { 344 status = __intel_cx0_write_once(encoder, lane, addr, data, committed); 345 346 if (status == 0) 347 return; 348 } 349 350 drm_err_once(display->drm, 351 "PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i); 352 } 353 354 static void intel_cx0_write(struct intel_encoder *encoder, 355 u8 lane_mask, u16 addr, u8 data, bool committed) 356 { 357 int lane; 358 359 for_each_cx0_lane_in_mask(lane_mask, lane) 360 __intel_cx0_write(encoder, lane, addr, data, committed); 361 } 362 363 static void intel_c20_sram_write(struct intel_encoder *encoder, 364 int lane, u16 addr, u16 data) 365 { 366 struct intel_display *display = to_intel_display(encoder); 367 368 assert_dc_off(display); 369 370 intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0); 371 intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0); 372 373 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_H, data >> 8, 0); 374 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_L, data & 0xff, 1); 375 } 376 377 static u16 intel_c20_sram_read(struct intel_encoder *encoder, 378 int lane, u16 addr) 379 { 380 struct intel_display *display = to_intel_display(encoder); 381 u16 val; 382 383 assert_dc_off(display); 384 385 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0); 386 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1); 387 388 val = intel_cx0_read(encoder, lane, PHY_C20_RD_DATA_H); 389 val <<= 8; 390 val |= intel_cx0_read(encoder, lane, PHY_C20_RD_DATA_L); 391 392 return val; 393 } 394 395 static void __intel_cx0_rmw(struct intel_encoder *encoder, 396 int lane, u16 addr, u8 clear, u8 set, bool committed) 397 { 398 u8 old, val; 399 400 old = __intel_cx0_read(encoder, lane, addr); 401 val = (old & ~clear) | set; 402 403 if (val != old) 404 __intel_cx0_write(encoder, lane, addr, val, committed); 405 } 406 407 static void intel_cx0_rmw(struct intel_encoder *encoder, 408 u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed) 409 { 410 u8 lane; 411 412 for_each_cx0_lane_in_mask(lane_mask, lane) 413 __intel_cx0_rmw(encoder, lane, addr, clear, set, committed); 414 } 415 416 static u8 intel_c10_get_tx_vboost_lvl(const struct intel_crtc_state *crtc_state) 417 { 418 if (intel_crtc_has_dp_encoder(crtc_state)) { 419 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 420 (crtc_state->port_clock == 540000 || 421 crtc_state->port_clock == 810000)) 422 return 5; 423 else 424 return 4; 425 } else { 426 return 5; 427 } 428 } 429 430 static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state) 431 { 432 if (intel_crtc_has_dp_encoder(crtc_state)) { 433 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 434 (crtc_state->port_clock == 540000 || 435 crtc_state->port_clock == 810000)) 436 return 5; 437 else 438 return 2; 439 } else { 440 return 6; 441 } 442 } 443 444 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, 445 const struct intel_crtc_state *crtc_state) 446 { 447 struct intel_display *display = to_intel_display(encoder); 448 const struct intel_ddi_buf_trans *trans; 449 u8 owned_lane_mask; 450 intel_wakeref_t wakeref; 451 int n_entries, ln; 452 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 453 454 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 455 return; 456 457 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); 458 459 wakeref = intel_cx0_phy_transaction_begin(encoder); 460 461 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 462 if (drm_WARN_ON_ONCE(display->drm, !trans)) { 463 intel_cx0_phy_transaction_end(encoder, wakeref); 464 return; 465 } 466 467 if (intel_encoder_is_c10phy(encoder)) { 468 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 469 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); 470 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3), 471 C10_CMN3_TXVBOOST_MASK, 472 C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)), 473 MB_WRITE_UNCOMMITTED); 474 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_TX(1), 475 C10_TX1_TERMCTL_MASK, 476 C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)), 477 MB_WRITE_COMMITTED); 478 } 479 480 for (ln = 0; ln < crtc_state->lane_count; ln++) { 481 int level = intel_ddi_level(encoder, crtc_state, ln); 482 int lane = ln / 2; 483 int tx = ln % 2; 484 u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; 485 486 if (!(lane_mask & owned_lane_mask)) 487 continue; 488 489 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0), 490 C10_PHY_OVRD_LEVEL_MASK, 491 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor), 492 MB_WRITE_COMMITTED); 493 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1), 494 C10_PHY_OVRD_LEVEL_MASK, 495 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing), 496 MB_WRITE_COMMITTED); 497 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2), 498 C10_PHY_OVRD_LEVEL_MASK, 499 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor), 500 MB_WRITE_COMMITTED); 501 } 502 503 /* Write Override enables in 0xD71 */ 504 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_OVRD, 505 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2, 506 MB_WRITE_COMMITTED); 507 508 if (intel_encoder_is_c10phy(encoder)) 509 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 510 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); 511 512 intel_cx0_phy_transaction_end(encoder, wakeref); 513 } 514 515 /* 516 * Basic DP link rates with 38.4 MHz reference clock. 517 * Note: The tables below are with SSC. In non-ssc 518 * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be 519 * programmed 0. 520 */ 521 522 static const struct intel_c10pll_state mtl_c10_dp_rbr = { 523 .clock = 162000, 524 .tx = 0x10, 525 .cmn = 0x21, 526 .pll[0] = 0xB4, 527 .pll[1] = 0, 528 .pll[2] = 0x30, 529 .pll[3] = 0x1, 530 .pll[4] = 0x26, 531 .pll[5] = 0x0C, 532 .pll[6] = 0x98, 533 .pll[7] = 0x46, 534 .pll[8] = 0x1, 535 .pll[9] = 0x1, 536 .pll[10] = 0, 537 .pll[11] = 0, 538 .pll[12] = 0xC0, 539 .pll[13] = 0, 540 .pll[14] = 0, 541 .pll[15] = 0x2, 542 .pll[16] = 0x84, 543 .pll[17] = 0x4F, 544 .pll[18] = 0xE5, 545 .pll[19] = 0x23, 546 }; 547 548 static const struct intel_c10pll_state mtl_c10_edp_r216 = { 549 .clock = 216000, 550 .tx = 0x10, 551 .cmn = 0x21, 552 .pll[0] = 0x4, 553 .pll[1] = 0, 554 .pll[2] = 0xA2, 555 .pll[3] = 0x1, 556 .pll[4] = 0x33, 557 .pll[5] = 0x10, 558 .pll[6] = 0x75, 559 .pll[7] = 0xB3, 560 .pll[8] = 0x1, 561 .pll[9] = 0x1, 562 .pll[10] = 0, 563 .pll[11] = 0, 564 .pll[12] = 0, 565 .pll[13] = 0, 566 .pll[14] = 0, 567 .pll[15] = 0x2, 568 .pll[16] = 0x85, 569 .pll[17] = 0x0F, 570 .pll[18] = 0xE6, 571 .pll[19] = 0x23, 572 }; 573 574 static const struct intel_c10pll_state mtl_c10_edp_r243 = { 575 .clock = 243000, 576 .tx = 0x10, 577 .cmn = 0x21, 578 .pll[0] = 0x34, 579 .pll[1] = 0, 580 .pll[2] = 0xDA, 581 .pll[3] = 0x1, 582 .pll[4] = 0x39, 583 .pll[5] = 0x12, 584 .pll[6] = 0xE3, 585 .pll[7] = 0xE9, 586 .pll[8] = 0x1, 587 .pll[9] = 0x1, 588 .pll[10] = 0, 589 .pll[11] = 0, 590 .pll[12] = 0x20, 591 .pll[13] = 0, 592 .pll[14] = 0, 593 .pll[15] = 0x2, 594 .pll[16] = 0x85, 595 .pll[17] = 0x8F, 596 .pll[18] = 0xE6, 597 .pll[19] = 0x23, 598 }; 599 600 static const struct intel_c10pll_state mtl_c10_dp_hbr1 = { 601 .clock = 270000, 602 .tx = 0x10, 603 .cmn = 0x21, 604 .pll[0] = 0xF4, 605 .pll[1] = 0, 606 .pll[2] = 0xF8, 607 .pll[3] = 0x0, 608 .pll[4] = 0x20, 609 .pll[5] = 0x0A, 610 .pll[6] = 0x29, 611 .pll[7] = 0x10, 612 .pll[8] = 0x1, /* Verify */ 613 .pll[9] = 0x1, 614 .pll[10] = 0, 615 .pll[11] = 0, 616 .pll[12] = 0xA0, 617 .pll[13] = 0, 618 .pll[14] = 0, 619 .pll[15] = 0x1, 620 .pll[16] = 0x84, 621 .pll[17] = 0x4F, 622 .pll[18] = 0xE5, 623 .pll[19] = 0x23, 624 }; 625 626 static const struct intel_c10pll_state mtl_c10_edp_r324 = { 627 .clock = 324000, 628 .tx = 0x10, 629 .cmn = 0x21, 630 .pll[0] = 0xB4, 631 .pll[1] = 0, 632 .pll[2] = 0x30, 633 .pll[3] = 0x1, 634 .pll[4] = 0x26, 635 .pll[5] = 0x0C, 636 .pll[6] = 0x98, 637 .pll[7] = 0x46, 638 .pll[8] = 0x1, 639 .pll[9] = 0x1, 640 .pll[10] = 0, 641 .pll[11] = 0, 642 .pll[12] = 0xC0, 643 .pll[13] = 0, 644 .pll[14] = 0, 645 .pll[15] = 0x1, 646 .pll[16] = 0x85, 647 .pll[17] = 0x4F, 648 .pll[18] = 0xE6, 649 .pll[19] = 0x23, 650 }; 651 652 static const struct intel_c10pll_state mtl_c10_edp_r432 = { 653 .clock = 432000, 654 .tx = 0x10, 655 .cmn = 0x21, 656 .pll[0] = 0x4, 657 .pll[1] = 0, 658 .pll[2] = 0xA2, 659 .pll[3] = 0x1, 660 .pll[4] = 0x33, 661 .pll[5] = 0x10, 662 .pll[6] = 0x75, 663 .pll[7] = 0xB3, 664 .pll[8] = 0x1, 665 .pll[9] = 0x1, 666 .pll[10] = 0, 667 .pll[11] = 0, 668 .pll[12] = 0, 669 .pll[13] = 0, 670 .pll[14] = 0, 671 .pll[15] = 0x1, 672 .pll[16] = 0x85, 673 .pll[17] = 0x0F, 674 .pll[18] = 0xE6, 675 .pll[19] = 0x23, 676 }; 677 678 static const struct intel_c10pll_state mtl_c10_dp_hbr2 = { 679 .clock = 540000, 680 .tx = 0x10, 681 .cmn = 0x21, 682 .pll[0] = 0xF4, 683 .pll[1] = 0, 684 .pll[2] = 0xF8, 685 .pll[3] = 0, 686 .pll[4] = 0x20, 687 .pll[5] = 0x0A, 688 .pll[6] = 0x29, 689 .pll[7] = 0x10, 690 .pll[8] = 0x1, 691 .pll[9] = 0x1, 692 .pll[10] = 0, 693 .pll[11] = 0, 694 .pll[12] = 0xA0, 695 .pll[13] = 0, 696 .pll[14] = 0, 697 .pll[15] = 0, 698 .pll[16] = 0x84, 699 .pll[17] = 0x4F, 700 .pll[18] = 0xE5, 701 .pll[19] = 0x23, 702 }; 703 704 static const struct intel_c10pll_state mtl_c10_edp_r675 = { 705 .clock = 675000, 706 .tx = 0x10, 707 .cmn = 0x21, 708 .pll[0] = 0xB4, 709 .pll[1] = 0, 710 .pll[2] = 0x3E, 711 .pll[3] = 0x1, 712 .pll[4] = 0xA8, 713 .pll[5] = 0x0C, 714 .pll[6] = 0x33, 715 .pll[7] = 0x54, 716 .pll[8] = 0x1, 717 .pll[9] = 0x1, 718 .pll[10] = 0, 719 .pll[11] = 0, 720 .pll[12] = 0xC8, 721 .pll[13] = 0, 722 .pll[14] = 0, 723 .pll[15] = 0, 724 .pll[16] = 0x85, 725 .pll[17] = 0x8F, 726 .pll[18] = 0xE6, 727 .pll[19] = 0x23, 728 }; 729 730 static const struct intel_c10pll_state mtl_c10_dp_hbr3 = { 731 .clock = 810000, 732 .tx = 0x10, 733 .cmn = 0x21, 734 .pll[0] = 0x34, 735 .pll[1] = 0, 736 .pll[2] = 0x84, 737 .pll[3] = 0x1, 738 .pll[4] = 0x30, 739 .pll[5] = 0x0F, 740 .pll[6] = 0x3D, 741 .pll[7] = 0x98, 742 .pll[8] = 0x1, 743 .pll[9] = 0x1, 744 .pll[10] = 0, 745 .pll[11] = 0, 746 .pll[12] = 0xF0, 747 .pll[13] = 0, 748 .pll[14] = 0, 749 .pll[15] = 0, 750 .pll[16] = 0x84, 751 .pll[17] = 0x0F, 752 .pll[18] = 0xE5, 753 .pll[19] = 0x23, 754 }; 755 756 static const struct intel_c10pll_state * const mtl_c10_dp_tables[] = { 757 &mtl_c10_dp_rbr, 758 &mtl_c10_dp_hbr1, 759 &mtl_c10_dp_hbr2, 760 &mtl_c10_dp_hbr3, 761 NULL, 762 }; 763 764 static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = { 765 &mtl_c10_dp_rbr, 766 &mtl_c10_edp_r216, 767 &mtl_c10_edp_r243, 768 &mtl_c10_dp_hbr1, 769 &mtl_c10_edp_r324, 770 &mtl_c10_edp_r432, 771 &mtl_c10_dp_hbr2, 772 &mtl_c10_edp_r675, 773 &mtl_c10_dp_hbr3, 774 NULL, 775 }; 776 777 /* C20 basic DP 1.4 tables */ 778 static const struct intel_c20pll_state mtl_c20_dp_rbr = { 779 .clock = 162000, 780 .tx = { 0xbe88, /* tx cfg0 */ 781 0x5800, /* tx cfg1 */ 782 0x0000, /* tx cfg2 */ 783 }, 784 .cmn = {0x0500, /* cmn cfg0*/ 785 0x0005, /* cmn cfg1 */ 786 0x0000, /* cmn cfg2 */ 787 0x0000, /* cmn cfg3 */ 788 }, 789 .mpllb = { 0x50a8, /* mpllb cfg0 */ 790 0x2120, /* mpllb cfg1 */ 791 0xcd9a, /* mpllb cfg2 */ 792 0xbfc1, /* mpllb cfg3 */ 793 0x5ab8, /* mpllb cfg4 */ 794 0x4c34, /* mpllb cfg5 */ 795 0x2000, /* mpllb cfg6 */ 796 0x0001, /* mpllb cfg7 */ 797 0x6000, /* mpllb cfg8 */ 798 0x0000, /* mpllb cfg9 */ 799 0x0000, /* mpllb cfg10 */ 800 }, 801 }; 802 803 static const struct intel_c20pll_state mtl_c20_dp_hbr1 = { 804 .clock = 270000, 805 .tx = { 0xbe88, /* tx cfg0 */ 806 0x4800, /* tx cfg1 */ 807 0x0000, /* tx cfg2 */ 808 }, 809 .cmn = {0x0500, /* cmn cfg0*/ 810 0x0005, /* cmn cfg1 */ 811 0x0000, /* cmn cfg2 */ 812 0x0000, /* cmn cfg3 */ 813 }, 814 .mpllb = { 0x308c, /* mpllb cfg0 */ 815 0x2110, /* mpllb cfg1 */ 816 0xcc9c, /* mpllb cfg2 */ 817 0xbfc1, /* mpllb cfg3 */ 818 0x4b9a, /* mpllb cfg4 */ 819 0x3f81, /* mpllb cfg5 */ 820 0x2000, /* mpllb cfg6 */ 821 0x0001, /* mpllb cfg7 */ 822 0x5000, /* mpllb cfg8 */ 823 0x0000, /* mpllb cfg9 */ 824 0x0000, /* mpllb cfg10 */ 825 }, 826 }; 827 828 static const struct intel_c20pll_state mtl_c20_dp_hbr2 = { 829 .clock = 540000, 830 .tx = { 0xbe88, /* tx cfg0 */ 831 0x4800, /* tx cfg1 */ 832 0x0000, /* tx cfg2 */ 833 }, 834 .cmn = {0x0500, /* cmn cfg0*/ 835 0x0005, /* cmn cfg1 */ 836 0x0000, /* cmn cfg2 */ 837 0x0000, /* cmn cfg3 */ 838 }, 839 .mpllb = { 0x108c, /* mpllb cfg0 */ 840 0x2108, /* mpllb cfg1 */ 841 0xcc9c, /* mpllb cfg2 */ 842 0xbfc1, /* mpllb cfg3 */ 843 0x4b9a, /* mpllb cfg4 */ 844 0x3f81, /* mpllb cfg5 */ 845 0x2000, /* mpllb cfg6 */ 846 0x0001, /* mpllb cfg7 */ 847 0x5000, /* mpllb cfg8 */ 848 0x0000, /* mpllb cfg9 */ 849 0x0000, /* mpllb cfg10 */ 850 }, 851 }; 852 853 static const struct intel_c20pll_state mtl_c20_dp_hbr3 = { 854 .clock = 810000, 855 .tx = { 0xbe88, /* tx cfg0 */ 856 0x4800, /* tx cfg1 */ 857 0x0000, /* tx cfg2 */ 858 }, 859 .cmn = {0x0500, /* cmn cfg0*/ 860 0x0005, /* cmn cfg1 */ 861 0x0000, /* cmn cfg2 */ 862 0x0000, /* cmn cfg3 */ 863 }, 864 .mpllb = { 0x10d2, /* mpllb cfg0 */ 865 0x2108, /* mpllb cfg1 */ 866 0x8d98, /* mpllb cfg2 */ 867 0xbfc1, /* mpllb cfg3 */ 868 0x7166, /* mpllb cfg4 */ 869 0x5f42, /* mpllb cfg5 */ 870 0x2000, /* mpllb cfg6 */ 871 0x0001, /* mpllb cfg7 */ 872 0x7800, /* mpllb cfg8 */ 873 0x0000, /* mpllb cfg9 */ 874 0x0000, /* mpllb cfg10 */ 875 }, 876 }; 877 878 /* C20 basic DP 2.0 tables */ 879 static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = { 880 .clock = 1000000, /* 10 Gbps */ 881 .tx = { 0xbe21, /* tx cfg0 */ 882 0xe800, /* tx cfg1 */ 883 0x0000, /* tx cfg2 */ 884 }, 885 .cmn = {0x0700, /* cmn cfg0*/ 886 0x0005, /* cmn cfg1 */ 887 0x0000, /* cmn cfg2 */ 888 0x0000, /* cmn cfg3 */ 889 }, 890 .mplla = { 0x3104, /* mplla cfg0 */ 891 0xd105, /* mplla cfg1 */ 892 0xc025, /* mplla cfg2 */ 893 0xc025, /* mplla cfg3 */ 894 0x8c00, /* mplla cfg4 */ 895 0x759a, /* mplla cfg5 */ 896 0x4000, /* mplla cfg6 */ 897 0x0003, /* mplla cfg7 */ 898 0x3555, /* mplla cfg8 */ 899 0x0001, /* mplla cfg9 */ 900 }, 901 }; 902 903 static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = { 904 .clock = 1350000, /* 13.5 Gbps */ 905 .tx = { 0xbea0, /* tx cfg0 */ 906 0x4800, /* tx cfg1 */ 907 0x0000, /* tx cfg2 */ 908 }, 909 .cmn = {0x0500, /* cmn cfg0*/ 910 0x0005, /* cmn cfg1 */ 911 0x0000, /* cmn cfg2 */ 912 0x0000, /* cmn cfg3 */ 913 }, 914 .mpllb = { 0x015f, /* mpllb cfg0 */ 915 0x2205, /* mpllb cfg1 */ 916 0x1b17, /* mpllb cfg2 */ 917 0xffc1, /* mpllb cfg3 */ 918 0xe100, /* mpllb cfg4 */ 919 0xbd00, /* mpllb cfg5 */ 920 0x2000, /* mpllb cfg6 */ 921 0x0001, /* mpllb cfg7 */ 922 0x4800, /* mpllb cfg8 */ 923 0x0000, /* mpllb cfg9 */ 924 0x0000, /* mpllb cfg10 */ 925 }, 926 }; 927 928 static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = { 929 .clock = 2000000, /* 20 Gbps */ 930 .tx = { 0xbe20, /* tx cfg0 */ 931 0x4800, /* tx cfg1 */ 932 0x0000, /* tx cfg2 */ 933 }, 934 .cmn = {0x0500, /* cmn cfg0*/ 935 0x0005, /* cmn cfg1 */ 936 0x0000, /* cmn cfg2 */ 937 0x0000, /* cmn cfg3 */ 938 }, 939 .mplla = { 0x3104, /* mplla cfg0 */ 940 0xd105, /* mplla cfg1 */ 941 0x9217, /* mplla cfg2 */ 942 0x9217, /* mplla cfg3 */ 943 0x8c00, /* mplla cfg4 */ 944 0x759a, /* mplla cfg5 */ 945 0x4000, /* mplla cfg6 */ 946 0x0003, /* mplla cfg7 */ 947 0x3555, /* mplla cfg8 */ 948 0x0001, /* mplla cfg9 */ 949 }, 950 }; 951 952 static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = { 953 &mtl_c20_dp_rbr, 954 &mtl_c20_dp_hbr1, 955 &mtl_c20_dp_hbr2, 956 &mtl_c20_dp_hbr3, 957 &mtl_c20_dp_uhbr10, 958 &mtl_c20_dp_uhbr13_5, 959 &mtl_c20_dp_uhbr20, 960 NULL, 961 }; 962 963 /* 964 * eDP link rates with 38.4 MHz reference clock. 965 */ 966 967 static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = { 968 .clock = 216000, 969 .tx = { 0xbe88, 970 0x4800, 971 0x0000, 972 }, 973 .cmn = { 0x0500, 974 0x0005, 975 0x0000, 976 0x0000, 977 }, 978 .mpllb = { 0x50e1, 979 0x2120, 980 0x8e18, 981 0xbfc1, 982 0x9000, 983 0x78f6, 984 0x0000, 985 0x0000, 986 0x0000, 987 0x0000, 988 0x0000, 989 }, 990 }; 991 992 static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = { 993 .clock = 243000, 994 .tx = { 0xbe88, 995 0x4800, 996 0x0000, 997 }, 998 .cmn = { 0x0500, 999 0x0005, 1000 0x0000, 1001 0x0000, 1002 }, 1003 .mpllb = { 0x50fd, 1004 0x2120, 1005 0x8f18, 1006 0xbfc1, 1007 0xa200, 1008 0x8814, 1009 0x2000, 1010 0x0001, 1011 0x1000, 1012 0x0000, 1013 0x0000, 1014 }, 1015 }; 1016 1017 static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = { 1018 .clock = 324000, 1019 .tx = { 0xbe88, 1020 0x4800, 1021 0x0000, 1022 }, 1023 .cmn = { 0x0500, 1024 0x0005, 1025 0x0000, 1026 0x0000, 1027 }, 1028 .mpllb = { 0x30a8, 1029 0x2110, 1030 0xcd9a, 1031 0xbfc1, 1032 0x6c00, 1033 0x5ab8, 1034 0x2000, 1035 0x0001, 1036 0x6000, 1037 0x0000, 1038 0x0000, 1039 }, 1040 }; 1041 1042 static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = { 1043 .clock = 432000, 1044 .tx = { 0xbe88, 1045 0x4800, 1046 0x0000, 1047 }, 1048 .cmn = { 0x0500, 1049 0x0005, 1050 0x0000, 1051 0x0000, 1052 }, 1053 .mpllb = { 0x30e1, 1054 0x2110, 1055 0x8e18, 1056 0xbfc1, 1057 0x9000, 1058 0x78f6, 1059 0x0000, 1060 0x0000, 1061 0x0000, 1062 0x0000, 1063 0x0000, 1064 }, 1065 }; 1066 1067 static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = { 1068 .clock = 675000, 1069 .tx = { 0xbe88, 1070 0x4800, 1071 0x0000, 1072 }, 1073 .cmn = { 0x0500, 1074 0x0005, 1075 0x0000, 1076 0x0000, 1077 }, 1078 .mpllb = { 0x10af, 1079 0x2108, 1080 0xce1a, 1081 0xbfc1, 1082 0x7080, 1083 0x5e80, 1084 0x2000, 1085 0x0001, 1086 0x6400, 1087 0x0000, 1088 0x0000, 1089 }, 1090 }; 1091 1092 static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = { 1093 &mtl_c20_dp_rbr, 1094 &xe2hpd_c20_edp_r216, 1095 &xe2hpd_c20_edp_r243, 1096 &mtl_c20_dp_hbr1, 1097 &xe2hpd_c20_edp_r324, 1098 &xe2hpd_c20_edp_r432, 1099 &mtl_c20_dp_hbr2, 1100 &xe2hpd_c20_edp_r675, 1101 &mtl_c20_dp_hbr3, 1102 NULL, 1103 }; 1104 1105 static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = { 1106 .clock = 1350000, /* 13.5 Gbps */ 1107 .tx = { 0xbea0, /* tx cfg0 */ 1108 0x4800, /* tx cfg1 */ 1109 0x0000, /* tx cfg2 */ 1110 }, 1111 .cmn = {0x0500, /* cmn cfg0*/ 1112 0x0005, /* cmn cfg1 */ 1113 0x0000, /* cmn cfg2 */ 1114 0x0000, /* cmn cfg3 */ 1115 }, 1116 .mpllb = { 0x015f, /* mpllb cfg0 */ 1117 0x2205, /* mpllb cfg1 */ 1118 0x1b17, /* mpllb cfg2 */ 1119 0xffc1, /* mpllb cfg3 */ 1120 0xbd00, /* mpllb cfg4 */ 1121 0x9ec3, /* mpllb cfg5 */ 1122 0x2000, /* mpllb cfg6 */ 1123 0x0001, /* mpllb cfg7 */ 1124 0x4800, /* mpllb cfg8 */ 1125 0x0000, /* mpllb cfg9 */ 1126 0x0000, /* mpllb cfg10 */ 1127 }, 1128 }; 1129 1130 static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = { 1131 &mtl_c20_dp_rbr, 1132 &mtl_c20_dp_hbr1, 1133 &mtl_c20_dp_hbr2, 1134 &mtl_c20_dp_hbr3, 1135 &mtl_c20_dp_uhbr10, 1136 &xe2hpd_c20_dp_uhbr13_5, 1137 NULL, 1138 }; 1139 1140 static const struct intel_c20pll_state * const xe3lpd_c20_dp_edp_tables[] = { 1141 &mtl_c20_dp_rbr, 1142 &xe2hpd_c20_edp_r216, 1143 &xe2hpd_c20_edp_r243, 1144 &mtl_c20_dp_hbr1, 1145 &xe2hpd_c20_edp_r324, 1146 &xe2hpd_c20_edp_r432, 1147 &mtl_c20_dp_hbr2, 1148 &xe2hpd_c20_edp_r675, 1149 &mtl_c20_dp_hbr3, 1150 &mtl_c20_dp_uhbr10, 1151 &xe2hpd_c20_dp_uhbr13_5, 1152 &mtl_c20_dp_uhbr20, 1153 NULL, 1154 }; 1155 1156 /* 1157 * HDMI link rates with 38.4 MHz reference clock. 1158 */ 1159 1160 static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = { 1161 .clock = 25200, 1162 .tx = 0x10, 1163 .cmn = 0x1, 1164 .pll[0] = 0x4, 1165 .pll[1] = 0, 1166 .pll[2] = 0xB2, 1167 .pll[3] = 0, 1168 .pll[4] = 0, 1169 .pll[5] = 0, 1170 .pll[6] = 0, 1171 .pll[7] = 0, 1172 .pll[8] = 0x20, 1173 .pll[9] = 0x1, 1174 .pll[10] = 0, 1175 .pll[11] = 0, 1176 .pll[12] = 0, 1177 .pll[13] = 0, 1178 .pll[14] = 0, 1179 .pll[15] = 0xD, 1180 .pll[16] = 0x6, 1181 .pll[17] = 0x8F, 1182 .pll[18] = 0x84, 1183 .pll[19] = 0x23, 1184 }; 1185 1186 static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = { 1187 .clock = 27000, 1188 .tx = 0x10, 1189 .cmn = 0x1, 1190 .pll[0] = 0x34, 1191 .pll[1] = 0, 1192 .pll[2] = 0xC0, 1193 .pll[3] = 0, 1194 .pll[4] = 0, 1195 .pll[5] = 0, 1196 .pll[6] = 0, 1197 .pll[7] = 0, 1198 .pll[8] = 0x20, 1199 .pll[9] = 0x1, 1200 .pll[10] = 0, 1201 .pll[11] = 0, 1202 .pll[12] = 0x80, 1203 .pll[13] = 0, 1204 .pll[14] = 0, 1205 .pll[15] = 0xD, 1206 .pll[16] = 0x6, 1207 .pll[17] = 0xCF, 1208 .pll[18] = 0x84, 1209 .pll[19] = 0x23, 1210 }; 1211 1212 static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = { 1213 .clock = 74250, 1214 .tx = 0x10, 1215 .cmn = 0x1, 1216 .pll[0] = 0xF4, 1217 .pll[1] = 0, 1218 .pll[2] = 0x7A, 1219 .pll[3] = 0, 1220 .pll[4] = 0, 1221 .pll[5] = 0, 1222 .pll[6] = 0, 1223 .pll[7] = 0, 1224 .pll[8] = 0x20, 1225 .pll[9] = 0x1, 1226 .pll[10] = 0, 1227 .pll[11] = 0, 1228 .pll[12] = 0x58, 1229 .pll[13] = 0, 1230 .pll[14] = 0, 1231 .pll[15] = 0xB, 1232 .pll[16] = 0x6, 1233 .pll[17] = 0xF, 1234 .pll[18] = 0x85, 1235 .pll[19] = 0x23, 1236 }; 1237 1238 static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = { 1239 .clock = 148500, 1240 .tx = 0x10, 1241 .cmn = 0x1, 1242 .pll[0] = 0xF4, 1243 .pll[1] = 0, 1244 .pll[2] = 0x7A, 1245 .pll[3] = 0, 1246 .pll[4] = 0, 1247 .pll[5] = 0, 1248 .pll[6] = 0, 1249 .pll[7] = 0, 1250 .pll[8] = 0x20, 1251 .pll[9] = 0x1, 1252 .pll[10] = 0, 1253 .pll[11] = 0, 1254 .pll[12] = 0x58, 1255 .pll[13] = 0, 1256 .pll[14] = 0, 1257 .pll[15] = 0xA, 1258 .pll[16] = 0x6, 1259 .pll[17] = 0xF, 1260 .pll[18] = 0x85, 1261 .pll[19] = 0x23, 1262 }; 1263 1264 static const struct intel_c10pll_state mtl_c10_hdmi_594 = { 1265 .clock = 594000, 1266 .tx = 0x10, 1267 .cmn = 0x1, 1268 .pll[0] = 0xF4, 1269 .pll[1] = 0, 1270 .pll[2] = 0x7A, 1271 .pll[3] = 0, 1272 .pll[4] = 0, 1273 .pll[5] = 0, 1274 .pll[6] = 0, 1275 .pll[7] = 0, 1276 .pll[8] = 0x20, 1277 .pll[9] = 0x1, 1278 .pll[10] = 0, 1279 .pll[11] = 0, 1280 .pll[12] = 0x58, 1281 .pll[13] = 0, 1282 .pll[14] = 0, 1283 .pll[15] = 0x8, 1284 .pll[16] = 0x6, 1285 .pll[17] = 0xF, 1286 .pll[18] = 0x85, 1287 .pll[19] = 0x23, 1288 }; 1289 1290 /* Precomputed C10 HDMI PLL tables */ 1291 static const struct intel_c10pll_state mtl_c10_hdmi_27027 = { 1292 .clock = 27027, 1293 .tx = 0x10, 1294 .cmn = 0x1, 1295 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00, 1296 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1297 .pll[10] = 0xFF, .pll[11] = 0xCC, .pll[12] = 0x9C, .pll[13] = 0xCB, .pll[14] = 0xCC, 1298 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1299 }; 1300 1301 static const struct intel_c10pll_state mtl_c10_hdmi_28320 = { 1302 .clock = 28320, 1303 .tx = 0x10, 1304 .cmn = 0x1, 1305 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00, 1306 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1307 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00, 1308 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1309 }; 1310 1311 static const struct intel_c10pll_state mtl_c10_hdmi_30240 = { 1312 .clock = 30240, 1313 .tx = 0x10, 1314 .cmn = 0x1, 1315 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00, 1316 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1317 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00, 1318 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1319 }; 1320 1321 static const struct intel_c10pll_state mtl_c10_hdmi_31500 = { 1322 .clock = 31500, 1323 .tx = 0x10, 1324 .cmn = 0x1, 1325 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00, 1326 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1327 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xA0, .pll[13] = 0x00, .pll[14] = 0x00, 1328 .pll[15] = 0x0C, .pll[16] = 0x09, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1329 }; 1330 1331 static const struct intel_c10pll_state mtl_c10_hdmi_36000 = { 1332 .clock = 36000, 1333 .tx = 0x10, 1334 .cmn = 0x1, 1335 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00, 1336 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1337 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00, 1338 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1339 }; 1340 1341 static const struct intel_c10pll_state mtl_c10_hdmi_40000 = { 1342 .clock = 40000, 1343 .tx = 0x10, 1344 .cmn = 0x1, 1345 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00, 1346 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1347 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x55, .pll[13] = 0x55, .pll[14] = 0x55, 1348 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1349 }; 1350 1351 static const struct intel_c10pll_state mtl_c10_hdmi_49500 = { 1352 .clock = 49500, 1353 .tx = 0x10, 1354 .cmn = 0x1, 1355 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00, 1356 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1357 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00, 1358 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1359 }; 1360 1361 static const struct intel_c10pll_state mtl_c10_hdmi_50000 = { 1362 .clock = 50000, 1363 .tx = 0x10, 1364 .cmn = 0x1, 1365 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00, 1366 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1367 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x2A, .pll[13] = 0xA9, .pll[14] = 0xAA, 1368 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1369 }; 1370 1371 static const struct intel_c10pll_state mtl_c10_hdmi_57284 = { 1372 .clock = 57284, 1373 .tx = 0x10, 1374 .cmn = 0x1, 1375 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00, 1376 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1377 .pll[10] = 0xFF, .pll[11] = 0x77, .pll[12] = 0x57, .pll[13] = 0x77, .pll[14] = 0x77, 1378 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1379 }; 1380 1381 static const struct intel_c10pll_state mtl_c10_hdmi_58000 = { 1382 .clock = 58000, 1383 .tx = 0x10, 1384 .cmn = 0x1, 1385 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00, 1386 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1387 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xD5, .pll[13] = 0x55, .pll[14] = 0x55, 1388 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1389 }; 1390 1391 static const struct intel_c10pll_state mtl_c10_hdmi_65000 = { 1392 .clock = 65000, 1393 .tx = 0x10, 1394 .cmn = 0x1, 1395 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00, 1396 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1397 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xB5, .pll[13] = 0x55, .pll[14] = 0x55, 1398 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1399 }; 1400 1401 static const struct intel_c10pll_state mtl_c10_hdmi_71000 = { 1402 .clock = 71000, 1403 .tx = 0x10, 1404 .cmn = 0x1, 1405 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00, 1406 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1407 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55, 1408 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1409 }; 1410 1411 static const struct intel_c10pll_state mtl_c10_hdmi_74176 = { 1412 .clock = 74176, 1413 .tx = 0x10, 1414 .cmn = 0x1, 1415 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, 1416 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1417 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44, 1418 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1419 }; 1420 1421 static const struct intel_c10pll_state mtl_c10_hdmi_75000 = { 1422 .clock = 75000, 1423 .tx = 0x10, 1424 .cmn = 0x1, 1425 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00, 1426 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1427 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00, 1428 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1429 }; 1430 1431 static const struct intel_c10pll_state mtl_c10_hdmi_78750 = { 1432 .clock = 78750, 1433 .tx = 0x10, 1434 .cmn = 0x1, 1435 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00, 1436 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1437 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x08, .pll[13] = 0x00, .pll[14] = 0x00, 1438 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1439 }; 1440 1441 static const struct intel_c10pll_state mtl_c10_hdmi_85500 = { 1442 .clock = 85500, 1443 .tx = 0x10, 1444 .cmn = 0x1, 1445 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00, 1446 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1447 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x10, .pll[13] = 0x00, .pll[14] = 0x00, 1448 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1449 }; 1450 1451 static const struct intel_c10pll_state mtl_c10_hdmi_88750 = { 1452 .clock = 88750, 1453 .tx = 0x10, 1454 .cmn = 0x1, 1455 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00, 1456 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1457 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x72, .pll[13] = 0xA9, .pll[14] = 0xAA, 1458 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1459 }; 1460 1461 static const struct intel_c10pll_state mtl_c10_hdmi_106500 = { 1462 .clock = 106500, 1463 .tx = 0x10, 1464 .cmn = 0x1, 1465 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00, 1466 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1467 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xF0, .pll[13] = 0x00, .pll[14] = 0x00, 1468 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1469 }; 1470 1471 static const struct intel_c10pll_state mtl_c10_hdmi_108000 = { 1472 .clock = 108000, 1473 .tx = 0x10, 1474 .cmn = 0x1, 1475 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00, 1476 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1477 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x80, .pll[13] = 0x00, .pll[14] = 0x00, 1478 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1479 }; 1480 1481 static const struct intel_c10pll_state mtl_c10_hdmi_115500 = { 1482 .clock = 115500, 1483 .tx = 0x10, 1484 .cmn = 0x1, 1485 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00, 1486 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1487 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00, 1488 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1489 }; 1490 1491 static const struct intel_c10pll_state mtl_c10_hdmi_119000 = { 1492 .clock = 119000, 1493 .tx = 0x10, 1494 .cmn = 0x1, 1495 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00, 1496 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1497 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55, 1498 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1499 }; 1500 1501 static const struct intel_c10pll_state mtl_c10_hdmi_135000 = { 1502 .clock = 135000, 1503 .tx = 0x10, 1504 .cmn = 0x1, 1505 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00, 1506 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1507 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00, 1508 .pll[15] = 0x0A, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1509 }; 1510 1511 static const struct intel_c10pll_state mtl_c10_hdmi_138500 = { 1512 .clock = 138500, 1513 .tx = 0x10, 1514 .cmn = 0x1, 1515 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00, 1516 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1517 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x22, .pll[13] = 0xA9, .pll[14] = 0xAA, 1518 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1519 }; 1520 1521 static const struct intel_c10pll_state mtl_c10_hdmi_147160 = { 1522 .clock = 147160, 1523 .tx = 0x10, 1524 .cmn = 0x1, 1525 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00, 1526 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1527 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xA5, .pll[13] = 0x55, .pll[14] = 0x55, 1528 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1529 }; 1530 1531 static const struct intel_c10pll_state mtl_c10_hdmi_148352 = { 1532 .clock = 148352, 1533 .tx = 0x10, 1534 .cmn = 0x1, 1535 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, 1536 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1537 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44, 1538 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1539 }; 1540 1541 static const struct intel_c10pll_state mtl_c10_hdmi_154000 = { 1542 .clock = 154000, 1543 .tx = 0x10, 1544 .cmn = 0x1, 1545 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00, 1546 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1547 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x35, .pll[13] = 0x55, .pll[14] = 0x55, 1548 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1549 }; 1550 1551 static const struct intel_c10pll_state mtl_c10_hdmi_162000 = { 1552 .clock = 162000, 1553 .tx = 0x10, 1554 .cmn = 0x1, 1555 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00, 1556 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1557 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x60, .pll[13] = 0x00, .pll[14] = 0x00, 1558 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1559 }; 1560 1561 static const struct intel_c10pll_state mtl_c10_hdmi_167000 = { 1562 .clock = 167000, 1563 .tx = 0x10, 1564 .cmn = 0x1, 1565 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00, 1566 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1567 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0xFA, .pll[13] = 0xA9, .pll[14] = 0xAA, 1568 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1569 }; 1570 1571 static const struct intel_c10pll_state mtl_c10_hdmi_197802 = { 1572 .clock = 197802, 1573 .tx = 0x10, 1574 .cmn = 0x1, 1575 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00, 1576 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1577 .pll[10] = 0xFF, .pll[11] = 0x99, .pll[12] = 0x05, .pll[13] = 0x98, .pll[14] = 0x99, 1578 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1579 }; 1580 1581 static const struct intel_c10pll_state mtl_c10_hdmi_198000 = { 1582 .clock = 198000, 1583 .tx = 0x10, 1584 .cmn = 0x1, 1585 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00, 1586 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1587 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00, 1588 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1589 }; 1590 1591 static const struct intel_c10pll_state mtl_c10_hdmi_209800 = { 1592 .clock = 209800, 1593 .tx = 0x10, 1594 .cmn = 0x1, 1595 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00, 1596 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1597 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x45, .pll[13] = 0x55, .pll[14] = 0x55, 1598 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1599 }; 1600 1601 static const struct intel_c10pll_state mtl_c10_hdmi_241500 = { 1602 .clock = 241500, 1603 .tx = 0x10, 1604 .cmn = 0x1, 1605 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00, 1606 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1607 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xC8, .pll[13] = 0x00, .pll[14] = 0x00, 1608 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1609 }; 1610 1611 static const struct intel_c10pll_state mtl_c10_hdmi_262750 = { 1612 .clock = 262750, 1613 .tx = 0x10, 1614 .cmn = 0x1, 1615 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00, 1616 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1617 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x6C, .pll[13] = 0xA9, .pll[14] = 0xAA, 1618 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1619 }; 1620 1621 static const struct intel_c10pll_state mtl_c10_hdmi_268500 = { 1622 .clock = 268500, 1623 .tx = 0x10, 1624 .cmn = 0x1, 1625 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00, 1626 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1627 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xEC, .pll[13] = 0x00, .pll[14] = 0x00, 1628 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1629 }; 1630 1631 static const struct intel_c10pll_state mtl_c10_hdmi_296703 = { 1632 .clock = 296703, 1633 .tx = 0x10, 1634 .cmn = 0x1, 1635 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, 1636 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1637 .pll[10] = 0xFF, .pll[11] = 0x33, .pll[12] = 0x44, .pll[13] = 0x33, .pll[14] = 0x33, 1638 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1639 }; 1640 1641 static const struct intel_c10pll_state mtl_c10_hdmi_297000 = { 1642 .clock = 297000, 1643 .tx = 0x10, 1644 .cmn = 0x1, 1645 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, 1646 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1647 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x58, .pll[13] = 0x00, .pll[14] = 0x00, 1648 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1649 }; 1650 1651 static const struct intel_c10pll_state mtl_c10_hdmi_319750 = { 1652 .clock = 319750, 1653 .tx = 0x10, 1654 .cmn = 0x1, 1655 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00, 1656 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1657 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x44, .pll[13] = 0xA9, .pll[14] = 0xAA, 1658 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1659 }; 1660 1661 static const struct intel_c10pll_state mtl_c10_hdmi_497750 = { 1662 .clock = 497750, 1663 .tx = 0x10, 1664 .cmn = 0x1, 1665 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00, 1666 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1667 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x9F, .pll[13] = 0x55, .pll[14] = 0x55, 1668 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, 1669 }; 1670 1671 static const struct intel_c10pll_state mtl_c10_hdmi_592000 = { 1672 .clock = 592000, 1673 .tx = 0x10, 1674 .cmn = 0x1, 1675 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, 1676 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1677 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x15, .pll[13] = 0x55, .pll[14] = 0x55, 1678 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1679 }; 1680 1681 static const struct intel_c10pll_state mtl_c10_hdmi_593407 = { 1682 .clock = 593407, 1683 .tx = 0x10, 1684 .cmn = 0x1, 1685 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, 1686 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, 1687 .pll[10] = 0xFF, .pll[11] = 0x3B, .pll[12] = 0x44, .pll[13] = 0xBA, .pll[14] = 0xBB, 1688 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, 1689 }; 1690 1691 static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = { 1692 &mtl_c10_hdmi_25_2, /* Consolidated Table */ 1693 &mtl_c10_hdmi_27_0, /* Consolidated Table */ 1694 &mtl_c10_hdmi_27027, 1695 &mtl_c10_hdmi_28320, 1696 &mtl_c10_hdmi_30240, 1697 &mtl_c10_hdmi_31500, 1698 &mtl_c10_hdmi_36000, 1699 &mtl_c10_hdmi_40000, 1700 &mtl_c10_hdmi_49500, 1701 &mtl_c10_hdmi_50000, 1702 &mtl_c10_hdmi_57284, 1703 &mtl_c10_hdmi_58000, 1704 &mtl_c10_hdmi_65000, 1705 &mtl_c10_hdmi_71000, 1706 &mtl_c10_hdmi_74176, 1707 &mtl_c10_hdmi_74_25, /* Consolidated Table */ 1708 &mtl_c10_hdmi_75000, 1709 &mtl_c10_hdmi_78750, 1710 &mtl_c10_hdmi_85500, 1711 &mtl_c10_hdmi_88750, 1712 &mtl_c10_hdmi_106500, 1713 &mtl_c10_hdmi_108000, 1714 &mtl_c10_hdmi_115500, 1715 &mtl_c10_hdmi_119000, 1716 &mtl_c10_hdmi_135000, 1717 &mtl_c10_hdmi_138500, 1718 &mtl_c10_hdmi_147160, 1719 &mtl_c10_hdmi_148352, 1720 &mtl_c10_hdmi_148_5, /* Consolidated Table */ 1721 &mtl_c10_hdmi_154000, 1722 &mtl_c10_hdmi_162000, 1723 &mtl_c10_hdmi_167000, 1724 &mtl_c10_hdmi_197802, 1725 &mtl_c10_hdmi_198000, 1726 &mtl_c10_hdmi_209800, 1727 &mtl_c10_hdmi_241500, 1728 &mtl_c10_hdmi_262750, 1729 &mtl_c10_hdmi_268500, 1730 &mtl_c10_hdmi_296703, 1731 &mtl_c10_hdmi_297000, 1732 &mtl_c10_hdmi_319750, 1733 &mtl_c10_hdmi_497750, 1734 &mtl_c10_hdmi_592000, 1735 &mtl_c10_hdmi_593407, 1736 &mtl_c10_hdmi_594, /* Consolidated Table */ 1737 NULL, 1738 }; 1739 1740 static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = { 1741 .clock = 25175, 1742 .tx = { 0xbe88, /* tx cfg0 */ 1743 0x9800, /* tx cfg1 */ 1744 0x0000, /* tx cfg2 */ 1745 }, 1746 .cmn = { 0x0500, /* cmn cfg0*/ 1747 0x0005, /* cmn cfg1 */ 1748 0x0000, /* cmn cfg2 */ 1749 0x0000, /* cmn cfg3 */ 1750 }, 1751 .mpllb = { 0xa0d2, /* mpllb cfg0 */ 1752 0x7d80, /* mpllb cfg1 */ 1753 0x0906, /* mpllb cfg2 */ 1754 0xbe40, /* mpllb cfg3 */ 1755 0x0000, /* mpllb cfg4 */ 1756 0x0000, /* mpllb cfg5 */ 1757 0x0200, /* mpllb cfg6 */ 1758 0x0001, /* mpllb cfg7 */ 1759 0x0000, /* mpllb cfg8 */ 1760 0x0000, /* mpllb cfg9 */ 1761 0x0001, /* mpllb cfg10 */ 1762 }, 1763 }; 1764 1765 static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = { 1766 .clock = 27000, 1767 .tx = { 0xbe88, /* tx cfg0 */ 1768 0x9800, /* tx cfg1 */ 1769 0x0000, /* tx cfg2 */ 1770 }, 1771 .cmn = { 0x0500, /* cmn cfg0*/ 1772 0x0005, /* cmn cfg1 */ 1773 0x0000, /* cmn cfg2 */ 1774 0x0000, /* cmn cfg3 */ 1775 }, 1776 .mpllb = { 0xa0e0, /* mpllb cfg0 */ 1777 0x7d80, /* mpllb cfg1 */ 1778 0x0906, /* mpllb cfg2 */ 1779 0xbe40, /* mpllb cfg3 */ 1780 0x0000, /* mpllb cfg4 */ 1781 0x0000, /* mpllb cfg5 */ 1782 0x2200, /* mpllb cfg6 */ 1783 0x0001, /* mpllb cfg7 */ 1784 0x8000, /* mpllb cfg8 */ 1785 0x0000, /* mpllb cfg9 */ 1786 0x0001, /* mpllb cfg10 */ 1787 }, 1788 }; 1789 1790 static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = { 1791 .clock = 74250, 1792 .tx = { 0xbe88, /* tx cfg0 */ 1793 0x9800, /* tx cfg1 */ 1794 0x0000, /* tx cfg2 */ 1795 }, 1796 .cmn = { 0x0500, /* cmn cfg0*/ 1797 0x0005, /* cmn cfg1 */ 1798 0x0000, /* cmn cfg2 */ 1799 0x0000, /* cmn cfg3 */ 1800 }, 1801 .mpllb = { 0x609a, /* mpllb cfg0 */ 1802 0x7d40, /* mpllb cfg1 */ 1803 0xca06, /* mpllb cfg2 */ 1804 0xbe40, /* mpllb cfg3 */ 1805 0x0000, /* mpllb cfg4 */ 1806 0x0000, /* mpllb cfg5 */ 1807 0x2200, /* mpllb cfg6 */ 1808 0x0001, /* mpllb cfg7 */ 1809 0x5800, /* mpllb cfg8 */ 1810 0x0000, /* mpllb cfg9 */ 1811 0x0001, /* mpllb cfg10 */ 1812 }, 1813 }; 1814 1815 static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = { 1816 .clock = 148500, 1817 .tx = { 0xbe88, /* tx cfg0 */ 1818 0x9800, /* tx cfg1 */ 1819 0x0000, /* tx cfg2 */ 1820 }, 1821 .cmn = { 0x0500, /* cmn cfg0*/ 1822 0x0005, /* cmn cfg1 */ 1823 0x0000, /* cmn cfg2 */ 1824 0x0000, /* cmn cfg3 */ 1825 }, 1826 .mpllb = { 0x409a, /* mpllb cfg0 */ 1827 0x7d20, /* mpllb cfg1 */ 1828 0xca06, /* mpllb cfg2 */ 1829 0xbe40, /* mpllb cfg3 */ 1830 0x0000, /* mpllb cfg4 */ 1831 0x0000, /* mpllb cfg5 */ 1832 0x2200, /* mpllb cfg6 */ 1833 0x0001, /* mpllb cfg7 */ 1834 0x5800, /* mpllb cfg8 */ 1835 0x0000, /* mpllb cfg9 */ 1836 0x0001, /* mpllb cfg10 */ 1837 }, 1838 }; 1839 1840 static const struct intel_c20pll_state mtl_c20_hdmi_594 = { 1841 .clock = 594000, 1842 .tx = { 0xbe88, /* tx cfg0 */ 1843 0x9800, /* tx cfg1 */ 1844 0x0000, /* tx cfg2 */ 1845 }, 1846 .cmn = { 0x0500, /* cmn cfg0*/ 1847 0x0005, /* cmn cfg1 */ 1848 0x0000, /* cmn cfg2 */ 1849 0x0000, /* cmn cfg3 */ 1850 }, 1851 .mpllb = { 0x009a, /* mpllb cfg0 */ 1852 0x7d08, /* mpllb cfg1 */ 1853 0xca06, /* mpllb cfg2 */ 1854 0xbe40, /* mpllb cfg3 */ 1855 0x0000, /* mpllb cfg4 */ 1856 0x0000, /* mpllb cfg5 */ 1857 0x2200, /* mpllb cfg6 */ 1858 0x0001, /* mpllb cfg7 */ 1859 0x5800, /* mpllb cfg8 */ 1860 0x0000, /* mpllb cfg9 */ 1861 0x0001, /* mpllb cfg10 */ 1862 }, 1863 }; 1864 1865 static const struct intel_c20pll_state mtl_c20_hdmi_300 = { 1866 .clock = 3000000, 1867 .tx = { 0xbe98, /* tx cfg0 */ 1868 0x8800, /* tx cfg1 */ 1869 0x0000, /* tx cfg2 */ 1870 }, 1871 .cmn = { 0x0500, /* cmn cfg0*/ 1872 0x0005, /* cmn cfg1 */ 1873 0x0000, /* cmn cfg2 */ 1874 0x0000, /* cmn cfg3 */ 1875 }, 1876 .mpllb = { 0x309c, /* mpllb cfg0 */ 1877 0x2110, /* mpllb cfg1 */ 1878 0xca06, /* mpllb cfg2 */ 1879 0xbe40, /* mpllb cfg3 */ 1880 0x0000, /* mpllb cfg4 */ 1881 0x0000, /* mpllb cfg5 */ 1882 0x2200, /* mpllb cfg6 */ 1883 0x0001, /* mpllb cfg7 */ 1884 0x2000, /* mpllb cfg8 */ 1885 0x0000, /* mpllb cfg9 */ 1886 0x0004, /* mpllb cfg10 */ 1887 }, 1888 }; 1889 1890 static const struct intel_c20pll_state mtl_c20_hdmi_600 = { 1891 .clock = 6000000, 1892 .tx = { 0xbe98, /* tx cfg0 */ 1893 0x8800, /* tx cfg1 */ 1894 0x0000, /* tx cfg2 */ 1895 }, 1896 .cmn = { 0x0500, /* cmn cfg0*/ 1897 0x0005, /* cmn cfg1 */ 1898 0x0000, /* cmn cfg2 */ 1899 0x0000, /* cmn cfg3 */ 1900 }, 1901 .mpllb = { 0x109c, /* mpllb cfg0 */ 1902 0x2108, /* mpllb cfg1 */ 1903 0xca06, /* mpllb cfg2 */ 1904 0xbe40, /* mpllb cfg3 */ 1905 0x0000, /* mpllb cfg4 */ 1906 0x0000, /* mpllb cfg5 */ 1907 0x2200, /* mpllb cfg6 */ 1908 0x0001, /* mpllb cfg7 */ 1909 0x2000, /* mpllb cfg8 */ 1910 0x0000, /* mpllb cfg9 */ 1911 0x0004, /* mpllb cfg10 */ 1912 }, 1913 }; 1914 1915 static const struct intel_c20pll_state mtl_c20_hdmi_800 = { 1916 .clock = 8000000, 1917 .tx = { 0xbe98, /* tx cfg0 */ 1918 0x8800, /* tx cfg1 */ 1919 0x0000, /* tx cfg2 */ 1920 }, 1921 .cmn = { 0x0500, /* cmn cfg0*/ 1922 0x0005, /* cmn cfg1 */ 1923 0x0000, /* cmn cfg2 */ 1924 0x0000, /* cmn cfg3 */ 1925 }, 1926 .mpllb = { 0x10d0, /* mpllb cfg0 */ 1927 0x2108, /* mpllb cfg1 */ 1928 0x4a06, /* mpllb cfg2 */ 1929 0xbe40, /* mpllb cfg3 */ 1930 0x0000, /* mpllb cfg4 */ 1931 0x0000, /* mpllb cfg5 */ 1932 0x2200, /* mpllb cfg6 */ 1933 0x0003, /* mpllb cfg7 */ 1934 0x2aaa, /* mpllb cfg8 */ 1935 0x0002, /* mpllb cfg9 */ 1936 0x0004, /* mpllb cfg10 */ 1937 }, 1938 }; 1939 1940 static const struct intel_c20pll_state mtl_c20_hdmi_1000 = { 1941 .clock = 10000000, 1942 .tx = { 0xbe98, /* tx cfg0 */ 1943 0x8800, /* tx cfg1 */ 1944 0x0000, /* tx cfg2 */ 1945 }, 1946 .cmn = { 0x0500, /* cmn cfg0*/ 1947 0x0005, /* cmn cfg1 */ 1948 0x0000, /* cmn cfg2 */ 1949 0x0000, /* cmn cfg3 */ 1950 }, 1951 .mpllb = { 0x1104, /* mpllb cfg0 */ 1952 0x2108, /* mpllb cfg1 */ 1953 0x0a06, /* mpllb cfg2 */ 1954 0xbe40, /* mpllb cfg3 */ 1955 0x0000, /* mpllb cfg4 */ 1956 0x0000, /* mpllb cfg5 */ 1957 0x2200, /* mpllb cfg6 */ 1958 0x0003, /* mpllb cfg7 */ 1959 0x3555, /* mpllb cfg8 */ 1960 0x0001, /* mpllb cfg9 */ 1961 0x0004, /* mpllb cfg10 */ 1962 }, 1963 }; 1964 1965 static const struct intel_c20pll_state mtl_c20_hdmi_1200 = { 1966 .clock = 12000000, 1967 .tx = { 0xbe98, /* tx cfg0 */ 1968 0x8800, /* tx cfg1 */ 1969 0x0000, /* tx cfg2 */ 1970 }, 1971 .cmn = { 0x0500, /* cmn cfg0*/ 1972 0x0005, /* cmn cfg1 */ 1973 0x0000, /* cmn cfg2 */ 1974 0x0000, /* cmn cfg3 */ 1975 }, 1976 .mpllb = { 0x1138, /* mpllb cfg0 */ 1977 0x2108, /* mpllb cfg1 */ 1978 0x5486, /* mpllb cfg2 */ 1979 0xfe40, /* mpllb cfg3 */ 1980 0x0000, /* mpllb cfg4 */ 1981 0x0000, /* mpllb cfg5 */ 1982 0x2200, /* mpllb cfg6 */ 1983 0x0001, /* mpllb cfg7 */ 1984 0x4000, /* mpllb cfg8 */ 1985 0x0000, /* mpllb cfg9 */ 1986 0x0004, /* mpllb cfg10 */ 1987 }, 1988 }; 1989 1990 static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = { 1991 &mtl_c20_hdmi_25_175, 1992 &mtl_c20_hdmi_27_0, 1993 &mtl_c20_hdmi_74_25, 1994 &mtl_c20_hdmi_148_5, 1995 &mtl_c20_hdmi_594, 1996 &mtl_c20_hdmi_300, 1997 &mtl_c20_hdmi_600, 1998 &mtl_c20_hdmi_800, 1999 &mtl_c20_hdmi_1000, 2000 &mtl_c20_hdmi_1200, 2001 NULL, 2002 }; 2003 2004 static int intel_c10_phy_check_hdmi_link_rate(int clock) 2005 { 2006 const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables; 2007 int i; 2008 2009 for (i = 0; tables[i]; i++) { 2010 if (clock == tables[i]->clock) 2011 return MODE_OK; 2012 } 2013 2014 return MODE_CLOCK_RANGE; 2015 } 2016 2017 static const struct intel_c10pll_state * const * 2018 intel_c10pll_tables_get(struct intel_crtc_state *crtc_state, 2019 struct intel_encoder *encoder) 2020 { 2021 if (intel_crtc_has_dp_encoder(crtc_state)) { 2022 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2023 return mtl_c10_edp_tables; 2024 else 2025 return mtl_c10_dp_tables; 2026 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2027 return mtl_c10_hdmi_tables; 2028 } 2029 2030 MISSING_CASE(encoder->type); 2031 return NULL; 2032 } 2033 2034 static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state, 2035 struct intel_encoder *encoder) 2036 { 2037 struct intel_display *display = to_intel_display(encoder); 2038 struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll; 2039 int i; 2040 2041 if (intel_crtc_has_dp_encoder(crtc_state)) { 2042 if (intel_panel_use_ssc(display)) { 2043 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2044 2045 pll_state->ssc_enabled = 2046 (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5); 2047 } 2048 } 2049 2050 if (pll_state->ssc_enabled) 2051 return; 2052 2053 drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); 2054 for (i = 4; i < 9; i++) 2055 pll_state->c10.pll[i] = 0; 2056 } 2057 2058 static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state, 2059 struct intel_encoder *encoder) 2060 { 2061 const struct intel_c10pll_state * const *tables; 2062 int i; 2063 2064 tables = intel_c10pll_tables_get(crtc_state, encoder); 2065 if (!tables) 2066 return -EINVAL; 2067 2068 for (i = 0; tables[i]; i++) { 2069 if (crtc_state->port_clock == tables[i]->clock) { 2070 crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i]; 2071 intel_c10pll_update_pll(crtc_state, encoder); 2072 crtc_state->dpll_hw_state.cx0pll.use_c10 = true; 2073 2074 return 0; 2075 } 2076 } 2077 2078 return -EINVAL; 2079 } 2080 2081 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, 2082 struct intel_c10pll_state *pll_state) 2083 { 2084 u8 lane = INTEL_CX0_LANE0; 2085 intel_wakeref_t wakeref; 2086 int i; 2087 2088 wakeref = intel_cx0_phy_transaction_begin(encoder); 2089 2090 /* 2091 * According to C10 VDR Register programming Sequence we need 2092 * to do this to read PHY internal registers from MsgBus. 2093 */ 2094 intel_cx0_rmw(encoder, lane, PHY_C10_VDR_CONTROL(1), 2095 0, C10_VDR_CTRL_MSGBUS_ACCESS, 2096 MB_WRITE_COMMITTED); 2097 2098 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) 2099 pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i)); 2100 2101 pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0)); 2102 pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0)); 2103 2104 intel_cx0_phy_transaction_end(encoder, wakeref); 2105 } 2106 2107 static void intel_c10_pll_program(struct intel_display *display, 2108 const struct intel_crtc_state *crtc_state, 2109 struct intel_encoder *encoder) 2110 { 2111 const struct intel_c10pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c10; 2112 int i; 2113 2114 intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), 2115 0, C10_VDR_CTRL_MSGBUS_ACCESS, 2116 MB_WRITE_COMMITTED); 2117 2118 /* Custom width needs to be programmed to 0 for both the phy lanes */ 2119 intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH, 2120 C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10, 2121 MB_WRITE_COMMITTED); 2122 intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), 2123 0, C10_VDR_CTRL_UPDATE_CFG, 2124 MB_WRITE_COMMITTED); 2125 2126 /* Program the pll values only for the master lane */ 2127 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) 2128 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i), 2129 pll_state->pll[i], 2130 (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED); 2131 2132 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED); 2133 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED); 2134 2135 intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1), 2136 0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, 2137 MB_WRITE_COMMITTED); 2138 } 2139 2140 static void intel_c10pll_dump_hw_state(struct intel_display *display, 2141 const struct intel_c10pll_state *hw_state) 2142 { 2143 bool fracen; 2144 int i; 2145 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; 2146 unsigned int multiplier, tx_clk_div; 2147 2148 fracen = hw_state->pll[0] & C10_PLL0_FRACEN; 2149 drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ", 2150 str_yes_no(fracen)); 2151 2152 if (fracen) { 2153 frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11]; 2154 frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13]; 2155 frac_den = hw_state->pll[10] << 8 | hw_state->pll[9]; 2156 drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n", 2157 frac_quot, frac_rem, frac_den); 2158 } 2159 2160 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 | 2161 hw_state->pll[2]) / 2 + 16; 2162 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]); 2163 drm_dbg_kms(display->drm, 2164 "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div); 2165 2166 drm_dbg_kms(display->drm, "c10pll_rawhw_state:"); 2167 drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, 2168 hw_state->cmn); 2169 2170 BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4); 2171 for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) 2172 drm_dbg_kms(display->drm, 2173 "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", 2174 i, hw_state->pll[i], i + 1, hw_state->pll[i + 1], 2175 i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); 2176 } 2177 2178 static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state) 2179 { 2180 struct intel_display *display = to_intel_display(crtc_state); 2181 struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; 2182 u64 datarate; 2183 u64 mpll_tx_clk_div; 2184 u64 vco_freq_shift; 2185 u64 vco_freq; 2186 u64 multiplier; 2187 u64 mpll_multiplier; 2188 u64 mpll_fracn_quot; 2189 u64 mpll_fracn_rem; 2190 u16 tx_misc; 2191 u8 mpllb_ana_freq_vco; 2192 u8 mpll_div_multiplier; 2193 2194 if (crtc_state->port_clock < 25175 || crtc_state->port_clock > 600000) 2195 return -EINVAL; 2196 2197 datarate = ((u64)crtc_state->port_clock * 1000) * 10; 2198 mpll_tx_clk_div = ilog2(div64_u64((u64)CLOCK_9999MHZ, (u64)datarate)); 2199 vco_freq_shift = ilog2(div64_u64((u64)CLOCK_4999MHZ * (u64)256, (u64)datarate)); 2200 vco_freq = (datarate << vco_freq_shift) >> 8; 2201 multiplier = div64_u64((vco_freq << 28), (REFCLK_38_4_MHZ >> 4)); 2202 mpll_multiplier = 2 * (multiplier >> 32); 2203 2204 mpll_fracn_quot = (multiplier >> 16) & 0xFFFF; 2205 mpll_fracn_rem = multiplier & 0xFFFF; 2206 2207 mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)), 2208 datarate), 255); 2209 2210 if (DISPLAY_VER(display) >= 20) 2211 tx_misc = 0x5; 2212 else 2213 tx_misc = 0x0; 2214 2215 if (vco_freq <= DATARATE_3000000000) 2216 mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_3; 2217 else if (vco_freq <= DATARATE_3500000000) 2218 mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_2; 2219 else if (vco_freq <= DATARATE_4000000000) 2220 mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_1; 2221 else 2222 mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0; 2223 2224 pll_state->clock = crtc_state->port_clock; 2225 pll_state->tx[0] = 0xbe88; 2226 pll_state->tx[1] = 0x9800 | C20_PHY_TX_MISC(tx_misc); 2227 pll_state->tx[2] = 0x0000; 2228 pll_state->cmn[0] = 0x0500; 2229 pll_state->cmn[1] = 0x0005; 2230 pll_state->cmn[2] = 0x0000; 2231 pll_state->cmn[3] = 0x0000; 2232 pll_state->mpllb[0] = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) | 2233 MPLL_MULTIPLIER(mpll_multiplier)); 2234 pll_state->mpllb[1] = (CAL_DAC_CODE(CAL_DAC_CODE_31) | 2235 WORD_CLK_DIV | 2236 MPLL_DIV_MULTIPLIER(mpll_div_multiplier)); 2237 pll_state->mpllb[2] = (MPLLB_ANA_FREQ_VCO(mpllb_ana_freq_vco) | 2238 CP_PROP(CP_PROP_20) | 2239 CP_INT(CP_INT_6)); 2240 pll_state->mpllb[3] = (V2I(V2I_2) | 2241 CP_PROP_GS(CP_PROP_GS_30) | 2242 CP_INT_GS(CP_INT_GS_28)); 2243 pll_state->mpllb[4] = 0x0000; 2244 pll_state->mpllb[5] = 0x0000; 2245 pll_state->mpllb[6] = (C20_MPLLB_FRACEN | SSC_UP_SPREAD); 2246 pll_state->mpllb[7] = MPLL_FRACN_DEN; 2247 pll_state->mpllb[8] = mpll_fracn_quot; 2248 pll_state->mpllb[9] = mpll_fracn_rem; 2249 pll_state->mpllb[10] = HDMI_DIV(HDMI_DIV_1); 2250 2251 return 0; 2252 } 2253 2254 static int intel_c20_phy_check_hdmi_link_rate(int clock) 2255 { 2256 const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables; 2257 int i; 2258 2259 for (i = 0; tables[i]; i++) { 2260 if (clock == tables[i]->clock) 2261 return MODE_OK; 2262 } 2263 2264 if (clock >= 25175 && clock <= 594000) 2265 return MODE_OK; 2266 2267 return MODE_CLOCK_RANGE; 2268 } 2269 2270 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock) 2271 { 2272 struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi); 2273 2274 if (intel_encoder_is_c10phy(&dig_port->base)) 2275 return intel_c10_phy_check_hdmi_link_rate(clock); 2276 return intel_c20_phy_check_hdmi_link_rate(clock); 2277 } 2278 2279 static const struct intel_c20pll_state * const * 2280 intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, 2281 struct intel_encoder *encoder) 2282 { 2283 struct intel_display *display = to_intel_display(crtc_state); 2284 2285 if (intel_crtc_has_dp_encoder(crtc_state)) { 2286 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 2287 if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support) 2288 return xe3lpd_c20_dp_edp_tables; 2289 if (DISPLAY_VERx100(display) == 1401) 2290 return xe2hpd_c20_edp_tables; 2291 } 2292 2293 if (DISPLAY_VER(display) >= 30) 2294 return xe3lpd_c20_dp_edp_tables; 2295 else if (DISPLAY_VERx100(display) == 1401) 2296 return xe2hpd_c20_dp_tables; 2297 else 2298 return mtl_c20_dp_tables; 2299 2300 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2301 return mtl_c20_hdmi_tables; 2302 } 2303 2304 MISSING_CASE(encoder->type); 2305 return NULL; 2306 } 2307 2308 static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state, 2309 struct intel_encoder *encoder) 2310 { 2311 const struct intel_c20pll_state * const *tables; 2312 int i; 2313 2314 /* try computed C20 HDMI tables before using consolidated tables */ 2315 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2316 if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0) 2317 return 0; 2318 } 2319 2320 tables = intel_c20_pll_tables_get(crtc_state, encoder); 2321 if (!tables) 2322 return -EINVAL; 2323 2324 for (i = 0; tables[i]; i++) { 2325 if (crtc_state->port_clock == tables[i]->clock) { 2326 crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; 2327 crtc_state->dpll_hw_state.cx0pll.use_c10 = false; 2328 return 0; 2329 } 2330 } 2331 2332 return -EINVAL; 2333 } 2334 2335 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, 2336 struct intel_encoder *encoder) 2337 { 2338 if (intel_encoder_is_c10phy(encoder)) 2339 return intel_c10pll_calc_state(crtc_state, encoder); 2340 return intel_c20pll_calc_state(crtc_state, encoder); 2341 } 2342 2343 static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state) 2344 { 2345 return state->tx[0] & C20_PHY_USE_MPLLB; 2346 } 2347 2348 static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder, 2349 const struct intel_c20pll_state *pll_state) 2350 { 2351 unsigned int frac, frac_en, frac_quot, frac_rem, frac_den; 2352 unsigned int multiplier, refclk = 38400; 2353 unsigned int tx_clk_div; 2354 unsigned int ref_clk_mpllb_div; 2355 unsigned int fb_clk_div4_en; 2356 unsigned int ref, vco; 2357 unsigned int tx_rate_mult; 2358 unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); 2359 2360 if (intel_c20phy_use_mpllb(pll_state)) { 2361 tx_rate_mult = 1; 2362 frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); 2363 frac_quot = pll_state->mpllb[8]; 2364 frac_rem = pll_state->mpllb[9]; 2365 frac_den = pll_state->mpllb[7]; 2366 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); 2367 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); 2368 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); 2369 fb_clk_div4_en = 0; 2370 } else { 2371 tx_rate_mult = 2; 2372 frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); 2373 frac_quot = pll_state->mplla[8]; 2374 frac_rem = pll_state->mplla[9]; 2375 frac_den = pll_state->mplla[7]; 2376 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); 2377 tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); 2378 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); 2379 fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); 2380 } 2381 2382 if (frac_en) 2383 frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den); 2384 else 2385 frac = 0; 2386 2387 ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div); 2388 vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10); 2389 2390 return vco << tx_rate_mult >> tx_clk_div >> tx_rate; 2391 } 2392 2393 static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, 2394 struct intel_c20pll_state *pll_state) 2395 { 2396 struct intel_display *display = to_intel_display(encoder); 2397 bool cntx; 2398 intel_wakeref_t wakeref; 2399 int i; 2400 2401 wakeref = intel_cx0_phy_transaction_begin(encoder); 2402 2403 /* 1. Read current context selection */ 2404 cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE; 2405 2406 /* Read Tx configuration */ 2407 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { 2408 if (cntx) 2409 pll_state->tx[i] = intel_c20_sram_read(encoder, 2410 INTEL_CX0_LANE0, 2411 PHY_C20_B_TX_CNTX_CFG(display, i)); 2412 else 2413 pll_state->tx[i] = intel_c20_sram_read(encoder, 2414 INTEL_CX0_LANE0, 2415 PHY_C20_A_TX_CNTX_CFG(display, i)); 2416 } 2417 2418 /* Read common configuration */ 2419 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { 2420 if (cntx) 2421 pll_state->cmn[i] = intel_c20_sram_read(encoder, 2422 INTEL_CX0_LANE0, 2423 PHY_C20_B_CMN_CNTX_CFG(display, i)); 2424 else 2425 pll_state->cmn[i] = intel_c20_sram_read(encoder, 2426 INTEL_CX0_LANE0, 2427 PHY_C20_A_CMN_CNTX_CFG(display, i)); 2428 } 2429 2430 if (intel_c20phy_use_mpllb(pll_state)) { 2431 /* MPLLB configuration */ 2432 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { 2433 if (cntx) 2434 pll_state->mpllb[i] = intel_c20_sram_read(encoder, 2435 INTEL_CX0_LANE0, 2436 PHY_C20_B_MPLLB_CNTX_CFG(display, i)); 2437 else 2438 pll_state->mpllb[i] = intel_c20_sram_read(encoder, 2439 INTEL_CX0_LANE0, 2440 PHY_C20_A_MPLLB_CNTX_CFG(display, i)); 2441 } 2442 } else { 2443 /* MPLLA configuration */ 2444 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { 2445 if (cntx) 2446 pll_state->mplla[i] = intel_c20_sram_read(encoder, 2447 INTEL_CX0_LANE0, 2448 PHY_C20_B_MPLLA_CNTX_CFG(display, i)); 2449 else 2450 pll_state->mplla[i] = intel_c20_sram_read(encoder, 2451 INTEL_CX0_LANE0, 2452 PHY_C20_A_MPLLA_CNTX_CFG(display, i)); 2453 } 2454 } 2455 2456 pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state); 2457 2458 intel_cx0_phy_transaction_end(encoder, wakeref); 2459 } 2460 2461 static void intel_c20pll_dump_hw_state(struct intel_display *display, 2462 const struct intel_c20pll_state *hw_state) 2463 { 2464 int i; 2465 2466 drm_dbg_kms(display->drm, "c20pll_hw_state:\n"); 2467 drm_dbg_kms(display->drm, 2468 "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", 2469 hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); 2470 drm_dbg_kms(display->drm, 2471 "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", 2472 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); 2473 2474 if (intel_c20phy_use_mpllb(hw_state)) { 2475 for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) 2476 drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, 2477 hw_state->mpllb[i]); 2478 } else { 2479 for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) 2480 drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i, 2481 hw_state->mplla[i]); 2482 } 2483 } 2484 2485 void intel_cx0pll_dump_hw_state(struct intel_display *display, 2486 const struct intel_cx0pll_state *hw_state) 2487 { 2488 if (hw_state->use_c10) 2489 intel_c10pll_dump_hw_state(display, &hw_state->c10); 2490 else 2491 intel_c20pll_dump_hw_state(display, &hw_state->c20); 2492 } 2493 2494 static u8 intel_c20_get_dp_rate(u32 clock) 2495 { 2496 switch (clock) { 2497 case 162000: /* 1.62 Gbps DP1.4 */ 2498 return 0; 2499 case 270000: /* 2.7 Gbps DP1.4 */ 2500 return 1; 2501 case 540000: /* 5.4 Gbps DP 1.4 */ 2502 return 2; 2503 case 810000: /* 8.1 Gbps DP1.4 */ 2504 return 3; 2505 case 216000: /* 2.16 Gbps eDP */ 2506 return 4; 2507 case 243000: /* 2.43 Gbps eDP */ 2508 return 5; 2509 case 324000: /* 3.24 Gbps eDP */ 2510 return 6; 2511 case 432000: /* 4.32 Gbps eDP */ 2512 return 7; 2513 case 1000000: /* 10 Gbps DP2.0 */ 2514 return 8; 2515 case 1350000: /* 13.5 Gbps DP2.0 */ 2516 return 9; 2517 case 2000000: /* 20 Gbps DP2.0 */ 2518 return 10; 2519 case 648000: /* 6.48 Gbps eDP*/ 2520 return 11; 2521 case 675000: /* 6.75 Gbps eDP*/ 2522 return 12; 2523 default: 2524 MISSING_CASE(clock); 2525 return 0; 2526 } 2527 } 2528 2529 static u8 intel_c20_get_hdmi_rate(u32 clock) 2530 { 2531 if (clock >= 25175 && clock <= 600000) 2532 return 0; 2533 2534 switch (clock) { 2535 case 300000: /* 3 Gbps */ 2536 case 600000: /* 6 Gbps */ 2537 case 1200000: /* 12 Gbps */ 2538 return 1; 2539 case 800000: /* 8 Gbps */ 2540 return 2; 2541 case 1000000: /* 10 Gbps */ 2542 return 3; 2543 default: 2544 MISSING_CASE(clock); 2545 return 0; 2546 } 2547 } 2548 2549 static bool is_dp2(u32 clock) 2550 { 2551 /* DP2.0 clock rates */ 2552 if (clock == 1000000 || clock == 1350000 || clock == 2000000) 2553 return true; 2554 2555 return false; 2556 } 2557 2558 static bool is_hdmi_frl(u32 clock) 2559 { 2560 switch (clock) { 2561 case 300000: /* 3 Gbps */ 2562 case 600000: /* 6 Gbps */ 2563 case 800000: /* 8 Gbps */ 2564 case 1000000: /* 10 Gbps */ 2565 case 1200000: /* 12 Gbps */ 2566 return true; 2567 default: 2568 return false; 2569 } 2570 } 2571 2572 static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder) 2573 { 2574 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2575 2576 /* banks should not be cleared for DPALT/USB4/TBT modes */ 2577 /* TODO: optimize re-calibration in legacy mode */ 2578 return intel_tc_port_in_legacy_mode(intel_dig_port); 2579 } 2580 2581 static int intel_get_c20_custom_width(u32 clock, bool dp) 2582 { 2583 if (dp && is_dp2(clock)) 2584 return 2; 2585 else if (is_hdmi_frl(clock)) 2586 return 1; 2587 else 2588 return 0; 2589 } 2590 2591 static void intel_c20_pll_program(struct intel_display *display, 2592 const struct intel_crtc_state *crtc_state, 2593 struct intel_encoder *encoder) 2594 { 2595 const struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; 2596 bool dp = false; 2597 u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); 2598 u32 clock = crtc_state->port_clock; 2599 bool cntx; 2600 int i; 2601 2602 if (intel_crtc_has_dp_encoder(crtc_state)) 2603 dp = true; 2604 2605 /* 1. Read current context selection */ 2606 cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0); 2607 2608 /* 2609 * 2. If there is a protocol switch from HDMI to DP or vice versa, clear 2610 * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA. 2611 * Protocol switch is only applicable for MPLLA 2612 */ 2613 if (intel_c20_protocol_switch_valid(encoder)) { 2614 for (i = 0; i < 4; i++) 2615 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0); 2616 usleep_range(4000, 4100); 2617 } 2618 2619 /* 3. Write SRAM configuration context. If A in use, write configuration to B context */ 2620 /* 3.1 Tx configuration */ 2621 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { 2622 if (cntx) 2623 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 2624 PHY_C20_A_TX_CNTX_CFG(display, i), 2625 pll_state->tx[i]); 2626 else 2627 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 2628 PHY_C20_B_TX_CNTX_CFG(display, i), 2629 pll_state->tx[i]); 2630 } 2631 2632 /* 3.2 common configuration */ 2633 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { 2634 if (cntx) 2635 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 2636 PHY_C20_A_CMN_CNTX_CFG(display, i), 2637 pll_state->cmn[i]); 2638 else 2639 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 2640 PHY_C20_B_CMN_CNTX_CFG(display, i), 2641 pll_state->cmn[i]); 2642 } 2643 2644 /* 3.3 mpllb or mplla configuration */ 2645 if (intel_c20phy_use_mpllb(pll_state)) { 2646 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { 2647 if (cntx) 2648 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 2649 PHY_C20_A_MPLLB_CNTX_CFG(display, i), 2650 pll_state->mpllb[i]); 2651 else 2652 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 2653 PHY_C20_B_MPLLB_CNTX_CFG(display, i), 2654 pll_state->mpllb[i]); 2655 } 2656 } else { 2657 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { 2658 if (cntx) 2659 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 2660 PHY_C20_A_MPLLA_CNTX_CFG(display, i), 2661 pll_state->mplla[i]); 2662 else 2663 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 2664 PHY_C20_B_MPLLA_CNTX_CFG(display, i), 2665 pll_state->mplla[i]); 2666 } 2667 } 2668 2669 /* 4. Program custom width to match the link protocol */ 2670 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH, 2671 PHY_C20_CUSTOM_WIDTH_MASK, 2672 PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock, dp)), 2673 MB_WRITE_COMMITTED); 2674 2675 /* 5. For DP or 6. For HDMI */ 2676 if (dp) { 2677 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, 2678 BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, 2679 BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)), 2680 MB_WRITE_COMMITTED); 2681 } else { 2682 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, 2683 BIT(7) | PHY_C20_CUSTOM_SERDES_MASK, 2684 is_hdmi_frl(clock) ? BIT(7) : 0, 2685 MB_WRITE_COMMITTED); 2686 2687 intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE, 2688 intel_c20_get_hdmi_rate(clock), 2689 MB_WRITE_COMMITTED); 2690 } 2691 2692 /* 2693 * 7. Write Vendor specific registers to toggle context setting to load 2694 * the updated programming toggle context bit 2695 */ 2696 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, 2697 BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); 2698 } 2699 2700 static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, 2701 const struct intel_c10pll_state *pll_state) 2702 { 2703 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; 2704 unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400; 2705 int tmpclk = 0; 2706 2707 if (pll_state->pll[0] & C10_PLL0_FRACEN) { 2708 frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; 2709 frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; 2710 frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; 2711 } 2712 2713 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | 2714 pll_state->pll[2]) / 2 + 16; 2715 2716 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]); 2717 hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); 2718 2719 tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + 2720 DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), 2721 10 << (tx_clk_div + 16)); 2722 tmpclk *= (hdmi_div ? 2 : 1); 2723 2724 return tmpclk; 2725 } 2726 2727 static void intel_program_port_clock_ctl(struct intel_encoder *encoder, 2728 const struct intel_crtc_state *crtc_state, 2729 bool lane_reversal) 2730 { 2731 struct intel_display *display = to_intel_display(encoder); 2732 u32 val = 0; 2733 2734 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2735 XELPDP_PORT_REVERSAL, 2736 lane_reversal ? XELPDP_PORT_REVERSAL : 0); 2737 2738 if (lane_reversal) 2739 val |= XELPDP_LANE1_PHY_CLOCK_SELECT; 2740 2741 val |= XELPDP_FORWARD_CLOCK_UNGATE; 2742 2743 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 2744 is_hdmi_frl(crtc_state->port_clock)) 2745 val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK); 2746 else 2747 val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK); 2748 2749 /* TODO: HDMI FRL */ 2750 /* DP2.0 10G and 20G rates enable MPLLA*/ 2751 if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) 2752 val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; 2753 else 2754 val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; 2755 2756 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 2757 XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE | 2758 XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA | 2759 XELPDP_SSC_ENABLE_PLLB, val); 2760 } 2761 2762 static u32 intel_cx0_get_powerdown_update(u8 lane_mask) 2763 { 2764 u32 val = 0; 2765 int lane = 0; 2766 2767 for_each_cx0_lane_in_mask(lane_mask, lane) 2768 val |= XELPDP_LANE_POWERDOWN_UPDATE(lane); 2769 2770 return val; 2771 } 2772 2773 static u32 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state) 2774 { 2775 u32 val = 0; 2776 int lane = 0; 2777 2778 for_each_cx0_lane_in_mask(lane_mask, lane) 2779 val |= XELPDP_LANE_POWERDOWN_NEW_STATE(lane, state); 2780 2781 return val; 2782 } 2783 2784 static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, 2785 u8 lane_mask, u8 state) 2786 { 2787 struct intel_display *display = to_intel_display(encoder); 2788 enum port port = encoder->port; 2789 enum phy phy = intel_encoder_to_phy(encoder); 2790 i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port); 2791 int lane; 2792 2793 intel_de_rmw(display, buf_ctl2_reg, 2794 intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK), 2795 intel_cx0_get_powerdown_state(lane_mask, state)); 2796 2797 /* Wait for pending transactions.*/ 2798 for_each_cx0_lane_in_mask(lane_mask, lane) 2799 if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), 2800 XELPDP_PORT_M2P_TRANSACTION_PENDING, 2801 XELPDP_MSGBUS_TIMEOUT_SLOW)) { 2802 drm_dbg_kms(display->drm, 2803 "PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n", 2804 phy_name(phy)); 2805 intel_cx0_bus_reset(encoder, lane); 2806 } 2807 2808 intel_de_rmw(display, buf_ctl2_reg, 2809 intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES), 2810 intel_cx0_get_powerdown_update(lane_mask)); 2811 2812 /* Update Timeout Value */ 2813 if (intel_de_wait_custom(display, buf_ctl2_reg, 2814 intel_cx0_get_powerdown_update(lane_mask), 0, 2815 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL)) 2816 drm_warn(display->drm, 2817 "PHY %c failed to bring out of Lane reset after %dus.\n", 2818 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US); 2819 } 2820 2821 static void intel_cx0_setup_powerdown(struct intel_encoder *encoder) 2822 { 2823 struct intel_display *display = to_intel_display(encoder); 2824 enum port port = encoder->port; 2825 2826 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), 2827 XELPDP_POWER_STATE_READY_MASK, 2828 XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY)); 2829 intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port), 2830 XELPDP_POWER_STATE_ACTIVE_MASK | 2831 XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, 2832 XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) | 2833 XELPDP_PLL_LANE_STAGGERING_DELAY(0)); 2834 } 2835 2836 static u32 intel_cx0_get_pclk_refclk_request(u8 lane_mask) 2837 { 2838 u32 val = 0; 2839 int lane = 0; 2840 2841 for_each_cx0_lane_in_mask(lane_mask, lane) 2842 val |= XELPDP_LANE_PCLK_REFCLK_REQUEST(lane); 2843 2844 return val; 2845 } 2846 2847 static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask) 2848 { 2849 u32 val = 0; 2850 int lane = 0; 2851 2852 for_each_cx0_lane_in_mask(lane_mask, lane) 2853 val |= XELPDP_LANE_PCLK_REFCLK_ACK(lane); 2854 2855 return val; 2856 } 2857 2858 static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder, 2859 bool lane_reversal) 2860 { 2861 struct intel_display *display = to_intel_display(encoder); 2862 enum port port = encoder->port; 2863 enum phy phy = intel_encoder_to_phy(encoder); 2864 u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); 2865 u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0; 2866 u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES 2867 ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1) 2868 : XELPDP_LANE_PIPE_RESET(0); 2869 u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES 2870 ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) | 2871 XELPDP_LANE_PHY_CURRENT_STATUS(1)) 2872 : XELPDP_LANE_PHY_CURRENT_STATUS(0); 2873 2874 if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL1(display, port), 2875 XELPDP_PORT_BUF_SOC_PHY_READY, 2876 XELPDP_PORT_BUF_SOC_PHY_READY, 2877 XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL)) 2878 drm_warn(display->drm, 2879 "PHY %c failed to bring out of SOC reset after %dus.\n", 2880 phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US); 2881 2882 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 2883 lane_pipe_reset); 2884 2885 if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port), 2886 lane_phy_current_status, lane_phy_current_status, 2887 XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL)) 2888 drm_warn(display->drm, 2889 "PHY %c failed to bring out of Lane reset after %dus.\n", 2890 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US); 2891 2892 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port), 2893 intel_cx0_get_pclk_refclk_request(owned_lane_mask), 2894 intel_cx0_get_pclk_refclk_request(lane_mask)); 2895 2896 if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port), 2897 intel_cx0_get_pclk_refclk_ack(owned_lane_mask), 2898 intel_cx0_get_pclk_refclk_ack(lane_mask), 2899 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL)) 2900 drm_warn(display->drm, 2901 "PHY %c failed to request refclk after %dus.\n", 2902 phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US); 2903 2904 intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, 2905 CX0_P2_STATE_RESET); 2906 intel_cx0_setup_powerdown(encoder); 2907 2908 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0); 2909 2910 if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port), 2911 lane_phy_current_status, 2912 XELPDP_PORT_RESET_END_TIMEOUT)) 2913 drm_warn(display->drm, 2914 "PHY %c failed to bring out of Lane reset after %dms.\n", 2915 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT); 2916 } 2917 2918 static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count, 2919 bool lane_reversal) 2920 { 2921 int i; 2922 u8 disables; 2923 bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder)); 2924 u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); 2925 2926 if (intel_encoder_is_c10phy(encoder)) 2927 intel_cx0_rmw(encoder, owned_lane_mask, 2928 PHY_C10_VDR_CONTROL(1), 0, 2929 C10_VDR_CTRL_MSGBUS_ACCESS, 2930 MB_WRITE_COMMITTED); 2931 2932 if (lane_reversal) 2933 disables = REG_GENMASK8(3, 0) >> lane_count; 2934 else 2935 disables = REG_GENMASK8(3, 0) << lane_count; 2936 2937 if (dp_alt_mode && lane_count == 1) { 2938 disables &= ~REG_GENMASK8(1, 0); 2939 disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1); 2940 } 2941 2942 for (i = 0; i < 4; i++) { 2943 int tx = i % 2 + 1; 2944 u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; 2945 2946 if (!(owned_lane_mask & lane_mask)) 2947 continue; 2948 2949 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_TX_CONTROL(tx, 2), 2950 CONTROL2_DISABLE_SINGLE_TX, 2951 disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0, 2952 MB_WRITE_COMMITTED); 2953 } 2954 2955 if (intel_encoder_is_c10phy(encoder)) 2956 intel_cx0_rmw(encoder, owned_lane_mask, 2957 PHY_C10_VDR_CONTROL(1), 0, 2958 C10_VDR_CTRL_UPDATE_CFG, 2959 MB_WRITE_COMMITTED); 2960 } 2961 2962 static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask) 2963 { 2964 u32 val = 0; 2965 int lane = 0; 2966 2967 for_each_cx0_lane_in_mask(lane_mask, lane) 2968 val |= XELPDP_LANE_PCLK_PLL_REQUEST(lane); 2969 2970 return val; 2971 } 2972 2973 static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask) 2974 { 2975 u32 val = 0; 2976 int lane = 0; 2977 2978 for_each_cx0_lane_in_mask(lane_mask, lane) 2979 val |= XELPDP_LANE_PCLK_PLL_ACK(lane); 2980 2981 return val; 2982 } 2983 2984 static void intel_cx0pll_enable(struct intel_encoder *encoder, 2985 const struct intel_crtc_state *crtc_state) 2986 { 2987 struct intel_display *display = to_intel_display(encoder); 2988 enum phy phy = intel_encoder_to_phy(encoder); 2989 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2990 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2991 u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 : 2992 INTEL_CX0_LANE0; 2993 intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); 2994 2995 /* 2996 * 1. Program PORT_CLOCK_CTL REGISTER to configure 2997 * clock muxes, gating and SSC 2998 */ 2999 intel_program_port_clock_ctl(encoder, crtc_state, lane_reversal); 3000 3001 /* 2. Bring PHY out of reset. */ 3002 intel_cx0_phy_lane_reset(encoder, lane_reversal); 3003 3004 /* 3005 * 3. Change Phy power state to Ready. 3006 * TODO: For DP alt mode use only one lane. 3007 */ 3008 intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, 3009 CX0_P2_STATE_READY); 3010 3011 /* 3012 * 4. Program PORT_MSGBUS_TIMER register's Message Bus Timer field to 0xA000. 3013 * (This is done inside intel_cx0_phy_transaction_begin(), since we would need 3014 * the right timer thresholds for readouts too.) 3015 */ 3016 3017 /* 5. Program PHY internal PLL internal registers. */ 3018 if (intel_encoder_is_c10phy(encoder)) 3019 intel_c10_pll_program(display, crtc_state, encoder); 3020 else 3021 intel_c20_pll_program(display, crtc_state, encoder); 3022 3023 /* 3024 * 6. Program the enabled and disabled owned PHY lane 3025 * transmitters over message bus 3026 */ 3027 intel_cx0_program_phy_lane(encoder, crtc_state->lane_count, lane_reversal); 3028 3029 /* 3030 * 7. Follow the Display Voltage Frequency Switching - Sequence 3031 * Before Frequency Change. We handle this step in bxt_set_cdclk(). 3032 */ 3033 3034 /* 3035 * 8. Program DDI_CLK_VALFREQ to match intended DDI 3036 * clock frequency. 3037 */ 3038 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 3039 crtc_state->port_clock); 3040 3041 /* 3042 * 9. Set PORT_CLOCK_CTL register PCLK PLL Request 3043 * LN<Lane for maxPCLK> to "1" to enable PLL. 3044 */ 3045 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 3046 intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES), 3047 intel_cx0_get_pclk_pll_request(maxpclk_lane)); 3048 3049 /* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */ 3050 if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 3051 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES), 3052 intel_cx0_get_pclk_pll_ack(maxpclk_lane), 3053 XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL)) 3054 drm_warn(display->drm, "Port %c PLL not locked after %dus.\n", 3055 phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US); 3056 3057 /* 3058 * 11. Follow the Display Voltage Frequency Switching Sequence After 3059 * Frequency Change. We handle this step in bxt_set_cdclk(). 3060 */ 3061 3062 /* TODO: enable TBT-ALT mode */ 3063 intel_cx0_phy_transaction_end(encoder, wakeref); 3064 } 3065 3066 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder) 3067 { 3068 struct intel_display *display = to_intel_display(encoder); 3069 u32 clock, val; 3070 3071 val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)); 3072 3073 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val); 3074 3075 drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE)); 3076 drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_REQUEST)); 3077 drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_ACK)); 3078 3079 switch (clock) { 3080 case XELPDP_DDI_CLOCK_SELECT_TBT_162: 3081 return 162000; 3082 case XELPDP_DDI_CLOCK_SELECT_TBT_270: 3083 return 270000; 3084 case XELPDP_DDI_CLOCK_SELECT_TBT_540: 3085 return 540000; 3086 case XELPDP_DDI_CLOCK_SELECT_TBT_810: 3087 return 810000; 3088 default: 3089 MISSING_CASE(clock); 3090 return 162000; 3091 } 3092 } 3093 3094 static int intel_mtl_tbt_clock_select(int clock) 3095 { 3096 switch (clock) { 3097 case 162000: 3098 return XELPDP_DDI_CLOCK_SELECT_TBT_162; 3099 case 270000: 3100 return XELPDP_DDI_CLOCK_SELECT_TBT_270; 3101 case 540000: 3102 return XELPDP_DDI_CLOCK_SELECT_TBT_540; 3103 case 810000: 3104 return XELPDP_DDI_CLOCK_SELECT_TBT_810; 3105 default: 3106 MISSING_CASE(clock); 3107 return XELPDP_DDI_CLOCK_SELECT_TBT_162; 3108 } 3109 } 3110 3111 static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, 3112 const struct intel_crtc_state *crtc_state) 3113 { 3114 struct intel_display *display = to_intel_display(encoder); 3115 enum phy phy = intel_encoder_to_phy(encoder); 3116 u32 val = 0; 3117 3118 /* 3119 * 1. Program PORT_CLOCK_CTL REGISTER to configure 3120 * clock muxes, gating and SSC 3121 */ 3122 val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(crtc_state->port_clock)); 3123 val |= XELPDP_FORWARD_CLOCK_UNGATE; 3124 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 3125 XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val); 3126 3127 /* 2. Read back PORT_CLOCK_CTL REGISTER */ 3128 val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)); 3129 3130 /* 3131 * 3. Follow the Display Voltage Frequency Switching - Sequence 3132 * Before Frequency Change. We handle this step in bxt_set_cdclk(). 3133 */ 3134 3135 /* 3136 * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL. 3137 */ 3138 val |= XELPDP_TBT_CLOCK_REQUEST; 3139 intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val); 3140 3141 /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */ 3142 if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 3143 XELPDP_TBT_CLOCK_ACK, 3144 XELPDP_TBT_CLOCK_ACK, 3145 100, 0, NULL)) 3146 drm_warn(display->drm, 3147 "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n", 3148 encoder->base.base.id, encoder->base.name, phy_name(phy)); 3149 3150 /* 3151 * 6. Follow the Display Voltage Frequency Switching Sequence After 3152 * Frequency Change. We handle this step in bxt_set_cdclk(). 3153 */ 3154 3155 /* 3156 * 7. Program DDI_CLK_VALFREQ to match intended DDI 3157 * clock frequency. 3158 */ 3159 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 3160 crtc_state->port_clock); 3161 } 3162 3163 void intel_mtl_pll_enable(struct intel_encoder *encoder, 3164 const struct intel_crtc_state *crtc_state) 3165 { 3166 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3167 3168 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 3169 intel_mtl_tbt_pll_enable(encoder, crtc_state); 3170 else 3171 intel_cx0pll_enable(encoder, crtc_state); 3172 } 3173 3174 static u8 cx0_power_control_disable_val(struct intel_encoder *encoder) 3175 { 3176 struct intel_display *display = to_intel_display(encoder); 3177 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3178 3179 if (intel_encoder_is_c10phy(encoder)) 3180 return CX0_P2PG_STATE_DISABLE; 3181 3182 if ((IS_BATTLEMAGE(i915) && encoder->port == PORT_A) || 3183 (DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP)) 3184 return CX0_P2PG_STATE_DISABLE; 3185 3186 return CX0_P4PG_STATE_DISABLE; 3187 } 3188 3189 static void intel_cx0pll_disable(struct intel_encoder *encoder) 3190 { 3191 struct intel_display *display = to_intel_display(encoder); 3192 enum phy phy = intel_encoder_to_phy(encoder); 3193 intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); 3194 3195 /* 1. Change owned PHY lane power to Disable state. */ 3196 intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, 3197 cx0_power_control_disable_val(encoder)); 3198 3199 /* 3200 * 2. Follow the Display Voltage Frequency Switching Sequence Before 3201 * Frequency Change. We handle this step in bxt_set_cdclk(). 3202 */ 3203 3204 /* 3205 * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK> 3206 * to "0" to disable PLL. 3207 */ 3208 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 3209 intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) | 3210 intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0); 3211 3212 /* 4. Program DDI_CLK_VALFREQ to 0. */ 3213 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0); 3214 3215 /* 3216 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0". 3217 */ 3218 if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 3219 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) | 3220 intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0, 3221 XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL)) 3222 drm_warn(display->drm, 3223 "Port %c PLL not unlocked after %dus.\n", 3224 phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US); 3225 3226 /* 3227 * 6. Follow the Display Voltage Frequency Switching Sequence After 3228 * Frequency Change. We handle this step in bxt_set_cdclk(). 3229 */ 3230 3231 /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */ 3232 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 3233 XELPDP_DDI_CLOCK_SELECT_MASK, 0); 3234 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 3235 XELPDP_FORWARD_CLOCK_UNGATE, 0); 3236 3237 intel_cx0_phy_transaction_end(encoder, wakeref); 3238 } 3239 3240 static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) 3241 { 3242 struct intel_display *display = to_intel_display(encoder); 3243 enum phy phy = intel_encoder_to_phy(encoder); 3244 3245 /* 3246 * 1. Follow the Display Voltage Frequency Switching Sequence Before 3247 * Frequency Change. We handle this step in bxt_set_cdclk(). 3248 */ 3249 3250 /* 3251 * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL. 3252 */ 3253 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 3254 XELPDP_TBT_CLOCK_REQUEST, 0); 3255 3256 /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ 3257 if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 3258 XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL)) 3259 drm_warn(display->drm, 3260 "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n", 3261 encoder->base.base.id, encoder->base.name, phy_name(phy)); 3262 3263 /* 3264 * 4. Follow the Display Voltage Frequency Switching Sequence After 3265 * Frequency Change. We handle this step in bxt_set_cdclk(). 3266 */ 3267 3268 /* 3269 * 5. Program PORT CLOCK CTRL register to disable and gate clocks 3270 */ 3271 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 3272 XELPDP_DDI_CLOCK_SELECT_MASK | 3273 XELPDP_FORWARD_CLOCK_UNGATE, 0); 3274 3275 /* 6. Program DDI_CLK_VALFREQ to 0. */ 3276 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0); 3277 } 3278 3279 void intel_mtl_pll_disable(struct intel_encoder *encoder) 3280 { 3281 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3282 3283 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 3284 intel_mtl_tbt_pll_disable(encoder); 3285 else 3286 intel_cx0pll_disable(encoder); 3287 } 3288 3289 enum icl_port_dpll_id 3290 intel_mtl_port_pll_type(struct intel_encoder *encoder, 3291 const struct intel_crtc_state *crtc_state) 3292 { 3293 struct intel_display *display = to_intel_display(encoder); 3294 u32 val, clock; 3295 3296 /* 3297 * TODO: Determine the PLL type from the SW state, once MTL PLL 3298 * handling is done via the standard shared DPLL framework. 3299 */ 3300 val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)); 3301 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val); 3302 3303 if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK || 3304 clock == XELPDP_DDI_CLOCK_SELECT_DIV18CLK) 3305 return ICL_PORT_DPLL_MG_PHY; 3306 else 3307 return ICL_PORT_DPLL_DEFAULT; 3308 } 3309 3310 static void intel_c10pll_state_verify(const struct intel_crtc_state *state, 3311 struct intel_crtc *crtc, 3312 struct intel_encoder *encoder, 3313 struct intel_c10pll_state *mpllb_hw_state) 3314 { 3315 struct intel_display *display = to_intel_display(state); 3316 const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10; 3317 int i; 3318 3319 for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { 3320 u8 expected = mpllb_sw_state->pll[i]; 3321 3322 INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->pll[i] != expected, 3323 "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", 3324 crtc->base.base.id, crtc->base.name, i, 3325 expected, mpllb_hw_state->pll[i]); 3326 } 3327 3328 INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->tx != mpllb_sw_state->tx, 3329 "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", 3330 crtc->base.base.id, crtc->base.name, 3331 mpllb_sw_state->tx, mpllb_hw_state->tx); 3332 3333 INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn != mpllb_sw_state->cmn, 3334 "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", 3335 crtc->base.base.id, crtc->base.name, 3336 mpllb_sw_state->cmn, mpllb_hw_state->cmn); 3337 } 3338 3339 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, 3340 struct intel_cx0pll_state *pll_state) 3341 { 3342 pll_state->use_c10 = false; 3343 3344 pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); 3345 if (pll_state->tbt_mode) 3346 return; 3347 3348 if (intel_encoder_is_c10phy(encoder)) { 3349 intel_c10pll_readout_hw_state(encoder, &pll_state->c10); 3350 pll_state->use_c10 = true; 3351 } else { 3352 intel_c20pll_readout_hw_state(encoder, &pll_state->c20); 3353 } 3354 } 3355 3356 static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a, 3357 const struct intel_c10pll_state *b) 3358 { 3359 if (a->tx != b->tx) 3360 return false; 3361 3362 if (a->cmn != b->cmn) 3363 return false; 3364 3365 if (memcmp(&a->pll, &b->pll, sizeof(a->pll)) != 0) 3366 return false; 3367 3368 return true; 3369 } 3370 3371 static bool mtl_compare_hw_state_c20(const struct intel_c20pll_state *a, 3372 const struct intel_c20pll_state *b) 3373 { 3374 if (memcmp(&a->tx, &b->tx, sizeof(a->tx)) != 0) 3375 return false; 3376 3377 if (memcmp(&a->cmn, &b->cmn, sizeof(a->cmn)) != 0) 3378 return false; 3379 3380 if (a->tx[0] & C20_PHY_USE_MPLLB) { 3381 if (memcmp(&a->mpllb, &b->mpllb, sizeof(a->mpllb)) != 0) 3382 return false; 3383 } else { 3384 if (memcmp(&a->mplla, &b->mplla, sizeof(a->mplla)) != 0) 3385 return false; 3386 } 3387 3388 return true; 3389 } 3390 3391 bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a, 3392 const struct intel_cx0pll_state *b) 3393 { 3394 if (a->tbt_mode || b->tbt_mode) 3395 return true; 3396 3397 if (a->use_c10 != b->use_c10) 3398 return false; 3399 3400 if (a->use_c10) 3401 return mtl_compare_hw_state_c10(&a->c10, 3402 &b->c10); 3403 else 3404 return mtl_compare_hw_state_c20(&a->c20, 3405 &b->c20); 3406 } 3407 3408 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder, 3409 const struct intel_cx0pll_state *pll_state) 3410 { 3411 if (intel_encoder_is_c10phy(encoder)) 3412 return intel_c10pll_calc_port_clock(encoder, &pll_state->c10); 3413 3414 return intel_c20pll_calc_port_clock(encoder, &pll_state->c20); 3415 } 3416 3417 static void intel_c20pll_state_verify(const struct intel_crtc_state *state, 3418 struct intel_crtc *crtc, 3419 struct intel_encoder *encoder, 3420 struct intel_c20pll_state *mpll_hw_state) 3421 { 3422 struct intel_display *display = to_intel_display(state); 3423 const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20; 3424 bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state); 3425 bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state); 3426 int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state); 3427 int i; 3428 3429 INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->clock != clock, 3430 "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)", 3431 crtc->base.base.id, crtc->base.name, 3432 mpll_sw_state->clock, mpll_hw_state->clock); 3433 3434 INTEL_DISPLAY_STATE_WARN(display, sw_use_mpllb != hw_use_mpllb, 3435 "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)", 3436 crtc->base.base.id, crtc->base.name, 3437 sw_use_mpllb, hw_use_mpllb); 3438 3439 if (hw_use_mpllb) { 3440 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) { 3441 INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i], 3442 "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)", 3443 crtc->base.base.id, crtc->base.name, i, 3444 mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]); 3445 } 3446 } else { 3447 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) { 3448 INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i], 3449 "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)", 3450 crtc->base.base.id, crtc->base.name, i, 3451 mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]); 3452 } 3453 } 3454 3455 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) { 3456 INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->tx[i] != mpll_sw_state->tx[i], 3457 "[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)", 3458 crtc->base.base.id, crtc->base.name, i, 3459 mpll_sw_state->tx[i], mpll_hw_state->tx[i]); 3460 } 3461 3462 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) { 3463 INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i], 3464 "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)", 3465 crtc->base.base.id, crtc->base.name, i, 3466 mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]); 3467 } 3468 } 3469 3470 void intel_cx0pll_state_verify(struct intel_atomic_state *state, 3471 struct intel_crtc *crtc) 3472 { 3473 struct intel_display *display = to_intel_display(state); 3474 const struct intel_crtc_state *new_crtc_state = 3475 intel_atomic_get_new_crtc_state(state, crtc); 3476 struct intel_encoder *encoder; 3477 struct intel_cx0pll_state mpll_hw_state = {}; 3478 3479 if (DISPLAY_VER(display) < 14) 3480 return; 3481 3482 if (!new_crtc_state->hw.active) 3483 return; 3484 3485 /* intel_get_crtc_new_encoder() only works for modeset/fastset commits */ 3486 if (!intel_crtc_needs_modeset(new_crtc_state) && 3487 !intel_crtc_needs_fastset(new_crtc_state)) 3488 return; 3489 3490 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 3491 intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state); 3492 3493 if (mpll_hw_state.tbt_mode) 3494 return; 3495 3496 if (intel_encoder_is_c10phy(encoder)) 3497 intel_c10pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c10); 3498 else 3499 intel_c20pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c20); 3500 } 3501