1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _TA_IF_H 26 #define _TA_IF_H 27 #include "ras.h" 28 29 #define RAS_TA_HOST_IF_VER 0 30 31 /* Responses have bit 31 set */ 32 #define RSP_ID_MASK (1U << 31) 33 #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK) 34 35 /* invalid node instance value */ 36 #define RAS_TA_INV_NODE 0xffff 37 38 /* RAS related enumerations */ 39 /**********************************************************/ 40 enum ras_ta_cmd_id { 41 RAS_TA_CMD_ID__ENABLE_FEATURES = 0, 42 RAS_TA_CMD_ID__DISABLE_FEATURES, 43 RAS_TA_CMD_ID__TRIGGER_ERROR, 44 RAS_TA_CMD_ID__QUERY_BLOCK_INFO, 45 RAS_TA_CMD_ID__QUERY_SUB_BLOCK_INFO, 46 RAS_TA_CMD_ID__QUERY_ADDRESS, 47 MAX_RAS_TA_CMD_ID 48 }; 49 50 enum ras_ta_status { 51 RAS_TA_STATUS__SUCCESS = 0x0000, 52 RAS_TA_STATUS__RESET_NEEDED = 0xA001, 53 RAS_TA_STATUS__ERROR_INVALID_PARAMETER = 0xA002, 54 RAS_TA_STATUS__ERROR_RAS_NOT_AVAILABLE = 0xA003, 55 RAS_TA_STATUS__ERROR_RAS_DUPLICATE_CMD = 0xA004, 56 RAS_TA_STATUS__ERROR_INJECTION_FAILED = 0xA005, 57 RAS_TA_STATUS__ERROR_ASD_READ_WRITE = 0xA006, 58 RAS_TA_STATUS__ERROR_TOGGLE_DF_CSTATE = 0xA007, 59 RAS_TA_STATUS__ERROR_TIMEOUT = 0xA008, 60 RAS_TA_STATUS__ERROR_BLOCK_DISABLED = 0XA009, 61 RAS_TA_STATUS__ERROR_GENERIC = 0xA00A, 62 RAS_TA_STATUS__ERROR_RAS_MMHUB_INIT = 0xA00B, 63 RAS_TA_STATUS__ERROR_GET_DEV_INFO = 0xA00C, 64 RAS_TA_STATUS__ERROR_UNSUPPORTED_DEV = 0xA00D, 65 RAS_TA_STATUS__ERROR_NOT_INITIALIZED = 0xA00E, 66 RAS_TA_STATUS__ERROR_TEE_INTERNAL = 0xA00F, 67 RAS_TA_STATUS__ERROR_UNSUPPORTED_FUNCTION = 0xA010, 68 RAS_TA_STATUS__ERROR_SYS_DRV_REG_ACCESS = 0xA011, 69 RAS_TA_STATUS__ERROR_RAS_READ_WRITE = 0xA012, 70 RAS_TA_STATUS__ERROR_NULL_PTR = 0xA013, 71 RAS_TA_STATUS__ERROR_UNSUPPORTED_IP = 0xA014, 72 RAS_TA_STATUS__ERROR_PCS_STATE_QUIET = 0xA015, 73 RAS_TA_STATUS__ERROR_PCS_STATE_ERROR = 0xA016, 74 RAS_TA_STATUS__ERROR_PCS_STATE_HANG = 0xA017, 75 RAS_TA_STATUS__ERROR_PCS_STATE_UNKNOWN = 0xA018, 76 RAS_TA_STATUS__ERROR_UNSUPPORTED_ERROR_INJ = 0xA019, 77 RAS_TA_STATUS__TEE_ERROR_ACCESS_DENIED = 0xA01A 78 }; 79 80 enum ras_ta_block { 81 RAS_TA_BLOCK__UMC = 0, 82 RAS_TA_BLOCK__SDMA, 83 RAS_TA_BLOCK__GFX, 84 RAS_TA_BLOCK__MMHUB, 85 RAS_TA_BLOCK__ATHUB, 86 RAS_TA_BLOCK__PCIE_BIF, 87 RAS_TA_BLOCK__HDP, 88 RAS_TA_BLOCK__XGMI_WAFL, 89 RAS_TA_BLOCK__DF, 90 RAS_TA_BLOCK__SMN, 91 RAS_TA_BLOCK__SEM, 92 RAS_TA_BLOCK__MP0, 93 RAS_TA_BLOCK__MP1, 94 RAS_TA_BLOCK__FUSE, 95 RAS_TA_BLOCK__MCA, 96 RAS_TA_BLOCK__VCN, 97 RAS_TA_BLOCK__JPEG, 98 RAS_TA_BLOCK__IH, 99 RAS_TA_BLOCK__MPIO, 100 RAS_TA_BLOCK__MMSCH, 101 RAS_TA_NUM_BLOCK_MAX 102 }; 103 104 enum ras_ta_mca_block { 105 RAS_TA_MCA_BLOCK__MP0 = 0, 106 RAS_TA_MCA_BLOCK__MP1 = 1, 107 RAS_TA_MCA_BLOCK__MPIO = 2, 108 RAS_TA_MCA_BLOCK__IOHC = 3, 109 RAS_TA_MCA_NUM_BLOCK_MAX 110 }; 111 112 enum ras_ta_error_type { 113 RAS_TA_ERROR__NONE = 0, 114 RAS_TA_ERROR__PARITY = 1, 115 RAS_TA_ERROR__SINGLE_CORRECTABLE = 2, 116 RAS_TA_ERROR__MULTI_UNCORRECTABLE = 4, 117 RAS_TA_ERROR__POISON = 8, 118 }; 119 120 enum ras_ta_address_type { 121 RAS_TA_MCA_TO_PA, 122 RAS_TA_PA_TO_MCA, 123 }; 124 125 enum ras_ta_nps_mode { 126 RAS_TA_UNKNOWN_MODE = 0, 127 RAS_TA_NPS1_MODE = 1, 128 RAS_TA_NPS2_MODE = 2, 129 RAS_TA_NPS4_MODE = 4, 130 RAS_TA_NPS8_MODE = 8, 131 }; 132 133 /* Input/output structures for RAS commands */ 134 /**********************************************************/ 135 136 struct ras_ta_enable_features_input { 137 enum ras_ta_block block_id; 138 enum ras_ta_error_type error_type; 139 }; 140 141 struct ras_ta_disable_features_input { 142 enum ras_ta_block block_id; 143 enum ras_ta_error_type error_type; 144 }; 145 146 struct ras_ta_trigger_error_input { 147 /* ras-block. i.e. umc, gfx */ 148 enum ras_ta_block block_id; 149 150 /* type of error. i.e. single_correctable */ 151 enum ras_ta_error_type inject_error_type; 152 153 /* mem block. i.e. hbm, sram etc. */ 154 uint32_t sub_block_index; 155 156 /* explicit address of error */ 157 uint64_t address; 158 159 /* method if error injection. i.e persistent, coherent etc. */ 160 uint64_t value; 161 }; 162 163 struct ras_ta_init_flags { 164 uint8_t poison_mode_en; 165 uint8_t dgpu_mode; 166 uint16_t xcc_mask; 167 uint8_t channel_dis_num; 168 uint8_t nps_mode; 169 uint32_t active_umc_mask; 170 uint8_t vram_type; 171 }; 172 173 struct ras_ta_mca_addr { 174 uint64_t err_addr; 175 uint32_t ch_inst; 176 uint32_t umc_inst; 177 uint32_t node_inst; 178 uint32_t socket_id; 179 }; 180 181 struct ras_ta_phy_addr { 182 uint64_t pa; 183 uint32_t bank; 184 uint32_t channel_idx; 185 }; 186 187 struct ras_ta_query_address_input { 188 enum ras_ta_address_type addr_type; 189 struct ras_ta_mca_addr ma; 190 struct ras_ta_phy_addr pa; 191 }; 192 193 struct ras_ta_output_flags { 194 uint8_t ras_init_success_flag; 195 uint8_t err_inject_switch_disable_flag; 196 uint8_t reg_access_failure_flag; 197 }; 198 199 struct ras_ta_query_address_output { 200 /* don't use the flags here */ 201 struct ras_ta_output_flags flags; 202 struct ras_ta_mca_addr ma; 203 struct ras_ta_phy_addr pa; 204 }; 205 206 /* Common input structure for RAS callbacks */ 207 /**********************************************************/ 208 union ras_ta_cmd_input { 209 struct ras_ta_init_flags init_flags; 210 struct ras_ta_enable_features_input enable_features; 211 struct ras_ta_disable_features_input disable_features; 212 struct ras_ta_trigger_error_input trigger_error; 213 struct ras_ta_query_address_input address; 214 uint32_t reserve_pad[256]; 215 }; 216 217 union ras_ta_cmd_output { 218 struct ras_ta_output_flags flags; 219 struct ras_ta_query_address_output address; 220 uint32_t reserve_pad[256]; 221 }; 222 223 struct ras_ta_cmd { 224 uint32_t cmd_id; 225 uint32_t resp_id; 226 uint32_t ras_status; 227 uint32_t if_version; 228 union ras_ta_cmd_input ras_in_message; 229 union ras_ta_cmd_output ras_out_message; 230 }; 231 232 #endif 233