1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __RAS_UMC_H__ 26 #define __RAS_UMC_H__ 27 #include "ras.h" 28 #include "eeprom.h" 29 #include "cmd.h" 30 31 #define UMC_VRAM_TYPE_UNKNOWN 0 32 #define UMC_VRAM_TYPE_GDDR1 1 33 #define UMC_VRAM_TYPE_DDR2 2 34 #define UMC_VRAM_TYPE_GDDR3 3 35 #define UMC_VRAM_TYPE_GDDR4 4 36 #define UMC_VRAM_TYPE_GDDR5 5 37 #define UMC_VRAM_TYPE_HBM 6 38 #define UMC_VRAM_TYPE_DDR3 7 39 #define UMC_VRAM_TYPE_DDR4 8 40 #define UMC_VRAM_TYPE_GDDR6 9 41 #define UMC_VRAM_TYPE_DDR5 10 42 #define UMC_VRAM_TYPE_LPDDR4 11 43 #define UMC_VRAM_TYPE_LPDDR5 12 44 #define UMC_VRAM_TYPE_HBM3E 13 45 46 #define UMC_ECC_NEW_DETECTED_TAG 0x1 47 #define UMC_INV_MEM_PFN (0xFFFFFFFFFFFFFFFF) 48 /* invalid node instance value */ 49 #define UMC_INV_AID_NODE 0xffff 50 51 /* 52 * a flag to indicate v2 format channel index stored in eeprom 53 * 54 * v1: store channel index within a umc instance in eeprom 55 * range in UMC v12: 0 ~ 7 56 * v2: store global channel index in eeprom 57 * range in UMC v12: 0 ~ 127 58 * 59 * NOTE: it's better to store it in eeprom_table_record.mem_channel, 60 * but there is only 8 bits in mem_channel, and the channel number may 61 * increase in the future, we decide to save it in 62 * eeprom_table_record.retired_page. retired_page is useless in v2, 63 * we depend on eeprom_table_record.address instead of retired_page in v2. 64 * Only 48 bits are saved on eeprom, use bit 47 here. 65 * 66 * UMC_CHANNEL_IDX_V2 is replaced by nps value in cur_nps_retired_row_pfn 67 * in eeprom v3 format, so they have no conflict. 68 */ 69 #define UMC_CHANNEL_IDX_V2 BIT_ULL(47) 70 71 /* three column bits and one row bit in MCA address flip 72 * in bad page retirement 73 */ 74 #define UMC_PA_FLIP_BITS_NUM 4 75 /* bits [63:58] of pa carry the nps mode for RAS_TA_PA_TO_MCA, 76 * RAS TA will use it to get the nps related to pa 77 */ 78 #define UMC_PA_NPS_SHIFT 58 79 80 enum umc_memory_partition_mode { 81 UMC_MEMORY_PARTITION_MODE_NONE = 0, 82 UMC_MEMORY_PARTITION_MODE_NPS1 = 1, 83 UMC_MEMORY_PARTITION_MODE_NPS2 = 2, 84 UMC_MEMORY_PARTITION_MODE_NPS3 = 3, 85 UMC_MEMORY_PARTITION_MODE_NPS4 = 4, 86 UMC_MEMORY_PARTITION_MODE_NPS6 = 6, 87 UMC_MEMORY_PARTITION_MODE_NPS8 = 8, 88 UMC_MEMORY_PARTITION_MODE_UNKNOWN 89 }; 90 91 struct ras_core_context; 92 struct ras_bank_ecc; 93 94 struct umc_flip_bits { 95 uint32_t flip_bits_in_pa[UMC_PA_FLIP_BITS_NUM]; 96 uint32_t flip_row_bit; 97 uint32_t r13_in_pa; 98 uint32_t bit_num; 99 }; 100 101 struct umc_mca_addr { 102 uint64_t err_addr; 103 uint32_t ch_inst; 104 uint32_t umc_inst; 105 uint32_t node_inst; 106 uint32_t socket_id; 107 }; 108 109 struct umc_phy_addr { 110 uint64_t pa; 111 uint32_t bank; 112 uint32_t channel_idx; 113 }; 114 115 struct umc_bank_addr { 116 uint32_t stack_id; /* SID */ 117 uint32_t bank_group; 118 uint32_t bank; 119 uint32_t row; 120 uint32_t column; 121 uint32_t channel; 122 uint32_t subchannel; /* Also called Pseudochannel (PC) */ 123 }; 124 125 struct ras_umc_ip_func { 126 int (*bank_to_eeprom_record)(struct ras_core_context *ras_core, 127 struct ras_bank_ecc *bank, struct eeprom_umc_record *record); 128 int (*eeprom_record_to_nps_pages)(struct ras_core_context *ras_core, 129 struct eeprom_umc_record *record, uint32_t nps, 130 uint64_t *pfns, uint32_t num); 131 int (*bank_to_soc_pa)(struct ras_core_context *ras_core, 132 struct umc_bank_addr bank_addr, uint64_t *soc_pa); 133 int (*soc_pa_to_bank)(struct ras_core_context *ras_core, 134 uint64_t soc_pa, struct umc_bank_addr *bank_addr); 135 void (*mca_ipid_parse)(struct ras_core_context *ras_core, uint64_t ipid, 136 uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid); 137 int (*ma2pa)(struct ras_core_context *ras_core, 138 struct umc_mca_addr *addr_in, struct umc_phy_addr *addr_out, 139 uint32_t nps); 140 uint64_t (*nps_pa_to_row_pa)(struct ras_core_context *ras_core, 141 uint64_t pa, enum umc_memory_partition_mode nps, bool zero_pfn_ok); 142 uint32_t (*get_die_id)(uint64_t mca_addr, uint64_t pa); 143 }; 144 145 struct eeprom_store_record { 146 /* point to data records array */ 147 struct eeprom_umc_record *bps; 148 /* the count of entries */ 149 int count; 150 /* the space can place new entries */ 151 int space_left; 152 /* logical bad page number */ 153 int bad_page_num; 154 /* the bad page number is ras_num_recs or 155 * ras_num_recs * retire_unit 156 */ 157 int bad_page_num_old; 158 }; 159 160 struct ras_umc_err_data { 161 struct eeprom_store_record rom_data; 162 struct eeprom_store_record ram_data; 163 enum umc_memory_partition_mode umc_nps_mode; 164 uint64_t last_retired_pfn; 165 }; 166 167 struct ras_umc { 168 u32 umc_ip_version; 169 u32 umc_vram_type; 170 u32 num_umc; 171 const struct ras_umc_ip_func *ip_func; 172 struct radix_tree_root root; 173 struct mutex tree_lock; 174 struct mutex umc_lock; 175 struct mutex bank_log_lock; 176 struct mutex pending_ecc_lock; 177 struct ras_umc_err_data umc_err_data; 178 struct list_head pending_ecc_list; 179 /* number of entries currently queued on pending_ecc_list */ 180 u32 pending_ecc_count; 181 /* number of entries dropped because pending_ecc_list was full */ 182 u32 pending_ecc_dropped; 183 }; 184 185 /* 186 * Upper bound on entries that can be queued on pending_ecc_list while a 187 * GPU reset is in progress. Beyond this, new ECC events are dropped to 188 * prevent unbounded kernel memory growth in case of an ECC storm or 189 * malicious/repeated UMC error injection. 190 */ 191 #define RAS_UMC_PENDING_ECC_MAX 8192 192 193 int ras_umc_sw_init(struct ras_core_context *ras); 194 int ras_umc_sw_fini(struct ras_core_context *ras); 195 int ras_umc_hw_init(struct ras_core_context *ras); 196 int ras_umc_hw_fini(struct ras_core_context *ras); 197 int ras_umc_psp_ma2pa(struct ras_core_context *ras_core, 198 struct umc_mca_addr *in, struct umc_phy_addr *out, 199 uint32_t nps); 200 int ras_umc_handle_bad_pages(struct ras_core_context *ras_core, void *data); 201 int ras_umc_log_bad_bank(struct ras_core_context *ras, struct ras_bank_ecc *bank); 202 int ras_umc_log_bad_bank_pending(struct ras_core_context *ras_core, struct ras_bank_ecc *bank); 203 int ras_umc_log_pending_bad_bank(struct ras_core_context *ras_core); 204 int ras_umc_clear_logged_ecc(struct ras_core_context *ras_core); 205 int ras_umc_load_bad_pages(struct ras_core_context *ras_core); 206 int ras_umc_get_saved_eeprom_count(struct ras_core_context *ras_core); 207 int ras_umc_clean_badpage_data(struct ras_core_context *ras_core); 208 int ras_umc_fill_eeprom_record(struct ras_core_context *ras_core, 209 uint64_t err_addr, uint32_t umc_inst, struct umc_phy_addr *cur_nps_addr, 210 enum umc_memory_partition_mode cur_nps, struct eeprom_umc_record *record); 211 212 int ras_umc_get_badpage_count(struct ras_core_context *ras_core); 213 int ras_umc_get_badpage_record(struct ras_core_context *ras_core, uint32_t index, void *record); 214 bool ras_umc_check_retired_addr(struct ras_core_context *ras_core, uint64_t addr); 215 int ras_umc_translate_soc_pa_and_bank(struct ras_core_context *ras_core, 216 uint64_t *soc_pa, struct umc_bank_addr *bank_addr, bool bank_to_pa); 217 int ras_umc_convert_record_to_nps_pages(struct ras_core_context *ras_core, 218 struct eeprom_umc_record *record, uint32_t nps, 219 uint64_t *page_pfn, uint32_t max_pages); 220 uint32_t ras_umc_bit_wise_xor(uint32_t val); 221 int ras_umc_ma2pa(struct ras_core_context *ras_core, 222 struct umc_mca_addr *addr_in, struct umc_phy_addr *addr_out, 223 uint32_t nps); 224 #endif 225