1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __RAS_H__ 26 #define __RAS_H__ 27 #include "ras_sys.h" 28 #include "ras_umc.h" 29 #include "aca.h" 30 #include "eeprom.h" 31 #include "core_status.h" 32 #include "ras_process.h" 33 #include "ras_gfx.h" 34 #include "cmd.h" 35 #include "ras_nbio.h" 36 #include "ras_mp1.h" 37 #include "ras_psp.h" 38 #include "log_ring.h" 39 #include "eeprom_fw.h" 40 41 #define RAS_HW_ERR "[Hardware Error]: " 42 43 #define RAS_GPU_PAGE_SHIFT 12 44 #define RAS_ADDR_TO_PFN(addr) ((addr) >> RAS_GPU_PAGE_SHIFT) 45 #define RAS_PFN_TO_ADDR(pfn) ((pfn) << RAS_GPU_PAGE_SHIFT) 46 47 #define RAS_CORE_RESET_GPU 0x10000 48 49 #define GPU_RESET_CAUSE_POISON (RAS_CORE_RESET_GPU | 0x0001) 50 #define GPU_RESET_CAUSE_FATAL (RAS_CORE_RESET_GPU | 0x0002) 51 #define GPU_RESET_CAUSE_RMA (RAS_CORE_RESET_GPU | 0x0004) 52 53 enum ras_gpu_health_status { 54 RAS_GPU_HEALTH_NONE = 0, 55 RAS_GPU_HEALTH_USABLE = 1, 56 RAS_GPU_RETIRED__ECC_REACH_THRESHOLD = 2, 57 RAS_GPU_IN_BAD_STATUS = 3, 58 }; 59 60 enum ras_core_fw_feature_flags { 61 RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0), 62 }; 63 64 enum ras_block_id { 65 RAS_BLOCK_ID__UMC = 0, 66 RAS_BLOCK_ID__SDMA, 67 RAS_BLOCK_ID__GFX, 68 RAS_BLOCK_ID__MMHUB, 69 RAS_BLOCK_ID__ATHUB, 70 RAS_BLOCK_ID__PCIE_BIF, 71 RAS_BLOCK_ID__HDP, 72 RAS_BLOCK_ID__XGMI_WAFL, 73 RAS_BLOCK_ID__DF, 74 RAS_BLOCK_ID__SMN, 75 RAS_BLOCK_ID__SEM, 76 RAS_BLOCK_ID__MP0, 77 RAS_BLOCK_ID__MP1, 78 RAS_BLOCK_ID__FUSE, 79 RAS_BLOCK_ID__MCA, 80 RAS_BLOCK_ID__VCN, 81 RAS_BLOCK_ID__JPEG, 82 RAS_BLOCK_ID__IH, 83 RAS_BLOCK_ID__MPIO, 84 85 RAS_BLOCK_ID__LAST 86 }; 87 88 enum ras_ecc_err_type { 89 RAS_ECC_ERR__NONE = 0, 90 RAS_ECC_ERR__PARITY = 1, 91 RAS_ECC_ERR__SINGLE_CORRECTABLE = 2, 92 RAS_ECC_ERR__MULTI_UNCORRECTABLE = 4, 93 RAS_ECC_ERR__POISON = 8, 94 }; 95 96 enum ras_err_type { 97 RAS_ERR_TYPE__UE = 0, 98 RAS_ERR_TYPE__CE, 99 RAS_ERR_TYPE__DE, 100 RAS_ERR_TYPE__LAST 101 }; 102 103 enum ras_seqno_type { 104 RAS_SEQNO_TYPE_INVALID = 0, 105 RAS_SEQNO_TYPE_UE, 106 RAS_SEQNO_TYPE_CE, 107 RAS_SEQNO_TYPE_DE, 108 RAS_SEQNO_TYPE_POISON_CONSUMPTION, 109 RAS_SEQNO_TYPE_COUNT_MAX, 110 }; 111 112 enum ras_seqno_fifo { 113 SEQNO_FIFO_INVALID = 0, 114 SEQNO_FIFO_POISON_CREATION, 115 SEQNO_FIFO_POISON_CONSUMPTION, 116 SEQNO_FIFO_COUNT_MAX 117 }; 118 119 enum ras_notify_event { 120 RAS_EVENT_ID__NONE, 121 RAS_EVENT_ID__BAD_PAGE_DETECTED, 122 RAS_EVENT_ID__POISON_CONSUMPTION, 123 RAS_EVENT_ID__RESERVE_BAD_PAGE, 124 RAS_EVENT_ID__DEVICE_RMA, 125 RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, 126 RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, 127 RAS_EVENT_ID__FATAL_ERROR_DETECTED, 128 RAS_EVENT_ID__RESET_GPU, 129 RAS_EVENT_ID__RESET_VF, 130 RAS_EVENT_ID__RAS_EVENT_PROC_BEGIN, 131 RAS_EVENT_ID__RAS_EVENT_PROC_END, 132 }; 133 134 enum ras_gpu_status { 135 RAS_GPU_STATUS__NOT_READY = 0, 136 RAS_GPU_STATUS__READY = 0x1, 137 RAS_GPU_STATUS__IN_RESET = 0x2, 138 RAS_GPU_STATUS__IS_RMA = 0x4, 139 RAS_GPU_STATUS__IS_VF = 0x8, 140 RAS_GPU_STATUS__DEVICE_LOST = 0x10, 141 }; 142 143 enum ras_fw_eeprom_cmd { 144 RAS_SMU_GetRASTableVersion = 0, 145 RAS_SMU_GetBadPageCount, 146 RAS_SMU_SetTimestamp, 147 RAS_SMU_GetTimestamp, 148 RAS_SMU_GetBadPageIpid, 149 RAS_SMU_EraseRasTable, 150 RAS_SMU_GetBadPageMcaAddr, 151 }; 152 153 struct ras_core_context; 154 struct ras_bank_ecc; 155 struct ras_umc; 156 struct ras_aca; 157 struct ras_process; 158 struct ras_nbio; 159 struct ras_log_ring; 160 struct ras_psp; 161 162 struct ras_mp1_sys_func { 163 int (*mp1_get_valid_bank_count)(struct ras_core_context *ras_core, 164 u32 msg, u32 *count); 165 int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core, 166 u32 msg, u32 idx, u32 reg_idx, u64 *val); 167 int (*mp1_send_eeprom_msg)(struct ras_core_context *ras_core, 168 enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg); 169 int (*mp1_get_ras_enabled_mask)(struct ras_core_context *ras_core, 170 uint64_t *enabled_mask); 171 int (*mp1_set_debug_mode)(struct ras_core_context *ras_core, bool enable); 172 }; 173 174 struct ras_eeprom_sys_func { 175 int (*eeprom_i2c_xfer)(struct ras_core_context *ras_core, 176 u32 eeprom_addr, u8 *eeprom_buf, u32 buf_size, bool read); 177 int (*update_eeprom_i2c_config)(struct ras_core_context *ras_core); 178 }; 179 180 struct ras_nbio_sys_func { 181 int (*set_ras_controller_irq_state)(struct ras_core_context *ras_core, 182 bool state); 183 int (*set_ras_err_event_athub_irq_state)(struct ras_core_context *ras_core, 184 bool state); 185 }; 186 187 struct ras_time { 188 int tm_sec; 189 int tm_min; 190 int tm_hour; 191 int tm_mday; 192 int tm_mon; 193 long tm_year; 194 }; 195 196 struct device_system_info { 197 uint32_t device_id; 198 uint32_t vendor_id; 199 uint32_t socket_id; 200 }; 201 202 enum gpu_mem_type { 203 GPU_MEM_TYPE_DEFAULT, 204 GPU_MEM_TYPE_RAS_PSP_RING, 205 GPU_MEM_TYPE_RAS_PSP_CMD, 206 GPU_MEM_TYPE_RAS_PSP_FENCE, 207 GPU_MEM_TYPE_RAS_TA_FW, 208 GPU_MEM_TYPE_RAS_TA_CMD, 209 }; 210 211 struct ras_psp_sys_func { 212 int (*get_ras_psp_system_status)(struct ras_core_context *ras_core, 213 struct ras_psp_sys_status *status); 214 int (*get_ras_ta_init_param)(struct ras_core_context *ras_core, 215 struct ras_ta_init_param *ras_ta_param); 216 }; 217 218 struct ras_sys_func { 219 int (*gpu_reset_lock)(struct ras_core_context *ras_core, 220 bool down, bool try); 221 int (*check_gpu_status)(struct ras_core_context *ras_core, 222 uint32_t *status); 223 int (*gen_seqno)(struct ras_core_context *ras_core, 224 enum ras_seqno_type seqno_type, uint64_t *seqno); 225 int (*async_handle_ras_event)(struct ras_core_context *ras_core, void *data); 226 int (*ras_notifier)(struct ras_core_context *ras_core, 227 enum ras_notify_event event_id, void *data); 228 u64 (*get_utc_second_timestamp)(struct ras_core_context *ras_core); 229 int (*get_device_system_info)(struct ras_core_context *ras_core, 230 struct device_system_info *dev_info); 231 bool (*detect_ras_interrupt)(struct ras_core_context *ras_core); 232 int (*get_gpu_mem)(struct ras_core_context *ras_core, 233 enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem); 234 int (*put_gpu_mem)(struct ras_core_context *ras_core, 235 enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem); 236 int (*check_address_sanity)(struct ras_core_context *ras_core, uint64_t addr); 237 }; 238 239 struct ras_ecc_count { 240 uint64_t new_ce_count; 241 uint64_t total_ce_count; 242 uint64_t new_ue_count; 243 uint64_t total_ue_count; 244 uint64_t new_de_count; 245 uint64_t total_de_count; 246 }; 247 248 struct ras_bank_ecc { 249 uint32_t nps; 250 uint64_t seq_no; 251 uint64_t status; 252 uint64_t ipid; 253 uint64_t addr; 254 uint64_t ts; 255 }; 256 257 struct ras_bank_ecc_node { 258 struct list_head node; 259 struct ras_bank_ecc ecc; 260 }; 261 262 struct ras_aca_config { 263 u32 socket_num_per_hive; 264 u32 aid_num_per_socket; 265 u32 xcd_num_per_aid; 266 }; 267 268 struct ras_mp1_config { 269 const struct ras_mp1_sys_func *mp1_sys_fn; 270 }; 271 272 struct ras_nbio_config { 273 const struct ras_nbio_sys_func *nbio_sys_fn; 274 }; 275 276 struct ras_psp_config { 277 const struct ras_psp_sys_func *psp_sys_fn; 278 }; 279 280 struct ras_umc_config { 281 uint32_t umc_vram_type; 282 uint32_t num_umc; 283 }; 284 285 struct ras_eeprom_config { 286 const struct ras_eeprom_sys_func *eeprom_sys_fn; 287 int eeprom_record_threshold_config; 288 uint32_t eeprom_record_threshold_count; 289 void *eeprom_i2c_adapter; 290 u32 eeprom_i2c_addr; 291 u32 eeprom_i2c_port; 292 u16 max_i2c_read_len; 293 u16 max_i2c_write_len; 294 }; 295 296 struct ras_core_config { 297 u32 aca_ip_version; 298 u32 umc_ip_version; 299 u32 mp1_ip_version; 300 u32 gfx_ip_version; 301 u32 nbio_ip_version; 302 u32 psp_ip_version; 303 304 bool poison_supported; 305 bool ras_eeprom_supported; 306 uint ras_debug_mask; 307 const struct ras_sys_func *sys_fn; 308 309 struct ras_aca_config aca_cfg; 310 struct ras_mp1_config mp1_cfg; 311 struct ras_nbio_config nbio_cfg; 312 struct ras_psp_config psp_cfg; 313 struct ras_eeprom_config eeprom_cfg; 314 struct ras_umc_config umc_cfg; 315 }; 316 317 struct ras_core_context { 318 void *dev; 319 struct ras_core_config *config; 320 u32 socket_num_per_hive; 321 u32 aid_num_per_socket; 322 u32 xcd_num_per_aid; 323 int max_ue_banks_per_query; 324 int max_ce_banks_per_query; 325 struct ras_aca ras_aca; 326 327 bool ras_eeprom_supported; 328 struct ras_eeprom_control ras_eeprom; 329 struct ras_fw_eeprom_control ras_fw_eeprom; 330 331 struct ras_psp ras_psp; 332 struct ras_umc ras_umc; 333 struct ras_nbio ras_nbio; 334 struct ras_gfx ras_gfx; 335 struct ras_mp1 ras_mp1; 336 struct ras_process ras_proc; 337 struct ras_log_ring ras_log_ring; 338 339 const struct ras_sys_func *sys_fn; 340 341 /* is poison mode supported */ 342 bool poison_supported; 343 344 bool is_rma; 345 bool is_initialized; 346 347 struct kfifo de_seqno_fifo; 348 struct kfifo consumption_seqno_fifo; 349 spinlock_t seqno_lock; 350 351 bool ras_core_enabled; 352 353 u64 ras_fw_features; 354 }; 355 356 struct ras_core_context *ras_core_create(struct ras_core_config *init_config); 357 void ras_core_destroy(struct ras_core_context *ras_core); 358 int ras_core_sw_init(struct ras_core_context *ras_core); 359 int ras_core_sw_fini(struct ras_core_context *ras_core); 360 int ras_core_hw_init(struct ras_core_context *ras_core); 361 int ras_core_hw_fini(struct ras_core_context *ras_core); 362 bool ras_core_is_ready(struct ras_core_context *ras_core); 363 uint64_t ras_core_gen_seqno(struct ras_core_context *ras_core, 364 enum ras_seqno_type seqno_type); 365 uint64_t ras_core_get_seqno(struct ras_core_context *ras_core, 366 enum ras_seqno_type seqno_type, bool pop); 367 368 int ras_core_put_seqno(struct ras_core_context *ras_core, 369 enum ras_seqno_type seqno_type, uint64_t seqno); 370 371 int ras_core_update_ecc_info(struct ras_core_context *ras_core); 372 int ras_core_query_block_ecc_data(struct ras_core_context *ras_core, 373 enum ras_block_id block, struct ras_ecc_count *ecc_count); 374 375 bool ras_core_gpu_in_reset(struct ras_core_context *ras_core); 376 bool ras_core_gpu_is_rma(struct ras_core_context *ras_core); 377 bool ras_core_gpu_is_vf(struct ras_core_context *ras_core); 378 bool ras_core_gpu_device_lost(struct ras_core_context *ras_core); 379 bool ras_core_handle_nbio_irq(struct ras_core_context *ras_core, void *data); 380 int ras_core_handle_fatal_error(struct ras_core_context *ras_core); 381 382 uint32_t ras_core_get_curr_nps_mode(struct ras_core_context *ras_core); 383 const char *ras_core_get_ras_block_name(enum ras_block_id block_id); 384 int ras_core_convert_timestamp_to_time(struct ras_core_context *ras_core, 385 uint64_t timestamp, struct ras_time *tm); 386 387 int ras_core_set_status(struct ras_core_context *ras_core, bool enable); 388 bool ras_core_is_enabled(struct ras_core_context *ras_core); 389 uint64_t ras_core_get_utc_second_timestamp(struct ras_core_context *ras_core); 390 int ras_core_translate_soc_pa_and_bank(struct ras_core_context *ras_core, 391 uint64_t *soc_pa, struct umc_bank_addr *bank_addr, bool bank_to_pa); 392 bool ras_core_ras_interrupt_detected(struct ras_core_context *ras_core); 393 int ras_core_get_gpu_mem(struct ras_core_context *ras_core, 394 enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem); 395 int ras_core_put_gpu_mem(struct ras_core_context *ras_core, 396 enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem); 397 bool ras_core_check_safety_watermark(struct ras_core_context *ras_core); 398 int ras_core_down_trylock_gpu_reset_lock(struct ras_core_context *ras_core); 399 void ras_core_down_gpu_reset_lock(struct ras_core_context *ras_core); 400 void ras_core_up_gpu_reset_lock(struct ras_core_context *ras_core); 401 int ras_core_event_notify(struct ras_core_context *ras_core, 402 enum ras_notify_event event_id, void *data); 403 int ras_core_get_device_system_info(struct ras_core_context *ras_core, 404 struct device_system_info *dev_info); 405 int ras_core_convert_soc_pa_to_cur_nps_pages(struct ras_core_context *ras_core, 406 uint64_t soc_pa, uint64_t *page_pfn, uint32_t max_pages); 407 int ras_core_check_address_sanity(struct ras_core_context *ras_core, uint64_t addr); 408 409 int ras_core_set_debug_mode(struct ras_core_context *ras_core, bool enable); 410 bool ras_core_is_ce_log_disabled(struct ras_core_context *ras_core); 411 #endif 412