1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 #ifndef __EEPROM_FW_H__ 25 #define __EEPROM_FW_H__ 26 27 struct ras_fw_eeprom_control { 28 uint32_t version; 29 /* record threshold */ 30 int record_threshold_config; 31 uint32_t record_threshold_count; 32 bool update_channel_flag; 33 34 /* Number of records in the table. 35 */ 36 u32 ras_num_recs; 37 38 /* Maximum possible number of records 39 * we could store, i.e. the maximum capacity 40 * of the table. 41 */ 42 u32 ras_max_record_count; 43 44 /* Protect table access via this mutex. 45 */ 46 struct mutex ras_tbl_mutex; 47 48 /* Record channel info which occurred bad pages 49 */ 50 u32 bad_channel_bitmap; 51 }; 52 53 void ras_fw_init_feature_flags(struct ras_core_context *ras_core); 54 bool ras_fw_eeprom_supported(struct ras_core_context *ras_core); 55 int ras_fw_get_table_version(struct ras_core_context *ras_core, 56 uint32_t *table_version); 57 int ras_fw_get_badpage_count(struct ras_core_context *ras_core, 58 uint32_t *count, uint32_t timeout); 59 int ras_fw_get_badpage_mca_addr(struct ras_core_context *ras_core, 60 uint16_t index, uint64_t *mca_addr); 61 int ras_fw_set_timestamp(struct ras_core_context *ras_core, 62 uint64_t timestamp); 63 int ras_fw_get_timestamp(struct ras_core_context *ras_core, 64 uint16_t index, uint64_t *timestamp); 65 int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core, 66 uint16_t index, uint64_t *ipid); 67 int ras_fw_erase_ras_table(struct ras_core_context *ras_core, 68 uint32_t *result); 69 int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core); 70 bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core); 71 int ras_fw_eeprom_append(struct ras_core_context *ras_core, 72 struct eeprom_umc_record *record, const u32 num); 73 int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core, 74 struct eeprom_umc_record *record_umc, 75 struct ras_bank_ecc *ras_ecc, 76 u32 rec_idx, const u32 num); 77 uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core); 78 int ras_fw_eeprom_update_record(struct ras_core_context *ras_core, 79 struct ras_bank_ecc *ras_ecc); 80 int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core); 81 int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core); 82 int ras_fw_eeprom_check_storage_status(struct ras_core_context *ras_core); 83 enum ras_gpu_health_status 84 ras_fw_eeprom_check_gpu_status(struct ras_core_context *ras_core); 85 void ras_fw_eeprom_sync_info(struct ras_core_context *ras_core); 86 87 #endif 88