1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __EEPROM_H__ 26 #define __EEPROM_H__ 27 #include "ras_sys.h" 28 29 #define RAS_TABLE_VER_V1 0x00010000 30 #define RAS_TABLE_VER_V2_1 0x00021000 31 #define RAS_TABLE_VER_V3 0x00030000 32 33 #define NONSTOP_OVER_THRESHOLD -2 34 #define WARN_NONSTOP_OVER_THRESHOLD -1 35 #define DISABLE_RETIRE_PAGE 0 36 37 /* 38 * Bad address pfn : eeprom_umc_record.retired_row_pfn[39:0], 39 * nps mode: eeprom_umc_record.retired_row_pfn[46:40] 40 */ 41 #define EEPROM_RECORD_UMC_ADDR_MASK 0xFFFFFFFFFFULL 42 #define EEPROM_RECORD_UMC_NPS_MASK 0x7F0000000000ULL 43 #define EEPROM_RECORD_UMC_NPS_SHIFT 40 44 45 #define EEPROM_RECORD_UMC_NPS_MODE(RECORD) \ 46 (((RECORD)->retired_row_pfn & EEPROM_RECORD_UMC_NPS_MASK) >> \ 47 EEPROM_RECORD_UMC_NPS_SHIFT) 48 49 #define EEPROM_RECORD_UMC_ADDR_PFN(RECORD) \ 50 ((RECORD)->retired_row_pfn & EEPROM_RECORD_UMC_ADDR_MASK) 51 52 #define EEPROM_RECORD_SETUP_UMC_ADDR_AND_NPS(RECORD, ADDR, NPS) \ 53 do { \ 54 uint64_t tmp = (NPS); \ 55 tmp = ((tmp << EEPROM_RECORD_UMC_NPS_SHIFT) & EEPROM_RECORD_UMC_NPS_MASK); \ 56 tmp |= (ADDR) & EEPROM_RECORD_UMC_ADDR_MASK; \ 57 (RECORD)->retired_row_pfn = tmp; \ 58 } while (0) 59 60 enum ras_eeprom_err_type { 61 RAS_EEPROM_ERR_NA, 62 RAS_EEPROM_ERR_RECOVERABLE, 63 RAS_EEPROM_ERR_NON_RECOVERABLE, 64 RAS_EEPROM_ERR_COUNT, 65 }; 66 67 struct ras_eeprom_table_header { 68 uint32_t header; 69 uint32_t version; 70 uint32_t first_rec_offset; 71 uint32_t tbl_size; 72 uint32_t checksum; 73 } __packed; 74 75 struct ras_eeprom_table_ras_info { 76 u8 rma_status; 77 u8 health_percent; 78 u16 ecc_page_threshold; 79 u32 padding[64 - 1]; 80 } __packed; 81 82 struct ras_eeprom_control { 83 struct ras_eeprom_table_header tbl_hdr; 84 struct ras_eeprom_table_ras_info tbl_rai; 85 86 /* record threshold */ 87 int record_threshold_config; 88 uint32_t record_threshold_count; 89 bool update_channel_flag; 90 91 const struct ras_eeprom_sys_func *sys_func; 92 void *i2c_adapter; 93 u32 i2c_port; 94 u16 max_read_len; 95 u16 max_write_len; 96 97 /* Base I2C EEPPROM 19-bit memory address, 98 * where the table is located. For more information, 99 * see top of amdgpu_eeprom.c. 100 */ 101 u32 i2c_address; 102 103 /* The byte offset off of @i2c_address 104 * where the table header is found, 105 * and where the records start--always 106 * right after the header. 107 */ 108 u32 ras_header_offset; 109 u32 ras_info_offset; 110 u32 ras_record_offset; 111 112 /* Number of records in the table. 113 */ 114 u32 ras_num_recs; 115 116 /* First record index to read, 0-based. 117 * Range is [0, num_recs-1]. This is 118 * an absolute index, starting right after 119 * the table header. 120 */ 121 u32 ras_fri; 122 123 /* Maximum possible number of records 124 * we could store, i.e. the maximum capacity 125 * of the table. 126 */ 127 u32 ras_max_record_count; 128 129 /* Protect table access via this mutex. 130 */ 131 struct mutex ras_tbl_mutex; 132 133 /* Record channel info which occurred bad pages 134 */ 135 u32 bad_channel_bitmap; 136 }; 137 138 /* 139 * Represents single table record. Packed to be easily serialized into byte 140 * stream. 141 */ 142 struct eeprom_umc_record { 143 144 union { 145 uint64_t address; 146 uint64_t offset; 147 }; 148 149 uint64_t retired_row_pfn; 150 uint64_t ts; 151 152 enum ras_eeprom_err_type err_type; 153 154 union { 155 unsigned char bank; 156 unsigned char cu; 157 }; 158 159 unsigned char mem_channel; 160 unsigned char mcumc_id; 161 162 /* The following variables will not be saved to eeprom. 163 */ 164 uint64_t cur_nps_retired_row_pfn; 165 uint32_t cur_nps_bank; 166 uint32_t cur_nps; 167 }; 168 169 struct ras_core_context; 170 int ras_eeprom_hw_init(struct ras_core_context *ras_core); 171 int ras_eeprom_hw_fini(struct ras_core_context *ras_core); 172 173 int ras_eeprom_reset_table(struct ras_core_context *ras_core); 174 175 bool ras_eeprom_check_safety_watermark(struct ras_core_context *ras_core); 176 177 int ras_eeprom_read(struct ras_core_context *ras_core, 178 struct eeprom_umc_record *records, const u32 num); 179 180 int ras_eeprom_append(struct ras_core_context *ras_core, 181 struct eeprom_umc_record *records, const u32 num); 182 183 uint32_t ras_eeprom_max_record_count(struct ras_core_context *ras_core); 184 uint32_t ras_eeprom_get_record_count(struct ras_core_context *ras_core); 185 void ras_eeprom_sync_info(struct ras_core_context *ras_core); 186 187 int ras_eeprom_check_storage_status(struct ras_core_context *ras_core); 188 enum ras_gpu_health_status 189 ras_eeprom_check_gpu_status(struct ras_core_context *ras_core); 190 #endif 191