1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "eeprom.h" 26 #include "ras.h" 27 28 /* These are memory addresses as would be seen by one or more EEPROM 29 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 30 * set of EEPROM devices. They form a continuous memory space. 31 * 32 * The I2C device address includes the device type identifier, 1010b, 33 * which is a reserved value and indicates that this is an I2C EEPROM 34 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 35 * address, namely bits 18, 17, and 16. This makes up the 7 bit 36 * address sent on the I2C bus with bit 0 being the direction bit, 37 * which is not represented here, and sent by the hardware directly. 38 * 39 * For instance, 40 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 41 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 42 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 43 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 44 * address memory in a device or a device on the I2C bus, depending on 45 * the status of pins 1-3. 46 * 47 * The RAS table lives either at address 0 or address 40000h of EEPROM. 48 */ 49 #define EEPROM_I2C_MADDR_0 0x0 50 #define EEPROM_I2C_MADDR_4 0x40000 51 52 #define EEPROM_PAGE_BITS 8 53 #define EEPROM_PAGE_SIZE (1U << EEPROM_PAGE_BITS) 54 #define EEPROM_PAGE_MASK (EEPROM_PAGE_SIZE - 1) 55 56 #define EEPROM_OFFSET_SIZE 2 57 #define MAKE_I2C_ADDR(_aa) ((0xA << 3) | (((_aa) >> 16) & 0xF)) 58 59 /* 60 * The 2 macros bellow represent the actual size in bytes that 61 * those entities occupy in the EEPROM memory. 62 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_umc_record) which 63 * uses uint64 to store 6b fields such as retired_page. 64 */ 65 #define RAS_TABLE_HEADER_SIZE 20 66 #define RAS_TABLE_RECORD_SIZE 24 67 68 /* Table hdr is 'AMDR' */ 69 #define RAS_TABLE_HDR_VAL 0x414d4452 70 71 /* Bad GPU tag ‘BADG’ */ 72 #define RAS_TABLE_HDR_BAD 0x42414447 73 74 /* 75 * EEPROM Table structure v1 76 * --------------------------------- 77 * | | 78 * | EEPROM TABLE HEADER | 79 * | ( size 20 Bytes ) | 80 * | | 81 * --------------------------------- 82 * | | 83 * | BAD PAGE RECORD AREA | 84 * | | 85 * --------------------------------- 86 */ 87 88 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 89 #define RAS_TBL_SIZE_BYTES (256 * 1024) 90 #define RAS_TABLE_START 0 91 #define RAS_HDR_START RAS_TABLE_START 92 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 93 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 94 / RAS_TABLE_RECORD_SIZE) 95 96 /* 97 * EEPROM Table structrue v2.1 98 * --------------------------------- 99 * | | 100 * | EEPROM TABLE HEADER | 101 * | ( size 20 Bytes ) | 102 * | | 103 * --------------------------------- 104 * | | 105 * | EEPROM TABLE RAS INFO | 106 * | (available info size 4 Bytes) | 107 * | ( reserved size 252 Bytes ) | 108 * | | 109 * --------------------------------- 110 * | | 111 * | BAD PAGE RECORD AREA | 112 * | | 113 * --------------------------------- 114 */ 115 116 /* EEPROM Table V2_1 */ 117 #define RAS_TABLE_V2_1_INFO_SIZE 256 118 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 119 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 120 RAS_TABLE_V2_1_INFO_SIZE) 121 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 122 RAS_TABLE_V2_1_INFO_SIZE) \ 123 / RAS_TABLE_RECORD_SIZE) 124 125 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 126 * offset off of RAS_TABLE_START. That is, this is something you can 127 * add to control->i2c_address, and then tell I2C layer to read 128 * from/write to there. _N is the so called absolute index, 129 * because it starts right after the table header. 130 */ 131 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 132 (_N) * RAS_TABLE_RECORD_SIZE) 133 134 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 135 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 136 137 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 138 * of "fri", return the absolute record index off of the end of 139 * the table header. 140 */ 141 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 142 (_C)->ras_max_record_count) 143 144 #define RAS_NUM_RECS(_tbl_hdr) \ 145 (((_tbl_hdr)->tbl_size < RAS_TABLE_HEADER_SIZE) ? 0u : \ 146 (((_tbl_hdr)->tbl_size - RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)) 147 148 #define RAS_NUM_RECS_V2_1(_tbl_hdr) \ 149 (((_tbl_hdr)->tbl_size < RAS_TABLE_HEADER_SIZE + \ 150 RAS_TABLE_V2_1_INFO_SIZE) ? 0u : \ 151 (((_tbl_hdr)->tbl_size - RAS_TABLE_HEADER_SIZE - \ 152 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE)) 153 154 #define to_ras_core_context(x) (container_of(x, struct ras_core_context, ras_eeprom)) 155 156 static bool __is_ras_eeprom_supported(struct ras_core_context *ras_core) 157 { 158 return ras_core->ras_eeprom_supported; 159 } 160 161 static bool __get_eeprom_i2c_addr(struct ras_core_context *ras_core, 162 struct ras_eeprom_control *control) 163 { 164 int ret = -EINVAL; 165 166 if (control->sys_func && 167 control->sys_func->update_eeprom_i2c_config) 168 ret = control->sys_func->update_eeprom_i2c_config(ras_core); 169 else 170 RAS_DEV_WARN(ras_core->dev, 171 "No eeprom i2c system config!\n"); 172 173 return !ret ? true : false; 174 } 175 176 static int __ras_eeprom_xfer(struct ras_core_context *ras_core, u32 eeprom_addr, 177 u8 *eeprom_buf, u32 buf_size, bool read) 178 { 179 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 180 int ret; 181 182 if (control->sys_func && control->sys_func->eeprom_i2c_xfer) { 183 ret = control->sys_func->eeprom_i2c_xfer(ras_core, 184 eeprom_addr, eeprom_buf, buf_size, read); 185 186 if ((ret > 0) && !read) { 187 /* According to EEPROM specs the length of the 188 * self-writing cycle, tWR (tW), is 10 ms. 189 * 190 * TODO: Use polling on ACK, aka Acknowledge 191 * Polling, to minimize waiting for the 192 * internal write cycle to complete, as it is 193 * usually smaller than tWR (tW). 194 */ 195 msleep(10); 196 } 197 198 return ret; 199 } 200 201 RAS_DEV_ERR(ras_core->dev, "Error: No eeprom i2c system xfer function!\n"); 202 return -EINVAL; 203 } 204 205 static int __eeprom_xfer(struct ras_core_context *ras_core, u32 eeprom_addr, 206 u8 *eeprom_buf, u32 buf_size, bool read) 207 { 208 u16 limit; 209 u16 ps; /* Partial size */ 210 int res = 0, r; 211 212 if (read) 213 limit = ras_core->ras_eeprom.max_read_len; 214 else 215 limit = ras_core->ras_eeprom.max_write_len; 216 217 if (limit && (limit <= EEPROM_OFFSET_SIZE)) { 218 RAS_DEV_ERR(ras_core->dev, 219 "maddr:0x%04X size:0x%02X:quirk max_%s_len must be > %d", 220 eeprom_addr, buf_size, 221 read ? "read" : "write", EEPROM_OFFSET_SIZE); 222 return -EINVAL; 223 } 224 225 ras_core_down_gpu_reset_lock(ras_core); 226 227 if (limit == 0) { 228 res = __ras_eeprom_xfer(ras_core, eeprom_addr, 229 eeprom_buf, buf_size, read); 230 } else { 231 /* The "limit" includes all data bytes sent/received, 232 * which would include the EEPROM_OFFSET_SIZE bytes. 233 * Account for them here. 234 */ 235 limit -= EEPROM_OFFSET_SIZE; 236 for ( ; buf_size > 0; 237 buf_size -= ps, eeprom_addr += ps, eeprom_buf += ps) { 238 ps = (buf_size < limit) ? buf_size : limit; 239 240 r = __ras_eeprom_xfer(ras_core, eeprom_addr, 241 eeprom_buf, ps, read); 242 if (r < 0) 243 break; 244 245 res += r; 246 } 247 } 248 249 ras_core_up_gpu_reset_lock(ras_core); 250 251 return res; 252 } 253 254 static int __eeprom_read(struct ras_core_context *ras_core, 255 u32 eeprom_addr, u8 *eeprom_buf, u32 bytes) 256 { 257 return __eeprom_xfer(ras_core, eeprom_addr, 258 eeprom_buf, bytes, true); 259 } 260 261 static int __eeprom_write(struct ras_core_context *ras_core, 262 u32 eeprom_addr, u8 *eeprom_buf, u32 bytes) 263 { 264 return __eeprom_xfer(ras_core, eeprom_addr, 265 eeprom_buf, bytes, false); 266 } 267 268 static void 269 __encode_table_header_to_buf(struct ras_eeprom_table_header *hdr, 270 unsigned char *buf) 271 { 272 u32 *pp = (uint32_t *)buf; 273 274 pp[0] = cpu_to_le32(hdr->header); 275 pp[1] = cpu_to_le32(hdr->version); 276 pp[2] = cpu_to_le32(hdr->first_rec_offset); 277 pp[3] = cpu_to_le32(hdr->tbl_size); 278 pp[4] = cpu_to_le32(hdr->checksum); 279 } 280 281 static void 282 __decode_table_header_from_buf(struct ras_eeprom_table_header *hdr, 283 unsigned char *buf) 284 { 285 u32 *pp = (uint32_t *)buf; 286 287 hdr->header = le32_to_cpu(pp[0]); 288 hdr->version = le32_to_cpu(pp[1]); 289 hdr->first_rec_offset = le32_to_cpu(pp[2]); 290 hdr->tbl_size = le32_to_cpu(pp[3]); 291 hdr->checksum = le32_to_cpu(pp[4]); 292 } 293 294 static int __write_table_header(struct ras_eeprom_control *control) 295 { 296 u8 buf[RAS_TABLE_HEADER_SIZE]; 297 struct ras_core_context *ras_core = to_ras_core_context(control); 298 int res; 299 300 memset(buf, 0, sizeof(buf)); 301 __encode_table_header_to_buf(&control->tbl_hdr, buf); 302 303 /* i2c may be unstable in gpu reset */ 304 res = __eeprom_write(ras_core, 305 control->i2c_address + 306 control->ras_header_offset, 307 buf, RAS_TABLE_HEADER_SIZE); 308 309 if (res < 0) { 310 RAS_DEV_ERR(ras_core->dev, 311 "Failed to write EEPROM table header:%d\n", res); 312 } else if (res < RAS_TABLE_HEADER_SIZE) { 313 RAS_DEV_ERR(ras_core->dev, 314 "Short write:%d out of %d\n", res, RAS_TABLE_HEADER_SIZE); 315 res = -EIO; 316 } else { 317 res = 0; 318 } 319 320 return res; 321 } 322 323 static void 324 __encode_table_ras_info_to_buf(struct ras_eeprom_table_ras_info *rai, 325 unsigned char *buf) 326 { 327 u32 *pp = (uint32_t *)buf; 328 u32 tmp; 329 330 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 331 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 332 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 333 pp[0] = cpu_to_le32(tmp); 334 } 335 336 static void 337 __decode_table_ras_info_from_buf(struct ras_eeprom_table_ras_info *rai, 338 unsigned char *buf) 339 { 340 u32 *pp = (uint32_t *)buf; 341 u32 tmp; 342 343 tmp = le32_to_cpu(pp[0]); 344 rai->rma_status = tmp & 0xFF; 345 rai->health_percent = (tmp >> 8) & 0xFF; 346 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 347 } 348 349 static int __write_table_ras_info(struct ras_eeprom_control *control) 350 { 351 struct ras_core_context *ras_core = to_ras_core_context(control); 352 u8 *buf; 353 int res; 354 355 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 356 if (!buf) { 357 RAS_DEV_ERR(ras_core->dev, 358 "Failed to alloc buf to write table ras info\n"); 359 return -ENOMEM; 360 } 361 362 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 363 364 /* i2c may be unstable in gpu reset */ 365 res = __eeprom_write(ras_core, 366 control->i2c_address + 367 control->ras_info_offset, 368 buf, RAS_TABLE_V2_1_INFO_SIZE); 369 370 if (res < 0) { 371 RAS_DEV_ERR(ras_core->dev, 372 "Failed to write EEPROM table ras info:%d\n", res); 373 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 374 RAS_DEV_ERR(ras_core->dev, 375 "Short write:%d out of %d\n", res, RAS_TABLE_V2_1_INFO_SIZE); 376 res = -EIO; 377 } else { 378 res = 0; 379 } 380 381 kfree(buf); 382 383 return res; 384 } 385 386 static u8 __calc_hdr_byte_sum(const struct ras_eeprom_control *control) 387 { 388 int ii; 389 u8 *pp, csum; 390 u32 sz; 391 392 /* Header checksum, skip checksum field in the calculation */ 393 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 394 pp = (u8 *) &control->tbl_hdr; 395 csum = 0; 396 for (ii = 0; ii < sz; ii++, pp++) 397 csum += *pp; 398 399 return csum; 400 } 401 402 static u8 __calc_ras_info_byte_sum(const struct ras_eeprom_control *control) 403 { 404 int ii; 405 u8 *pp, csum; 406 u32 sz; 407 408 sz = sizeof(control->tbl_rai); 409 pp = (u8 *) &control->tbl_rai; 410 csum = 0; 411 for (ii = 0; ii < sz; ii++, pp++) 412 csum += *pp; 413 414 return csum; 415 } 416 417 static int ras_eeprom_correct_header_tag( 418 struct ras_eeprom_control *control, 419 uint32_t header) 420 { 421 struct ras_eeprom_table_header *hdr = &control->tbl_hdr; 422 u8 *hh; 423 int res; 424 u8 csum; 425 426 csum = -hdr->checksum; 427 428 hh = (void *) &hdr->header; 429 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 430 hh = (void *) &header; 431 csum += hh[0] + hh[1] + hh[2] + hh[3]; 432 csum = -csum; 433 mutex_lock(&control->ras_tbl_mutex); 434 hdr->header = header; 435 hdr->checksum = csum; 436 res = __write_table_header(control); 437 mutex_unlock(&control->ras_tbl_mutex); 438 439 return res; 440 } 441 442 static void ras_set_eeprom_table_version(struct ras_eeprom_control *control) 443 { 444 struct ras_eeprom_table_header *hdr = &control->tbl_hdr; 445 446 hdr->version = RAS_TABLE_VER_V3; 447 } 448 449 int ras_eeprom_reset_table(struct ras_core_context *ras_core) 450 { 451 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 452 struct ras_eeprom_table_header *hdr = &control->tbl_hdr; 453 struct ras_eeprom_table_ras_info *rai = &control->tbl_rai; 454 u8 csum; 455 int res; 456 457 mutex_lock(&control->ras_tbl_mutex); 458 459 hdr->header = RAS_TABLE_HDR_VAL; 460 ras_set_eeprom_table_version(control); 461 462 if (hdr->version >= RAS_TABLE_VER_V2_1) { 463 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 464 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 465 RAS_TABLE_V2_1_INFO_SIZE; 466 rai->rma_status = RAS_GPU_HEALTH_USABLE; 467 /** 468 * GPU health represented as a percentage. 469 * 0 means worst health, 100 means fully health. 470 */ 471 rai->health_percent = 100; 472 /* ecc_page_threshold = 0 means disable bad page retirement */ 473 rai->ecc_page_threshold = control->record_threshold_count; 474 } else { 475 hdr->first_rec_offset = RAS_RECORD_START; 476 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 477 } 478 479 csum = __calc_hdr_byte_sum(control); 480 if (hdr->version >= RAS_TABLE_VER_V2_1) 481 csum += __calc_ras_info_byte_sum(control); 482 csum = -csum; 483 hdr->checksum = csum; 484 res = __write_table_header(control); 485 if (!res && hdr->version > RAS_TABLE_VER_V1) 486 res = __write_table_ras_info(control); 487 488 control->ras_num_recs = 0; 489 control->ras_fri = 0; 490 491 control->bad_channel_bitmap = 0; 492 ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, 493 &control->ras_num_recs); 494 ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, 495 &control->bad_channel_bitmap); 496 control->update_channel_flag = false; 497 498 mutex_unlock(&control->ras_tbl_mutex); 499 500 return res; 501 } 502 503 static void 504 __encode_table_record_to_buf(struct ras_eeprom_control *control, 505 struct eeprom_umc_record *record, 506 unsigned char *buf) 507 { 508 __le64 tmp = 0; 509 int i = 0; 510 511 /* Next are all record fields according to EEPROM page spec in LE foramt */ 512 buf[i++] = record->err_type; 513 514 buf[i++] = record->bank; 515 516 tmp = cpu_to_le64(record->ts); 517 memcpy(buf + i, &tmp, 8); 518 i += 8; 519 520 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 521 memcpy(buf + i, &tmp, 6); 522 i += 6; 523 524 buf[i++] = record->mem_channel; 525 buf[i++] = record->mcumc_id; 526 527 tmp = cpu_to_le64((record->retired_row_pfn & 0xffffffffffff)); 528 memcpy(buf + i, &tmp, 6); 529 } 530 531 static void 532 __decode_table_record_from_buf(struct ras_eeprom_control *control, 533 struct eeprom_umc_record *record, 534 unsigned char *buf) 535 { 536 __le64 tmp = 0; 537 int i = 0; 538 539 /* Next are all record fields according to EEPROM page spec in LE foramt */ 540 record->err_type = buf[i++]; 541 542 record->bank = buf[i++]; 543 544 memcpy(&tmp, buf + i, 8); 545 record->ts = le64_to_cpu(tmp); 546 i += 8; 547 548 memcpy(&tmp, buf + i, 6); 549 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 550 i += 6; 551 552 record->mem_channel = buf[i++]; 553 record->mcumc_id = buf[i++]; 554 555 memcpy(&tmp, buf + i, 6); 556 record->retired_row_pfn = (le64_to_cpu(tmp) & 0xffffffffffff); 557 } 558 559 bool ras_eeprom_check_safety_watermark(struct ras_core_context *ras_core) 560 { 561 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 562 bool ret = false; 563 int bad_page_count; 564 565 if (!__is_ras_eeprom_supported(ras_core) || 566 !control->record_threshold_config) 567 return false; 568 569 bad_page_count = ras_umc_get_badpage_count(ras_core); 570 if (control->tbl_hdr.header == RAS_TABLE_HDR_BAD) { 571 if (bad_page_count > control->record_threshold_count) 572 RAS_DEV_WARN(ras_core->dev, "RAS records:%d exceed threshold:%d", 573 bad_page_count, control->record_threshold_count); 574 575 if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) || 576 (control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) { 577 RAS_DEV_WARN(ras_core->dev, 578 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n"); 579 ret = false; 580 } else { 581 ras_core->is_rma = true; 582 RAS_DEV_WARN(ras_core->dev, 583 "Please consider adjusting the customized threshold.\n"); 584 ret = true; 585 } 586 } 587 588 return ret; 589 } 590 591 /** 592 * __ras_eeprom_write -- write indexed from buffer to EEPROM 593 * @control: pointer to control structure 594 * @buf: pointer to buffer containing data to write 595 * @fri: start writing at this index 596 * @num: number of records to write 597 * 598 * The caller must hold the table mutex in @control. 599 * Return 0 on success, -errno otherwise. 600 */ 601 static int __ras_eeprom_write(struct ras_eeprom_control *control, 602 u8 *buf, const u32 fri, const u32 num) 603 { 604 struct ras_core_context *ras_core = to_ras_core_context(control); 605 u32 buf_size; 606 int res; 607 608 /* i2c may be unstable in gpu reset */ 609 buf_size = num * RAS_TABLE_RECORD_SIZE; 610 res = __eeprom_write(ras_core, 611 control->i2c_address + RAS_INDEX_TO_OFFSET(control, fri), 612 buf, buf_size); 613 if (res < 0) { 614 RAS_DEV_ERR(ras_core->dev, 615 "Writing %d EEPROM table records error:%d\n", num, res); 616 } else if (res < buf_size) { 617 /* Short write, return error.*/ 618 RAS_DEV_ERR(ras_core->dev, 619 "Wrote %d records out of %d\n", 620 (res/RAS_TABLE_RECORD_SIZE), num); 621 res = -EIO; 622 } else { 623 res = 0; 624 } 625 626 return res; 627 } 628 629 static int ras_eeprom_append_table(struct ras_eeprom_control *control, 630 struct eeprom_umc_record *record, 631 const u32 num) 632 { 633 u32 a, b, i; 634 u8 *buf, *pp; 635 int res; 636 637 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 638 if (!buf) 639 return -ENOMEM; 640 641 /* Encode all of them in one go. 642 */ 643 pp = buf; 644 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 645 __encode_table_record_to_buf(control, &record[i], pp); 646 647 /* update bad channel bitmap */ 648 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 649 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 650 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 651 control->update_channel_flag = true; 652 } 653 } 654 655 /* a, first record index to write into. 656 * b, last record index to write into. 657 * a = first index to read (fri) + number of records in the table, 658 * b = a + @num - 1. 659 * Let N = control->ras_max_num_record_count, then we have, 660 * case 0: 0 <= a <= b < N, 661 * just append @num records starting at a; 662 * case 1: 0 <= a < N <= b, 663 * append (N - a) records starting at a, and 664 * append the remainder, b % N + 1, starting at 0. 665 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 666 * case 2a: 0 <= a <= b < N 667 * append num records starting at a; and fix fri if b overwrote it, 668 * and since a <= b, if b overwrote it then a must've also, 669 * and if b didn't overwrite it, then a didn't also. 670 * case 2b: 0 <= b < a < N 671 * write num records starting at a, which wraps around 0=N 672 * and overwrite fri unconditionally. Now from case 2a, 673 * this means that b eclipsed fri to overwrite it and wrap 674 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 675 * set fri = b + 1 (mod N). 676 * Now, since fri is updated in every case, except the trivial case 0, 677 * the number of records present in the table after writing, is, 678 * num_recs - 1 = b - fri (mod N), and we take the positive value, 679 * by adding an arbitrary multiple of N before taking the modulo N 680 * as shown below. 681 */ 682 a = control->ras_fri + control->ras_num_recs; 683 b = a + num - 1; 684 if (b < control->ras_max_record_count) { 685 res = __ras_eeprom_write(control, buf, a, num); 686 } else if (a < control->ras_max_record_count) { 687 u32 g0, g1; 688 689 g0 = control->ras_max_record_count - a; 690 g1 = b % control->ras_max_record_count + 1; 691 res = __ras_eeprom_write(control, buf, a, g0); 692 if (res) 693 goto Out; 694 res = __ras_eeprom_write(control, 695 buf + g0 * RAS_TABLE_RECORD_SIZE, 696 0, g1); 697 if (res) 698 goto Out; 699 if (g1 > control->ras_fri) 700 control->ras_fri = g1 % control->ras_max_record_count; 701 } else { 702 a %= control->ras_max_record_count; 703 b %= control->ras_max_record_count; 704 705 if (a <= b) { 706 /* Note that, b - a + 1 = num. */ 707 res = __ras_eeprom_write(control, buf, a, num); 708 if (res) 709 goto Out; 710 if (b >= control->ras_fri) 711 control->ras_fri = (b + 1) % control->ras_max_record_count; 712 } else { 713 u32 g0, g1; 714 715 /* b < a, which means, we write from 716 * a to the end of the table, and from 717 * the start of the table to b. 718 */ 719 g0 = control->ras_max_record_count - a; 720 g1 = b + 1; 721 res = __ras_eeprom_write(control, buf, a, g0); 722 if (res) 723 goto Out; 724 res = __ras_eeprom_write(control, 725 buf + g0 * RAS_TABLE_RECORD_SIZE, 0, g1); 726 if (res) 727 goto Out; 728 control->ras_fri = g1 % control->ras_max_record_count; 729 } 730 } 731 control->ras_num_recs = 1 + 732 (control->ras_max_record_count + b - control->ras_fri) 733 % control->ras_max_record_count; 734 Out: 735 kfree(buf); 736 return res; 737 } 738 739 static int ras_eeprom_update_header(struct ras_eeprom_control *control) 740 { 741 struct ras_core_context *ras_core = to_ras_core_context(control); 742 int threshold_config = control->record_threshold_config; 743 u8 *buf, *pp, csum; 744 u32 buf_size; 745 int bad_page_count; 746 int res; 747 748 bad_page_count = ras_umc_get_badpage_count(ras_core); 749 ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, 750 &bad_page_count); 751 752 /* Modify the header if it exceeds. 753 */ 754 if (threshold_config != 0 && 755 bad_page_count > control->record_threshold_count) { 756 RAS_DEV_WARN(ras_core->dev, 757 "Saved bad pages %d reaches threshold value %d\n", 758 bad_page_count, control->record_threshold_count); 759 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 760 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { 761 control->tbl_rai.rma_status = RAS_GPU_RETIRED__ECC_REACH_THRESHOLD; 762 control->tbl_rai.health_percent = 0; 763 } 764 765 if ((threshold_config != WARN_NONSTOP_OVER_THRESHOLD) && 766 (threshold_config != NONSTOP_OVER_THRESHOLD)) 767 ras_core->is_rma = true; 768 769 /* ignore the -ENOTSUPP return value */ 770 ras_core_event_notify(ras_core, RAS_EVENT_ID__DEVICE_RMA, NULL); 771 } 772 773 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 774 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 775 RAS_TABLE_V2_1_INFO_SIZE + 776 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 777 else 778 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 779 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 780 control->tbl_hdr.checksum = 0; 781 782 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 783 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 784 if (!buf) { 785 RAS_DEV_ERR(ras_core->dev, 786 "allocating memory for table of size %d bytes failed\n", 787 control->tbl_hdr.tbl_size); 788 res = -ENOMEM; 789 goto Out; 790 } 791 792 res = __eeprom_read(ras_core, 793 control->i2c_address + 794 control->ras_record_offset, 795 buf, buf_size); 796 if (res < 0) { 797 RAS_DEV_ERR(ras_core->dev, 798 "EEPROM failed reading records:%d\n", res); 799 goto Out; 800 } else if (res < buf_size) { 801 RAS_DEV_ERR(ras_core->dev, 802 "EEPROM read %d out of %d bytes\n", res, buf_size); 803 res = -EIO; 804 goto Out; 805 } 806 807 /** 808 * bad page records have been stored in eeprom, 809 * now calculate gpu health percent 810 */ 811 if (threshold_config != 0 && 812 control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 && 813 bad_page_count <= control->record_threshold_count) 814 control->tbl_rai.health_percent = ((control->record_threshold_count - 815 bad_page_count) * 100) / control->record_threshold_count; 816 817 /* Recalc the checksum. 818 */ 819 csum = 0; 820 for (pp = buf; pp < buf + buf_size; pp++) 821 csum += *pp; 822 823 csum += __calc_hdr_byte_sum(control); 824 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 825 csum += __calc_ras_info_byte_sum(control); 826 /* avoid sign extension when assigning to "checksum" */ 827 csum = -csum; 828 control->tbl_hdr.checksum = csum; 829 res = __write_table_header(control); 830 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 831 res = __write_table_ras_info(control); 832 Out: 833 kfree(buf); 834 return res; 835 } 836 837 /** 838 * ras_eeprom_append -- append records to the EEPROM RAS table 839 * @ras_core: pointer to ras core context 840 * @record: array of records to append 841 * @num: number of records in @record array 842 * 843 * Append @num records to the table, calculate the checksum and write 844 * the table back to EEPROM. The maximum number of records that 845 * can be appended is between 1 and control->ras_max_record_count, 846 * regardless of how many records are already stored in the table. 847 * 848 * Return 0 on success or if EEPROM is not supported, -errno on error. 849 */ 850 int ras_eeprom_append(struct ras_core_context *ras_core, 851 struct eeprom_umc_record *record, const u32 num) 852 { 853 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 854 int res; 855 856 if (!__is_ras_eeprom_supported(ras_core)) 857 return 0; 858 859 if (num == 0) { 860 RAS_DEV_ERR(ras_core->dev, "will not append 0 records\n"); 861 return -EINVAL; 862 } else if ((num + control->ras_num_recs) > control->ras_max_record_count) { 863 RAS_DEV_ERR(ras_core->dev, 864 "cannot append %d records than the size of table %d\n", 865 num, control->ras_max_record_count); 866 return -EINVAL; 867 } 868 869 mutex_lock(&control->ras_tbl_mutex); 870 res = ras_eeprom_append_table(control, record, num); 871 if (!res) 872 res = ras_eeprom_update_header(control); 873 874 mutex_unlock(&control->ras_tbl_mutex); 875 876 return res; 877 } 878 879 /** 880 * __ras_eeprom_read -- read indexed from EEPROM into buffer 881 * @control: pointer to control structure 882 * @buf: pointer to buffer to read into 883 * @fri: first record index, start reading at this index, absolute index 884 * @num: number of records to read 885 * 886 * The caller must hold the table mutex in @control. 887 * Return 0 on success, -errno otherwise. 888 */ 889 static int __ras_eeprom_read(struct ras_eeprom_control *control, 890 u8 *buf, const u32 fri, const u32 num) 891 { 892 struct ras_core_context *ras_core = to_ras_core_context(control); 893 u32 buf_size; 894 int res; 895 896 /* i2c may be unstable in gpu reset */ 897 buf_size = num * RAS_TABLE_RECORD_SIZE; 898 res = __eeprom_read(ras_core, 899 control->i2c_address + 900 RAS_INDEX_TO_OFFSET(control, fri), 901 buf, buf_size); 902 if (res < 0) { 903 RAS_DEV_ERR(ras_core->dev, 904 "Reading %d EEPROM table records error:%d\n", num, res); 905 } else if (res < buf_size) { 906 /* Short read, return error. 907 */ 908 RAS_DEV_ERR(ras_core->dev, 909 "Read %d records out of %d\n", 910 (res/RAS_TABLE_RECORD_SIZE), num); 911 res = -EIO; 912 } else { 913 res = 0; 914 } 915 916 return res; 917 } 918 919 int ras_eeprom_read(struct ras_core_context *ras_core, 920 struct eeprom_umc_record *record, const u32 num) 921 { 922 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 923 int i, res; 924 u8 *buf, *pp; 925 u32 g0, g1; 926 927 if (!__is_ras_eeprom_supported(ras_core)) 928 return 0; 929 930 if (num == 0) { 931 RAS_DEV_ERR(ras_core->dev, "will not read 0 records\n"); 932 return -EINVAL; 933 } else if (num > control->ras_num_recs) { 934 RAS_DEV_ERR(ras_core->dev, 935 "too many records to read:%d available:%d\n", 936 num, control->ras_num_recs); 937 return -EINVAL; 938 } 939 940 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 941 if (!buf) 942 return -ENOMEM; 943 944 /* Determine how many records to read, from the first record 945 * index, fri, to the end of the table, and from the beginning 946 * of the table, such that the total number of records is 947 * @num, and we handle wrap around when fri > 0 and 948 * fri + num > RAS_MAX_RECORD_COUNT. 949 * 950 * First we compute the index of the last element 951 * which would be fetched from each region, 952 * g0 is in [fri, fri + num - 1], and 953 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 954 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 955 * the last element to fetch, we set g0 to _the number_ 956 * of elements to fetch, @num, since we know that the last 957 * indexed to be fetched does not exceed the table. 958 * 959 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 960 * we set g0 to the number of elements to read 961 * until the end of the table, and g1 to the number of 962 * elements to read from the beginning of the table. 963 */ 964 g0 = control->ras_fri + num - 1; 965 g1 = g0 % control->ras_max_record_count; 966 if (g0 < control->ras_max_record_count) { 967 g0 = num; 968 g1 = 0; 969 } else { 970 g0 = control->ras_max_record_count - control->ras_fri; 971 g1 += 1; 972 } 973 974 mutex_lock(&control->ras_tbl_mutex); 975 res = __ras_eeprom_read(control, buf, control->ras_fri, g0); 976 if (res) 977 goto Out; 978 if (g1) { 979 res = __ras_eeprom_read(control, 980 buf + g0 * RAS_TABLE_RECORD_SIZE, 0, g1); 981 if (res) 982 goto Out; 983 } 984 985 res = 0; 986 987 /* Read up everything? Then transform. 988 */ 989 pp = buf; 990 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 991 __decode_table_record_from_buf(control, &record[i], pp); 992 993 /* update bad channel bitmap */ 994 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 995 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 996 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 997 control->update_channel_flag = true; 998 } 999 } 1000 Out: 1001 kfree(buf); 1002 mutex_unlock(&control->ras_tbl_mutex); 1003 1004 return res; 1005 } 1006 1007 uint32_t ras_eeprom_max_record_count(struct ras_core_context *ras_core) 1008 { 1009 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 1010 1011 /* get available eeprom table version first before eeprom table init */ 1012 ras_set_eeprom_table_version(control); 1013 1014 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1015 return RAS_MAX_RECORD_COUNT_V2_1; 1016 else 1017 return RAS_MAX_RECORD_COUNT; 1018 } 1019 1020 /** 1021 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1022 * @control: pointer to control structure 1023 * 1024 * Check the checksum of the stored in EEPROM RAS table. 1025 * 1026 * Return 0 if the checksum is correct, 1027 * positive if it is not correct, and 1028 * -errno on I/O error. 1029 */ 1030 static int __verify_ras_table_checksum(struct ras_eeprom_control *control) 1031 { 1032 struct ras_core_context *ras_core = to_ras_core_context(control); 1033 int buf_size, res; 1034 u8 csum, *buf, *pp; 1035 1036 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1037 buf_size = RAS_TABLE_HEADER_SIZE + 1038 RAS_TABLE_V2_1_INFO_SIZE + 1039 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1040 else 1041 buf_size = RAS_TABLE_HEADER_SIZE + 1042 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1043 1044 buf = kzalloc(buf_size, GFP_KERNEL); 1045 if (!buf) { 1046 RAS_DEV_ERR(ras_core->dev, 1047 "Out of memory checking RAS table checksum.\n"); 1048 return -ENOMEM; 1049 } 1050 1051 res = __eeprom_read(ras_core, 1052 control->i2c_address + 1053 control->ras_header_offset, 1054 buf, buf_size); 1055 if (res < buf_size) { 1056 RAS_DEV_ERR(ras_core->dev, 1057 "Partial read for checksum, res:%d\n", res); 1058 /* On partial reads, return -EIO. 1059 */ 1060 if (res >= 0) 1061 res = -EIO; 1062 goto Out; 1063 } 1064 1065 csum = 0; 1066 for (pp = buf; pp < buf + buf_size; pp++) 1067 csum += *pp; 1068 Out: 1069 kfree(buf); 1070 return res < 0 ? res : csum; 1071 } 1072 1073 static int __read_table_ras_info(struct ras_eeprom_control *control) 1074 { 1075 struct ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1076 struct ras_core_context *ras_core = to_ras_core_context(control); 1077 unsigned char *buf; 1078 int res; 1079 1080 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1081 if (!buf) { 1082 RAS_DEV_ERR(ras_core->dev, 1083 "Failed to alloc buf to read EEPROM table ras info\n"); 1084 return -ENOMEM; 1085 } 1086 1087 /** 1088 * EEPROM table V2_1 supports ras info, 1089 * read EEPROM table ras info 1090 */ 1091 res = __eeprom_read(ras_core, 1092 control->i2c_address + control->ras_info_offset, 1093 buf, RAS_TABLE_V2_1_INFO_SIZE); 1094 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1095 RAS_DEV_ERR(ras_core->dev, 1096 "Failed to read EEPROM table ras info, res:%d\n", res); 1097 res = res >= 0 ? -EIO : res; 1098 goto Out; 1099 } 1100 1101 __decode_table_ras_info_from_buf(rai, buf); 1102 1103 Out: 1104 kfree(buf); 1105 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1106 } 1107 1108 static int __check_ras_table_status(struct ras_core_context *ras_core) 1109 { 1110 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 1111 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1112 struct ras_eeprom_table_header *hdr; 1113 int res; 1114 1115 hdr = &control->tbl_hdr; 1116 1117 if (!__is_ras_eeprom_supported(ras_core)) 1118 return 0; 1119 1120 if (!__get_eeprom_i2c_addr(ras_core, control)) 1121 return -EINVAL; 1122 1123 control->ras_header_offset = RAS_HDR_START; 1124 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1125 mutex_init(&control->ras_tbl_mutex); 1126 1127 /* Read the table header from EEPROM address */ 1128 res = __eeprom_read(ras_core, 1129 control->i2c_address + control->ras_header_offset, 1130 buf, RAS_TABLE_HEADER_SIZE); 1131 if (res < RAS_TABLE_HEADER_SIZE) { 1132 RAS_DEV_ERR(ras_core->dev, 1133 "Failed to read EEPROM table header, res:%d\n", res); 1134 return res >= 0 ? -EIO : res; 1135 } 1136 1137 __decode_table_header_from_buf(hdr, buf); 1138 1139 if (hdr->header != RAS_TABLE_HDR_VAL && 1140 hdr->header != RAS_TABLE_HDR_BAD) { 1141 RAS_DEV_INFO(ras_core->dev, "Creating a new EEPROM table"); 1142 return ras_eeprom_reset_table(ras_core); 1143 } 1144 1145 switch (hdr->version) { 1146 case RAS_TABLE_VER_V2_1: 1147 case RAS_TABLE_VER_V3: 1148 if (hdr->tbl_size < RAS_TABLE_HEADER_SIZE + RAS_TABLE_V2_1_INFO_SIZE) { 1149 RAS_DEV_ERR(ras_core->dev, 1150 "RAS header invalid, tbl_size %u smaller than minimum %u, resetting table\n", 1151 hdr->tbl_size, 1152 RAS_TABLE_HEADER_SIZE + RAS_TABLE_V2_1_INFO_SIZE); 1153 return ras_eeprom_reset_table(ras_core); 1154 } 1155 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1156 control->ras_record_offset = RAS_RECORD_START_V2_1; 1157 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1158 break; 1159 case RAS_TABLE_VER_V1: 1160 if (hdr->tbl_size < RAS_TABLE_HEADER_SIZE) { 1161 RAS_DEV_ERR(ras_core->dev, 1162 "RAS header invalid, tbl_size %u smaller than minimum %u, resetting table\n", 1163 hdr->tbl_size, RAS_TABLE_HEADER_SIZE); 1164 return ras_eeprom_reset_table(ras_core); 1165 } 1166 control->ras_num_recs = RAS_NUM_RECS(hdr); 1167 control->ras_record_offset = RAS_RECORD_START; 1168 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1169 break; 1170 default: 1171 RAS_DEV_ERR(ras_core->dev, 1172 "RAS header invalid, unsupported version: %u", 1173 hdr->version); 1174 return -EINVAL; 1175 } 1176 1177 if (control->ras_num_recs > control->ras_max_record_count) { 1178 RAS_DEV_ERR(ras_core->dev, 1179 "RAS header invalid, records in header: %u max allowed :%u", 1180 control->ras_num_recs, control->ras_max_record_count); 1181 return -EINVAL; 1182 } 1183 1184 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1185 if (hdr->first_rec_offset < control->ras_record_offset || 1186 control->ras_fri >= control->ras_max_record_count) { 1187 RAS_DEV_ERR(ras_core->dev, 1188 "RAS header invalid, ras_fri: %u, first_rec_offset:0x%x", 1189 control->ras_fri, hdr->first_rec_offset); 1190 return -EINVAL; 1191 } 1192 1193 return 0; 1194 } 1195 1196 int ras_eeprom_check_storage_status(struct ras_core_context *ras_core) 1197 { 1198 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 1199 struct ras_eeprom_table_header *hdr; 1200 int bad_page_count; 1201 int res = 0; 1202 1203 if (!__is_ras_eeprom_supported(ras_core)) 1204 return 0; 1205 1206 if (!__get_eeprom_i2c_addr(ras_core, control)) 1207 return -EINVAL; 1208 1209 hdr = &control->tbl_hdr; 1210 1211 bad_page_count = ras_umc_get_badpage_count(ras_core); 1212 if (hdr->header == RAS_TABLE_HDR_VAL) { 1213 RAS_DEV_INFO(ras_core->dev, 1214 "Found existing EEPROM table with %d records\n", 1215 bad_page_count); 1216 1217 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1218 res = __read_table_ras_info(control); 1219 if (res) 1220 return res; 1221 } 1222 1223 res = __verify_ras_table_checksum(control); 1224 if (res) 1225 RAS_DEV_ERR(ras_core->dev, 1226 "RAS table incorrect checksum or error:%d\n", res); 1227 1228 /* Warn if we are at 90% of the threshold or above 1229 */ 1230 if (10 * bad_page_count >= 9 * control->record_threshold_count) 1231 RAS_DEV_WARN(ras_core->dev, 1232 "RAS records:%u exceeds 90%% of threshold:%d\n", 1233 bad_page_count, 1234 control->record_threshold_count); 1235 1236 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1237 control->record_threshold_config != 0) { 1238 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1239 res = __read_table_ras_info(control); 1240 if (res) 1241 return res; 1242 } 1243 1244 res = __verify_ras_table_checksum(control); 1245 if (res) 1246 RAS_DEV_ERR(ras_core->dev, 1247 "RAS Table incorrect checksum or error:%d\n", res); 1248 1249 if (control->record_threshold_count >= bad_page_count) { 1250 /* This means that, the threshold was increased since 1251 * the last time the system was booted, and now, 1252 * ras->record_threshold_count - control->num_recs > 0, 1253 * so that at least one more record can be saved, 1254 * before the page count threshold is reached. 1255 */ 1256 RAS_DEV_INFO(ras_core->dev, 1257 "records:%d threshold:%d, resetting RAS table header signature", 1258 bad_page_count, 1259 control->record_threshold_count); 1260 res = ras_eeprom_correct_header_tag(control, RAS_TABLE_HDR_VAL); 1261 } else { 1262 RAS_DEV_ERR(ras_core->dev, "RAS records:%d exceed threshold:%d", 1263 bad_page_count, control->record_threshold_count); 1264 /* send the event when threshold is exceeded, and ignore the 1265 * return value here 1266 */ 1267 ras_core_event_notify(ras_core, RAS_EVENT_ID__DEVICE_RMA, NULL); 1268 1269 if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) || 1270 (control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) { 1271 RAS_DEV_WARN(ras_core->dev, 1272 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); 1273 res = 0; 1274 } else { 1275 ras_core->is_rma = true; 1276 RAS_DEV_ERR(ras_core->dev, 1277 "User defined threshold is set, runtime service will be halt when threshold is reached\n"); 1278 } 1279 } 1280 } 1281 1282 return res < 0 ? res : 0; 1283 } 1284 1285 int ras_eeprom_hw_init(struct ras_core_context *ras_core) 1286 { 1287 struct ras_eeprom_control *control; 1288 struct ras_eeprom_config *eeprom_cfg; 1289 1290 if (!ras_core) 1291 return -EINVAL; 1292 1293 ras_core->is_rma = false; 1294 1295 control = &ras_core->ras_eeprom; 1296 1297 memset(control, 0, sizeof(*control)); 1298 1299 eeprom_cfg = &ras_core->config->eeprom_cfg; 1300 control->record_threshold_config = 1301 eeprom_cfg->eeprom_record_threshold_config; 1302 1303 control->record_threshold_count = ras_eeprom_max_record_count(ras_core); 1304 if (eeprom_cfg->eeprom_record_threshold_count < 1305 control->record_threshold_count) 1306 control->record_threshold_count = 1307 eeprom_cfg->eeprom_record_threshold_count; 1308 1309 control->sys_func = eeprom_cfg->eeprom_sys_fn; 1310 control->max_read_len = eeprom_cfg->max_i2c_read_len; 1311 control->max_write_len = eeprom_cfg->max_i2c_write_len; 1312 control->i2c_adapter = eeprom_cfg->eeprom_i2c_adapter; 1313 control->i2c_port = eeprom_cfg->eeprom_i2c_port; 1314 control->i2c_address = eeprom_cfg->eeprom_i2c_addr; 1315 1316 control->update_channel_flag = false; 1317 1318 return __check_ras_table_status(ras_core); 1319 } 1320 1321 int ras_eeprom_hw_fini(struct ras_core_context *ras_core) 1322 { 1323 struct ras_eeprom_control *control; 1324 1325 if (!ras_core) 1326 return -EINVAL; 1327 1328 control = &ras_core->ras_eeprom; 1329 mutex_destroy(&control->ras_tbl_mutex); 1330 1331 return 0; 1332 } 1333 1334 uint32_t ras_eeprom_get_record_count(struct ras_core_context *ras_core) 1335 { 1336 if (!ras_core) 1337 return 0; 1338 1339 return ras_core->ras_eeprom.ras_num_recs; 1340 } 1341 1342 void ras_eeprom_sync_info(struct ras_core_context *ras_core) 1343 { 1344 struct ras_eeprom_control *control; 1345 1346 if (!ras_core) 1347 return; 1348 1349 control = &ras_core->ras_eeprom; 1350 ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, 1351 &control->ras_num_recs); 1352 ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, 1353 &control->bad_channel_bitmap); 1354 } 1355 1356 enum ras_gpu_health_status 1357 ras_eeprom_check_gpu_status(struct ras_core_context *ras_core) 1358 { 1359 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 1360 struct ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1361 1362 if (!__is_ras_eeprom_supported(ras_core) || 1363 !control->record_threshold_config) 1364 return RAS_GPU_HEALTH_NONE; 1365 1366 if (control->tbl_hdr.header == RAS_TABLE_HDR_BAD) 1367 return RAS_GPU_IN_BAD_STATUS; 1368 1369 return rai->rma_status; 1370 } 1371