1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __CMD_H__ 26 #define __CMD_H__ 27 #include "ras.h" 28 #include "eeprom.h" 29 #include "log_ring.h" 30 #include "ras_cper.h" 31 32 #define RAS_CMD_MAX_IN_SIZE 256 33 #define RAS_CMD_MAX_GPU_NUM 32 34 #define RAS_CMD_MAX_BAD_PAGES_PER_GROUP 32 35 36 /* position of instance value in sub_block_index of 37 * ta_ras_trigger_error_input, the sub block uses lower 12 bits 38 */ 39 #define RAS_TA_INST_MASK 0xfffff000 40 #define RAS_TA_INST_SHIFT 0xc 41 42 enum ras_cmd_interface_type { 43 RAS_CMD_INTERFACE_TYPE_NONE, 44 RAS_CMD_INTERFACE_TYPE_AMDGPU, 45 RAS_CMD_INTERFACE_TYPE_VF, 46 RAS_CMD_INTERFACE_TYPE_PF, 47 }; 48 49 enum ras_cmd_id_range { 50 RAS_CMD_ID_COMMON_START = 0, 51 RAS_CMD_ID_COMMON_END = 0x10000, 52 RAS_CMD_ID_AMDGPU_START = RAS_CMD_ID_COMMON_END, 53 RAS_CMD_ID_AMDGPU_END = 0x20000, 54 RAS_CMD_ID_MXGPU_START = RAS_CMD_ID_AMDGPU_END, 55 RAS_CMD_ID_MXGPU_END = 0x30000, 56 RAS_CMD_ID_MXGPU_VF_START = RAS_CMD_ID_MXGPU_END, 57 RAS_CMD_ID_MXGPU_VF_END = 0x40000, 58 }; 59 60 enum ras_cmd_id { 61 RAS_CMD__BEGIN = RAS_CMD_ID_COMMON_START, 62 RAS_CMD__QUERY_INTERFACE_INFO, 63 RAS_CMD__GET_DEVICES_INFO, 64 RAS_CMD__GET_BLOCK_ECC_STATUS, 65 RAS_CMD__INJECT_ERROR, 66 RAS_CMD__GET_BAD_PAGES, 67 RAS_CMD__CLEAR_BAD_PAGE_INFO, 68 RAS_CMD__RESET_ALL_ERROR_COUNTS, 69 RAS_CMD__GET_SAFE_FB_ADDRESS_RANGES, 70 RAS_CMD__TRANSLATE_FB_ADDRESS, 71 RAS_CMD__GET_LINK_TOPOLOGY, 72 RAS_CMD__GET_CPER_SNAPSHOT, 73 RAS_CMD__GET_CPER_RECORD, 74 RAS_CMD__GET_BATCH_TRACE_SNAPSHOT, 75 RAS_CMD__GET_BATCH_TRACE_RECORD, 76 RAS_CMD__GET_ALL_BLOCK_ECC_STATUS, 77 RAS_CMD__SET_CMD_AUTO_UPDATE, 78 RAS_CMD__CHECK_ADDRESS_VALIDITY, 79 RAS_CMD__CONVERT_RETIRED_ADDRESS, 80 RAS_CMD__SUPPORTED_MAX = RAS_CMD_ID_COMMON_END, 81 }; 82 83 enum ras_cmd_response { 84 RAS_CMD__SUCCESS = 0, 85 RAS_CMD__SUCCESS_EXEED_BUFFER, 86 RAS_CMD__ERROR_UKNOWN_CMD, 87 RAS_CMD__ERROR_INVALID_CMD, 88 RAS_CMD__ERROR_VERSION, 89 RAS_CMD__ERROR_INVALID_INPUT_SIZE, 90 RAS_CMD__ERROR_INVALID_INPUT_DATA, 91 RAS_CMD__ERROR_DRV_INIT_FAIL, 92 RAS_CMD__ERROR_ACCESS_DENIED, 93 RAS_CMD__ERROR_GENERIC, 94 RAS_CMD__ERROR_TIMEOUT, 95 }; 96 97 enum ras_error_type { 98 RAS_TYPE_ERROR__NONE = 0, 99 RAS_TYPE_ERROR__PARITY = 1, 100 RAS_TYPE_ERROR__SINGLE_CORRECTABLE = 2, 101 RAS_TYPE_ERROR__MULTI_UNCORRECTABLE = 4, 102 RAS_TYPE_ERROR__POISON = 8, 103 }; 104 105 struct ras_core_context; 106 struct ras_cmd_ctx; 107 108 struct ras_cmd_func_map { 109 uint32_t cmd_id; 110 int (*func)(struct ras_core_context *ras_core, 111 struct ras_cmd_ctx *cmd, void *data); 112 }; 113 114 struct ras_device_bdf { 115 union { 116 struct { 117 uint32_t function : 3; 118 uint32_t device : 5; 119 uint32_t bus : 8; 120 uint32_t domain : 16; 121 }; 122 uint32_t u32_all; 123 }; 124 }; 125 126 struct ras_cmd_param { 127 uint32_t idx_vf; 128 void *data; 129 }; 130 131 #pragma pack(push, 8) 132 struct ras_cmd_ctx { 133 uint32_t magic; 134 union { 135 struct { 136 uint16_t ras_cmd_minor_ver : 10; 137 uint16_t ras_cmd_major_ver : 6; 138 }; 139 uint16_t ras_cmd_ver; 140 }; 141 union { 142 struct { 143 uint16_t plat_major_ver : 10; 144 uint16_t plat_minor_ver : 6; 145 }; 146 uint16_t plat_ver; 147 }; 148 uint32_t cmd_id; 149 uint32_t cmd_res; 150 uint32_t input_size; 151 uint32_t output_size; 152 uint32_t output_buf_size; 153 uint32_t reserved[5]; 154 uint8_t input_buff_raw[RAS_CMD_MAX_IN_SIZE]; 155 uint8_t output_buff_raw[]; 156 }; 157 158 struct ras_cmd_dev_handle { 159 uint64_t dev_handle; 160 }; 161 162 struct ras_cmd_block_ecc_info_req { 163 struct ras_cmd_dev_handle dev; 164 uint32_t block_id; 165 uint32_t subblock_id; 166 uint32_t reserved[4]; 167 }; 168 169 struct ras_cmd_block_ecc_info_rsp { 170 uint32_t version; 171 uint32_t ce_count; 172 uint32_t ue_count; 173 uint32_t de_count; 174 uint32_t reserved[6]; 175 }; 176 177 struct ras_cmd_inject_error_req { 178 struct ras_cmd_dev_handle dev; 179 uint32_t block_id; 180 uint32_t subblock_id; 181 uint64_t address; 182 uint32_t error_type; 183 uint32_t instance_mask; 184 union { 185 struct { 186 /* vf index */ 187 uint64_t vf_idx : 6; 188 /* method of error injection. i.e persistent, coherent etc */ 189 uint64_t method : 10; 190 uint64_t rsv : 48; 191 }; 192 uint64_t value; 193 }; 194 uint32_t reserved[8]; 195 }; 196 197 struct ras_cmd_inject_error_rsp { 198 uint32_t version; 199 uint32_t reserved[5]; 200 uint64_t address; 201 }; 202 203 struct ras_cmd_dev_info { 204 uint64_t dev_handle; 205 uint32_t location_id; 206 uint32_t ecc_enabled; 207 uint32_t ecc_supported; 208 uint32_t vf_num; 209 uint32_t asic_type; 210 uint32_t oam_id; 211 uint32_t reserved[8]; 212 }; 213 214 struct ras_cmd_devices_info_rsp { 215 uint32_t version; 216 uint32_t dev_num; 217 uint32_t reserved[6]; 218 struct ras_cmd_dev_info devs[RAS_CMD_MAX_GPU_NUM]; 219 }; 220 221 struct ras_cmd_bad_page_record { 222 union { 223 uint64_t address; 224 uint64_t offset; 225 }; 226 uint64_t retired_page; 227 uint64_t ts; 228 229 uint32_t err_type; 230 231 union { 232 unsigned char bank; 233 unsigned char cu; 234 }; 235 236 unsigned char mem_channel; 237 unsigned char mcumc_id; 238 239 unsigned char valid; 240 unsigned char reserved[8]; 241 }; 242 243 struct ras_cmd_bad_pages_info_req { 244 struct ras_cmd_dev_handle device; 245 uint32_t group_index; 246 uint32_t reserved[5]; 247 }; 248 249 struct ras_cmd_bad_pages_info_rsp { 250 uint32_t version; 251 uint32_t group_index; 252 uint32_t bp_in_group; 253 uint32_t bp_total_cnt; 254 uint32_t reserved[4]; 255 struct ras_cmd_bad_page_record records[RAS_CMD_MAX_BAD_PAGES_PER_GROUP]; 256 }; 257 258 struct ras_query_interface_info_req { 259 uint32_t reserved[8]; 260 }; 261 262 struct ras_query_interface_info_rsp { 263 uint32_t version; 264 uint32_t ras_cmd_major_ver; 265 uint32_t ras_cmd_minor_ver; 266 uint32_t plat_major_ver; 267 uint32_t plat_minor_ver; 268 uint8_t interface_type; 269 uint8_t rsv[3]; 270 uint32_t reserved[8]; 271 }; 272 273 #define RAS_MAX_NUM_SAFE_RANGES 64 274 struct ras_cmd_ras_safe_fb_address_ranges_rsp { 275 uint32_t version; 276 uint32_t num_ranges; 277 uint32_t reserved[4]; 278 struct { 279 uint64_t start; 280 uint64_t size; 281 uint32_t idx; 282 uint32_t reserved[3]; 283 } range[RAS_MAX_NUM_SAFE_RANGES]; 284 }; 285 286 enum ras_fb_addr_type { 287 RAS_FB_ADDR_SOC_PHY, /* SPA */ 288 RAS_FB_ADDR_BANK, 289 RAS_FB_ADDR_VF_PHY, /* GPA */ 290 RAS_FB_ADDR_UNKNOWN 291 }; 292 293 struct ras_fb_bank_addr { 294 uint32_t stack_id; /* SID */ 295 uint32_t bank_group; 296 uint32_t bank; 297 uint32_t row; 298 uint32_t column; 299 uint32_t channel; 300 uint32_t subchannel; /* Also called Pseudochannel (PC) */ 301 uint32_t reserved[3]; 302 }; 303 304 struct ras_fb_vf_phy_addr { 305 uint32_t vf_idx; 306 uint32_t reserved; 307 uint64_t addr; 308 }; 309 310 union ras_translate_fb_address { 311 struct ras_fb_bank_addr bank_addr; 312 uint64_t soc_phy_addr; 313 struct ras_fb_vf_phy_addr vf_phy_addr; 314 }; 315 316 struct ras_cmd_translate_fb_address_req { 317 struct ras_cmd_dev_handle dev; 318 enum ras_fb_addr_type src_addr_type; 319 enum ras_fb_addr_type dest_addr_type; 320 union ras_translate_fb_address trans_addr; 321 }; 322 323 struct ras_cmd_translate_fb_address_rsp { 324 uint32_t version; 325 uint32_t reserved[5]; 326 union ras_translate_fb_address trans_addr; 327 }; 328 329 struct ras_dev_link_topology_req { 330 struct ras_cmd_dev_handle src; 331 struct ras_cmd_dev_handle dst; 332 }; 333 334 struct ras_dev_link_topology_rsp { 335 uint32_t version; 336 uint32_t link_status; /* HW status of the link */ 337 uint32_t link_type; /* type of the link */ 338 uint32_t num_hops; /* number of hops */ 339 uint32_t reserved[8]; 340 }; 341 342 struct ras_cmd_cper_snapshot_req { 343 struct ras_cmd_dev_handle dev; 344 }; 345 346 struct ras_cmd_cper_snapshot_rsp { 347 uint32_t version; 348 uint32_t reserved[4]; 349 uint32_t total_cper_num; 350 uint64_t start_cper_id; 351 uint64_t latest_cper_id; 352 }; 353 354 struct ras_cmd_cper_record_req { 355 struct ras_cmd_dev_handle dev; 356 uint64_t cper_start_id; 357 uint32_t cper_num; 358 uint32_t buf_size; 359 uint64_t buf_ptr; 360 uint32_t reserved[4]; 361 }; 362 363 struct ras_cmd_cper_record_rsp { 364 uint32_t version; 365 uint32_t real_data_size; 366 uint32_t real_cper_num; 367 uint32_t remain_num; 368 uint32_t reserved[4]; 369 }; 370 371 struct ras_cmd_batch_trace_snapshot_req { 372 struct ras_cmd_dev_handle dev; 373 }; 374 375 struct ras_cmd_batch_trace_snapshot_rsp { 376 uint32_t version; 377 uint32_t reserved[4]; 378 uint32_t total_batch_num; 379 uint64_t start_batch_id; 380 uint64_t latest_batch_id; 381 }; 382 383 struct ras_cmd_batch_trace_record_req { 384 struct ras_cmd_dev_handle dev; 385 uint64_t start_batch_id; 386 uint32_t batch_num; 387 uint32_t reserved[5]; 388 }; 389 390 struct batch_ras_trace_info { 391 uint64_t batch_id; 392 uint16_t offset; 393 uint8_t trace_num; 394 uint8_t rsv; 395 uint32_t reserved; 396 }; 397 398 #define RAS_CMD_MAX_BATCH_NUM 300 399 #define RAS_CMD_MAX_TRACE_NUM 300 400 401 /* Upper bounds for RAS_CMD__GET_CPER_RECORD to limit kernel allocations and work. */ 402 #define RAS_CMD_MAX_CPER_BUF_SZ (2 * 1024U * 1024U) /* 2 MiB */ 403 struct ras_cmd_batch_trace_record_rsp { 404 uint32_t version; 405 uint16_t real_batch_num; 406 uint16_t remain_num; 407 uint64_t start_batch_id; 408 uint32_t reserved[2]; 409 struct batch_ras_trace_info batchs[RAS_CMD_MAX_BATCH_NUM]; 410 struct ras_log_info records[RAS_CMD_MAX_TRACE_NUM]; 411 }; 412 413 struct ras_cmd_auto_update_req { 414 struct ras_cmd_dev_handle dev; 415 uint32_t mode; 416 uint32_t cmd_id; 417 uint64_t addr; 418 uint32_t len; 419 uint32_t reserved[5]; 420 }; 421 422 struct ras_cmd_auto_update_rsp { 423 uint32_t version; 424 uint32_t reserved[4]; 425 }; 426 427 struct ras_cmd_address_check_req { 428 struct ras_cmd_dev_handle dev; 429 uint64_t address; 430 uint32_t flags; 431 uint32_t vf_idx; 432 uint32_t reserved[4]; 433 }; 434 435 struct ras_cmd_address_check_rsp { 436 uint32_t version; 437 uint32_t result; 438 uint32_t reserved[6]; 439 }; 440 441 struct ras_cmd_convert_retired_address_req { 442 struct ras_cmd_dev_handle dev; 443 uint64_t address; 444 uint32_t reserved[6]; 445 }; 446 447 #define RAS_CMD_MAX_RETIRED_ADDR_COUNT 32 448 struct ras_cmd_convert_retired_address_rsp { 449 uint32_t version; 450 uint32_t retired_count; 451 uint64_t retired_addr[RAS_CMD_MAX_RETIRED_ADDR_COUNT]; 452 }; 453 454 struct ras_cmd_blocks_ecc_req { 455 struct ras_cmd_dev_handle dev; 456 }; 457 458 struct ras_cmd_block_ecc { 459 uint32_t ce_count; 460 uint32_t ue_count; 461 uint32_t de_count; 462 }; 463 464 #define MAX_RAS_BLOCK_NUM 20 465 struct ras_cmd_blocks_ecc_rsp { 466 uint32_t version; 467 uint32_t reserved[5]; 468 struct ras_cmd_block_ecc blocks[MAX_RAS_BLOCK_NUM]; 469 }; 470 471 #pragma pack(pop) 472 473 int ras_cmd_init(struct ras_core_context *ras_core); 474 int ras_cmd_fini(struct ras_core_context *ras_core); 475 int rascore_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd, void *data); 476 int ras_cmd_query_interface_info(struct ras_core_context *ras_core, 477 struct ras_query_interface_info_rsp *rsp); 478 int ras_cmd_translate_soc_pa_to_bank(struct ras_core_context *ras_core, 479 uint64_t soc_pa, struct ras_fb_bank_addr *bank_addr); 480 int ras_cmd_translate_bank_to_soc_pa(struct ras_core_context *ras_core, 481 struct ras_fb_bank_addr bank_addr, uint64_t *soc_pa); 482 #endif 483