1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __SMU_V15_0_H__ 24 #define __SMU_V15_0_H__ 25 26 #include "amdgpu_smu.h" 27 28 #define SMU15_DRIVER_IF_VERSION_INV 0xFFFFFFFF 29 #define SMU15_DRIVER_IF_VERSION_SMU_V15_0 0x7 30 31 32 #define FEATURE_MASK(feature) (1ULL << feature) 33 34 /* MP Apertures */ 35 #define MP0_Public 0x03800000 36 #define MP0_SRAM 0x03900000 37 #define MP1_Public 0x03b00000 38 #define MP1_SRAM 0x03c00004 39 40 /* address block */ 41 #define smnMP1_FIRMWARE_FLAGS 0x3010024 42 #define smnMP1_PUB_CTRL 0x3010d10 43 44 #define MAX_DPM_LEVELS 16 45 #define MAX_PCIE_CONF 3 46 47 #define SMU15_TOOL_SIZE 0x19000 48 49 #define CTF_OFFSET_EDGE 5 50 #define CTF_OFFSET_HOTSPOT 5 51 #define CTF_OFFSET_MEM 5 52 53 extern const int decoded_link_speed[5]; 54 extern const int decoded_link_width[8]; 55 56 #define DECODE_GEN_SPEED(gen_speed_idx) (decoded_link_speed[gen_speed_idx]) 57 #define DECODE_LANE_WIDTH(lane_width_idx) (decoded_link_width[lane_width_idx]) 58 59 struct smu_15_0_max_sustainable_clocks { 60 uint32_t display_clock; 61 uint32_t phy_clock; 62 uint32_t pixel_clock; 63 uint32_t uclock; 64 uint32_t dcef_clock; 65 uint32_t soc_clock; 66 }; 67 68 struct smu_15_0_dpm_clk_level { 69 bool enabled; 70 uint32_t value; 71 }; 72 73 struct smu_15_0_dpm_table { 74 uint32_t min; /* MHz */ 75 uint32_t max; /* MHz */ 76 uint32_t count; 77 bool is_fine_grained; 78 struct smu_15_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; 79 }; 80 81 struct smu_15_0_pcie_table { 82 uint8_t pcie_gen[MAX_PCIE_CONF]; 83 uint8_t pcie_lane[MAX_PCIE_CONF]; 84 uint16_t clk_freq[MAX_PCIE_CONF]; 85 uint32_t num_of_link_levels; 86 }; 87 88 struct smu_15_0_dpm_tables { 89 struct smu_15_0_dpm_table soc_table; 90 struct smu_15_0_dpm_table gfx_table; 91 struct smu_15_0_dpm_table uclk_table; 92 struct smu_15_0_dpm_table eclk_table; 93 struct smu_15_0_dpm_table vclk_table; 94 struct smu_15_0_dpm_table dclk_table; 95 struct smu_15_0_dpm_table dcef_table; 96 struct smu_15_0_dpm_table pixel_table; 97 struct smu_15_0_dpm_table display_table; 98 struct smu_15_0_dpm_table phy_table; 99 struct smu_15_0_dpm_table fclk_table; 100 struct smu_15_0_pcie_table pcie_table; 101 }; 102 103 struct smu_15_0_dpm_context { 104 struct smu_15_0_dpm_tables dpm_tables; 105 uint32_t workload_policy_mask; 106 uint32_t dcef_min_ds_clk; 107 }; 108 109 enum smu_15_0_power_state { 110 smu_15_0_POWER_STATE__D0 = 0, 111 smu_15_0_POWER_STATE__D1, 112 smu_15_0_POWER_STATE__D3, /* Sleep*/ 113 smu_15_0_POWER_STATE__D4, /* Hibernate*/ 114 smu_15_0_POWER_STATE__D5, /* Power off*/ 115 }; 116 117 struct smu_15_0_power_context { 118 uint32_t power_source; 119 uint8_t in_power_limit_boost_mode; 120 enum smu_15_0_power_state power_state; 121 }; 122 123 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) 124 125 int smu_v15_0_init_microcode(struct smu_context *smu); 126 127 void smu_v15_0_fini_microcode(struct smu_context *smu); 128 129 int smu_v15_0_load_microcode(struct smu_context *smu); 130 131 int smu_v15_0_init_smc_tables(struct smu_context *smu); 132 133 int smu_v15_0_fini_smc_tables(struct smu_context *smu); 134 135 int smu_v15_0_init_power(struct smu_context *smu); 136 137 int smu_v15_0_fini_power(struct smu_context *smu); 138 139 int smu_v15_0_check_fw_status(struct smu_context *smu); 140 141 int smu_v15_0_setup_pptable(struct smu_context *smu); 142 143 int smu_v15_0_get_vbios_bootup_values(struct smu_context *smu); 144 145 int smu_v15_0_check_fw_version(struct smu_context *smu); 146 147 int smu_v15_0_set_driver_table_location(struct smu_context *smu); 148 149 int smu_v15_0_set_tool_table_location(struct smu_context *smu); 150 151 int smu_v15_0_notify_memory_pool_location(struct smu_context *smu); 152 153 int smu_v15_0_system_features_control(struct smu_context *smu, 154 bool en); 155 156 int smu_v15_0_set_allowed_mask(struct smu_context *smu); 157 158 int smu_v15_0_notify_display_change(struct smu_context *smu); 159 160 int smu_v15_0_get_current_power_limit(struct smu_context *smu, 161 uint32_t *power_limit); 162 163 int smu_v15_0_set_power_limit(struct smu_context *smu, 164 enum smu_ppt_limit_type limit_type, 165 uint32_t limit); 166 167 int smu_v15_0_gfx_off_control(struct smu_context *smu, bool enable); 168 169 int smu_v15_0_register_irq_handler(struct smu_context *smu); 170 171 int smu_v15_0_baco_set_armd3_sequence(struct smu_context *smu, 172 enum smu_baco_seq baco_seq); 173 174 int smu_v15_0_get_bamaco_support(struct smu_context *smu); 175 176 enum smu_baco_state smu_v15_0_baco_get_state(struct smu_context *smu); 177 178 int smu_v15_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state); 179 180 int smu_v15_0_baco_enter(struct smu_context *smu); 181 int smu_v15_0_baco_exit(struct smu_context *smu); 182 183 int smu_v15_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 184 uint32_t *min, uint32_t *max); 185 186 int smu_v15_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 187 uint32_t min, uint32_t max, bool automatic); 188 189 int smu_v15_0_set_hard_freq_limited_range(struct smu_context *smu, 190 enum smu_clk_type clk_type, 191 uint32_t min, 192 uint32_t max); 193 194 int smu_v15_0_set_performance_level(struct smu_context *smu, 195 enum amd_dpm_forced_level level); 196 197 int smu_v15_0_set_power_source(struct smu_context *smu, 198 enum smu_power_src_type power_src); 199 200 int smu_v15_0_set_single_dpm_table(struct smu_context *smu, 201 enum smu_clk_type clk_type, 202 struct smu_15_0_dpm_table *single_dpm_table); 203 204 int smu_v15_0_gfx_ulv_control(struct smu_context *smu, 205 bool enablement); 206 207 int smu_v15_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 208 uint64_t event_arg); 209 210 int smu_v15_0_set_vcn_enable(struct smu_context *smu, 211 bool enable, 212 int inst); 213 214 int smu_v15_0_set_jpeg_enable(struct smu_context *smu, 215 bool enable); 216 217 int smu_v15_0_init_pptable_microcode(struct smu_context *smu); 218 219 int smu_v15_0_run_btc(struct smu_context *smu); 220 221 int smu_v15_0_gpo_control(struct smu_context *smu, 222 bool enablement); 223 224 int smu_v15_0_deep_sleep_control(struct smu_context *smu, 225 bool enablement); 226 227 int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu); 228 229 int smu_v15_0_get_pptable_from_firmware(struct smu_context *smu, 230 void **table, 231 uint32_t *size, 232 uint32_t pptable_id); 233 234 int smu_v15_0_od_edit_dpm_table(struct smu_context *smu, 235 enum PP_OD_DPM_TABLE_COMMAND type, 236 long input[], uint32_t size); 237 238 int smu_v15_0_enable_thermal_alert(struct smu_context *smu); 239 240 int smu_v15_0_disable_thermal_alert(struct smu_context *smu); 241 242 #endif 243 #endif 244