1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include "amdgpu.h" 26 #include "kgd_pp_interface.h" 27 #include "dm_pp_interface.h" 28 #include "dm_pp_smu.h" 29 #include "smu_types.h" 30 #include "linux/firmware.h" 31 32 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 33 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 34 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 35 #define SMU_FW_NAME_LEN 0x24 36 37 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 38 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 39 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 40 41 // Power Throttlers 42 #define SMU_THROTTLER_PPT0_BIT 0 43 #define SMU_THROTTLER_PPT1_BIT 1 44 #define SMU_THROTTLER_PPT2_BIT 2 45 #define SMU_THROTTLER_PPT3_BIT 3 46 #define SMU_THROTTLER_SPL_BIT 4 47 #define SMU_THROTTLER_FPPT_BIT 5 48 #define SMU_THROTTLER_SPPT_BIT 6 49 #define SMU_THROTTLER_SPPT_APU_BIT 7 50 51 // Current Throttlers 52 #define SMU_THROTTLER_TDC_GFX_BIT 16 53 #define SMU_THROTTLER_TDC_SOC_BIT 17 54 #define SMU_THROTTLER_TDC_MEM_BIT 18 55 #define SMU_THROTTLER_TDC_VDD_BIT 19 56 #define SMU_THROTTLER_TDC_CVIP_BIT 20 57 #define SMU_THROTTLER_EDC_CPU_BIT 21 58 #define SMU_THROTTLER_EDC_GFX_BIT 22 59 #define SMU_THROTTLER_APCC_BIT 23 60 61 // Temperature 62 #define SMU_THROTTLER_TEMP_GPU_BIT 32 63 #define SMU_THROTTLER_TEMP_CORE_BIT 33 64 #define SMU_THROTTLER_TEMP_MEM_BIT 34 65 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 66 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 67 #define SMU_THROTTLER_TEMP_SOC_BIT 37 68 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 69 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 70 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 71 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 72 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 73 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 74 #define SMU_THROTTLER_VRHOT0_BIT 44 75 #define SMU_THROTTLER_VRHOT1_BIT 45 76 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 77 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 78 79 // Other 80 #define SMU_THROTTLER_PPM_BIT 56 81 #define SMU_THROTTLER_FIT_BIT 57 82 83 struct smu_hw_power_state { 84 unsigned int magic; 85 }; 86 87 struct smu_power_state; 88 89 enum smu_state_ui_label { 90 SMU_STATE_UI_LABEL_NONE, 91 SMU_STATE_UI_LABEL_BATTERY, 92 SMU_STATE_UI_TABEL_MIDDLE_LOW, 93 SMU_STATE_UI_LABEL_BALLANCED, 94 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 95 SMU_STATE_UI_LABEL_PERFORMANCE, 96 SMU_STATE_UI_LABEL_BACO, 97 }; 98 99 enum smu_state_classification_flag { 100 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 101 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 102 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 103 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 104 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 105 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 106 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 107 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 108 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 109 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 111 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 112 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 113 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 114 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 115 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 116 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 117 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 118 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 119 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 120 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 121 }; 122 123 struct smu_state_classification_block { 124 enum smu_state_ui_label ui_label; 125 enum smu_state_classification_flag flags; 126 int bios_index; 127 bool temporary_state; 128 bool to_be_deleted; 129 }; 130 131 struct smu_state_pcie_block { 132 unsigned int lanes; 133 }; 134 135 enum smu_refreshrate_source { 136 SMU_REFRESHRATE_SOURCE_EDID, 137 SMU_REFRESHRATE_SOURCE_EXPLICIT 138 }; 139 140 struct smu_state_display_block { 141 bool disable_frame_modulation; 142 bool limit_refreshrate; 143 enum smu_refreshrate_source refreshrate_source; 144 int explicit_refreshrate; 145 int edid_refreshrate_index; 146 bool enable_vari_bright; 147 }; 148 149 struct smu_state_memory_block { 150 bool dll_off; 151 uint8_t m3arb; 152 uint8_t unused[3]; 153 }; 154 155 struct smu_state_software_algorithm_block { 156 bool disable_load_balancing; 157 bool enable_sleep_for_timestamps; 158 }; 159 160 struct smu_temperature_range { 161 int min; 162 int max; 163 int edge_emergency_max; 164 int hotspot_min; 165 int hotspot_crit_max; 166 int hotspot_emergency_max; 167 int mem_min; 168 int mem_crit_max; 169 int mem_emergency_max; 170 int software_shutdown_temp; 171 int software_shutdown_temp_offset; 172 }; 173 174 struct smu_state_validation_block { 175 bool single_display_only; 176 bool disallow_on_dc; 177 uint8_t supported_power_levels; 178 }; 179 180 struct smu_uvd_clocks { 181 uint32_t vclk; 182 uint32_t dclk; 183 }; 184 185 /** 186 * Structure to hold a SMU Power State. 187 */ 188 struct smu_power_state { 189 uint32_t id; 190 struct list_head ordered_list; 191 struct list_head all_states_list; 192 193 struct smu_state_classification_block classification; 194 struct smu_state_validation_block validation; 195 struct smu_state_pcie_block pcie; 196 struct smu_state_display_block display; 197 struct smu_state_memory_block memory; 198 struct smu_state_software_algorithm_block software; 199 struct smu_uvd_clocks uvd_clocks; 200 struct smu_hw_power_state hardware; 201 }; 202 203 enum smu_power_src_type { 204 SMU_POWER_SOURCE_AC, 205 SMU_POWER_SOURCE_DC, 206 SMU_POWER_SOURCE_COUNT, 207 }; 208 209 enum smu_ppt_limit_type { 210 SMU_DEFAULT_PPT_LIMIT = 0, 211 SMU_FAST_PPT_LIMIT, 212 }; 213 214 enum smu_ppt_limit_level { 215 SMU_PPT_LIMIT_MIN = -1, 216 SMU_PPT_LIMIT_CURRENT, 217 SMU_PPT_LIMIT_DEFAULT, 218 SMU_PPT_LIMIT_MAX, 219 }; 220 221 enum smu_memory_pool_size { 222 SMU_MEMORY_POOL_SIZE_ZERO = 0, 223 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 224 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 225 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 226 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 227 }; 228 229 struct smu_user_dpm_profile { 230 uint32_t fan_mode; 231 uint32_t power_limit; 232 uint32_t fan_speed_pwm; 233 uint32_t fan_speed_rpm; 234 uint32_t flags; 235 uint32_t user_od; 236 237 /* user clock state information */ 238 uint32_t clk_mask[SMU_CLK_COUNT]; 239 uint32_t clk_dependency; 240 }; 241 242 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 243 do { \ 244 tables[table_id].size = s; \ 245 tables[table_id].align = a; \ 246 tables[table_id].domain = d; \ 247 } while (0) 248 249 struct smu_table { 250 uint64_t size; 251 uint32_t align; 252 uint8_t domain; 253 uint64_t mc_address; 254 void *cpu_addr; 255 struct amdgpu_bo *bo; 256 }; 257 258 enum smu_perf_level_designation { 259 PERF_LEVEL_ACTIVITY, 260 PERF_LEVEL_POWER_CONTAINMENT, 261 }; 262 263 struct smu_performance_level { 264 uint32_t core_clock; 265 uint32_t memory_clock; 266 uint32_t vddc; 267 uint32_t vddci; 268 uint32_t non_local_mem_freq; 269 uint32_t non_local_mem_width; 270 }; 271 272 struct smu_clock_info { 273 uint32_t min_mem_clk; 274 uint32_t max_mem_clk; 275 uint32_t min_eng_clk; 276 uint32_t max_eng_clk; 277 uint32_t min_bus_bandwidth; 278 uint32_t max_bus_bandwidth; 279 }; 280 281 struct smu_bios_boot_up_values { 282 uint32_t revision; 283 uint32_t gfxclk; 284 uint32_t uclk; 285 uint32_t socclk; 286 uint32_t dcefclk; 287 uint32_t eclk; 288 uint32_t vclk; 289 uint32_t dclk; 290 uint16_t vddc; 291 uint16_t vddci; 292 uint16_t mvddc; 293 uint16_t vdd_gfx; 294 uint8_t cooling_id; 295 uint32_t pp_table_id; 296 uint32_t format_revision; 297 uint32_t content_revision; 298 uint32_t fclk; 299 uint32_t lclk; 300 uint32_t firmware_caps; 301 }; 302 303 enum smu_table_id { 304 SMU_TABLE_PPTABLE = 0, 305 SMU_TABLE_WATERMARKS, 306 SMU_TABLE_CUSTOM_DPM, 307 SMU_TABLE_DPMCLOCKS, 308 SMU_TABLE_AVFS, 309 SMU_TABLE_AVFS_PSM_DEBUG, 310 SMU_TABLE_AVFS_FUSE_OVERRIDE, 311 SMU_TABLE_PMSTATUSLOG, 312 SMU_TABLE_SMU_METRICS, 313 SMU_TABLE_DRIVER_SMU_CONFIG, 314 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 315 SMU_TABLE_OVERDRIVE, 316 SMU_TABLE_I2C_COMMANDS, 317 SMU_TABLE_PACE, 318 SMU_TABLE_ECCINFO, 319 SMU_TABLE_COMBO_PPTABLE, 320 SMU_TABLE_COUNT, 321 }; 322 323 struct smu_table_context { 324 void *power_play_table; 325 uint32_t power_play_table_size; 326 void *hardcode_pptable; 327 unsigned long metrics_time; 328 void *metrics_table; 329 void *clocks_table; 330 void *watermarks_table; 331 332 void *max_sustainable_clocks; 333 struct smu_bios_boot_up_values boot_values; 334 void *driver_pptable; 335 void *combo_pptable; 336 void *ecc_table; 337 void *driver_smu_config_table; 338 struct smu_table tables[SMU_TABLE_COUNT]; 339 /* 340 * The driver table is just a staging buffer for 341 * uploading/downloading content from the SMU. 342 * 343 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 344 * SMU_MSG_TransferTableDram2Smu instructs SMU 345 * which content driver is interested. 346 */ 347 struct smu_table driver_table; 348 struct smu_table memory_pool; 349 struct smu_table dummy_read_1_table; 350 uint8_t thermal_controller_type; 351 352 void *overdrive_table; 353 void *boot_overdrive_table; 354 void *user_overdrive_table; 355 356 uint32_t gpu_metrics_table_size; 357 void *gpu_metrics_table; 358 }; 359 360 struct smu_dpm_context { 361 uint32_t dpm_context_size; 362 void *dpm_context; 363 void *golden_dpm_context; 364 enum amd_dpm_forced_level dpm_level; 365 enum amd_dpm_forced_level saved_dpm_level; 366 enum amd_dpm_forced_level requested_dpm_level; 367 struct smu_power_state *dpm_request_power_state; 368 struct smu_power_state *dpm_current_power_state; 369 struct mclock_latency_table *mclk_latency_table; 370 }; 371 372 struct smu_power_gate { 373 bool uvd_gated; 374 bool vce_gated; 375 atomic_t vcn_gated; 376 atomic_t jpeg_gated; 377 atomic_t vpe_gated; 378 atomic_t umsch_mm_gated; 379 }; 380 381 struct smu_power_context { 382 void *power_context; 383 uint32_t power_context_size; 384 struct smu_power_gate power_gate; 385 }; 386 387 #define SMU_FEATURE_MAX (64) 388 struct smu_feature { 389 uint32_t feature_num; 390 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 391 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 392 }; 393 394 struct smu_clocks { 395 uint32_t engine_clock; 396 uint32_t memory_clock; 397 uint32_t bus_bandwidth; 398 uint32_t engine_clock_in_sr; 399 uint32_t dcef_clock; 400 uint32_t dcef_clock_in_sr; 401 }; 402 403 #define MAX_REGULAR_DPM_NUM 16 404 struct mclk_latency_entries { 405 uint32_t frequency; 406 uint32_t latency; 407 }; 408 struct mclock_latency_table { 409 uint32_t count; 410 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 411 }; 412 413 enum smu_reset_mode { 414 SMU_RESET_MODE_0, 415 SMU_RESET_MODE_1, 416 SMU_RESET_MODE_2, 417 }; 418 419 enum smu_baco_state { 420 SMU_BACO_STATE_ENTER = 0, 421 SMU_BACO_STATE_EXIT, 422 }; 423 424 struct smu_baco_context { 425 uint32_t state; 426 bool platform_support; 427 bool maco_support; 428 }; 429 430 struct smu_freq_info { 431 uint32_t min; 432 uint32_t max; 433 uint32_t freq_level; 434 }; 435 436 struct pstates_clk_freq { 437 uint32_t min; 438 uint32_t standard; 439 uint32_t peak; 440 struct smu_freq_info custom; 441 struct smu_freq_info curr; 442 }; 443 444 struct smu_umd_pstate_table { 445 struct pstates_clk_freq gfxclk_pstate; 446 struct pstates_clk_freq socclk_pstate; 447 struct pstates_clk_freq uclk_pstate; 448 struct pstates_clk_freq vclk_pstate; 449 struct pstates_clk_freq dclk_pstate; 450 struct pstates_clk_freq fclk_pstate; 451 }; 452 453 struct cmn2asic_msg_mapping { 454 int valid_mapping; 455 int map_to; 456 int valid_in_vf; 457 }; 458 459 struct cmn2asic_mapping { 460 int valid_mapping; 461 int map_to; 462 }; 463 464 struct stb_context { 465 uint32_t stb_buf_size; 466 bool enabled; 467 spinlock_t lock; 468 }; 469 470 #define WORKLOAD_POLICY_MAX 7 471 472 struct smu_context { 473 struct amdgpu_device *adev; 474 struct amdgpu_irq_src irq_source; 475 476 const struct pptable_funcs *ppt_funcs; 477 const struct cmn2asic_msg_mapping *message_map; 478 const struct cmn2asic_mapping *clock_map; 479 const struct cmn2asic_mapping *feature_map; 480 const struct cmn2asic_mapping *table_map; 481 const struct cmn2asic_mapping *pwr_src_map; 482 const struct cmn2asic_mapping *workload_map; 483 struct mutex message_lock; 484 uint64_t pool_size; 485 486 struct smu_table_context smu_table; 487 struct smu_dpm_context smu_dpm; 488 struct smu_power_context smu_power; 489 struct smu_feature smu_feature; 490 struct amd_pp_display_configuration *display_config; 491 struct smu_baco_context smu_baco; 492 struct smu_temperature_range thermal_range; 493 void *od_settings; 494 495 struct smu_umd_pstate_table pstate_table; 496 uint32_t pstate_sclk; 497 uint32_t pstate_mclk; 498 499 bool od_enabled; 500 uint32_t current_power_limit; 501 uint32_t default_power_limit; 502 uint32_t max_power_limit; 503 uint32_t min_power_limit; 504 505 /* soft pptable */ 506 uint32_t ppt_offset_bytes; 507 uint32_t ppt_size_bytes; 508 uint8_t *ppt_start_addr; 509 510 bool support_power_containment; 511 bool disable_watermark; 512 513 #define WATERMARKS_EXIST (1 << 0) 514 #define WATERMARKS_LOADED (1 << 1) 515 uint32_t watermarks_bitmap; 516 uint32_t hard_min_uclk_req_from_dal; 517 bool disable_uclk_switch; 518 519 uint32_t workload_mask; 520 uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 521 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 522 uint32_t power_profile_mode; 523 uint32_t default_power_profile_mode; 524 bool pm_enabled; 525 bool is_apu; 526 527 uint32_t smc_driver_if_version; 528 uint32_t smc_fw_if_version; 529 uint32_t smc_fw_version; 530 531 bool uploading_custom_pp_table; 532 bool dc_controlled_by_gpio; 533 534 struct work_struct throttling_logging_work; 535 atomic64_t throttle_int_counter; 536 struct work_struct interrupt_work; 537 538 unsigned fan_max_rpm; 539 unsigned manual_fan_speed_pwm; 540 541 uint32_t gfx_default_hard_min_freq; 542 uint32_t gfx_default_soft_max_freq; 543 uint32_t gfx_actual_hard_min_freq; 544 uint32_t gfx_actual_soft_max_freq; 545 546 /* APU only */ 547 uint32_t cpu_default_soft_min_freq; 548 uint32_t cpu_default_soft_max_freq; 549 uint32_t cpu_actual_soft_min_freq; 550 uint32_t cpu_actual_soft_max_freq; 551 uint32_t cpu_core_id_select; 552 uint16_t cpu_core_num; 553 554 struct smu_user_dpm_profile user_dpm_profile; 555 556 struct stb_context stb_context; 557 558 struct firmware pptable_firmware; 559 560 u32 param_reg; 561 u32 msg_reg; 562 u32 resp_reg; 563 564 u32 debug_param_reg; 565 u32 debug_msg_reg; 566 u32 debug_resp_reg; 567 568 struct delayed_work swctf_delayed_work; 569 570 enum pp_xgmi_plpd_mode plpd_mode; 571 }; 572 573 struct i2c_adapter; 574 575 /** 576 * struct pptable_funcs - Callbacks used to interact with the SMU. 577 */ 578 struct pptable_funcs { 579 /** 580 * @run_btc: Calibrate voltage/frequency curve to fit the system's 581 * power delivery and voltage margins. Required for adaptive 582 * voltage frequency scaling (AVFS). 583 */ 584 int (*run_btc)(struct smu_context *smu); 585 586 /** 587 * @get_allowed_feature_mask: Get allowed feature mask. 588 * &feature_mask: Array to store feature mask. 589 * &num: Elements in &feature_mask. 590 */ 591 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 592 593 /** 594 * @get_current_power_state: Get the current power state. 595 * 596 * Return: Current power state on success, negative errno on failure. 597 */ 598 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 599 600 /** 601 * @set_default_dpm_table: Retrieve the default overdrive settings from 602 * the SMU. 603 */ 604 int (*set_default_dpm_table)(struct smu_context *smu); 605 606 int (*set_power_state)(struct smu_context *smu); 607 608 /** 609 * @populate_umd_state_clk: Populate the UMD power state table with 610 * defaults. 611 */ 612 int (*populate_umd_state_clk)(struct smu_context *smu); 613 614 /** 615 * @print_clk_levels: Print DPM clock levels for a clock domain 616 * to buffer. Star current level. 617 * 618 * Used for sysfs interfaces. 619 * Return: Number of characters written to the buffer 620 */ 621 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 622 623 /** 624 * @emit_clk_levels: Print DPM clock levels for a clock domain 625 * to buffer using sysfs_emit_at. Star current level. 626 * 627 * Used for sysfs interfaces. 628 * &buf: sysfs buffer 629 * &offset: offset within buffer to start printing, which is updated by the 630 * function. 631 * 632 * Return: 0 on Success or Negative to indicate an error occurred. 633 */ 634 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 635 636 /** 637 * @force_clk_levels: Set a range of allowed DPM levels for a clock 638 * domain. 639 * &clk_type: Clock domain. 640 * &mask: Range of allowed DPM levels. 641 */ 642 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 643 644 /** 645 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 646 * &type: Type of edit. 647 * &input: Edit parameters. 648 * &size: Size of &input. 649 */ 650 int (*od_edit_dpm_table)(struct smu_context *smu, 651 enum PP_OD_DPM_TABLE_COMMAND type, 652 long *input, uint32_t size); 653 654 /** 655 * @restore_user_od_settings: Restore the user customized 656 * OD settings on S3/S4/Runpm resume. 657 */ 658 int (*restore_user_od_settings)(struct smu_context *smu); 659 660 /** 661 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 662 * domain. 663 */ 664 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 665 enum smu_clk_type clk_type, 666 struct 667 pp_clock_levels_with_latency 668 *clocks); 669 /** 670 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 671 * domain. 672 */ 673 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 674 enum amd_pp_clock_type type, 675 struct 676 pp_clock_levels_with_voltage 677 *clocks); 678 679 /** 680 * @get_power_profile_mode: Print all power profile modes to 681 * buffer. Star current mode. 682 */ 683 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 684 685 /** 686 * @set_power_profile_mode: Set a power profile mode. Also used to 687 * create/set custom power profile modes. 688 * &input: Power profile mode parameters. 689 * &size: Size of &input. 690 */ 691 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 692 693 /** 694 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 695 * management. 696 */ 697 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 698 699 /** 700 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 701 * management. 702 */ 703 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 704 705 /** 706 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU 707 */ 708 int (*set_gfx_power_up_by_imu)(struct smu_context *smu); 709 710 /** 711 * @read_sensor: Read data from a sensor. 712 * &sensor: Sensor to read data from. 713 * &data: Sensor reading. 714 * &size: Size of &data. 715 */ 716 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 717 void *data, uint32_t *size); 718 719 /** 720 * @get_apu_thermal_limit: get apu core limit from smu 721 * &limit: current limit temperature in millidegrees Celsius 722 */ 723 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit); 724 725 /** 726 * @set_apu_thermal_limit: update all controllers with new limit 727 * &limit: limit temperature to be setted, in millidegrees Celsius 728 */ 729 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit); 730 731 /** 732 * @pre_display_config_changed: Prepare GPU for a display configuration 733 * change. 734 * 735 * Disable display tracking and pin memory clock speed to maximum. Used 736 * in display component synchronization. 737 */ 738 int (*pre_display_config_changed)(struct smu_context *smu); 739 740 /** 741 * @display_config_changed: Notify the SMU of the current display 742 * configuration. 743 * 744 * Allows SMU to properly track blanking periods for memory clock 745 * adjustment. Used in display component synchronization. 746 */ 747 int (*display_config_changed)(struct smu_context *smu); 748 749 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 750 751 /** 752 * @notify_smc_display_config: Applies display requirements to the 753 * current power state. 754 * 755 * Optimize deep sleep DCEFclk and mclk for the current display 756 * configuration. Used in display component synchronization. 757 */ 758 int (*notify_smc_display_config)(struct smu_context *smu); 759 760 /** 761 * @is_dpm_running: Check if DPM is running. 762 * 763 * Return: True if DPM is running, false otherwise. 764 */ 765 bool (*is_dpm_running)(struct smu_context *smu); 766 767 /** 768 * @get_fan_speed_pwm: Get the current fan speed in PWM. 769 */ 770 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 771 772 /** 773 * @get_fan_speed_rpm: Get the current fan speed in rpm. 774 */ 775 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 776 777 /** 778 * @set_watermarks_table: Configure and upload the watermarks tables to 779 * the SMU. 780 */ 781 int (*set_watermarks_table)(struct smu_context *smu, 782 struct pp_smu_wm_range_sets *clock_ranges); 783 784 /** 785 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 786 */ 787 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 788 789 /** 790 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 791 * &clocks_in_khz: Array of DPM levels. 792 * &num_states: Elements in &clocks_in_khz. 793 */ 794 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 795 796 /** 797 * @set_default_od_settings: Set the overdrive tables to defaults. 798 */ 799 int (*set_default_od_settings)(struct smu_context *smu); 800 801 /** 802 * @set_performance_level: Set a performance level. 803 */ 804 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 805 806 /** 807 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 808 * clock switching. 809 * 810 * Disabling this feature forces memory clock speed to maximum. 811 * Enabling sets the minimum memory clock capable of driving the 812 * current display configuration. 813 */ 814 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 815 816 /** 817 * @dump_pptable: Print the power play table to the system log. 818 */ 819 void (*dump_pptable)(struct smu_context *smu); 820 821 /** 822 * @get_power_limit: Get the device's power limits. 823 */ 824 int (*get_power_limit)(struct smu_context *smu, 825 uint32_t *current_power_limit, 826 uint32_t *default_power_limit, 827 uint32_t *max_power_limit, 828 uint32_t *min_power_limit); 829 830 /** 831 * @get_ppt_limit: Get the device's ppt limits. 832 */ 833 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 834 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 835 836 /** 837 * @set_df_cstate: Set data fabric cstate. 838 */ 839 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 840 841 /** 842 * @select_xgmi_plpd_policy: Select xgmi per-link power down policy. 843 */ 844 int (*select_xgmi_plpd_policy)(struct smu_context *smu, 845 enum pp_xgmi_plpd_mode mode); 846 847 /** 848 * @update_pcie_parameters: Update and upload the system's PCIe 849 * capabilites to the SMU. 850 * &pcie_gen_cap: Maximum allowed PCIe generation. 851 * &pcie_width_cap: Maximum allowed PCIe width. 852 */ 853 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap); 854 855 /** 856 * @i2c_init: Initialize i2c. 857 * 858 * The i2c bus is used internally by the SMU voltage regulators and 859 * other devices. The i2c's EEPROM also stores bad page tables on boards 860 * with ECC. 861 */ 862 int (*i2c_init)(struct smu_context *smu); 863 864 /** 865 * @i2c_fini: Tear down i2c. 866 */ 867 void (*i2c_fini)(struct smu_context *smu); 868 869 /** 870 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 871 */ 872 void (*get_unique_id)(struct smu_context *smu); 873 874 /** 875 * @get_dpm_clock_table: Get a copy of the DPM clock table. 876 * 877 * Used by display component in bandwidth and watermark calculations. 878 */ 879 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 880 881 /** 882 * @init_microcode: Request the SMU's firmware from the kernel. 883 */ 884 int (*init_microcode)(struct smu_context *smu); 885 886 /** 887 * @load_microcode: Load firmware onto the SMU. 888 */ 889 int (*load_microcode)(struct smu_context *smu); 890 891 /** 892 * @fini_microcode: Release the SMU's firmware. 893 */ 894 void (*fini_microcode)(struct smu_context *smu); 895 896 /** 897 * @init_smc_tables: Initialize the SMU tables. 898 */ 899 int (*init_smc_tables)(struct smu_context *smu); 900 901 /** 902 * @fini_smc_tables: Release the SMU tables. 903 */ 904 int (*fini_smc_tables)(struct smu_context *smu); 905 906 /** 907 * @init_power: Initialize the power gate table context. 908 */ 909 int (*init_power)(struct smu_context *smu); 910 911 /** 912 * @fini_power: Release the power gate table context. 913 */ 914 int (*fini_power)(struct smu_context *smu); 915 916 /** 917 * @check_fw_status: Check the SMU's firmware status. 918 * 919 * Return: Zero if check passes, negative errno on failure. 920 */ 921 int (*check_fw_status)(struct smu_context *smu); 922 923 /** 924 * @set_mp1_state: put SMU into a correct state for comming 925 * resume from runpm or gpu reset. 926 */ 927 int (*set_mp1_state)(struct smu_context *smu, 928 enum pp_mp1_state mp1_state); 929 930 /** 931 * @setup_pptable: Initialize the power play table and populate it with 932 * default values. 933 */ 934 int (*setup_pptable)(struct smu_context *smu); 935 936 /** 937 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 938 */ 939 int (*get_vbios_bootup_values)(struct smu_context *smu); 940 941 /** 942 * @check_fw_version: Print driver and SMU interface versions to the 943 * system log. 944 * 945 * Interface mismatch is not a critical failure. 946 */ 947 int (*check_fw_version)(struct smu_context *smu); 948 949 /** 950 * @powergate_sdma: Power up/down system direct memory access. 951 */ 952 int (*powergate_sdma)(struct smu_context *smu, bool gate); 953 954 /** 955 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 956 * gating. 957 */ 958 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 959 960 /** 961 * @write_pptable: Write the power play table to the SMU. 962 */ 963 int (*write_pptable)(struct smu_context *smu); 964 965 /** 966 * @set_driver_table_location: Send the location of the driver table to 967 * the SMU. 968 */ 969 int (*set_driver_table_location)(struct smu_context *smu); 970 971 /** 972 * @set_tool_table_location: Send the location of the tool table to the 973 * SMU. 974 */ 975 int (*set_tool_table_location)(struct smu_context *smu); 976 977 /** 978 * @notify_memory_pool_location: Send the location of the memory pool to 979 * the SMU. 980 */ 981 int (*notify_memory_pool_location)(struct smu_context *smu); 982 983 /** 984 * @system_features_control: Enable/disable all SMU features. 985 */ 986 int (*system_features_control)(struct smu_context *smu, bool en); 987 988 /** 989 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 990 * &msg: Type of message. 991 * ¶m: Message parameter. 992 * &read_arg: SMU response (optional). 993 */ 994 int (*send_smc_msg_with_param)(struct smu_context *smu, 995 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 996 997 /** 998 * @send_smc_msg: Send a message to the SMU. 999 * &msg: Type of message. 1000 * &read_arg: SMU response (optional). 1001 */ 1002 int (*send_smc_msg)(struct smu_context *smu, 1003 enum smu_message_type msg, 1004 uint32_t *read_arg); 1005 1006 /** 1007 * @init_display_count: Notify the SMU of the number of display 1008 * components in current display configuration. 1009 */ 1010 int (*init_display_count)(struct smu_context *smu, uint32_t count); 1011 1012 /** 1013 * @set_allowed_mask: Notify the SMU of the features currently allowed 1014 * by the driver. 1015 */ 1016 int (*set_allowed_mask)(struct smu_context *smu); 1017 1018 /** 1019 * @get_enabled_mask: Get a mask of features that are currently enabled 1020 * on the SMU. 1021 * &feature_mask: Enabled feature mask. 1022 */ 1023 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1024 1025 /** 1026 * @feature_is_enabled: Test if a feature is enabled. 1027 * 1028 * Return: One if enabled, zero if disabled. 1029 */ 1030 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1031 1032 /** 1033 * @disable_all_features_with_exception: Disable all features with 1034 * exception to those in &mask. 1035 */ 1036 int (*disable_all_features_with_exception)(struct smu_context *smu, 1037 enum smu_feature_mask mask); 1038 1039 /** 1040 * @notify_display_change: General interface call to let SMU know about DC change 1041 */ 1042 int (*notify_display_change)(struct smu_context *smu); 1043 1044 /** 1045 * @set_power_limit: Set power limit in watts. 1046 */ 1047 int (*set_power_limit)(struct smu_context *smu, 1048 enum smu_ppt_limit_type limit_type, 1049 uint32_t limit); 1050 1051 /** 1052 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1053 * table with values from the SMU. 1054 */ 1055 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1056 1057 /** 1058 * @enable_thermal_alert: Enable thermal alert interrupts. 1059 */ 1060 int (*enable_thermal_alert)(struct smu_context *smu); 1061 1062 /** 1063 * @disable_thermal_alert: Disable thermal alert interrupts. 1064 */ 1065 int (*disable_thermal_alert)(struct smu_context *smu); 1066 1067 /** 1068 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1069 * clock speed in MHz. 1070 */ 1071 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1072 1073 /** 1074 * @display_clock_voltage_request: Set a hard minimum frequency 1075 * for a clock domain. 1076 */ 1077 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1078 pp_display_clock_request 1079 *clock_req); 1080 1081 /** 1082 * @get_fan_control_mode: Get the current fan control mode. 1083 */ 1084 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1085 1086 /** 1087 * @set_fan_control_mode: Set the fan control mode. 1088 */ 1089 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1090 1091 /** 1092 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1093 */ 1094 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1095 1096 /** 1097 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1098 */ 1099 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1100 1101 /** 1102 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1103 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1104 */ 1105 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1106 1107 /** 1108 * @gfx_off_control: Enable/disable graphics engine poweroff. 1109 */ 1110 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1111 1112 1113 /** 1114 * @get_gfx_off_status: Get graphics engine poweroff status. 1115 * 1116 * Return: 1117 * 0 - GFXOFF(default). 1118 * 1 - Transition out of GFX State. 1119 * 2 - Not in GFXOFF. 1120 * 3 - Transition into GFXOFF. 1121 */ 1122 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1123 1124 /** 1125 * @gfx_off_entrycount: total GFXOFF entry count at the time of 1126 * query since system power-up 1127 */ 1128 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount); 1129 1130 /** 1131 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging 1132 */ 1133 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); 1134 1135 /** 1136 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval 1137 */ 1138 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency); 1139 1140 /** 1141 * @register_irq_handler: Register interupt request handlers. 1142 */ 1143 int (*register_irq_handler)(struct smu_context *smu); 1144 1145 /** 1146 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1147 */ 1148 int (*set_azalia_d3_pme)(struct smu_context *smu); 1149 1150 /** 1151 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1152 * clock speeds table. 1153 * 1154 * Provides a way for the display component (DC) to get the max 1155 * sustainable clocks from the SMU. 1156 */ 1157 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1158 1159 /** 1160 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off). 1161 */ 1162 bool (*baco_is_support)(struct smu_context *smu); 1163 1164 /** 1165 * @baco_get_state: Get the current BACO state. 1166 * 1167 * Return: Current BACO state. 1168 */ 1169 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1170 1171 /** 1172 * @baco_set_state: Enter/exit BACO. 1173 */ 1174 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1175 1176 /** 1177 * @baco_enter: Enter BACO. 1178 */ 1179 int (*baco_enter)(struct smu_context *smu); 1180 1181 /** 1182 * @baco_exit: Exit Baco. 1183 */ 1184 int (*baco_exit)(struct smu_context *smu); 1185 1186 /** 1187 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1188 */ 1189 bool (*mode1_reset_is_support)(struct smu_context *smu); 1190 /** 1191 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1192 */ 1193 bool (*mode2_reset_is_support)(struct smu_context *smu); 1194 1195 /** 1196 * @mode1_reset: Perform mode1 reset. 1197 * 1198 * Complete GPU reset. 1199 */ 1200 int (*mode1_reset)(struct smu_context *smu); 1201 1202 /** 1203 * @mode2_reset: Perform mode2 reset. 1204 * 1205 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1206 * IPs reset varies by asic. 1207 */ 1208 int (*mode2_reset)(struct smu_context *smu); 1209 /* for gfx feature enablement after mode2 reset */ 1210 int (*enable_gfx_features)(struct smu_context *smu); 1211 1212 /** 1213 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1214 * domain in MHz. 1215 */ 1216 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1217 1218 /** 1219 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1220 * domain in MHz. 1221 */ 1222 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 1223 1224 /** 1225 * @set_power_source: Notify the SMU of the current power source. 1226 */ 1227 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1228 1229 /** 1230 * @log_thermal_throttling_event: Print a thermal throttling warning to 1231 * the system's log. 1232 */ 1233 void (*log_thermal_throttling_event)(struct smu_context *smu); 1234 1235 /** 1236 * @get_pp_feature_mask: Print a human readable table of enabled 1237 * features to buffer. 1238 */ 1239 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1240 1241 /** 1242 * @set_pp_feature_mask: Request the SMU enable/disable features to 1243 * match those enabled in &new_mask. 1244 */ 1245 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1246 1247 /** 1248 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1249 * 1250 * Return: Size of &table 1251 */ 1252 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1253 1254 /** 1255 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1256 */ 1257 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1258 1259 /** 1260 * @gfx_ulv_control: Enable/disable ultra low voltage. 1261 */ 1262 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1263 1264 /** 1265 * @deep_sleep_control: Enable/disable deep sleep. 1266 */ 1267 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1268 1269 /** 1270 * @get_fan_parameters: Get fan parameters. 1271 * 1272 * Get maximum fan speed from the power play table. 1273 */ 1274 int (*get_fan_parameters)(struct smu_context *smu); 1275 1276 /** 1277 * @post_init: Helper function for asic specific workarounds. 1278 */ 1279 int (*post_init)(struct smu_context *smu); 1280 1281 /** 1282 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1283 */ 1284 void (*interrupt_work)(struct smu_context *smu); 1285 1286 /** 1287 * @gpo_control: Enable/disable graphics power optimization if supported. 1288 */ 1289 int (*gpo_control)(struct smu_context *smu, bool enablement); 1290 1291 /** 1292 * @gfx_state_change_set: Send the current graphics state to the SMU. 1293 */ 1294 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1295 1296 /** 1297 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1298 * parameters to defaults. 1299 */ 1300 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1301 1302 /** 1303 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1304 */ 1305 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1306 1307 /** 1308 * @wait_for_event: Wait for events from SMU. 1309 */ 1310 int (*wait_for_event)(struct smu_context *smu, 1311 enum smu_event_type event, uint64_t event_arg); 1312 1313 /** 1314 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1315 * of SMUBUS table. 1316 */ 1317 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1318 1319 /** 1320 * @get_ecc_table: message SMU to get ECC INFO table. 1321 */ 1322 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1323 1324 1325 /** 1326 * @stb_collect_info: Collects Smart Trace Buffers data. 1327 */ 1328 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1329 1330 /** 1331 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1332 */ 1333 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1334 1335 /** 1336 * @set_config_table: Apply the input DriverSmuConfig table settings. 1337 */ 1338 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1339 1340 /** 1341 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1342 * of SMUBUS table. 1343 */ 1344 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1345 1346 /** 1347 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP 1348 */ 1349 int (*init_pptable_microcode)(struct smu_context *smu); 1350 1351 /** 1352 * @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power 1353 * management. 1354 */ 1355 int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable); 1356 1357 /** 1358 * @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power 1359 * management. 1360 */ 1361 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable); 1362 }; 1363 1364 typedef enum { 1365 METRICS_CURR_GFXCLK, 1366 METRICS_CURR_SOCCLK, 1367 METRICS_CURR_UCLK, 1368 METRICS_CURR_VCLK, 1369 METRICS_CURR_VCLK1, 1370 METRICS_CURR_DCLK, 1371 METRICS_CURR_DCLK1, 1372 METRICS_CURR_FCLK, 1373 METRICS_CURR_DCEFCLK, 1374 METRICS_AVERAGE_CPUCLK, 1375 METRICS_AVERAGE_GFXCLK, 1376 METRICS_AVERAGE_SOCCLK, 1377 METRICS_AVERAGE_FCLK, 1378 METRICS_AVERAGE_UCLK, 1379 METRICS_AVERAGE_VCLK, 1380 METRICS_AVERAGE_DCLK, 1381 METRICS_AVERAGE_VCLK1, 1382 METRICS_AVERAGE_DCLK1, 1383 METRICS_AVERAGE_GFXACTIVITY, 1384 METRICS_AVERAGE_MEMACTIVITY, 1385 METRICS_AVERAGE_VCNACTIVITY, 1386 METRICS_AVERAGE_SOCKETPOWER, 1387 METRICS_TEMPERATURE_EDGE, 1388 METRICS_TEMPERATURE_HOTSPOT, 1389 METRICS_TEMPERATURE_MEM, 1390 METRICS_TEMPERATURE_VRGFX, 1391 METRICS_TEMPERATURE_VRSOC, 1392 METRICS_TEMPERATURE_VRMEM, 1393 METRICS_THROTTLER_STATUS, 1394 METRICS_CURR_FANSPEED, 1395 METRICS_VOLTAGE_VDDSOC, 1396 METRICS_VOLTAGE_VDDGFX, 1397 METRICS_SS_APU_SHARE, 1398 METRICS_SS_DGPU_SHARE, 1399 METRICS_UNIQUE_ID_UPPER32, 1400 METRICS_UNIQUE_ID_LOWER32, 1401 METRICS_PCIE_RATE, 1402 METRICS_PCIE_WIDTH, 1403 METRICS_CURR_FANPWM, 1404 METRICS_CURR_SOCKETPOWER, 1405 } MetricsMember_t; 1406 1407 enum smu_cmn2asic_mapping_type { 1408 CMN2ASIC_MAPPING_MSG, 1409 CMN2ASIC_MAPPING_CLK, 1410 CMN2ASIC_MAPPING_FEATURE, 1411 CMN2ASIC_MAPPING_TABLE, 1412 CMN2ASIC_MAPPING_PWR, 1413 CMN2ASIC_MAPPING_WORKLOAD, 1414 }; 1415 1416 enum smu_baco_seq { 1417 BACO_SEQ_BACO = 0, 1418 BACO_SEQ_MSR, 1419 BACO_SEQ_BAMACO, 1420 BACO_SEQ_ULPS, 1421 BACO_SEQ_COUNT, 1422 }; 1423 1424 #define MSG_MAP(msg, index, valid_in_vf) \ 1425 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)} 1426 1427 #define CLK_MAP(clk, index) \ 1428 [SMU_##clk] = {1, (index)} 1429 1430 #define FEA_MAP(fea) \ 1431 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1432 1433 #define FEA_MAP_REVERSE(fea) \ 1434 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1435 1436 #define FEA_MAP_HALF_REVERSE(fea) \ 1437 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1438 1439 #define TAB_MAP(tab) \ 1440 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1441 1442 #define TAB_MAP_VALID(tab) \ 1443 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1444 1445 #define TAB_MAP_INVALID(tab) \ 1446 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1447 1448 #define PWR_MAP(tab) \ 1449 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1450 1451 #define WORKLOAD_MAP(profile, workload) \ 1452 [profile] = {1, (workload)} 1453 1454 /** 1455 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1456 * 1457 * @dst: Pointer to destination struct 1458 * @first_dst_member: The member name in @dst where the overwrite begins 1459 * @last_dst_member: The member name in @dst where the overwrite ends after 1460 * @src: Pointer to the source struct 1461 * @first_src_member: The member name in @src where the copy begins 1462 * 1463 */ 1464 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1465 src, first_src_member) \ 1466 ({ \ 1467 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1468 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1469 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1470 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1471 __dst_offset; \ 1472 BUILD_BUG_ON(__src_size != __dst_size); \ 1473 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1474 (u8 *)(src) + __src_offset, \ 1475 __dst_size); \ 1476 }) 1477 1478 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1479 int smu_get_power_limit(void *handle, 1480 uint32_t *limit, 1481 enum pp_power_limit_level pp_limit_level, 1482 enum pp_power_type pp_power_type); 1483 1484 bool smu_mode1_reset_is_support(struct smu_context *smu); 1485 bool smu_mode2_reset_is_support(struct smu_context *smu); 1486 int smu_mode1_reset(struct smu_context *smu); 1487 1488 extern const struct amd_ip_funcs smu_ip_funcs; 1489 1490 bool is_support_sw_smu(struct amdgpu_device *adev); 1491 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1492 int smu_write_watermarks_table(struct smu_context *smu); 1493 1494 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1495 uint32_t *min, uint32_t *max); 1496 1497 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1498 uint32_t min, uint32_t max); 1499 1500 int smu_set_gfx_power_up_by_imu(struct smu_context *smu); 1501 1502 int smu_set_ac_dc(struct smu_context *smu); 1503 1504 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 1505 enum pp_xgmi_plpd_mode mode); 1506 1507 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); 1508 1509 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); 1510 1511 int smu_set_residency_gfxoff(struct smu_context *smu, bool value); 1512 1513 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1514 1515 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1516 1517 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1518 uint64_t event_arg); 1519 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1520 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1521 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1522 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1523 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1524 #endif 1525 #endif 1526