1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include <linux/acpi_amd_wbrf.h> 26 #include <linux/units.h> 27 28 #include "amdgpu.h" 29 #include "kgd_pp_interface.h" 30 #include "dm_pp_interface.h" 31 #include "dm_pp_smu.h" 32 #include "smu_types.h" 33 #include "linux/firmware.h" 34 35 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 36 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 37 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 38 #define SMU_FW_NAME_LEN 0x24 39 40 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 41 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 42 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 43 44 // Power Throttlers 45 #define SMU_THROTTLER_PPT0_BIT 0 46 #define SMU_THROTTLER_PPT1_BIT 1 47 #define SMU_THROTTLER_PPT2_BIT 2 48 #define SMU_THROTTLER_PPT3_BIT 3 49 #define SMU_THROTTLER_SPL_BIT 4 50 #define SMU_THROTTLER_FPPT_BIT 5 51 #define SMU_THROTTLER_SPPT_BIT 6 52 #define SMU_THROTTLER_SPPT_APU_BIT 7 53 54 // Current Throttlers 55 #define SMU_THROTTLER_TDC_GFX_BIT 16 56 #define SMU_THROTTLER_TDC_SOC_BIT 17 57 #define SMU_THROTTLER_TDC_MEM_BIT 18 58 #define SMU_THROTTLER_TDC_VDD_BIT 19 59 #define SMU_THROTTLER_TDC_CVIP_BIT 20 60 #define SMU_THROTTLER_EDC_CPU_BIT 21 61 #define SMU_THROTTLER_EDC_GFX_BIT 22 62 #define SMU_THROTTLER_APCC_BIT 23 63 64 // Temperature 65 #define SMU_THROTTLER_TEMP_GPU_BIT 32 66 #define SMU_THROTTLER_TEMP_CORE_BIT 33 67 #define SMU_THROTTLER_TEMP_MEM_BIT 34 68 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 69 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 70 #define SMU_THROTTLER_TEMP_SOC_BIT 37 71 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 72 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 73 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 74 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 75 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 76 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 77 #define SMU_THROTTLER_VRHOT0_BIT 44 78 #define SMU_THROTTLER_VRHOT1_BIT 45 79 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 80 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 81 82 // Other 83 #define SMU_THROTTLER_PPM_BIT 56 84 #define SMU_THROTTLER_FIT_BIT 57 85 86 struct smu_hw_power_state { 87 unsigned int magic; 88 }; 89 90 struct smu_power_state; 91 92 enum smu_state_ui_label { 93 SMU_STATE_UI_LABEL_NONE, 94 SMU_STATE_UI_LABEL_BATTERY, 95 SMU_STATE_UI_TABEL_MIDDLE_LOW, 96 SMU_STATE_UI_LABEL_BALLANCED, 97 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 98 SMU_STATE_UI_LABEL_PERFORMANCE, 99 SMU_STATE_UI_LABEL_BACO, 100 }; 101 102 enum smu_state_classification_flag { 103 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 104 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 105 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 106 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 107 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 108 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 109 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 111 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 112 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 113 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 114 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 115 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 116 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 117 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 118 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 119 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 120 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 121 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 122 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 123 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 124 }; 125 126 struct smu_state_classification_block { 127 enum smu_state_ui_label ui_label; 128 enum smu_state_classification_flag flags; 129 int bios_index; 130 bool temporary_state; 131 bool to_be_deleted; 132 }; 133 134 struct smu_state_pcie_block { 135 unsigned int lanes; 136 }; 137 138 enum smu_refreshrate_source { 139 SMU_REFRESHRATE_SOURCE_EDID, 140 SMU_REFRESHRATE_SOURCE_EXPLICIT 141 }; 142 143 struct smu_state_display_block { 144 bool disable_frame_modulation; 145 bool limit_refreshrate; 146 enum smu_refreshrate_source refreshrate_source; 147 int explicit_refreshrate; 148 int edid_refreshrate_index; 149 bool enable_vari_bright; 150 }; 151 152 struct smu_state_memory_block { 153 bool dll_off; 154 uint8_t m3arb; 155 uint8_t unused[3]; 156 }; 157 158 struct smu_state_software_algorithm_block { 159 bool disable_load_balancing; 160 bool enable_sleep_for_timestamps; 161 }; 162 163 struct smu_temperature_range { 164 int min; 165 int max; 166 int edge_emergency_max; 167 int hotspot_min; 168 int hotspot_crit_max; 169 int hotspot_emergency_max; 170 int mem_min; 171 int mem_crit_max; 172 int mem_emergency_max; 173 int software_shutdown_temp; 174 int software_shutdown_temp_offset; 175 }; 176 177 struct smu_state_validation_block { 178 bool single_display_only; 179 bool disallow_on_dc; 180 uint8_t supported_power_levels; 181 }; 182 183 struct smu_uvd_clocks { 184 uint32_t vclk; 185 uint32_t dclk; 186 }; 187 188 /** 189 * Structure to hold a SMU Power State. 190 */ 191 struct smu_power_state { 192 uint32_t id; 193 struct list_head ordered_list; 194 struct list_head all_states_list; 195 196 struct smu_state_classification_block classification; 197 struct smu_state_validation_block validation; 198 struct smu_state_pcie_block pcie; 199 struct smu_state_display_block display; 200 struct smu_state_memory_block memory; 201 struct smu_state_software_algorithm_block software; 202 struct smu_uvd_clocks uvd_clocks; 203 struct smu_hw_power_state hardware; 204 }; 205 206 enum smu_power_src_type { 207 SMU_POWER_SOURCE_AC, 208 SMU_POWER_SOURCE_DC, 209 SMU_POWER_SOURCE_COUNT, 210 }; 211 212 enum smu_ppt_limit_type { 213 SMU_DEFAULT_PPT_LIMIT = 0, 214 SMU_FAST_PPT_LIMIT, 215 }; 216 217 enum smu_ppt_limit_level { 218 SMU_PPT_LIMIT_MIN = -1, 219 SMU_PPT_LIMIT_CURRENT, 220 SMU_PPT_LIMIT_DEFAULT, 221 SMU_PPT_LIMIT_MAX, 222 }; 223 224 enum smu_memory_pool_size { 225 SMU_MEMORY_POOL_SIZE_ZERO = 0, 226 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 227 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 228 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 229 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 230 }; 231 232 struct smu_user_dpm_profile { 233 uint32_t fan_mode; 234 uint32_t power_limit; 235 uint32_t fan_speed_pwm; 236 uint32_t fan_speed_rpm; 237 uint32_t flags; 238 uint32_t user_od; 239 240 /* user clock state information */ 241 uint32_t clk_mask[SMU_CLK_COUNT]; 242 uint32_t clk_dependency; 243 }; 244 245 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 246 do { \ 247 tables[table_id].size = s; \ 248 tables[table_id].align = a; \ 249 tables[table_id].domain = d; \ 250 } while (0) 251 252 struct smu_table { 253 uint64_t size; 254 uint32_t align; 255 uint8_t domain; 256 uint64_t mc_address; 257 void *cpu_addr; 258 struct amdgpu_bo *bo; 259 uint32_t version; 260 }; 261 262 enum smu_perf_level_designation { 263 PERF_LEVEL_ACTIVITY, 264 PERF_LEVEL_POWER_CONTAINMENT, 265 }; 266 267 struct smu_performance_level { 268 uint32_t core_clock; 269 uint32_t memory_clock; 270 uint32_t vddc; 271 uint32_t vddci; 272 uint32_t non_local_mem_freq; 273 uint32_t non_local_mem_width; 274 }; 275 276 struct smu_clock_info { 277 uint32_t min_mem_clk; 278 uint32_t max_mem_clk; 279 uint32_t min_eng_clk; 280 uint32_t max_eng_clk; 281 uint32_t min_bus_bandwidth; 282 uint32_t max_bus_bandwidth; 283 }; 284 285 struct smu_bios_boot_up_values { 286 uint32_t revision; 287 uint32_t gfxclk; 288 uint32_t uclk; 289 uint32_t socclk; 290 uint32_t dcefclk; 291 uint32_t eclk; 292 uint32_t vclk; 293 uint32_t dclk; 294 uint16_t vddc; 295 uint16_t vddci; 296 uint16_t mvddc; 297 uint16_t vdd_gfx; 298 uint8_t cooling_id; 299 uint32_t pp_table_id; 300 uint32_t format_revision; 301 uint32_t content_revision; 302 uint32_t fclk; 303 uint32_t lclk; 304 uint32_t firmware_caps; 305 }; 306 307 enum smu_table_id { 308 SMU_TABLE_PPTABLE = 0, 309 SMU_TABLE_WATERMARKS, 310 SMU_TABLE_CUSTOM_DPM, 311 SMU_TABLE_DPMCLOCKS, 312 SMU_TABLE_AVFS, 313 SMU_TABLE_AVFS_PSM_DEBUG, 314 SMU_TABLE_AVFS_FUSE_OVERRIDE, 315 SMU_TABLE_PMSTATUSLOG, 316 SMU_TABLE_SMU_METRICS, 317 SMU_TABLE_DRIVER_SMU_CONFIG, 318 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 319 SMU_TABLE_OVERDRIVE, 320 SMU_TABLE_I2C_COMMANDS, 321 SMU_TABLE_PACE, 322 SMU_TABLE_ECCINFO, 323 SMU_TABLE_COMBO_PPTABLE, 324 SMU_TABLE_WIFIBAND, 325 SMU_TABLE_COUNT, 326 }; 327 328 struct smu_table_context { 329 void *power_play_table; 330 uint32_t power_play_table_size; 331 void *hardcode_pptable; 332 unsigned long metrics_time; 333 void *metrics_table; 334 void *clocks_table; 335 void *watermarks_table; 336 337 void *max_sustainable_clocks; 338 struct smu_bios_boot_up_values boot_values; 339 void *driver_pptable; 340 void *combo_pptable; 341 void *ecc_table; 342 void *driver_smu_config_table; 343 struct smu_table tables[SMU_TABLE_COUNT]; 344 /* 345 * The driver table is just a staging buffer for 346 * uploading/downloading content from the SMU. 347 * 348 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 349 * SMU_MSG_TransferTableDram2Smu instructs SMU 350 * which content driver is interested. 351 */ 352 struct smu_table driver_table; 353 struct smu_table memory_pool; 354 struct smu_table dummy_read_1_table; 355 uint8_t thermal_controller_type; 356 357 void *overdrive_table; 358 void *boot_overdrive_table; 359 void *user_overdrive_table; 360 361 uint32_t gpu_metrics_table_size; 362 void *gpu_metrics_table; 363 }; 364 365 struct smu_context; 366 struct smu_dpm_policy; 367 368 struct smu_dpm_policy_desc { 369 const char *name; 370 char *(*get_desc)(struct smu_dpm_policy *dpm_policy, int level); 371 }; 372 373 struct smu_dpm_policy { 374 struct smu_dpm_policy_desc *desc; 375 enum pp_pm_policy policy_type; 376 unsigned long level_mask; 377 int current_level; 378 int (*set_policy)(struct smu_context *ctxt, int level); 379 }; 380 381 struct smu_dpm_policy_ctxt { 382 struct smu_dpm_policy policies[PP_PM_POLICY_NUM]; 383 unsigned long policy_mask; 384 }; 385 386 struct smu_dpm_context { 387 uint32_t dpm_context_size; 388 void *dpm_context; 389 void *golden_dpm_context; 390 enum amd_dpm_forced_level dpm_level; 391 enum amd_dpm_forced_level saved_dpm_level; 392 enum amd_dpm_forced_level requested_dpm_level; 393 struct smu_power_state *dpm_request_power_state; 394 struct smu_power_state *dpm_current_power_state; 395 struct mclock_latency_table *mclk_latency_table; 396 struct smu_dpm_policy_ctxt *dpm_policies; 397 }; 398 399 struct smu_power_gate { 400 bool uvd_gated; 401 bool vce_gated; 402 atomic_t vcn_gated; 403 atomic_t jpeg_gated; 404 atomic_t vpe_gated; 405 atomic_t umsch_mm_gated; 406 }; 407 408 struct smu_power_context { 409 void *power_context; 410 uint32_t power_context_size; 411 struct smu_power_gate power_gate; 412 }; 413 414 #define SMU_FEATURE_MAX (64) 415 struct smu_feature { 416 uint32_t feature_num; 417 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 418 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 419 }; 420 421 struct smu_clocks { 422 uint32_t engine_clock; 423 uint32_t memory_clock; 424 uint32_t bus_bandwidth; 425 uint32_t engine_clock_in_sr; 426 uint32_t dcef_clock; 427 uint32_t dcef_clock_in_sr; 428 }; 429 430 #define MAX_REGULAR_DPM_NUM 16 431 struct mclk_latency_entries { 432 uint32_t frequency; 433 uint32_t latency; 434 }; 435 struct mclock_latency_table { 436 uint32_t count; 437 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 438 }; 439 440 enum smu_reset_mode { 441 SMU_RESET_MODE_0, 442 SMU_RESET_MODE_1, 443 SMU_RESET_MODE_2, 444 }; 445 446 enum smu_baco_state { 447 SMU_BACO_STATE_ENTER = 0, 448 SMU_BACO_STATE_EXIT, 449 SMU_BACO_STATE_NONE, 450 }; 451 452 struct smu_baco_context { 453 uint32_t state; 454 bool platform_support; 455 bool maco_support; 456 }; 457 458 struct smu_freq_info { 459 uint32_t min; 460 uint32_t max; 461 uint32_t freq_level; 462 }; 463 464 struct pstates_clk_freq { 465 uint32_t min; 466 uint32_t standard; 467 uint32_t peak; 468 struct smu_freq_info custom; 469 struct smu_freq_info curr; 470 }; 471 472 struct smu_umd_pstate_table { 473 struct pstates_clk_freq gfxclk_pstate; 474 struct pstates_clk_freq socclk_pstate; 475 struct pstates_clk_freq uclk_pstate; 476 struct pstates_clk_freq vclk_pstate; 477 struct pstates_clk_freq dclk_pstate; 478 struct pstates_clk_freq fclk_pstate; 479 }; 480 481 struct cmn2asic_msg_mapping { 482 int valid_mapping; 483 int map_to; 484 uint32_t flags; 485 }; 486 487 struct cmn2asic_mapping { 488 int valid_mapping; 489 int map_to; 490 }; 491 492 struct stb_context { 493 uint32_t stb_buf_size; 494 bool enabled; 495 spinlock_t lock; 496 }; 497 498 #define WORKLOAD_POLICY_MAX 7 499 500 /* 501 * Configure wbrf event handling pace as there can be only one 502 * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms. 503 */ 504 #define SMU_WBRF_EVENT_HANDLING_PACE 10 505 506 struct smu_context { 507 struct amdgpu_device *adev; 508 struct amdgpu_irq_src irq_source; 509 510 const struct pptable_funcs *ppt_funcs; 511 const struct cmn2asic_msg_mapping *message_map; 512 const struct cmn2asic_mapping *clock_map; 513 const struct cmn2asic_mapping *feature_map; 514 const struct cmn2asic_mapping *table_map; 515 const struct cmn2asic_mapping *pwr_src_map; 516 const struct cmn2asic_mapping *workload_map; 517 struct mutex message_lock; 518 uint64_t pool_size; 519 520 struct smu_table_context smu_table; 521 struct smu_dpm_context smu_dpm; 522 struct smu_power_context smu_power; 523 struct smu_feature smu_feature; 524 struct amd_pp_display_configuration *display_config; 525 struct smu_baco_context smu_baco; 526 struct smu_temperature_range thermal_range; 527 void *od_settings; 528 529 struct smu_umd_pstate_table pstate_table; 530 uint32_t pstate_sclk; 531 uint32_t pstate_mclk; 532 533 bool od_enabled; 534 uint32_t current_power_limit; 535 uint32_t default_power_limit; 536 uint32_t max_power_limit; 537 uint32_t min_power_limit; 538 539 /* soft pptable */ 540 uint32_t ppt_offset_bytes; 541 uint32_t ppt_size_bytes; 542 uint8_t *ppt_start_addr; 543 544 bool support_power_containment; 545 bool disable_watermark; 546 547 #define WATERMARKS_EXIST (1 << 0) 548 #define WATERMARKS_LOADED (1 << 1) 549 uint32_t watermarks_bitmap; 550 uint32_t hard_min_uclk_req_from_dal; 551 bool disable_uclk_switch; 552 553 uint32_t workload_mask; 554 uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 555 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 556 uint32_t power_profile_mode; 557 uint32_t default_power_profile_mode; 558 bool pm_enabled; 559 bool is_apu; 560 561 uint32_t smc_driver_if_version; 562 uint32_t smc_fw_if_version; 563 uint32_t smc_fw_version; 564 uint32_t smc_fw_caps; 565 566 bool uploading_custom_pp_table; 567 bool dc_controlled_by_gpio; 568 569 struct work_struct throttling_logging_work; 570 atomic64_t throttle_int_counter; 571 struct work_struct interrupt_work; 572 573 unsigned fan_max_rpm; 574 unsigned manual_fan_speed_pwm; 575 576 uint32_t gfx_default_hard_min_freq; 577 uint32_t gfx_default_soft_max_freq; 578 uint32_t gfx_actual_hard_min_freq; 579 uint32_t gfx_actual_soft_max_freq; 580 581 /* APU only */ 582 uint32_t cpu_default_soft_min_freq; 583 uint32_t cpu_default_soft_max_freq; 584 uint32_t cpu_actual_soft_min_freq; 585 uint32_t cpu_actual_soft_max_freq; 586 uint32_t cpu_core_id_select; 587 uint16_t cpu_core_num; 588 589 struct smu_user_dpm_profile user_dpm_profile; 590 591 struct stb_context stb_context; 592 593 struct firmware pptable_firmware; 594 595 u32 param_reg; 596 u32 msg_reg; 597 u32 resp_reg; 598 599 u32 debug_param_reg; 600 u32 debug_msg_reg; 601 u32 debug_resp_reg; 602 603 struct delayed_work swctf_delayed_work; 604 605 /* data structures for wbrf feature support */ 606 bool wbrf_supported; 607 struct notifier_block wbrf_notifier; 608 struct delayed_work wbrf_delayed_work; 609 }; 610 611 struct i2c_adapter; 612 613 /** 614 * struct pptable_funcs - Callbacks used to interact with the SMU. 615 */ 616 struct pptable_funcs { 617 /** 618 * @run_btc: Calibrate voltage/frequency curve to fit the system's 619 * power delivery and voltage margins. Required for adaptive 620 * voltage frequency scaling (AVFS). 621 */ 622 int (*run_btc)(struct smu_context *smu); 623 624 /** 625 * @get_allowed_feature_mask: Get allowed feature mask. 626 * &feature_mask: Array to store feature mask. 627 * &num: Elements in &feature_mask. 628 */ 629 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 630 631 /** 632 * @get_current_power_state: Get the current power state. 633 * 634 * Return: Current power state on success, negative errno on failure. 635 */ 636 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 637 638 /** 639 * @set_default_dpm_table: Retrieve the default overdrive settings from 640 * the SMU. 641 */ 642 int (*set_default_dpm_table)(struct smu_context *smu); 643 644 int (*set_power_state)(struct smu_context *smu); 645 646 /** 647 * @populate_umd_state_clk: Populate the UMD power state table with 648 * defaults. 649 */ 650 int (*populate_umd_state_clk)(struct smu_context *smu); 651 652 /** 653 * @print_clk_levels: Print DPM clock levels for a clock domain 654 * to buffer. Star current level. 655 * 656 * Used for sysfs interfaces. 657 * Return: Number of characters written to the buffer 658 */ 659 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 660 661 /** 662 * @emit_clk_levels: Print DPM clock levels for a clock domain 663 * to buffer using sysfs_emit_at. Star current level. 664 * 665 * Used for sysfs interfaces. 666 * &buf: sysfs buffer 667 * &offset: offset within buffer to start printing, which is updated by the 668 * function. 669 * 670 * Return: 0 on Success or Negative to indicate an error occurred. 671 */ 672 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 673 674 /** 675 * @force_clk_levels: Set a range of allowed DPM levels for a clock 676 * domain. 677 * &clk_type: Clock domain. 678 * &mask: Range of allowed DPM levels. 679 */ 680 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 681 682 /** 683 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 684 * &type: Type of edit. 685 * &input: Edit parameters. 686 * &size: Size of &input. 687 */ 688 int (*od_edit_dpm_table)(struct smu_context *smu, 689 enum PP_OD_DPM_TABLE_COMMAND type, 690 long *input, uint32_t size); 691 692 /** 693 * @restore_user_od_settings: Restore the user customized 694 * OD settings on S3/S4/Runpm resume. 695 */ 696 int (*restore_user_od_settings)(struct smu_context *smu); 697 698 /** 699 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 700 * domain. 701 */ 702 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 703 enum smu_clk_type clk_type, 704 struct 705 pp_clock_levels_with_latency 706 *clocks); 707 /** 708 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 709 * domain. 710 */ 711 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 712 enum amd_pp_clock_type type, 713 struct 714 pp_clock_levels_with_voltage 715 *clocks); 716 717 /** 718 * @get_power_profile_mode: Print all power profile modes to 719 * buffer. Star current mode. 720 */ 721 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 722 723 /** 724 * @set_power_profile_mode: Set a power profile mode. Also used to 725 * create/set custom power profile modes. 726 * &input: Power profile mode parameters. 727 * &size: Size of &input. 728 */ 729 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 730 731 /** 732 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 733 * management. 734 */ 735 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 736 737 /** 738 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 739 * management. 740 */ 741 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 742 743 /** 744 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU 745 */ 746 int (*set_gfx_power_up_by_imu)(struct smu_context *smu); 747 748 /** 749 * @read_sensor: Read data from a sensor. 750 * &sensor: Sensor to read data from. 751 * &data: Sensor reading. 752 * &size: Size of &data. 753 */ 754 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 755 void *data, uint32_t *size); 756 757 /** 758 * @get_apu_thermal_limit: get apu core limit from smu 759 * &limit: current limit temperature in millidegrees Celsius 760 */ 761 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit); 762 763 /** 764 * @set_apu_thermal_limit: update all controllers with new limit 765 * &limit: limit temperature to be setted, in millidegrees Celsius 766 */ 767 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit); 768 769 /** 770 * @pre_display_config_changed: Prepare GPU for a display configuration 771 * change. 772 * 773 * Disable display tracking and pin memory clock speed to maximum. Used 774 * in display component synchronization. 775 */ 776 int (*pre_display_config_changed)(struct smu_context *smu); 777 778 /** 779 * @display_config_changed: Notify the SMU of the current display 780 * configuration. 781 * 782 * Allows SMU to properly track blanking periods for memory clock 783 * adjustment. Used in display component synchronization. 784 */ 785 int (*display_config_changed)(struct smu_context *smu); 786 787 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 788 789 /** 790 * @notify_smc_display_config: Applies display requirements to the 791 * current power state. 792 * 793 * Optimize deep sleep DCEFclk and mclk for the current display 794 * configuration. Used in display component synchronization. 795 */ 796 int (*notify_smc_display_config)(struct smu_context *smu); 797 798 /** 799 * @is_dpm_running: Check if DPM is running. 800 * 801 * Return: True if DPM is running, false otherwise. 802 */ 803 bool (*is_dpm_running)(struct smu_context *smu); 804 805 /** 806 * @get_fan_speed_pwm: Get the current fan speed in PWM. 807 */ 808 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 809 810 /** 811 * @get_fan_speed_rpm: Get the current fan speed in rpm. 812 */ 813 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 814 815 /** 816 * @set_watermarks_table: Configure and upload the watermarks tables to 817 * the SMU. 818 */ 819 int (*set_watermarks_table)(struct smu_context *smu, 820 struct pp_smu_wm_range_sets *clock_ranges); 821 822 /** 823 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 824 */ 825 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 826 827 /** 828 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 829 * &clocks_in_khz: Array of DPM levels. 830 * &num_states: Elements in &clocks_in_khz. 831 */ 832 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 833 834 /** 835 * @set_default_od_settings: Set the overdrive tables to defaults. 836 */ 837 int (*set_default_od_settings)(struct smu_context *smu); 838 839 /** 840 * @set_performance_level: Set a performance level. 841 */ 842 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 843 844 /** 845 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 846 * clock switching. 847 * 848 * Disabling this feature forces memory clock speed to maximum. 849 * Enabling sets the minimum memory clock capable of driving the 850 * current display configuration. 851 */ 852 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 853 854 /** 855 * @dump_pptable: Print the power play table to the system log. 856 */ 857 void (*dump_pptable)(struct smu_context *smu); 858 859 /** 860 * @get_power_limit: Get the device's power limits. 861 */ 862 int (*get_power_limit)(struct smu_context *smu, 863 uint32_t *current_power_limit, 864 uint32_t *default_power_limit, 865 uint32_t *max_power_limit, 866 uint32_t *min_power_limit); 867 868 /** 869 * @get_ppt_limit: Get the device's ppt limits. 870 */ 871 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 872 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 873 874 /** 875 * @set_df_cstate: Set data fabric cstate. 876 */ 877 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 878 879 /** 880 * @update_pcie_parameters: Update and upload the system's PCIe 881 * capabilites to the SMU. 882 * &pcie_gen_cap: Maximum allowed PCIe generation. 883 * &pcie_width_cap: Maximum allowed PCIe width. 884 */ 885 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap); 886 887 /** 888 * @i2c_init: Initialize i2c. 889 * 890 * The i2c bus is used internally by the SMU voltage regulators and 891 * other devices. The i2c's EEPROM also stores bad page tables on boards 892 * with ECC. 893 */ 894 int (*i2c_init)(struct smu_context *smu); 895 896 /** 897 * @i2c_fini: Tear down i2c. 898 */ 899 void (*i2c_fini)(struct smu_context *smu); 900 901 /** 902 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 903 */ 904 void (*get_unique_id)(struct smu_context *smu); 905 906 /** 907 * @get_dpm_clock_table: Get a copy of the DPM clock table. 908 * 909 * Used by display component in bandwidth and watermark calculations. 910 */ 911 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 912 913 /** 914 * @init_microcode: Request the SMU's firmware from the kernel. 915 */ 916 int (*init_microcode)(struct smu_context *smu); 917 918 /** 919 * @load_microcode: Load firmware onto the SMU. 920 */ 921 int (*load_microcode)(struct smu_context *smu); 922 923 /** 924 * @fini_microcode: Release the SMU's firmware. 925 */ 926 void (*fini_microcode)(struct smu_context *smu); 927 928 /** 929 * @init_smc_tables: Initialize the SMU tables. 930 */ 931 int (*init_smc_tables)(struct smu_context *smu); 932 933 /** 934 * @fini_smc_tables: Release the SMU tables. 935 */ 936 int (*fini_smc_tables)(struct smu_context *smu); 937 938 /** 939 * @init_power: Initialize the power gate table context. 940 */ 941 int (*init_power)(struct smu_context *smu); 942 943 /** 944 * @fini_power: Release the power gate table context. 945 */ 946 int (*fini_power)(struct smu_context *smu); 947 948 /** 949 * @check_fw_status: Check the SMU's firmware status. 950 * 951 * Return: Zero if check passes, negative errno on failure. 952 */ 953 int (*check_fw_status)(struct smu_context *smu); 954 955 /** 956 * @set_mp1_state: put SMU into a correct state for comming 957 * resume from runpm or gpu reset. 958 */ 959 int (*set_mp1_state)(struct smu_context *smu, 960 enum pp_mp1_state mp1_state); 961 962 /** 963 * @setup_pptable: Initialize the power play table and populate it with 964 * default values. 965 */ 966 int (*setup_pptable)(struct smu_context *smu); 967 968 /** 969 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 970 */ 971 int (*get_vbios_bootup_values)(struct smu_context *smu); 972 973 /** 974 * @check_fw_version: Print driver and SMU interface versions to the 975 * system log. 976 * 977 * Interface mismatch is not a critical failure. 978 */ 979 int (*check_fw_version)(struct smu_context *smu); 980 981 /** 982 * @powergate_sdma: Power up/down system direct memory access. 983 */ 984 int (*powergate_sdma)(struct smu_context *smu, bool gate); 985 986 /** 987 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 988 * gating. 989 */ 990 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 991 992 /** 993 * @write_pptable: Write the power play table to the SMU. 994 */ 995 int (*write_pptable)(struct smu_context *smu); 996 997 /** 998 * @set_driver_table_location: Send the location of the driver table to 999 * the SMU. 1000 */ 1001 int (*set_driver_table_location)(struct smu_context *smu); 1002 1003 /** 1004 * @set_tool_table_location: Send the location of the tool table to the 1005 * SMU. 1006 */ 1007 int (*set_tool_table_location)(struct smu_context *smu); 1008 1009 /** 1010 * @notify_memory_pool_location: Send the location of the memory pool to 1011 * the SMU. 1012 */ 1013 int (*notify_memory_pool_location)(struct smu_context *smu); 1014 1015 /** 1016 * @system_features_control: Enable/disable all SMU features. 1017 */ 1018 int (*system_features_control)(struct smu_context *smu, bool en); 1019 1020 /** 1021 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 1022 * &msg: Type of message. 1023 * ¶m: Message parameter. 1024 * &read_arg: SMU response (optional). 1025 */ 1026 int (*send_smc_msg_with_param)(struct smu_context *smu, 1027 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 1028 1029 /** 1030 * @send_smc_msg: Send a message to the SMU. 1031 * &msg: Type of message. 1032 * &read_arg: SMU response (optional). 1033 */ 1034 int (*send_smc_msg)(struct smu_context *smu, 1035 enum smu_message_type msg, 1036 uint32_t *read_arg); 1037 1038 /** 1039 * @init_display_count: Notify the SMU of the number of display 1040 * components in current display configuration. 1041 */ 1042 int (*init_display_count)(struct smu_context *smu, uint32_t count); 1043 1044 /** 1045 * @set_allowed_mask: Notify the SMU of the features currently allowed 1046 * by the driver. 1047 */ 1048 int (*set_allowed_mask)(struct smu_context *smu); 1049 1050 /** 1051 * @get_enabled_mask: Get a mask of features that are currently enabled 1052 * on the SMU. 1053 * &feature_mask: Enabled feature mask. 1054 */ 1055 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1056 1057 /** 1058 * @feature_is_enabled: Test if a feature is enabled. 1059 * 1060 * Return: One if enabled, zero if disabled. 1061 */ 1062 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1063 1064 /** 1065 * @disable_all_features_with_exception: Disable all features with 1066 * exception to those in &mask. 1067 */ 1068 int (*disable_all_features_with_exception)(struct smu_context *smu, 1069 enum smu_feature_mask mask); 1070 1071 /** 1072 * @notify_display_change: General interface call to let SMU know about DC change 1073 */ 1074 int (*notify_display_change)(struct smu_context *smu); 1075 1076 /** 1077 * @set_power_limit: Set power limit in watts. 1078 */ 1079 int (*set_power_limit)(struct smu_context *smu, 1080 enum smu_ppt_limit_type limit_type, 1081 uint32_t limit); 1082 1083 /** 1084 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1085 * table with values from the SMU. 1086 */ 1087 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1088 1089 /** 1090 * @enable_thermal_alert: Enable thermal alert interrupts. 1091 */ 1092 int (*enable_thermal_alert)(struct smu_context *smu); 1093 1094 /** 1095 * @disable_thermal_alert: Disable thermal alert interrupts. 1096 */ 1097 int (*disable_thermal_alert)(struct smu_context *smu); 1098 1099 /** 1100 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1101 * clock speed in MHz. 1102 */ 1103 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1104 1105 /** 1106 * @display_clock_voltage_request: Set a hard minimum frequency 1107 * for a clock domain. 1108 */ 1109 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1110 pp_display_clock_request 1111 *clock_req); 1112 1113 /** 1114 * @get_fan_control_mode: Get the current fan control mode. 1115 */ 1116 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1117 1118 /** 1119 * @set_fan_control_mode: Set the fan control mode. 1120 */ 1121 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1122 1123 /** 1124 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1125 */ 1126 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1127 1128 /** 1129 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1130 */ 1131 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1132 1133 /** 1134 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1135 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1136 */ 1137 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1138 1139 /** 1140 * @gfx_off_control: Enable/disable graphics engine poweroff. 1141 */ 1142 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1143 1144 1145 /** 1146 * @get_gfx_off_status: Get graphics engine poweroff status. 1147 * 1148 * Return: 1149 * 0 - GFXOFF(default). 1150 * 1 - Transition out of GFX State. 1151 * 2 - Not in GFXOFF. 1152 * 3 - Transition into GFXOFF. 1153 */ 1154 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1155 1156 /** 1157 * @gfx_off_entrycount: total GFXOFF entry count at the time of 1158 * query since system power-up 1159 */ 1160 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount); 1161 1162 /** 1163 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging 1164 */ 1165 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); 1166 1167 /** 1168 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval 1169 */ 1170 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency); 1171 1172 /** 1173 * @register_irq_handler: Register interupt request handlers. 1174 */ 1175 int (*register_irq_handler)(struct smu_context *smu); 1176 1177 /** 1178 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1179 */ 1180 int (*set_azalia_d3_pme)(struct smu_context *smu); 1181 1182 /** 1183 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1184 * clock speeds table. 1185 * 1186 * Provides a way for the display component (DC) to get the max 1187 * sustainable clocks from the SMU. 1188 */ 1189 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1190 1191 /** 1192 * @get_bamaco_support: Check if GPU supports BACO/MACO 1193 * BACO: Bus Active, Chip Off 1194 * MACO: Memory Active, Chip Off 1195 */ 1196 int (*get_bamaco_support)(struct smu_context *smu); 1197 1198 /** 1199 * @baco_get_state: Get the current BACO state. 1200 * 1201 * Return: Current BACO state. 1202 */ 1203 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1204 1205 /** 1206 * @baco_set_state: Enter/exit BACO. 1207 */ 1208 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1209 1210 /** 1211 * @baco_enter: Enter BACO. 1212 */ 1213 int (*baco_enter)(struct smu_context *smu); 1214 1215 /** 1216 * @baco_exit: Exit Baco. 1217 */ 1218 int (*baco_exit)(struct smu_context *smu); 1219 1220 /** 1221 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1222 */ 1223 bool (*mode1_reset_is_support)(struct smu_context *smu); 1224 /** 1225 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1226 */ 1227 bool (*mode2_reset_is_support)(struct smu_context *smu); 1228 1229 /** 1230 * @mode1_reset: Perform mode1 reset. 1231 * 1232 * Complete GPU reset. 1233 */ 1234 int (*mode1_reset)(struct smu_context *smu); 1235 1236 /** 1237 * @mode2_reset: Perform mode2 reset. 1238 * 1239 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1240 * IPs reset varies by asic. 1241 */ 1242 int (*mode2_reset)(struct smu_context *smu); 1243 /* for gfx feature enablement after mode2 reset */ 1244 int (*enable_gfx_features)(struct smu_context *smu); 1245 1246 /** 1247 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1248 * domain in MHz. 1249 */ 1250 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1251 1252 /** 1253 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1254 * domain in MHz. 1255 */ 1256 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 1257 1258 /** 1259 * @set_power_source: Notify the SMU of the current power source. 1260 */ 1261 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1262 1263 /** 1264 * @log_thermal_throttling_event: Print a thermal throttling warning to 1265 * the system's log. 1266 */ 1267 void (*log_thermal_throttling_event)(struct smu_context *smu); 1268 1269 /** 1270 * @get_pp_feature_mask: Print a human readable table of enabled 1271 * features to buffer. 1272 */ 1273 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1274 1275 /** 1276 * @set_pp_feature_mask: Request the SMU enable/disable features to 1277 * match those enabled in &new_mask. 1278 */ 1279 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1280 1281 /** 1282 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1283 * 1284 * Return: Size of &table 1285 */ 1286 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1287 1288 /** 1289 * @get_pm_metrics: Get one snapshot of power management metrics from 1290 * PMFW. 1291 * 1292 * Return: Size of the metrics sample 1293 */ 1294 ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics, 1295 size_t size); 1296 1297 /** 1298 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1299 */ 1300 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1301 1302 /** 1303 * @gfx_ulv_control: Enable/disable ultra low voltage. 1304 */ 1305 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1306 1307 /** 1308 * @deep_sleep_control: Enable/disable deep sleep. 1309 */ 1310 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1311 1312 /** 1313 * @get_fan_parameters: Get fan parameters. 1314 * 1315 * Get maximum fan speed from the power play table. 1316 */ 1317 int (*get_fan_parameters)(struct smu_context *smu); 1318 1319 /** 1320 * @post_init: Helper function for asic specific workarounds. 1321 */ 1322 int (*post_init)(struct smu_context *smu); 1323 1324 /** 1325 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1326 */ 1327 void (*interrupt_work)(struct smu_context *smu); 1328 1329 /** 1330 * @gpo_control: Enable/disable graphics power optimization if supported. 1331 */ 1332 int (*gpo_control)(struct smu_context *smu, bool enablement); 1333 1334 /** 1335 * @gfx_state_change_set: Send the current graphics state to the SMU. 1336 */ 1337 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1338 1339 /** 1340 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1341 * parameters to defaults. 1342 */ 1343 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1344 1345 /** 1346 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1347 */ 1348 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1349 1350 /** 1351 * @wait_for_event: Wait for events from SMU. 1352 */ 1353 int (*wait_for_event)(struct smu_context *smu, 1354 enum smu_event_type event, uint64_t event_arg); 1355 1356 /** 1357 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1358 * of SMUBUS table. 1359 */ 1360 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1361 1362 /** 1363 * @send_rma_reason: message rma reason event to SMU. 1364 */ 1365 int (*send_rma_reason)(struct smu_context *smu); 1366 1367 /** 1368 * @get_ecc_table: message SMU to get ECC INFO table. 1369 */ 1370 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1371 1372 1373 /** 1374 * @stb_collect_info: Collects Smart Trace Buffers data. 1375 */ 1376 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1377 1378 /** 1379 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1380 */ 1381 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1382 1383 /** 1384 * @set_config_table: Apply the input DriverSmuConfig table settings. 1385 */ 1386 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1387 1388 /** 1389 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1390 * of SMUBUS table. 1391 */ 1392 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1393 1394 /** 1395 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP 1396 */ 1397 int (*init_pptable_microcode)(struct smu_context *smu); 1398 1399 /** 1400 * @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power 1401 * management. 1402 */ 1403 int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable); 1404 1405 /** 1406 * @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power 1407 * management. 1408 */ 1409 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable); 1410 1411 /** 1412 * @set_mall_enable: Init MALL power gating control. 1413 */ 1414 int (*set_mall_enable)(struct smu_context *smu); 1415 1416 /** 1417 * @notify_rlc_state: Notify RLC power state to SMU. 1418 */ 1419 int (*notify_rlc_state)(struct smu_context *smu, bool en); 1420 1421 /** 1422 * @is_asic_wbrf_supported: check whether PMFW supports the wbrf feature 1423 */ 1424 bool (*is_asic_wbrf_supported)(struct smu_context *smu); 1425 1426 /** 1427 * @enable_uclk_shadow: Enable the uclk shadow feature on wbrf supported 1428 */ 1429 int (*enable_uclk_shadow)(struct smu_context *smu, bool enable); 1430 1431 /** 1432 * @set_wbrf_exclusion_ranges: notify SMU the wifi bands occupied 1433 */ 1434 int (*set_wbrf_exclusion_ranges)(struct smu_context *smu, 1435 struct freq_band_range *exclusion_ranges); 1436 }; 1437 1438 typedef enum { 1439 METRICS_CURR_GFXCLK, 1440 METRICS_CURR_SOCCLK, 1441 METRICS_CURR_UCLK, 1442 METRICS_CURR_VCLK, 1443 METRICS_CURR_VCLK1, 1444 METRICS_CURR_DCLK, 1445 METRICS_CURR_DCLK1, 1446 METRICS_CURR_FCLK, 1447 METRICS_CURR_DCEFCLK, 1448 METRICS_AVERAGE_CPUCLK, 1449 METRICS_AVERAGE_GFXCLK, 1450 METRICS_AVERAGE_SOCCLK, 1451 METRICS_AVERAGE_FCLK, 1452 METRICS_AVERAGE_UCLK, 1453 METRICS_AVERAGE_VCLK, 1454 METRICS_AVERAGE_DCLK, 1455 METRICS_AVERAGE_VCLK1, 1456 METRICS_AVERAGE_DCLK1, 1457 METRICS_AVERAGE_GFXACTIVITY, 1458 METRICS_AVERAGE_MEMACTIVITY, 1459 METRICS_AVERAGE_VCNACTIVITY, 1460 METRICS_AVERAGE_SOCKETPOWER, 1461 METRICS_TEMPERATURE_EDGE, 1462 METRICS_TEMPERATURE_HOTSPOT, 1463 METRICS_TEMPERATURE_MEM, 1464 METRICS_TEMPERATURE_VRGFX, 1465 METRICS_TEMPERATURE_VRSOC, 1466 METRICS_TEMPERATURE_VRMEM, 1467 METRICS_THROTTLER_STATUS, 1468 METRICS_CURR_FANSPEED, 1469 METRICS_VOLTAGE_VDDSOC, 1470 METRICS_VOLTAGE_VDDGFX, 1471 METRICS_SS_APU_SHARE, 1472 METRICS_SS_DGPU_SHARE, 1473 METRICS_UNIQUE_ID_UPPER32, 1474 METRICS_UNIQUE_ID_LOWER32, 1475 METRICS_PCIE_RATE, 1476 METRICS_PCIE_WIDTH, 1477 METRICS_CURR_FANPWM, 1478 METRICS_CURR_SOCKETPOWER, 1479 METRICS_AVERAGE_VPECLK, 1480 METRICS_AVERAGE_IPUCLK, 1481 METRICS_AVERAGE_MPIPUCLK, 1482 METRICS_THROTTLER_RESIDENCY_PROCHOT, 1483 METRICS_THROTTLER_RESIDENCY_SPL, 1484 METRICS_THROTTLER_RESIDENCY_FPPT, 1485 METRICS_THROTTLER_RESIDENCY_SPPT, 1486 METRICS_THROTTLER_RESIDENCY_THM_CORE, 1487 METRICS_THROTTLER_RESIDENCY_THM_GFX, 1488 METRICS_THROTTLER_RESIDENCY_THM_SOC, 1489 } MetricsMember_t; 1490 1491 enum smu_cmn2asic_mapping_type { 1492 CMN2ASIC_MAPPING_MSG, 1493 CMN2ASIC_MAPPING_CLK, 1494 CMN2ASIC_MAPPING_FEATURE, 1495 CMN2ASIC_MAPPING_TABLE, 1496 CMN2ASIC_MAPPING_PWR, 1497 CMN2ASIC_MAPPING_WORKLOAD, 1498 }; 1499 1500 enum smu_baco_seq { 1501 BACO_SEQ_BACO = 0, 1502 BACO_SEQ_MSR, 1503 BACO_SEQ_BAMACO, 1504 BACO_SEQ_ULPS, 1505 BACO_SEQ_COUNT, 1506 }; 1507 1508 #define MSG_MAP(msg, index, flags) \ 1509 [SMU_MSG_##msg] = {1, (index), (flags)} 1510 1511 #define CLK_MAP(clk, index) \ 1512 [SMU_##clk] = {1, (index)} 1513 1514 #define FEA_MAP(fea) \ 1515 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1516 1517 #define FEA_MAP_REVERSE(fea) \ 1518 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1519 1520 #define FEA_MAP_HALF_REVERSE(fea) \ 1521 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1522 1523 #define TAB_MAP(tab) \ 1524 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1525 1526 #define TAB_MAP_VALID(tab) \ 1527 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1528 1529 #define TAB_MAP_INVALID(tab) \ 1530 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1531 1532 #define PWR_MAP(tab) \ 1533 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1534 1535 #define WORKLOAD_MAP(profile, workload) \ 1536 [profile] = {1, (workload)} 1537 1538 /** 1539 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1540 * 1541 * @dst: Pointer to destination struct 1542 * @first_dst_member: The member name in @dst where the overwrite begins 1543 * @last_dst_member: The member name in @dst where the overwrite ends after 1544 * @src: Pointer to the source struct 1545 * @first_src_member: The member name in @src where the copy begins 1546 * 1547 */ 1548 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1549 src, first_src_member) \ 1550 ({ \ 1551 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1552 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1553 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1554 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1555 __dst_offset; \ 1556 BUILD_BUG_ON(__src_size != __dst_size); \ 1557 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1558 (u8 *)(src) + __src_offset, \ 1559 __dst_size); \ 1560 }) 1561 1562 typedef struct { 1563 uint16_t LowFreq; 1564 uint16_t HighFreq; 1565 } WifiOneBand_t; 1566 1567 typedef struct { 1568 uint32_t WifiBandEntryNum; 1569 WifiOneBand_t WifiBandEntry[11]; 1570 uint32_t MmHubPadding[8]; 1571 } WifiBandEntryTable_t; 1572 1573 #define STR_SOC_PSTATE_POLICY "soc_pstate" 1574 #define STR_XGMI_PLPD_POLICY "xgmi_plpd" 1575 1576 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 1577 enum pp_pm_policy p_type); 1578 1579 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1580 int smu_get_power_limit(void *handle, 1581 uint32_t *limit, 1582 enum pp_power_limit_level pp_limit_level, 1583 enum pp_power_type pp_power_type); 1584 1585 bool smu_mode1_reset_is_support(struct smu_context *smu); 1586 bool smu_mode2_reset_is_support(struct smu_context *smu); 1587 int smu_mode1_reset(struct smu_context *smu); 1588 1589 extern const struct amd_ip_funcs smu_ip_funcs; 1590 1591 bool is_support_sw_smu(struct amdgpu_device *adev); 1592 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1593 int smu_write_watermarks_table(struct smu_context *smu); 1594 1595 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1596 uint32_t *min, uint32_t *max); 1597 1598 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1599 uint32_t min, uint32_t max); 1600 1601 int smu_set_gfx_power_up_by_imu(struct smu_context *smu); 1602 1603 int smu_set_ac_dc(struct smu_context *smu); 1604 1605 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 1606 enum pp_xgmi_plpd_mode mode); 1607 1608 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); 1609 1610 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); 1611 1612 int smu_set_residency_gfxoff(struct smu_context *smu, bool value); 1613 1614 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1615 1616 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1617 1618 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1619 uint64_t event_arg); 1620 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1621 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1622 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1623 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1624 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1625 int smu_send_rma_reason(struct smu_context *smu); 1626 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 1627 int level); 1628 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 1629 enum pp_pm_policy p_type, char *sysbuf); 1630 1631 #endif 1632 #endif 1633