1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include <linux/acpi_amd_wbrf.h> 26 #include <linux/units.h> 27 28 #include "amdgpu.h" 29 #include "kgd_pp_interface.h" 30 #include "dm_pp_interface.h" 31 #include "dm_pp_smu.h" 32 #include "smu_types.h" 33 #include "linux/firmware.h" 34 35 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 36 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 37 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 38 #define SMU_FW_NAME_LEN 0x24 39 40 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 41 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 42 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 43 44 // Power Throttlers 45 #define SMU_THROTTLER_PPT0_BIT 0 46 #define SMU_THROTTLER_PPT1_BIT 1 47 #define SMU_THROTTLER_PPT2_BIT 2 48 #define SMU_THROTTLER_PPT3_BIT 3 49 #define SMU_THROTTLER_SPL_BIT 4 50 #define SMU_THROTTLER_FPPT_BIT 5 51 #define SMU_THROTTLER_SPPT_BIT 6 52 #define SMU_THROTTLER_SPPT_APU_BIT 7 53 54 // Current Throttlers 55 #define SMU_THROTTLER_TDC_GFX_BIT 16 56 #define SMU_THROTTLER_TDC_SOC_BIT 17 57 #define SMU_THROTTLER_TDC_MEM_BIT 18 58 #define SMU_THROTTLER_TDC_VDD_BIT 19 59 #define SMU_THROTTLER_TDC_CVIP_BIT 20 60 #define SMU_THROTTLER_EDC_CPU_BIT 21 61 #define SMU_THROTTLER_EDC_GFX_BIT 22 62 #define SMU_THROTTLER_APCC_BIT 23 63 64 // Temperature 65 #define SMU_THROTTLER_TEMP_GPU_BIT 32 66 #define SMU_THROTTLER_TEMP_CORE_BIT 33 67 #define SMU_THROTTLER_TEMP_MEM_BIT 34 68 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 69 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 70 #define SMU_THROTTLER_TEMP_SOC_BIT 37 71 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 72 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 73 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 74 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 75 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 76 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 77 #define SMU_THROTTLER_VRHOT0_BIT 44 78 #define SMU_THROTTLER_VRHOT1_BIT 45 79 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 80 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 81 82 // Other 83 #define SMU_THROTTLER_PPM_BIT 56 84 #define SMU_THROTTLER_FIT_BIT 57 85 86 struct smu_hw_power_state { 87 unsigned int magic; 88 }; 89 90 struct smu_power_state; 91 92 enum smu_state_ui_label { 93 SMU_STATE_UI_LABEL_NONE, 94 SMU_STATE_UI_LABEL_BATTERY, 95 SMU_STATE_UI_TABEL_MIDDLE_LOW, 96 SMU_STATE_UI_LABEL_BALLANCED, 97 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 98 SMU_STATE_UI_LABEL_PERFORMANCE, 99 SMU_STATE_UI_LABEL_BACO, 100 }; 101 102 enum smu_state_classification_flag { 103 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 104 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 105 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 106 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 107 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 108 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 109 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 111 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 112 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 113 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 114 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 115 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 116 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 117 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 118 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 119 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 120 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 121 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 122 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 123 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 124 }; 125 126 struct smu_state_classification_block { 127 enum smu_state_ui_label ui_label; 128 enum smu_state_classification_flag flags; 129 int bios_index; 130 bool temporary_state; 131 bool to_be_deleted; 132 }; 133 134 struct smu_state_pcie_block { 135 unsigned int lanes; 136 }; 137 138 enum smu_refreshrate_source { 139 SMU_REFRESHRATE_SOURCE_EDID, 140 SMU_REFRESHRATE_SOURCE_EXPLICIT 141 }; 142 143 struct smu_state_display_block { 144 bool disable_frame_modulation; 145 bool limit_refreshrate; 146 enum smu_refreshrate_source refreshrate_source; 147 int explicit_refreshrate; 148 int edid_refreshrate_index; 149 bool enable_vari_bright; 150 }; 151 152 struct smu_state_memory_block { 153 bool dll_off; 154 uint8_t m3arb; 155 uint8_t unused[3]; 156 }; 157 158 struct smu_state_software_algorithm_block { 159 bool disable_load_balancing; 160 bool enable_sleep_for_timestamps; 161 }; 162 163 struct smu_temperature_range { 164 int min; 165 int max; 166 int edge_emergency_max; 167 int hotspot_min; 168 int hotspot_crit_max; 169 int hotspot_emergency_max; 170 int mem_min; 171 int mem_crit_max; 172 int mem_emergency_max; 173 int software_shutdown_temp; 174 int software_shutdown_temp_offset; 175 }; 176 177 struct smu_state_validation_block { 178 bool single_display_only; 179 bool disallow_on_dc; 180 uint8_t supported_power_levels; 181 }; 182 183 struct smu_uvd_clocks { 184 uint32_t vclk; 185 uint32_t dclk; 186 }; 187 188 /** 189 * Structure to hold a SMU Power State. 190 */ 191 struct smu_power_state { 192 uint32_t id; 193 struct list_head ordered_list; 194 struct list_head all_states_list; 195 196 struct smu_state_classification_block classification; 197 struct smu_state_validation_block validation; 198 struct smu_state_pcie_block pcie; 199 struct smu_state_display_block display; 200 struct smu_state_memory_block memory; 201 struct smu_state_software_algorithm_block software; 202 struct smu_uvd_clocks uvd_clocks; 203 struct smu_hw_power_state hardware; 204 }; 205 206 enum smu_power_src_type { 207 SMU_POWER_SOURCE_AC, 208 SMU_POWER_SOURCE_DC, 209 SMU_POWER_SOURCE_COUNT, 210 }; 211 212 enum smu_ppt_limit_type { 213 SMU_DEFAULT_PPT_LIMIT = 0, 214 SMU_FAST_PPT_LIMIT, 215 }; 216 217 enum smu_ppt_limit_level { 218 SMU_PPT_LIMIT_MIN = -1, 219 SMU_PPT_LIMIT_CURRENT, 220 SMU_PPT_LIMIT_DEFAULT, 221 SMU_PPT_LIMIT_MAX, 222 }; 223 224 enum smu_memory_pool_size { 225 SMU_MEMORY_POOL_SIZE_ZERO = 0, 226 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 227 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 228 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 229 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 230 }; 231 232 struct smu_user_dpm_profile { 233 uint32_t fan_mode; 234 uint32_t power_limit; 235 uint32_t fan_speed_pwm; 236 uint32_t fan_speed_rpm; 237 uint32_t flags; 238 uint32_t user_od; 239 240 /* user clock state information */ 241 uint32_t clk_mask[SMU_CLK_COUNT]; 242 uint32_t clk_dependency; 243 }; 244 245 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 246 do { \ 247 tables[table_id].size = s; \ 248 tables[table_id].align = a; \ 249 tables[table_id].domain = d; \ 250 } while (0) 251 252 struct smu_table { 253 uint64_t size; 254 uint32_t align; 255 uint8_t domain; 256 uint64_t mc_address; 257 void *cpu_addr; 258 struct amdgpu_bo *bo; 259 uint32_t version; 260 }; 261 262 enum smu_perf_level_designation { 263 PERF_LEVEL_ACTIVITY, 264 PERF_LEVEL_POWER_CONTAINMENT, 265 }; 266 267 struct smu_performance_level { 268 uint32_t core_clock; 269 uint32_t memory_clock; 270 uint32_t vddc; 271 uint32_t vddci; 272 uint32_t non_local_mem_freq; 273 uint32_t non_local_mem_width; 274 }; 275 276 struct smu_clock_info { 277 uint32_t min_mem_clk; 278 uint32_t max_mem_clk; 279 uint32_t min_eng_clk; 280 uint32_t max_eng_clk; 281 uint32_t min_bus_bandwidth; 282 uint32_t max_bus_bandwidth; 283 }; 284 285 struct smu_bios_boot_up_values { 286 uint32_t revision; 287 uint32_t gfxclk; 288 uint32_t uclk; 289 uint32_t socclk; 290 uint32_t dcefclk; 291 uint32_t eclk; 292 uint32_t vclk; 293 uint32_t dclk; 294 uint16_t vddc; 295 uint16_t vddci; 296 uint16_t mvddc; 297 uint16_t vdd_gfx; 298 uint8_t cooling_id; 299 uint32_t pp_table_id; 300 uint32_t format_revision; 301 uint32_t content_revision; 302 uint32_t fclk; 303 uint32_t lclk; 304 uint32_t firmware_caps; 305 }; 306 307 enum smu_table_id { 308 SMU_TABLE_PPTABLE = 0, 309 SMU_TABLE_WATERMARKS, 310 SMU_TABLE_CUSTOM_DPM, 311 SMU_TABLE_DPMCLOCKS, 312 SMU_TABLE_AVFS, 313 SMU_TABLE_AVFS_PSM_DEBUG, 314 SMU_TABLE_AVFS_FUSE_OVERRIDE, 315 SMU_TABLE_PMSTATUSLOG, 316 SMU_TABLE_SMU_METRICS, 317 SMU_TABLE_DRIVER_SMU_CONFIG, 318 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 319 SMU_TABLE_OVERDRIVE, 320 SMU_TABLE_I2C_COMMANDS, 321 SMU_TABLE_PACE, 322 SMU_TABLE_ECCINFO, 323 SMU_TABLE_COMBO_PPTABLE, 324 SMU_TABLE_WIFIBAND, 325 SMU_TABLE_COUNT, 326 }; 327 328 struct smu_table_context { 329 void *power_play_table; 330 uint32_t power_play_table_size; 331 void *hardcode_pptable; 332 unsigned long metrics_time; 333 void *metrics_table; 334 void *clocks_table; 335 void *watermarks_table; 336 337 void *max_sustainable_clocks; 338 struct smu_bios_boot_up_values boot_values; 339 void *driver_pptable; 340 void *combo_pptable; 341 void *ecc_table; 342 void *driver_smu_config_table; 343 struct smu_table tables[SMU_TABLE_COUNT]; 344 /* 345 * The driver table is just a staging buffer for 346 * uploading/downloading content from the SMU. 347 * 348 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 349 * SMU_MSG_TransferTableDram2Smu instructs SMU 350 * which content driver is interested. 351 */ 352 struct smu_table driver_table; 353 struct smu_table memory_pool; 354 struct smu_table dummy_read_1_table; 355 uint8_t thermal_controller_type; 356 357 void *overdrive_table; 358 void *boot_overdrive_table; 359 void *user_overdrive_table; 360 361 uint32_t gpu_metrics_table_size; 362 void *gpu_metrics_table; 363 }; 364 365 struct smu_context; 366 struct smu_dpm_policy; 367 368 struct smu_dpm_policy_desc { 369 const char *name; 370 char *(*get_desc)(struct smu_dpm_policy *dpm_policy, int level); 371 }; 372 373 struct smu_dpm_policy { 374 struct smu_dpm_policy_desc *desc; 375 enum pp_pm_policy policy_type; 376 unsigned long level_mask; 377 int current_level; 378 int (*set_policy)(struct smu_context *ctxt, int level); 379 }; 380 381 struct smu_dpm_policy_ctxt { 382 struct smu_dpm_policy policies[PP_PM_POLICY_NUM]; 383 unsigned long policy_mask; 384 }; 385 386 struct smu_dpm_context { 387 uint32_t dpm_context_size; 388 void *dpm_context; 389 void *golden_dpm_context; 390 enum amd_dpm_forced_level dpm_level; 391 enum amd_dpm_forced_level saved_dpm_level; 392 enum amd_dpm_forced_level requested_dpm_level; 393 struct smu_power_state *dpm_request_power_state; 394 struct smu_power_state *dpm_current_power_state; 395 struct mclock_latency_table *mclk_latency_table; 396 struct smu_dpm_policy_ctxt *dpm_policies; 397 }; 398 399 struct smu_power_gate { 400 bool uvd_gated; 401 bool vce_gated; 402 atomic_t vcn_gated[AMDGPU_MAX_VCN_INSTANCES]; 403 atomic_t jpeg_gated; 404 atomic_t vpe_gated; 405 atomic_t umsch_mm_gated; 406 }; 407 408 struct smu_power_context { 409 void *power_context; 410 uint32_t power_context_size; 411 struct smu_power_gate power_gate; 412 }; 413 414 #define SMU_FEATURE_MAX (64) 415 struct smu_feature { 416 uint32_t feature_num; 417 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 418 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 419 }; 420 421 struct smu_clocks { 422 uint32_t engine_clock; 423 uint32_t memory_clock; 424 uint32_t bus_bandwidth; 425 uint32_t engine_clock_in_sr; 426 uint32_t dcef_clock; 427 uint32_t dcef_clock_in_sr; 428 }; 429 430 #define MAX_REGULAR_DPM_NUM 16 431 struct mclk_latency_entries { 432 uint32_t frequency; 433 uint32_t latency; 434 }; 435 struct mclock_latency_table { 436 uint32_t count; 437 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 438 }; 439 440 enum smu_reset_mode { 441 SMU_RESET_MODE_0, 442 SMU_RESET_MODE_1, 443 SMU_RESET_MODE_2, 444 SMU_RESET_MODE_3, 445 SMU_RESET_MODE_4, 446 }; 447 448 enum smu_baco_state { 449 SMU_BACO_STATE_ENTER = 0, 450 SMU_BACO_STATE_EXIT, 451 SMU_BACO_STATE_NONE, 452 }; 453 454 struct smu_baco_context { 455 uint32_t state; 456 bool platform_support; 457 bool maco_support; 458 }; 459 460 struct smu_freq_info { 461 uint32_t min; 462 uint32_t max; 463 uint32_t freq_level; 464 }; 465 466 struct pstates_clk_freq { 467 uint32_t min; 468 uint32_t standard; 469 uint32_t peak; 470 struct smu_freq_info custom; 471 struct smu_freq_info curr; 472 }; 473 474 struct smu_umd_pstate_table { 475 struct pstates_clk_freq gfxclk_pstate; 476 struct pstates_clk_freq socclk_pstate; 477 struct pstates_clk_freq uclk_pstate; 478 struct pstates_clk_freq vclk_pstate; 479 struct pstates_clk_freq dclk_pstate; 480 struct pstates_clk_freq fclk_pstate; 481 }; 482 483 struct cmn2asic_msg_mapping { 484 int valid_mapping; 485 int map_to; 486 uint32_t flags; 487 }; 488 489 struct cmn2asic_mapping { 490 int valid_mapping; 491 int map_to; 492 }; 493 494 struct stb_context { 495 uint32_t stb_buf_size; 496 bool enabled; 497 spinlock_t lock; 498 }; 499 500 enum smu_fw_status { 501 SMU_FW_INIT = 0, 502 SMU_FW_RUNTIME, 503 SMU_FW_HANG, 504 }; 505 506 #define WORKLOAD_POLICY_MAX 7 507 508 /* 509 * Configure wbrf event handling pace as there can be only one 510 * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms. 511 */ 512 #define SMU_WBRF_EVENT_HANDLING_PACE 10 513 514 struct smu_context { 515 struct amdgpu_device *adev; 516 struct amdgpu_irq_src irq_source; 517 518 const struct pptable_funcs *ppt_funcs; 519 const struct cmn2asic_msg_mapping *message_map; 520 const struct cmn2asic_mapping *clock_map; 521 const struct cmn2asic_mapping *feature_map; 522 const struct cmn2asic_mapping *table_map; 523 const struct cmn2asic_mapping *pwr_src_map; 524 const struct cmn2asic_mapping *workload_map; 525 struct mutex message_lock; 526 uint64_t pool_size; 527 528 struct smu_table_context smu_table; 529 struct smu_dpm_context smu_dpm; 530 struct smu_power_context smu_power; 531 struct smu_feature smu_feature; 532 struct amd_pp_display_configuration *display_config; 533 struct smu_baco_context smu_baco; 534 struct smu_temperature_range thermal_range; 535 void *od_settings; 536 537 struct smu_umd_pstate_table pstate_table; 538 uint32_t pstate_sclk; 539 uint32_t pstate_mclk; 540 541 bool od_enabled; 542 uint32_t current_power_limit; 543 uint32_t default_power_limit; 544 uint32_t max_power_limit; 545 uint32_t min_power_limit; 546 547 /* soft pptable */ 548 uint32_t ppt_offset_bytes; 549 uint32_t ppt_size_bytes; 550 uint8_t *ppt_start_addr; 551 552 bool support_power_containment; 553 bool disable_watermark; 554 555 #define WATERMARKS_EXIST (1 << 0) 556 #define WATERMARKS_LOADED (1 << 1) 557 uint32_t watermarks_bitmap; 558 uint32_t hard_min_uclk_req_from_dal; 559 bool disable_uclk_switch; 560 561 /* asic agnostic workload mask */ 562 uint32_t workload_mask; 563 /* default/user workload preference */ 564 uint32_t power_profile_mode; 565 uint32_t workload_refcount[PP_SMC_POWER_PROFILE_COUNT]; 566 /* backend specific custom workload settings */ 567 long *custom_profile_params; 568 bool pm_enabled; 569 bool is_apu; 570 571 uint32_t smc_driver_if_version; 572 uint32_t smc_fw_if_version; 573 uint32_t smc_fw_version; 574 uint32_t smc_fw_caps; 575 uint8_t smc_fw_state; 576 577 bool uploading_custom_pp_table; 578 bool dc_controlled_by_gpio; 579 580 struct work_struct throttling_logging_work; 581 atomic64_t throttle_int_counter; 582 struct work_struct interrupt_work; 583 584 unsigned fan_max_rpm; 585 unsigned manual_fan_speed_pwm; 586 587 uint32_t gfx_default_hard_min_freq; 588 uint32_t gfx_default_soft_max_freq; 589 uint32_t gfx_actual_hard_min_freq; 590 uint32_t gfx_actual_soft_max_freq; 591 592 /* APU only */ 593 uint32_t cpu_default_soft_min_freq; 594 uint32_t cpu_default_soft_max_freq; 595 uint32_t cpu_actual_soft_min_freq; 596 uint32_t cpu_actual_soft_max_freq; 597 uint32_t cpu_core_id_select; 598 uint16_t cpu_core_num; 599 600 struct smu_user_dpm_profile user_dpm_profile; 601 602 struct stb_context stb_context; 603 604 struct firmware pptable_firmware; 605 606 u32 param_reg; 607 u32 msg_reg; 608 u32 resp_reg; 609 610 u32 debug_param_reg; 611 u32 debug_msg_reg; 612 u32 debug_resp_reg; 613 614 struct delayed_work swctf_delayed_work; 615 616 /* data structures for wbrf feature support */ 617 bool wbrf_supported; 618 struct notifier_block wbrf_notifier; 619 struct delayed_work wbrf_delayed_work; 620 }; 621 622 struct i2c_adapter; 623 624 /** 625 * struct pptable_funcs - Callbacks used to interact with the SMU. 626 */ 627 struct pptable_funcs { 628 /** 629 * @run_btc: Calibrate voltage/frequency curve to fit the system's 630 * power delivery and voltage margins. Required for adaptive 631 * voltage frequency scaling (AVFS). 632 */ 633 int (*run_btc)(struct smu_context *smu); 634 635 /** 636 * @get_allowed_feature_mask: Get allowed feature mask. 637 * &feature_mask: Array to store feature mask. 638 * &num: Elements in &feature_mask. 639 */ 640 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 641 642 /** 643 * @get_current_power_state: Get the current power state. 644 * 645 * Return: Current power state on success, negative errno on failure. 646 */ 647 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 648 649 /** 650 * @set_default_dpm_table: Retrieve the default overdrive settings from 651 * the SMU. 652 */ 653 int (*set_default_dpm_table)(struct smu_context *smu); 654 655 int (*set_power_state)(struct smu_context *smu); 656 657 /** 658 * @populate_umd_state_clk: Populate the UMD power state table with 659 * defaults. 660 */ 661 int (*populate_umd_state_clk)(struct smu_context *smu); 662 663 /** 664 * @print_clk_levels: Print DPM clock levels for a clock domain 665 * to buffer. Star current level. 666 * 667 * Used for sysfs interfaces. 668 * Return: Number of characters written to the buffer 669 */ 670 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 671 672 /** 673 * @emit_clk_levels: Print DPM clock levels for a clock domain 674 * to buffer using sysfs_emit_at. Star current level. 675 * 676 * Used for sysfs interfaces. 677 * &buf: sysfs buffer 678 * &offset: offset within buffer to start printing, which is updated by the 679 * function. 680 * 681 * Return: 0 on Success or Negative to indicate an error occurred. 682 */ 683 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 684 685 /** 686 * @force_clk_levels: Set a range of allowed DPM levels for a clock 687 * domain. 688 * &clk_type: Clock domain. 689 * &mask: Range of allowed DPM levels. 690 */ 691 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 692 693 /** 694 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 695 * &type: Type of edit. 696 * &input: Edit parameters. 697 * &size: Size of &input. 698 */ 699 int (*od_edit_dpm_table)(struct smu_context *smu, 700 enum PP_OD_DPM_TABLE_COMMAND type, 701 long *input, uint32_t size); 702 703 /** 704 * @restore_user_od_settings: Restore the user customized 705 * OD settings on S3/S4/Runpm resume. 706 */ 707 int (*restore_user_od_settings)(struct smu_context *smu); 708 709 /** 710 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 711 * domain. 712 */ 713 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 714 enum smu_clk_type clk_type, 715 struct 716 pp_clock_levels_with_latency 717 *clocks); 718 /** 719 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 720 * domain. 721 */ 722 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 723 enum amd_pp_clock_type type, 724 struct 725 pp_clock_levels_with_voltage 726 *clocks); 727 728 /** 729 * @get_power_profile_mode: Print all power profile modes to 730 * buffer. Star current mode. 731 */ 732 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 733 734 /** 735 * @set_power_profile_mode: Set a power profile mode. Also used to 736 * create/set custom power profile modes. 737 * &input: Power profile mode parameters. 738 * &workload_mask: mask of workloads to enable 739 * &custom_params: custom profile parameters 740 * &custom_params_max_idx: max valid idx into custom_params 741 */ 742 int (*set_power_profile_mode)(struct smu_context *smu, u32 workload_mask, 743 long *custom_params, u32 custom_params_max_idx); 744 745 /** 746 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 747 * management. 748 */ 749 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int inst); 750 751 /** 752 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 753 * management. 754 */ 755 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 756 757 /** 758 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU 759 */ 760 int (*set_gfx_power_up_by_imu)(struct smu_context *smu); 761 762 /** 763 * @read_sensor: Read data from a sensor. 764 * &sensor: Sensor to read data from. 765 * &data: Sensor reading. 766 * &size: Size of &data. 767 */ 768 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 769 void *data, uint32_t *size); 770 771 /** 772 * @get_apu_thermal_limit: get apu core limit from smu 773 * &limit: current limit temperature in millidegrees Celsius 774 */ 775 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit); 776 777 /** 778 * @set_apu_thermal_limit: update all controllers with new limit 779 * &limit: limit temperature to be setted, in millidegrees Celsius 780 */ 781 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit); 782 783 /** 784 * @pre_display_config_changed: Prepare GPU for a display configuration 785 * change. 786 * 787 * Disable display tracking and pin memory clock speed to maximum. Used 788 * in display component synchronization. 789 */ 790 int (*pre_display_config_changed)(struct smu_context *smu); 791 792 /** 793 * @display_config_changed: Notify the SMU of the current display 794 * configuration. 795 * 796 * Allows SMU to properly track blanking periods for memory clock 797 * adjustment. Used in display component synchronization. 798 */ 799 int (*display_config_changed)(struct smu_context *smu); 800 801 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 802 803 /** 804 * @notify_smc_display_config: Applies display requirements to the 805 * current power state. 806 * 807 * Optimize deep sleep DCEFclk and mclk for the current display 808 * configuration. Used in display component synchronization. 809 */ 810 int (*notify_smc_display_config)(struct smu_context *smu); 811 812 /** 813 * @is_dpm_running: Check if DPM is running. 814 * 815 * Return: True if DPM is running, false otherwise. 816 */ 817 bool (*is_dpm_running)(struct smu_context *smu); 818 819 /** 820 * @get_fan_speed_pwm: Get the current fan speed in PWM. 821 */ 822 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 823 824 /** 825 * @get_fan_speed_rpm: Get the current fan speed in rpm. 826 */ 827 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 828 829 /** 830 * @set_watermarks_table: Configure and upload the watermarks tables to 831 * the SMU. 832 */ 833 int (*set_watermarks_table)(struct smu_context *smu, 834 struct pp_smu_wm_range_sets *clock_ranges); 835 836 /** 837 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 838 */ 839 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 840 841 /** 842 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 843 * &clocks_in_khz: Array of DPM levels. 844 * &num_states: Elements in &clocks_in_khz. 845 */ 846 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 847 848 /** 849 * @set_default_od_settings: Set the overdrive tables to defaults. 850 */ 851 int (*set_default_od_settings)(struct smu_context *smu); 852 853 /** 854 * @set_performance_level: Set a performance level. 855 */ 856 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 857 858 /** 859 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 860 * clock switching. 861 * 862 * Disabling this feature forces memory clock speed to maximum. 863 * Enabling sets the minimum memory clock capable of driving the 864 * current display configuration. 865 */ 866 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 867 868 /** 869 * @get_power_limit: Get the device's power limits. 870 */ 871 int (*get_power_limit)(struct smu_context *smu, 872 uint32_t *current_power_limit, 873 uint32_t *default_power_limit, 874 uint32_t *max_power_limit, 875 uint32_t *min_power_limit); 876 877 /** 878 * @get_ppt_limit: Get the device's ppt limits. 879 */ 880 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 881 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 882 883 /** 884 * @set_df_cstate: Set data fabric cstate. 885 */ 886 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 887 888 /** 889 * @update_pcie_parameters: Update and upload the system's PCIe 890 * capabilites to the SMU. 891 * &pcie_gen_cap: Maximum allowed PCIe generation. 892 * &pcie_width_cap: Maximum allowed PCIe width. 893 */ 894 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap); 895 896 /** 897 * @i2c_init: Initialize i2c. 898 * 899 * The i2c bus is used internally by the SMU voltage regulators and 900 * other devices. The i2c's EEPROM also stores bad page tables on boards 901 * with ECC. 902 */ 903 int (*i2c_init)(struct smu_context *smu); 904 905 /** 906 * @i2c_fini: Tear down i2c. 907 */ 908 void (*i2c_fini)(struct smu_context *smu); 909 910 /** 911 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 912 */ 913 void (*get_unique_id)(struct smu_context *smu); 914 915 /** 916 * @get_dpm_clock_table: Get a copy of the DPM clock table. 917 * 918 * Used by display component in bandwidth and watermark calculations. 919 */ 920 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 921 922 /** 923 * @init_microcode: Request the SMU's firmware from the kernel. 924 */ 925 int (*init_microcode)(struct smu_context *smu); 926 927 /** 928 * @load_microcode: Load firmware onto the SMU. 929 */ 930 int (*load_microcode)(struct smu_context *smu); 931 932 /** 933 * @fini_microcode: Release the SMU's firmware. 934 */ 935 void (*fini_microcode)(struct smu_context *smu); 936 937 /** 938 * @init_smc_tables: Initialize the SMU tables. 939 */ 940 int (*init_smc_tables)(struct smu_context *smu); 941 942 /** 943 * @fini_smc_tables: Release the SMU tables. 944 */ 945 int (*fini_smc_tables)(struct smu_context *smu); 946 947 /** 948 * @init_power: Initialize the power gate table context. 949 */ 950 int (*init_power)(struct smu_context *smu); 951 952 /** 953 * @fini_power: Release the power gate table context. 954 */ 955 int (*fini_power)(struct smu_context *smu); 956 957 /** 958 * @check_fw_status: Check the SMU's firmware status. 959 * 960 * Return: Zero if check passes, negative errno on failure. 961 */ 962 int (*check_fw_status)(struct smu_context *smu); 963 964 /** 965 * @set_mp1_state: put SMU into a correct state for comming 966 * resume from runpm or gpu reset. 967 */ 968 int (*set_mp1_state)(struct smu_context *smu, 969 enum pp_mp1_state mp1_state); 970 971 /** 972 * @setup_pptable: Initialize the power play table and populate it with 973 * default values. 974 */ 975 int (*setup_pptable)(struct smu_context *smu); 976 977 /** 978 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 979 */ 980 int (*get_vbios_bootup_values)(struct smu_context *smu); 981 982 /** 983 * @check_fw_version: Print driver and SMU interface versions to the 984 * system log. 985 * 986 * Interface mismatch is not a critical failure. 987 */ 988 int (*check_fw_version)(struct smu_context *smu); 989 990 /** 991 * @powergate_sdma: Power up/down system direct memory access. 992 */ 993 int (*powergate_sdma)(struct smu_context *smu, bool gate); 994 995 /** 996 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 997 * gating. 998 */ 999 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 1000 1001 /** 1002 * @write_pptable: Write the power play table to the SMU. 1003 */ 1004 int (*write_pptable)(struct smu_context *smu); 1005 1006 /** 1007 * @set_driver_table_location: Send the location of the driver table to 1008 * the SMU. 1009 */ 1010 int (*set_driver_table_location)(struct smu_context *smu); 1011 1012 /** 1013 * @set_tool_table_location: Send the location of the tool table to the 1014 * SMU. 1015 */ 1016 int (*set_tool_table_location)(struct smu_context *smu); 1017 1018 /** 1019 * @notify_memory_pool_location: Send the location of the memory pool to 1020 * the SMU. 1021 */ 1022 int (*notify_memory_pool_location)(struct smu_context *smu); 1023 1024 /** 1025 * @system_features_control: Enable/disable all SMU features. 1026 */ 1027 int (*system_features_control)(struct smu_context *smu, bool en); 1028 1029 /** 1030 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 1031 * &msg: Type of message. 1032 * ¶m: Message parameter. 1033 * &read_arg: SMU response (optional). 1034 */ 1035 int (*send_smc_msg_with_param)(struct smu_context *smu, 1036 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 1037 1038 /** 1039 * @send_smc_msg: Send a message to the SMU. 1040 * &msg: Type of message. 1041 * &read_arg: SMU response (optional). 1042 */ 1043 int (*send_smc_msg)(struct smu_context *smu, 1044 enum smu_message_type msg, 1045 uint32_t *read_arg); 1046 1047 /** 1048 * @init_display_count: Notify the SMU of the number of display 1049 * components in current display configuration. 1050 */ 1051 int (*init_display_count)(struct smu_context *smu, uint32_t count); 1052 1053 /** 1054 * @set_allowed_mask: Notify the SMU of the features currently allowed 1055 * by the driver. 1056 */ 1057 int (*set_allowed_mask)(struct smu_context *smu); 1058 1059 /** 1060 * @get_enabled_mask: Get a mask of features that are currently enabled 1061 * on the SMU. 1062 * &feature_mask: Enabled feature mask. 1063 */ 1064 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1065 1066 /** 1067 * @feature_is_enabled: Test if a feature is enabled. 1068 * 1069 * Return: One if enabled, zero if disabled. 1070 */ 1071 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1072 1073 /** 1074 * @disable_all_features_with_exception: Disable all features with 1075 * exception to those in &mask. 1076 */ 1077 int (*disable_all_features_with_exception)(struct smu_context *smu, 1078 enum smu_feature_mask mask); 1079 1080 /** 1081 * @notify_display_change: General interface call to let SMU know about DC change 1082 */ 1083 int (*notify_display_change)(struct smu_context *smu); 1084 1085 /** 1086 * @set_power_limit: Set power limit in watts. 1087 */ 1088 int (*set_power_limit)(struct smu_context *smu, 1089 enum smu_ppt_limit_type limit_type, 1090 uint32_t limit); 1091 1092 /** 1093 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1094 * table with values from the SMU. 1095 */ 1096 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1097 1098 /** 1099 * @enable_thermal_alert: Enable thermal alert interrupts. 1100 */ 1101 int (*enable_thermal_alert)(struct smu_context *smu); 1102 1103 /** 1104 * @disable_thermal_alert: Disable thermal alert interrupts. 1105 */ 1106 int (*disable_thermal_alert)(struct smu_context *smu); 1107 1108 /** 1109 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1110 * clock speed in MHz. 1111 */ 1112 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1113 1114 /** 1115 * @display_clock_voltage_request: Set a hard minimum frequency 1116 * for a clock domain. 1117 */ 1118 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1119 pp_display_clock_request 1120 *clock_req); 1121 1122 /** 1123 * @get_fan_control_mode: Get the current fan control mode. 1124 */ 1125 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1126 1127 /** 1128 * @set_fan_control_mode: Set the fan control mode. 1129 */ 1130 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1131 1132 /** 1133 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1134 */ 1135 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1136 1137 /** 1138 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1139 */ 1140 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1141 1142 /** 1143 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1144 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1145 */ 1146 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1147 1148 /** 1149 * @gfx_off_control: Enable/disable graphics engine poweroff. 1150 */ 1151 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1152 1153 1154 /** 1155 * @get_gfx_off_status: Get graphics engine poweroff status. 1156 * 1157 * Return: 1158 * 0 - GFXOFF(default). 1159 * 1 - Transition out of GFX State. 1160 * 2 - Not in GFXOFF. 1161 * 3 - Transition into GFXOFF. 1162 */ 1163 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1164 1165 /** 1166 * @gfx_off_entrycount: total GFXOFF entry count at the time of 1167 * query since system power-up 1168 */ 1169 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount); 1170 1171 /** 1172 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging 1173 */ 1174 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); 1175 1176 /** 1177 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval 1178 */ 1179 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency); 1180 1181 /** 1182 * @register_irq_handler: Register interupt request handlers. 1183 */ 1184 int (*register_irq_handler)(struct smu_context *smu); 1185 1186 /** 1187 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1188 */ 1189 int (*set_azalia_d3_pme)(struct smu_context *smu); 1190 1191 /** 1192 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1193 * clock speeds table. 1194 * 1195 * Provides a way for the display component (DC) to get the max 1196 * sustainable clocks from the SMU. 1197 */ 1198 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1199 1200 /** 1201 * @get_bamaco_support: Check if GPU supports BACO/MACO 1202 * BACO: Bus Active, Chip Off 1203 * MACO: Memory Active, Chip Off 1204 */ 1205 int (*get_bamaco_support)(struct smu_context *smu); 1206 1207 /** 1208 * @baco_get_state: Get the current BACO state. 1209 * 1210 * Return: Current BACO state. 1211 */ 1212 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1213 1214 /** 1215 * @baco_set_state: Enter/exit BACO. 1216 */ 1217 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1218 1219 /** 1220 * @baco_enter: Enter BACO. 1221 */ 1222 int (*baco_enter)(struct smu_context *smu); 1223 1224 /** 1225 * @baco_exit: Exit Baco. 1226 */ 1227 int (*baco_exit)(struct smu_context *smu); 1228 1229 /** 1230 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1231 */ 1232 bool (*mode1_reset_is_support)(struct smu_context *smu); 1233 1234 /** 1235 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1236 */ 1237 bool (*mode2_reset_is_support)(struct smu_context *smu); 1238 1239 /** 1240 * @link_reset_is_support: Check if GPU supports link reset. 1241 */ 1242 bool (*link_reset_is_support)(struct smu_context *smu); 1243 1244 /** 1245 * @mode1_reset: Perform mode1 reset. 1246 * 1247 * Complete GPU reset. 1248 */ 1249 int (*mode1_reset)(struct smu_context *smu); 1250 1251 /** 1252 * @mode2_reset: Perform mode2 reset. 1253 * 1254 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1255 * IPs reset varies by asic. 1256 */ 1257 int (*mode2_reset)(struct smu_context *smu); 1258 /* for gfx feature enablement after mode2 reset */ 1259 int (*enable_gfx_features)(struct smu_context *smu); 1260 1261 /** 1262 * @link_reset: Perform link reset. 1263 * 1264 * The gfx device driver reset 1265 */ 1266 int (*link_reset)(struct smu_context *smu); 1267 1268 /** 1269 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1270 * domain in MHz. 1271 */ 1272 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1273 1274 /** 1275 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1276 * domain in MHz. 1277 */ 1278 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max, 1279 bool automatic); 1280 1281 /** 1282 * @set_power_source: Notify the SMU of the current power source. 1283 */ 1284 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1285 1286 /** 1287 * @log_thermal_throttling_event: Print a thermal throttling warning to 1288 * the system's log. 1289 */ 1290 void (*log_thermal_throttling_event)(struct smu_context *smu); 1291 1292 /** 1293 * @get_pp_feature_mask: Print a human readable table of enabled 1294 * features to buffer. 1295 */ 1296 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1297 1298 /** 1299 * @set_pp_feature_mask: Request the SMU enable/disable features to 1300 * match those enabled in &new_mask. 1301 */ 1302 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1303 1304 /** 1305 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1306 * 1307 * Return: Size of &table 1308 */ 1309 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1310 1311 /** 1312 * @get_pm_metrics: Get one snapshot of power management metrics from 1313 * PMFW. 1314 * 1315 * Return: Size of the metrics sample 1316 */ 1317 ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics, 1318 size_t size); 1319 1320 /** 1321 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1322 */ 1323 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1324 1325 /** 1326 * @gfx_ulv_control: Enable/disable ultra low voltage. 1327 */ 1328 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1329 1330 /** 1331 * @deep_sleep_control: Enable/disable deep sleep. 1332 */ 1333 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1334 1335 /** 1336 * @get_fan_parameters: Get fan parameters. 1337 * 1338 * Get maximum fan speed from the power play table. 1339 */ 1340 int (*get_fan_parameters)(struct smu_context *smu); 1341 1342 /** 1343 * @post_init: Helper function for asic specific workarounds. 1344 */ 1345 int (*post_init)(struct smu_context *smu); 1346 1347 /** 1348 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1349 */ 1350 void (*interrupt_work)(struct smu_context *smu); 1351 1352 /** 1353 * @gpo_control: Enable/disable graphics power optimization if supported. 1354 */ 1355 int (*gpo_control)(struct smu_context *smu, bool enablement); 1356 1357 /** 1358 * @gfx_state_change_set: Send the current graphics state to the SMU. 1359 */ 1360 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1361 1362 /** 1363 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1364 * parameters to defaults. 1365 */ 1366 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1367 1368 /** 1369 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1370 */ 1371 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1372 1373 /** 1374 * @wait_for_event: Wait for events from SMU. 1375 */ 1376 int (*wait_for_event)(struct smu_context *smu, 1377 enum smu_event_type event, uint64_t event_arg); 1378 1379 /** 1380 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1381 * of SMUBUS table. 1382 */ 1383 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1384 1385 /** 1386 * @send_rma_reason: message rma reason event to SMU. 1387 */ 1388 int (*send_rma_reason)(struct smu_context *smu); 1389 1390 /** 1391 * @reset_sdma: message SMU to soft reset sdma instance. 1392 */ 1393 int (*reset_sdma)(struct smu_context *smu, uint32_t inst_mask); 1394 /** 1395 * @reset_sdma_is_supported: Check if support resets the SDMA engine. 1396 */ 1397 bool (*reset_sdma_is_supported)(struct smu_context *smu); 1398 1399 /** 1400 * @get_ecc_table: message SMU to get ECC INFO table. 1401 */ 1402 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1403 1404 1405 /** 1406 * @stb_collect_info: Collects Smart Trace Buffers data. 1407 */ 1408 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1409 1410 /** 1411 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1412 */ 1413 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1414 1415 /** 1416 * @set_config_table: Apply the input DriverSmuConfig table settings. 1417 */ 1418 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1419 1420 /** 1421 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1422 * of SMUBUS table. 1423 */ 1424 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1425 1426 /** 1427 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP 1428 */ 1429 int (*init_pptable_microcode)(struct smu_context *smu); 1430 1431 /** 1432 * @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power 1433 * management. 1434 */ 1435 int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable); 1436 1437 /** 1438 * @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power 1439 * management. 1440 */ 1441 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable); 1442 1443 /** 1444 * @set_mall_enable: Init MALL power gating control. 1445 */ 1446 int (*set_mall_enable)(struct smu_context *smu); 1447 1448 /** 1449 * @notify_rlc_state: Notify RLC power state to SMU. 1450 */ 1451 int (*notify_rlc_state)(struct smu_context *smu, bool en); 1452 1453 /** 1454 * @is_asic_wbrf_supported: check whether PMFW supports the wbrf feature 1455 */ 1456 bool (*is_asic_wbrf_supported)(struct smu_context *smu); 1457 1458 /** 1459 * @enable_uclk_shadow: Enable the uclk shadow feature on wbrf supported 1460 */ 1461 int (*enable_uclk_shadow)(struct smu_context *smu, bool enable); 1462 1463 /** 1464 * @set_wbrf_exclusion_ranges: notify SMU the wifi bands occupied 1465 */ 1466 int (*set_wbrf_exclusion_ranges)(struct smu_context *smu, 1467 struct freq_band_range *exclusion_ranges); 1468 }; 1469 1470 typedef enum { 1471 METRICS_CURR_GFXCLK, 1472 METRICS_CURR_SOCCLK, 1473 METRICS_CURR_UCLK, 1474 METRICS_CURR_VCLK, 1475 METRICS_CURR_VCLK1, 1476 METRICS_CURR_DCLK, 1477 METRICS_CURR_DCLK1, 1478 METRICS_CURR_FCLK, 1479 METRICS_CURR_DCEFCLK, 1480 METRICS_AVERAGE_CPUCLK, 1481 METRICS_AVERAGE_GFXCLK, 1482 METRICS_AVERAGE_SOCCLK, 1483 METRICS_AVERAGE_FCLK, 1484 METRICS_AVERAGE_UCLK, 1485 METRICS_AVERAGE_VCLK, 1486 METRICS_AVERAGE_DCLK, 1487 METRICS_AVERAGE_VCLK1, 1488 METRICS_AVERAGE_DCLK1, 1489 METRICS_AVERAGE_GFXACTIVITY, 1490 METRICS_AVERAGE_MEMACTIVITY, 1491 METRICS_AVERAGE_VCNACTIVITY, 1492 METRICS_AVERAGE_SOCKETPOWER, 1493 METRICS_TEMPERATURE_EDGE, 1494 METRICS_TEMPERATURE_HOTSPOT, 1495 METRICS_TEMPERATURE_MEM, 1496 METRICS_TEMPERATURE_VRGFX, 1497 METRICS_TEMPERATURE_VRSOC, 1498 METRICS_TEMPERATURE_VRMEM, 1499 METRICS_THROTTLER_STATUS, 1500 METRICS_CURR_FANSPEED, 1501 METRICS_VOLTAGE_VDDSOC, 1502 METRICS_VOLTAGE_VDDGFX, 1503 METRICS_SS_APU_SHARE, 1504 METRICS_SS_DGPU_SHARE, 1505 METRICS_UNIQUE_ID_UPPER32, 1506 METRICS_UNIQUE_ID_LOWER32, 1507 METRICS_PCIE_RATE, 1508 METRICS_PCIE_WIDTH, 1509 METRICS_CURR_FANPWM, 1510 METRICS_CURR_SOCKETPOWER, 1511 METRICS_AVERAGE_VPECLK, 1512 METRICS_AVERAGE_IPUCLK, 1513 METRICS_AVERAGE_MPIPUCLK, 1514 METRICS_THROTTLER_RESIDENCY_PROCHOT, 1515 METRICS_THROTTLER_RESIDENCY_SPL, 1516 METRICS_THROTTLER_RESIDENCY_FPPT, 1517 METRICS_THROTTLER_RESIDENCY_SPPT, 1518 METRICS_THROTTLER_RESIDENCY_THM_CORE, 1519 METRICS_THROTTLER_RESIDENCY_THM_GFX, 1520 METRICS_THROTTLER_RESIDENCY_THM_SOC, 1521 } MetricsMember_t; 1522 1523 enum smu_cmn2asic_mapping_type { 1524 CMN2ASIC_MAPPING_MSG, 1525 CMN2ASIC_MAPPING_CLK, 1526 CMN2ASIC_MAPPING_FEATURE, 1527 CMN2ASIC_MAPPING_TABLE, 1528 CMN2ASIC_MAPPING_PWR, 1529 CMN2ASIC_MAPPING_WORKLOAD, 1530 }; 1531 1532 enum smu_baco_seq { 1533 BACO_SEQ_BACO = 0, 1534 BACO_SEQ_MSR, 1535 BACO_SEQ_BAMACO, 1536 BACO_SEQ_ULPS, 1537 BACO_SEQ_COUNT, 1538 }; 1539 1540 #define MSG_MAP(msg, index, flags) \ 1541 [SMU_MSG_##msg] = {1, (index), (flags)} 1542 1543 #define CLK_MAP(clk, index) \ 1544 [SMU_##clk] = {1, (index)} 1545 1546 #define FEA_MAP(fea) \ 1547 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1548 1549 #define FEA_MAP_REVERSE(fea) \ 1550 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1551 1552 #define FEA_MAP_HALF_REVERSE(fea) \ 1553 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1554 1555 #define TAB_MAP(tab) \ 1556 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1557 1558 #define TAB_MAP_VALID(tab) \ 1559 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1560 1561 #define TAB_MAP_INVALID(tab) \ 1562 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1563 1564 #define PWR_MAP(tab) \ 1565 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1566 1567 #define WORKLOAD_MAP(profile, workload) \ 1568 [profile] = {1, (workload)} 1569 1570 /** 1571 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1572 * 1573 * @dst: Pointer to destination struct 1574 * @first_dst_member: The member name in @dst where the overwrite begins 1575 * @last_dst_member: The member name in @dst where the overwrite ends after 1576 * @src: Pointer to the source struct 1577 * @first_src_member: The member name in @src where the copy begins 1578 * 1579 */ 1580 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1581 src, first_src_member) \ 1582 ({ \ 1583 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1584 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1585 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1586 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1587 __dst_offset; \ 1588 BUILD_BUG_ON(__src_size != __dst_size); \ 1589 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1590 (u8 *)(src) + __src_offset, \ 1591 __dst_size); \ 1592 }) 1593 1594 typedef struct { 1595 uint16_t LowFreq; 1596 uint16_t HighFreq; 1597 } WifiOneBand_t; 1598 1599 typedef struct { 1600 uint32_t WifiBandEntryNum; 1601 WifiOneBand_t WifiBandEntry[11]; 1602 uint32_t MmHubPadding[8]; 1603 } WifiBandEntryTable_t; 1604 1605 #define STR_SOC_PSTATE_POLICY "soc_pstate" 1606 #define STR_XGMI_PLPD_POLICY "xgmi_plpd" 1607 1608 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 1609 enum pp_pm_policy p_type); 1610 1611 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1612 int smu_get_power_limit(void *handle, 1613 uint32_t *limit, 1614 enum pp_power_limit_level pp_limit_level, 1615 enum pp_power_type pp_power_type); 1616 1617 bool smu_mode1_reset_is_support(struct smu_context *smu); 1618 bool smu_mode2_reset_is_support(struct smu_context *smu); 1619 bool smu_link_reset_is_support(struct smu_context *smu); 1620 int smu_mode1_reset(struct smu_context *smu); 1621 int smu_link_reset(struct smu_context *smu); 1622 1623 extern const struct amd_ip_funcs smu_ip_funcs; 1624 1625 bool is_support_sw_smu(struct amdgpu_device *adev); 1626 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1627 int smu_write_watermarks_table(struct smu_context *smu); 1628 1629 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1630 uint32_t *min, uint32_t *max); 1631 1632 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1633 uint32_t min, uint32_t max); 1634 1635 int smu_set_gfx_power_up_by_imu(struct smu_context *smu); 1636 1637 int smu_set_ac_dc(struct smu_context *smu); 1638 1639 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 1640 enum pp_xgmi_plpd_mode mode); 1641 1642 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); 1643 1644 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); 1645 1646 int smu_set_residency_gfxoff(struct smu_context *smu, bool value); 1647 1648 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1649 1650 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1651 1652 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1653 uint64_t event_arg); 1654 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1655 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1656 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1657 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1658 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1659 int smu_send_rma_reason(struct smu_context *smu); 1660 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask); 1661 bool smu_reset_sdma_is_supported(struct smu_context *smu); 1662 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 1663 int level); 1664 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 1665 enum pp_pm_policy p_type, char *sysbuf); 1666 1667 #endif 1668 #endif 1669