1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include "amdgpu.h" 26 #include "kgd_pp_interface.h" 27 #include "dm_pp_interface.h" 28 #include "dm_pp_smu.h" 29 #include "smu_types.h" 30 #include "linux/firmware.h" 31 32 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 33 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 34 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 35 #define SMU_FW_NAME_LEN 0x24 36 37 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 38 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 39 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 40 41 // Power Throttlers 42 #define SMU_THROTTLER_PPT0_BIT 0 43 #define SMU_THROTTLER_PPT1_BIT 1 44 #define SMU_THROTTLER_PPT2_BIT 2 45 #define SMU_THROTTLER_PPT3_BIT 3 46 #define SMU_THROTTLER_SPL_BIT 4 47 #define SMU_THROTTLER_FPPT_BIT 5 48 #define SMU_THROTTLER_SPPT_BIT 6 49 #define SMU_THROTTLER_SPPT_APU_BIT 7 50 51 // Current Throttlers 52 #define SMU_THROTTLER_TDC_GFX_BIT 16 53 #define SMU_THROTTLER_TDC_SOC_BIT 17 54 #define SMU_THROTTLER_TDC_MEM_BIT 18 55 #define SMU_THROTTLER_TDC_VDD_BIT 19 56 #define SMU_THROTTLER_TDC_CVIP_BIT 20 57 #define SMU_THROTTLER_EDC_CPU_BIT 21 58 #define SMU_THROTTLER_EDC_GFX_BIT 22 59 #define SMU_THROTTLER_APCC_BIT 23 60 61 // Temperature 62 #define SMU_THROTTLER_TEMP_GPU_BIT 32 63 #define SMU_THROTTLER_TEMP_CORE_BIT 33 64 #define SMU_THROTTLER_TEMP_MEM_BIT 34 65 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 66 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 67 #define SMU_THROTTLER_TEMP_SOC_BIT 37 68 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 69 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 70 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 71 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 72 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 73 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 74 #define SMU_THROTTLER_VRHOT0_BIT 44 75 #define SMU_THROTTLER_VRHOT1_BIT 45 76 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 77 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 78 79 // Other 80 #define SMU_THROTTLER_PPM_BIT 56 81 #define SMU_THROTTLER_FIT_BIT 57 82 83 struct smu_hw_power_state { 84 unsigned int magic; 85 }; 86 87 struct smu_power_state; 88 89 enum smu_state_ui_label { 90 SMU_STATE_UI_LABEL_NONE, 91 SMU_STATE_UI_LABEL_BATTERY, 92 SMU_STATE_UI_TABEL_MIDDLE_LOW, 93 SMU_STATE_UI_LABEL_BALLANCED, 94 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 95 SMU_STATE_UI_LABEL_PERFORMANCE, 96 SMU_STATE_UI_LABEL_BACO, 97 }; 98 99 enum smu_state_classification_flag { 100 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 101 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 102 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 103 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 104 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 105 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 106 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 107 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 108 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 109 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 111 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 112 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 113 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 114 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 115 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 116 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 117 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 118 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 119 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 120 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 121 }; 122 123 struct smu_state_classification_block { 124 enum smu_state_ui_label ui_label; 125 enum smu_state_classification_flag flags; 126 int bios_index; 127 bool temporary_state; 128 bool to_be_deleted; 129 }; 130 131 struct smu_state_pcie_block { 132 unsigned int lanes; 133 }; 134 135 enum smu_refreshrate_source { 136 SMU_REFRESHRATE_SOURCE_EDID, 137 SMU_REFRESHRATE_SOURCE_EXPLICIT 138 }; 139 140 struct smu_state_display_block { 141 bool disable_frame_modulation; 142 bool limit_refreshrate; 143 enum smu_refreshrate_source refreshrate_source; 144 int explicit_refreshrate; 145 int edid_refreshrate_index; 146 bool enable_vari_bright; 147 }; 148 149 struct smu_state_memory_block { 150 bool dll_off; 151 uint8_t m3arb; 152 uint8_t unused[3]; 153 }; 154 155 struct smu_state_software_algorithm_block { 156 bool disable_load_balancing; 157 bool enable_sleep_for_timestamps; 158 }; 159 160 struct smu_temperature_range { 161 int min; 162 int max; 163 int edge_emergency_max; 164 int hotspot_min; 165 int hotspot_crit_max; 166 int hotspot_emergency_max; 167 int mem_min; 168 int mem_crit_max; 169 int mem_emergency_max; 170 int software_shutdown_temp; 171 int software_shutdown_temp_offset; 172 }; 173 174 struct smu_state_validation_block { 175 bool single_display_only; 176 bool disallow_on_dc; 177 uint8_t supported_power_levels; 178 }; 179 180 struct smu_uvd_clocks { 181 uint32_t vclk; 182 uint32_t dclk; 183 }; 184 185 /** 186 * Structure to hold a SMU Power State. 187 */ 188 struct smu_power_state { 189 uint32_t id; 190 struct list_head ordered_list; 191 struct list_head all_states_list; 192 193 struct smu_state_classification_block classification; 194 struct smu_state_validation_block validation; 195 struct smu_state_pcie_block pcie; 196 struct smu_state_display_block display; 197 struct smu_state_memory_block memory; 198 struct smu_state_software_algorithm_block software; 199 struct smu_uvd_clocks uvd_clocks; 200 struct smu_hw_power_state hardware; 201 }; 202 203 enum smu_power_src_type { 204 SMU_POWER_SOURCE_AC, 205 SMU_POWER_SOURCE_DC, 206 SMU_POWER_SOURCE_COUNT, 207 }; 208 209 enum smu_ppt_limit_type { 210 SMU_DEFAULT_PPT_LIMIT = 0, 211 SMU_FAST_PPT_LIMIT, 212 }; 213 214 enum smu_ppt_limit_level { 215 SMU_PPT_LIMIT_MIN = -1, 216 SMU_PPT_LIMIT_CURRENT, 217 SMU_PPT_LIMIT_DEFAULT, 218 SMU_PPT_LIMIT_MAX, 219 }; 220 221 enum smu_memory_pool_size { 222 SMU_MEMORY_POOL_SIZE_ZERO = 0, 223 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 224 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 225 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 226 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 227 }; 228 229 struct smu_user_dpm_profile { 230 uint32_t fan_mode; 231 uint32_t power_limit; 232 uint32_t fan_speed_pwm; 233 uint32_t fan_speed_rpm; 234 uint32_t flags; 235 uint32_t user_od; 236 237 /* user clock state information */ 238 uint32_t clk_mask[SMU_CLK_COUNT]; 239 uint32_t clk_dependency; 240 }; 241 242 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 243 do { \ 244 tables[table_id].size = s; \ 245 tables[table_id].align = a; \ 246 tables[table_id].domain = d; \ 247 } while (0) 248 249 struct smu_table { 250 uint64_t size; 251 uint32_t align; 252 uint8_t domain; 253 uint64_t mc_address; 254 void *cpu_addr; 255 struct amdgpu_bo *bo; 256 uint32_t version; 257 }; 258 259 enum smu_perf_level_designation { 260 PERF_LEVEL_ACTIVITY, 261 PERF_LEVEL_POWER_CONTAINMENT, 262 }; 263 264 struct smu_performance_level { 265 uint32_t core_clock; 266 uint32_t memory_clock; 267 uint32_t vddc; 268 uint32_t vddci; 269 uint32_t non_local_mem_freq; 270 uint32_t non_local_mem_width; 271 }; 272 273 struct smu_clock_info { 274 uint32_t min_mem_clk; 275 uint32_t max_mem_clk; 276 uint32_t min_eng_clk; 277 uint32_t max_eng_clk; 278 uint32_t min_bus_bandwidth; 279 uint32_t max_bus_bandwidth; 280 }; 281 282 struct smu_bios_boot_up_values { 283 uint32_t revision; 284 uint32_t gfxclk; 285 uint32_t uclk; 286 uint32_t socclk; 287 uint32_t dcefclk; 288 uint32_t eclk; 289 uint32_t vclk; 290 uint32_t dclk; 291 uint16_t vddc; 292 uint16_t vddci; 293 uint16_t mvddc; 294 uint16_t vdd_gfx; 295 uint8_t cooling_id; 296 uint32_t pp_table_id; 297 uint32_t format_revision; 298 uint32_t content_revision; 299 uint32_t fclk; 300 uint32_t lclk; 301 uint32_t firmware_caps; 302 }; 303 304 enum smu_table_id { 305 SMU_TABLE_PPTABLE = 0, 306 SMU_TABLE_WATERMARKS, 307 SMU_TABLE_CUSTOM_DPM, 308 SMU_TABLE_DPMCLOCKS, 309 SMU_TABLE_AVFS, 310 SMU_TABLE_AVFS_PSM_DEBUG, 311 SMU_TABLE_AVFS_FUSE_OVERRIDE, 312 SMU_TABLE_PMSTATUSLOG, 313 SMU_TABLE_SMU_METRICS, 314 SMU_TABLE_DRIVER_SMU_CONFIG, 315 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 316 SMU_TABLE_OVERDRIVE, 317 SMU_TABLE_I2C_COMMANDS, 318 SMU_TABLE_PACE, 319 SMU_TABLE_ECCINFO, 320 SMU_TABLE_COMBO_PPTABLE, 321 SMU_TABLE_COUNT, 322 }; 323 324 struct smu_table_context { 325 void *power_play_table; 326 uint32_t power_play_table_size; 327 void *hardcode_pptable; 328 unsigned long metrics_time; 329 void *metrics_table; 330 void *clocks_table; 331 void *watermarks_table; 332 333 void *max_sustainable_clocks; 334 struct smu_bios_boot_up_values boot_values; 335 void *driver_pptable; 336 void *combo_pptable; 337 void *ecc_table; 338 void *driver_smu_config_table; 339 struct smu_table tables[SMU_TABLE_COUNT]; 340 /* 341 * The driver table is just a staging buffer for 342 * uploading/downloading content from the SMU. 343 * 344 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 345 * SMU_MSG_TransferTableDram2Smu instructs SMU 346 * which content driver is interested. 347 */ 348 struct smu_table driver_table; 349 struct smu_table memory_pool; 350 struct smu_table dummy_read_1_table; 351 uint8_t thermal_controller_type; 352 353 void *overdrive_table; 354 void *boot_overdrive_table; 355 void *user_overdrive_table; 356 357 uint32_t gpu_metrics_table_size; 358 void *gpu_metrics_table; 359 }; 360 361 struct smu_dpm_context { 362 uint32_t dpm_context_size; 363 void *dpm_context; 364 void *golden_dpm_context; 365 enum amd_dpm_forced_level dpm_level; 366 enum amd_dpm_forced_level saved_dpm_level; 367 enum amd_dpm_forced_level requested_dpm_level; 368 struct smu_power_state *dpm_request_power_state; 369 struct smu_power_state *dpm_current_power_state; 370 struct mclock_latency_table *mclk_latency_table; 371 }; 372 373 struct smu_power_gate { 374 bool uvd_gated; 375 bool vce_gated; 376 atomic_t vcn_gated; 377 atomic_t jpeg_gated; 378 atomic_t vpe_gated; 379 atomic_t umsch_mm_gated; 380 }; 381 382 struct smu_power_context { 383 void *power_context; 384 uint32_t power_context_size; 385 struct smu_power_gate power_gate; 386 }; 387 388 #define SMU_FEATURE_MAX (64) 389 struct smu_feature { 390 uint32_t feature_num; 391 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 392 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 393 }; 394 395 struct smu_clocks { 396 uint32_t engine_clock; 397 uint32_t memory_clock; 398 uint32_t bus_bandwidth; 399 uint32_t engine_clock_in_sr; 400 uint32_t dcef_clock; 401 uint32_t dcef_clock_in_sr; 402 }; 403 404 #define MAX_REGULAR_DPM_NUM 16 405 struct mclk_latency_entries { 406 uint32_t frequency; 407 uint32_t latency; 408 }; 409 struct mclock_latency_table { 410 uint32_t count; 411 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 412 }; 413 414 enum smu_reset_mode { 415 SMU_RESET_MODE_0, 416 SMU_RESET_MODE_1, 417 SMU_RESET_MODE_2, 418 }; 419 420 enum smu_baco_state { 421 SMU_BACO_STATE_ENTER = 0, 422 SMU_BACO_STATE_EXIT, 423 SMU_BACO_STATE_NONE, 424 }; 425 426 struct smu_baco_context { 427 uint32_t state; 428 bool platform_support; 429 bool maco_support; 430 }; 431 432 struct smu_freq_info { 433 uint32_t min; 434 uint32_t max; 435 uint32_t freq_level; 436 }; 437 438 struct pstates_clk_freq { 439 uint32_t min; 440 uint32_t standard; 441 uint32_t peak; 442 struct smu_freq_info custom; 443 struct smu_freq_info curr; 444 }; 445 446 struct smu_umd_pstate_table { 447 struct pstates_clk_freq gfxclk_pstate; 448 struct pstates_clk_freq socclk_pstate; 449 struct pstates_clk_freq uclk_pstate; 450 struct pstates_clk_freq vclk_pstate; 451 struct pstates_clk_freq dclk_pstate; 452 struct pstates_clk_freq fclk_pstate; 453 }; 454 455 struct cmn2asic_msg_mapping { 456 int valid_mapping; 457 int map_to; 458 int valid_in_vf; 459 }; 460 461 struct cmn2asic_mapping { 462 int valid_mapping; 463 int map_to; 464 }; 465 466 struct stb_context { 467 uint32_t stb_buf_size; 468 bool enabled; 469 spinlock_t lock; 470 }; 471 472 #define WORKLOAD_POLICY_MAX 7 473 474 struct smu_context { 475 struct amdgpu_device *adev; 476 struct amdgpu_irq_src irq_source; 477 478 const struct pptable_funcs *ppt_funcs; 479 const struct cmn2asic_msg_mapping *message_map; 480 const struct cmn2asic_mapping *clock_map; 481 const struct cmn2asic_mapping *feature_map; 482 const struct cmn2asic_mapping *table_map; 483 const struct cmn2asic_mapping *pwr_src_map; 484 const struct cmn2asic_mapping *workload_map; 485 struct mutex message_lock; 486 uint64_t pool_size; 487 488 struct smu_table_context smu_table; 489 struct smu_dpm_context smu_dpm; 490 struct smu_power_context smu_power; 491 struct smu_feature smu_feature; 492 struct amd_pp_display_configuration *display_config; 493 struct smu_baco_context smu_baco; 494 struct smu_temperature_range thermal_range; 495 void *od_settings; 496 497 struct smu_umd_pstate_table pstate_table; 498 uint32_t pstate_sclk; 499 uint32_t pstate_mclk; 500 501 bool od_enabled; 502 uint32_t current_power_limit; 503 uint32_t default_power_limit; 504 uint32_t max_power_limit; 505 uint32_t min_power_limit; 506 507 /* soft pptable */ 508 uint32_t ppt_offset_bytes; 509 uint32_t ppt_size_bytes; 510 uint8_t *ppt_start_addr; 511 512 bool support_power_containment; 513 bool disable_watermark; 514 515 #define WATERMARKS_EXIST (1 << 0) 516 #define WATERMARKS_LOADED (1 << 1) 517 uint32_t watermarks_bitmap; 518 uint32_t hard_min_uclk_req_from_dal; 519 bool disable_uclk_switch; 520 521 uint32_t workload_mask; 522 uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 523 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 524 uint32_t power_profile_mode; 525 uint32_t default_power_profile_mode; 526 bool pm_enabled; 527 bool is_apu; 528 529 uint32_t smc_driver_if_version; 530 uint32_t smc_fw_if_version; 531 uint32_t smc_fw_version; 532 533 bool uploading_custom_pp_table; 534 bool dc_controlled_by_gpio; 535 536 struct work_struct throttling_logging_work; 537 atomic64_t throttle_int_counter; 538 struct work_struct interrupt_work; 539 540 unsigned fan_max_rpm; 541 unsigned manual_fan_speed_pwm; 542 543 uint32_t gfx_default_hard_min_freq; 544 uint32_t gfx_default_soft_max_freq; 545 uint32_t gfx_actual_hard_min_freq; 546 uint32_t gfx_actual_soft_max_freq; 547 548 /* APU only */ 549 uint32_t cpu_default_soft_min_freq; 550 uint32_t cpu_default_soft_max_freq; 551 uint32_t cpu_actual_soft_min_freq; 552 uint32_t cpu_actual_soft_max_freq; 553 uint32_t cpu_core_id_select; 554 uint16_t cpu_core_num; 555 556 struct smu_user_dpm_profile user_dpm_profile; 557 558 struct stb_context stb_context; 559 560 struct firmware pptable_firmware; 561 562 u32 param_reg; 563 u32 msg_reg; 564 u32 resp_reg; 565 566 u32 debug_param_reg; 567 u32 debug_msg_reg; 568 u32 debug_resp_reg; 569 570 struct delayed_work swctf_delayed_work; 571 572 enum pp_xgmi_plpd_mode plpd_mode; 573 }; 574 575 struct i2c_adapter; 576 577 /** 578 * struct pptable_funcs - Callbacks used to interact with the SMU. 579 */ 580 struct pptable_funcs { 581 /** 582 * @run_btc: Calibrate voltage/frequency curve to fit the system's 583 * power delivery and voltage margins. Required for adaptive 584 * voltage frequency scaling (AVFS). 585 */ 586 int (*run_btc)(struct smu_context *smu); 587 588 /** 589 * @get_allowed_feature_mask: Get allowed feature mask. 590 * &feature_mask: Array to store feature mask. 591 * &num: Elements in &feature_mask. 592 */ 593 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 594 595 /** 596 * @get_current_power_state: Get the current power state. 597 * 598 * Return: Current power state on success, negative errno on failure. 599 */ 600 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 601 602 /** 603 * @set_default_dpm_table: Retrieve the default overdrive settings from 604 * the SMU. 605 */ 606 int (*set_default_dpm_table)(struct smu_context *smu); 607 608 int (*set_power_state)(struct smu_context *smu); 609 610 /** 611 * @populate_umd_state_clk: Populate the UMD power state table with 612 * defaults. 613 */ 614 int (*populate_umd_state_clk)(struct smu_context *smu); 615 616 /** 617 * @print_clk_levels: Print DPM clock levels for a clock domain 618 * to buffer. Star current level. 619 * 620 * Used for sysfs interfaces. 621 * Return: Number of characters written to the buffer 622 */ 623 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 624 625 /** 626 * @emit_clk_levels: Print DPM clock levels for a clock domain 627 * to buffer using sysfs_emit_at. Star current level. 628 * 629 * Used for sysfs interfaces. 630 * &buf: sysfs buffer 631 * &offset: offset within buffer to start printing, which is updated by the 632 * function. 633 * 634 * Return: 0 on Success or Negative to indicate an error occurred. 635 */ 636 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 637 638 /** 639 * @force_clk_levels: Set a range of allowed DPM levels for a clock 640 * domain. 641 * &clk_type: Clock domain. 642 * &mask: Range of allowed DPM levels. 643 */ 644 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 645 646 /** 647 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 648 * &type: Type of edit. 649 * &input: Edit parameters. 650 * &size: Size of &input. 651 */ 652 int (*od_edit_dpm_table)(struct smu_context *smu, 653 enum PP_OD_DPM_TABLE_COMMAND type, 654 long *input, uint32_t size); 655 656 /** 657 * @restore_user_od_settings: Restore the user customized 658 * OD settings on S3/S4/Runpm resume. 659 */ 660 int (*restore_user_od_settings)(struct smu_context *smu); 661 662 /** 663 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 664 * domain. 665 */ 666 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 667 enum smu_clk_type clk_type, 668 struct 669 pp_clock_levels_with_latency 670 *clocks); 671 /** 672 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 673 * domain. 674 */ 675 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 676 enum amd_pp_clock_type type, 677 struct 678 pp_clock_levels_with_voltage 679 *clocks); 680 681 /** 682 * @get_power_profile_mode: Print all power profile modes to 683 * buffer. Star current mode. 684 */ 685 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 686 687 /** 688 * @set_power_profile_mode: Set a power profile mode. Also used to 689 * create/set custom power profile modes. 690 * &input: Power profile mode parameters. 691 * &size: Size of &input. 692 */ 693 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 694 695 /** 696 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 697 * management. 698 */ 699 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 700 701 /** 702 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 703 * management. 704 */ 705 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 706 707 /** 708 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU 709 */ 710 int (*set_gfx_power_up_by_imu)(struct smu_context *smu); 711 712 /** 713 * @read_sensor: Read data from a sensor. 714 * &sensor: Sensor to read data from. 715 * &data: Sensor reading. 716 * &size: Size of &data. 717 */ 718 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 719 void *data, uint32_t *size); 720 721 /** 722 * @get_apu_thermal_limit: get apu core limit from smu 723 * &limit: current limit temperature in millidegrees Celsius 724 */ 725 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit); 726 727 /** 728 * @set_apu_thermal_limit: update all controllers with new limit 729 * &limit: limit temperature to be setted, in millidegrees Celsius 730 */ 731 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit); 732 733 /** 734 * @pre_display_config_changed: Prepare GPU for a display configuration 735 * change. 736 * 737 * Disable display tracking and pin memory clock speed to maximum. Used 738 * in display component synchronization. 739 */ 740 int (*pre_display_config_changed)(struct smu_context *smu); 741 742 /** 743 * @display_config_changed: Notify the SMU of the current display 744 * configuration. 745 * 746 * Allows SMU to properly track blanking periods for memory clock 747 * adjustment. Used in display component synchronization. 748 */ 749 int (*display_config_changed)(struct smu_context *smu); 750 751 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 752 753 /** 754 * @notify_smc_display_config: Applies display requirements to the 755 * current power state. 756 * 757 * Optimize deep sleep DCEFclk and mclk for the current display 758 * configuration. Used in display component synchronization. 759 */ 760 int (*notify_smc_display_config)(struct smu_context *smu); 761 762 /** 763 * @is_dpm_running: Check if DPM is running. 764 * 765 * Return: True if DPM is running, false otherwise. 766 */ 767 bool (*is_dpm_running)(struct smu_context *smu); 768 769 /** 770 * @get_fan_speed_pwm: Get the current fan speed in PWM. 771 */ 772 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 773 774 /** 775 * @get_fan_speed_rpm: Get the current fan speed in rpm. 776 */ 777 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 778 779 /** 780 * @set_watermarks_table: Configure and upload the watermarks tables to 781 * the SMU. 782 */ 783 int (*set_watermarks_table)(struct smu_context *smu, 784 struct pp_smu_wm_range_sets *clock_ranges); 785 786 /** 787 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 788 */ 789 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 790 791 /** 792 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 793 * &clocks_in_khz: Array of DPM levels. 794 * &num_states: Elements in &clocks_in_khz. 795 */ 796 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 797 798 /** 799 * @set_default_od_settings: Set the overdrive tables to defaults. 800 */ 801 int (*set_default_od_settings)(struct smu_context *smu); 802 803 /** 804 * @set_performance_level: Set a performance level. 805 */ 806 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 807 808 /** 809 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 810 * clock switching. 811 * 812 * Disabling this feature forces memory clock speed to maximum. 813 * Enabling sets the minimum memory clock capable of driving the 814 * current display configuration. 815 */ 816 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 817 818 /** 819 * @dump_pptable: Print the power play table to the system log. 820 */ 821 void (*dump_pptable)(struct smu_context *smu); 822 823 /** 824 * @get_power_limit: Get the device's power limits. 825 */ 826 int (*get_power_limit)(struct smu_context *smu, 827 uint32_t *current_power_limit, 828 uint32_t *default_power_limit, 829 uint32_t *max_power_limit, 830 uint32_t *min_power_limit); 831 832 /** 833 * @get_ppt_limit: Get the device's ppt limits. 834 */ 835 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 836 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 837 838 /** 839 * @set_df_cstate: Set data fabric cstate. 840 */ 841 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 842 843 /** 844 * @select_xgmi_plpd_policy: Select xgmi per-link power down policy. 845 */ 846 int (*select_xgmi_plpd_policy)(struct smu_context *smu, 847 enum pp_xgmi_plpd_mode mode); 848 849 /** 850 * @update_pcie_parameters: Update and upload the system's PCIe 851 * capabilites to the SMU. 852 * &pcie_gen_cap: Maximum allowed PCIe generation. 853 * &pcie_width_cap: Maximum allowed PCIe width. 854 */ 855 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap); 856 857 /** 858 * @i2c_init: Initialize i2c. 859 * 860 * The i2c bus is used internally by the SMU voltage regulators and 861 * other devices. The i2c's EEPROM also stores bad page tables on boards 862 * with ECC. 863 */ 864 int (*i2c_init)(struct smu_context *smu); 865 866 /** 867 * @i2c_fini: Tear down i2c. 868 */ 869 void (*i2c_fini)(struct smu_context *smu); 870 871 /** 872 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 873 */ 874 void (*get_unique_id)(struct smu_context *smu); 875 876 /** 877 * @get_dpm_clock_table: Get a copy of the DPM clock table. 878 * 879 * Used by display component in bandwidth and watermark calculations. 880 */ 881 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 882 883 /** 884 * @init_microcode: Request the SMU's firmware from the kernel. 885 */ 886 int (*init_microcode)(struct smu_context *smu); 887 888 /** 889 * @load_microcode: Load firmware onto the SMU. 890 */ 891 int (*load_microcode)(struct smu_context *smu); 892 893 /** 894 * @fini_microcode: Release the SMU's firmware. 895 */ 896 void (*fini_microcode)(struct smu_context *smu); 897 898 /** 899 * @init_smc_tables: Initialize the SMU tables. 900 */ 901 int (*init_smc_tables)(struct smu_context *smu); 902 903 /** 904 * @fini_smc_tables: Release the SMU tables. 905 */ 906 int (*fini_smc_tables)(struct smu_context *smu); 907 908 /** 909 * @init_power: Initialize the power gate table context. 910 */ 911 int (*init_power)(struct smu_context *smu); 912 913 /** 914 * @fini_power: Release the power gate table context. 915 */ 916 int (*fini_power)(struct smu_context *smu); 917 918 /** 919 * @check_fw_status: Check the SMU's firmware status. 920 * 921 * Return: Zero if check passes, negative errno on failure. 922 */ 923 int (*check_fw_status)(struct smu_context *smu); 924 925 /** 926 * @set_mp1_state: put SMU into a correct state for comming 927 * resume from runpm or gpu reset. 928 */ 929 int (*set_mp1_state)(struct smu_context *smu, 930 enum pp_mp1_state mp1_state); 931 932 /** 933 * @setup_pptable: Initialize the power play table and populate it with 934 * default values. 935 */ 936 int (*setup_pptable)(struct smu_context *smu); 937 938 /** 939 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 940 */ 941 int (*get_vbios_bootup_values)(struct smu_context *smu); 942 943 /** 944 * @check_fw_version: Print driver and SMU interface versions to the 945 * system log. 946 * 947 * Interface mismatch is not a critical failure. 948 */ 949 int (*check_fw_version)(struct smu_context *smu); 950 951 /** 952 * @powergate_sdma: Power up/down system direct memory access. 953 */ 954 int (*powergate_sdma)(struct smu_context *smu, bool gate); 955 956 /** 957 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 958 * gating. 959 */ 960 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 961 962 /** 963 * @write_pptable: Write the power play table to the SMU. 964 */ 965 int (*write_pptable)(struct smu_context *smu); 966 967 /** 968 * @set_driver_table_location: Send the location of the driver table to 969 * the SMU. 970 */ 971 int (*set_driver_table_location)(struct smu_context *smu); 972 973 /** 974 * @set_tool_table_location: Send the location of the tool table to the 975 * SMU. 976 */ 977 int (*set_tool_table_location)(struct smu_context *smu); 978 979 /** 980 * @notify_memory_pool_location: Send the location of the memory pool to 981 * the SMU. 982 */ 983 int (*notify_memory_pool_location)(struct smu_context *smu); 984 985 /** 986 * @system_features_control: Enable/disable all SMU features. 987 */ 988 int (*system_features_control)(struct smu_context *smu, bool en); 989 990 /** 991 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 992 * &msg: Type of message. 993 * ¶m: Message parameter. 994 * &read_arg: SMU response (optional). 995 */ 996 int (*send_smc_msg_with_param)(struct smu_context *smu, 997 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 998 999 /** 1000 * @send_smc_msg: Send a message to the SMU. 1001 * &msg: Type of message. 1002 * &read_arg: SMU response (optional). 1003 */ 1004 int (*send_smc_msg)(struct smu_context *smu, 1005 enum smu_message_type msg, 1006 uint32_t *read_arg); 1007 1008 /** 1009 * @init_display_count: Notify the SMU of the number of display 1010 * components in current display configuration. 1011 */ 1012 int (*init_display_count)(struct smu_context *smu, uint32_t count); 1013 1014 /** 1015 * @set_allowed_mask: Notify the SMU of the features currently allowed 1016 * by the driver. 1017 */ 1018 int (*set_allowed_mask)(struct smu_context *smu); 1019 1020 /** 1021 * @get_enabled_mask: Get a mask of features that are currently enabled 1022 * on the SMU. 1023 * &feature_mask: Enabled feature mask. 1024 */ 1025 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1026 1027 /** 1028 * @feature_is_enabled: Test if a feature is enabled. 1029 * 1030 * Return: One if enabled, zero if disabled. 1031 */ 1032 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1033 1034 /** 1035 * @disable_all_features_with_exception: Disable all features with 1036 * exception to those in &mask. 1037 */ 1038 int (*disable_all_features_with_exception)(struct smu_context *smu, 1039 enum smu_feature_mask mask); 1040 1041 /** 1042 * @notify_display_change: General interface call to let SMU know about DC change 1043 */ 1044 int (*notify_display_change)(struct smu_context *smu); 1045 1046 /** 1047 * @set_power_limit: Set power limit in watts. 1048 */ 1049 int (*set_power_limit)(struct smu_context *smu, 1050 enum smu_ppt_limit_type limit_type, 1051 uint32_t limit); 1052 1053 /** 1054 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1055 * table with values from the SMU. 1056 */ 1057 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1058 1059 /** 1060 * @enable_thermal_alert: Enable thermal alert interrupts. 1061 */ 1062 int (*enable_thermal_alert)(struct smu_context *smu); 1063 1064 /** 1065 * @disable_thermal_alert: Disable thermal alert interrupts. 1066 */ 1067 int (*disable_thermal_alert)(struct smu_context *smu); 1068 1069 /** 1070 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1071 * clock speed in MHz. 1072 */ 1073 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1074 1075 /** 1076 * @display_clock_voltage_request: Set a hard minimum frequency 1077 * for a clock domain. 1078 */ 1079 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1080 pp_display_clock_request 1081 *clock_req); 1082 1083 /** 1084 * @get_fan_control_mode: Get the current fan control mode. 1085 */ 1086 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1087 1088 /** 1089 * @set_fan_control_mode: Set the fan control mode. 1090 */ 1091 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1092 1093 /** 1094 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1095 */ 1096 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1097 1098 /** 1099 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1100 */ 1101 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1102 1103 /** 1104 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1105 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1106 */ 1107 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1108 1109 /** 1110 * @gfx_off_control: Enable/disable graphics engine poweroff. 1111 */ 1112 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1113 1114 1115 /** 1116 * @get_gfx_off_status: Get graphics engine poweroff status. 1117 * 1118 * Return: 1119 * 0 - GFXOFF(default). 1120 * 1 - Transition out of GFX State. 1121 * 2 - Not in GFXOFF. 1122 * 3 - Transition into GFXOFF. 1123 */ 1124 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1125 1126 /** 1127 * @gfx_off_entrycount: total GFXOFF entry count at the time of 1128 * query since system power-up 1129 */ 1130 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount); 1131 1132 /** 1133 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging 1134 */ 1135 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); 1136 1137 /** 1138 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval 1139 */ 1140 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency); 1141 1142 /** 1143 * @register_irq_handler: Register interupt request handlers. 1144 */ 1145 int (*register_irq_handler)(struct smu_context *smu); 1146 1147 /** 1148 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1149 */ 1150 int (*set_azalia_d3_pme)(struct smu_context *smu); 1151 1152 /** 1153 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1154 * clock speeds table. 1155 * 1156 * Provides a way for the display component (DC) to get the max 1157 * sustainable clocks from the SMU. 1158 */ 1159 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1160 1161 /** 1162 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off). 1163 */ 1164 bool (*baco_is_support)(struct smu_context *smu); 1165 1166 /** 1167 * @baco_get_state: Get the current BACO state. 1168 * 1169 * Return: Current BACO state. 1170 */ 1171 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1172 1173 /** 1174 * @baco_set_state: Enter/exit BACO. 1175 */ 1176 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1177 1178 /** 1179 * @baco_enter: Enter BACO. 1180 */ 1181 int (*baco_enter)(struct smu_context *smu); 1182 1183 /** 1184 * @baco_exit: Exit Baco. 1185 */ 1186 int (*baco_exit)(struct smu_context *smu); 1187 1188 /** 1189 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1190 */ 1191 bool (*mode1_reset_is_support)(struct smu_context *smu); 1192 /** 1193 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1194 */ 1195 bool (*mode2_reset_is_support)(struct smu_context *smu); 1196 1197 /** 1198 * @mode1_reset: Perform mode1 reset. 1199 * 1200 * Complete GPU reset. 1201 */ 1202 int (*mode1_reset)(struct smu_context *smu); 1203 1204 /** 1205 * @mode2_reset: Perform mode2 reset. 1206 * 1207 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1208 * IPs reset varies by asic. 1209 */ 1210 int (*mode2_reset)(struct smu_context *smu); 1211 /* for gfx feature enablement after mode2 reset */ 1212 int (*enable_gfx_features)(struct smu_context *smu); 1213 1214 /** 1215 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1216 * domain in MHz. 1217 */ 1218 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1219 1220 /** 1221 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1222 * domain in MHz. 1223 */ 1224 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 1225 1226 /** 1227 * @set_power_source: Notify the SMU of the current power source. 1228 */ 1229 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1230 1231 /** 1232 * @log_thermal_throttling_event: Print a thermal throttling warning to 1233 * the system's log. 1234 */ 1235 void (*log_thermal_throttling_event)(struct smu_context *smu); 1236 1237 /** 1238 * @get_pp_feature_mask: Print a human readable table of enabled 1239 * features to buffer. 1240 */ 1241 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1242 1243 /** 1244 * @set_pp_feature_mask: Request the SMU enable/disable features to 1245 * match those enabled in &new_mask. 1246 */ 1247 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1248 1249 /** 1250 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1251 * 1252 * Return: Size of &table 1253 */ 1254 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1255 1256 /** 1257 * @get_pm_metrics: Get one snapshot of power management metrics from 1258 * PMFW. 1259 * 1260 * Return: Size of the metrics sample 1261 */ 1262 ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics, 1263 size_t size); 1264 1265 /** 1266 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1267 */ 1268 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1269 1270 /** 1271 * @gfx_ulv_control: Enable/disable ultra low voltage. 1272 */ 1273 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1274 1275 /** 1276 * @deep_sleep_control: Enable/disable deep sleep. 1277 */ 1278 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1279 1280 /** 1281 * @get_fan_parameters: Get fan parameters. 1282 * 1283 * Get maximum fan speed from the power play table. 1284 */ 1285 int (*get_fan_parameters)(struct smu_context *smu); 1286 1287 /** 1288 * @post_init: Helper function for asic specific workarounds. 1289 */ 1290 int (*post_init)(struct smu_context *smu); 1291 1292 /** 1293 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1294 */ 1295 void (*interrupt_work)(struct smu_context *smu); 1296 1297 /** 1298 * @gpo_control: Enable/disable graphics power optimization if supported. 1299 */ 1300 int (*gpo_control)(struct smu_context *smu, bool enablement); 1301 1302 /** 1303 * @gfx_state_change_set: Send the current graphics state to the SMU. 1304 */ 1305 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1306 1307 /** 1308 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1309 * parameters to defaults. 1310 */ 1311 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1312 1313 /** 1314 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1315 */ 1316 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1317 1318 /** 1319 * @wait_for_event: Wait for events from SMU. 1320 */ 1321 int (*wait_for_event)(struct smu_context *smu, 1322 enum smu_event_type event, uint64_t event_arg); 1323 1324 /** 1325 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1326 * of SMUBUS table. 1327 */ 1328 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1329 1330 /** 1331 * @get_ecc_table: message SMU to get ECC INFO table. 1332 */ 1333 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1334 1335 1336 /** 1337 * @stb_collect_info: Collects Smart Trace Buffers data. 1338 */ 1339 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1340 1341 /** 1342 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1343 */ 1344 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1345 1346 /** 1347 * @set_config_table: Apply the input DriverSmuConfig table settings. 1348 */ 1349 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1350 1351 /** 1352 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1353 * of SMUBUS table. 1354 */ 1355 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1356 1357 /** 1358 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP 1359 */ 1360 int (*init_pptable_microcode)(struct smu_context *smu); 1361 1362 /** 1363 * @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power 1364 * management. 1365 */ 1366 int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable); 1367 1368 /** 1369 * @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power 1370 * management. 1371 */ 1372 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable); 1373 1374 /** 1375 * @notify_rlc_state: Notify RLC power state to SMU. 1376 */ 1377 int (*notify_rlc_state)(struct smu_context *smu, bool en); 1378 }; 1379 1380 typedef enum { 1381 METRICS_CURR_GFXCLK, 1382 METRICS_CURR_SOCCLK, 1383 METRICS_CURR_UCLK, 1384 METRICS_CURR_VCLK, 1385 METRICS_CURR_VCLK1, 1386 METRICS_CURR_DCLK, 1387 METRICS_CURR_DCLK1, 1388 METRICS_CURR_FCLK, 1389 METRICS_CURR_DCEFCLK, 1390 METRICS_AVERAGE_CPUCLK, 1391 METRICS_AVERAGE_GFXCLK, 1392 METRICS_AVERAGE_SOCCLK, 1393 METRICS_AVERAGE_FCLK, 1394 METRICS_AVERAGE_UCLK, 1395 METRICS_AVERAGE_VCLK, 1396 METRICS_AVERAGE_DCLK, 1397 METRICS_AVERAGE_VCLK1, 1398 METRICS_AVERAGE_DCLK1, 1399 METRICS_AVERAGE_GFXACTIVITY, 1400 METRICS_AVERAGE_MEMACTIVITY, 1401 METRICS_AVERAGE_VCNACTIVITY, 1402 METRICS_AVERAGE_SOCKETPOWER, 1403 METRICS_TEMPERATURE_EDGE, 1404 METRICS_TEMPERATURE_HOTSPOT, 1405 METRICS_TEMPERATURE_MEM, 1406 METRICS_TEMPERATURE_VRGFX, 1407 METRICS_TEMPERATURE_VRSOC, 1408 METRICS_TEMPERATURE_VRMEM, 1409 METRICS_THROTTLER_STATUS, 1410 METRICS_CURR_FANSPEED, 1411 METRICS_VOLTAGE_VDDSOC, 1412 METRICS_VOLTAGE_VDDGFX, 1413 METRICS_SS_APU_SHARE, 1414 METRICS_SS_DGPU_SHARE, 1415 METRICS_UNIQUE_ID_UPPER32, 1416 METRICS_UNIQUE_ID_LOWER32, 1417 METRICS_PCIE_RATE, 1418 METRICS_PCIE_WIDTH, 1419 METRICS_CURR_FANPWM, 1420 METRICS_CURR_SOCKETPOWER, 1421 } MetricsMember_t; 1422 1423 enum smu_cmn2asic_mapping_type { 1424 CMN2ASIC_MAPPING_MSG, 1425 CMN2ASIC_MAPPING_CLK, 1426 CMN2ASIC_MAPPING_FEATURE, 1427 CMN2ASIC_MAPPING_TABLE, 1428 CMN2ASIC_MAPPING_PWR, 1429 CMN2ASIC_MAPPING_WORKLOAD, 1430 }; 1431 1432 enum smu_baco_seq { 1433 BACO_SEQ_BACO = 0, 1434 BACO_SEQ_MSR, 1435 BACO_SEQ_BAMACO, 1436 BACO_SEQ_ULPS, 1437 BACO_SEQ_COUNT, 1438 }; 1439 1440 #define MSG_MAP(msg, index, valid_in_vf) \ 1441 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)} 1442 1443 #define CLK_MAP(clk, index) \ 1444 [SMU_##clk] = {1, (index)} 1445 1446 #define FEA_MAP(fea) \ 1447 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1448 1449 #define FEA_MAP_REVERSE(fea) \ 1450 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1451 1452 #define FEA_MAP_HALF_REVERSE(fea) \ 1453 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1454 1455 #define TAB_MAP(tab) \ 1456 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1457 1458 #define TAB_MAP_VALID(tab) \ 1459 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1460 1461 #define TAB_MAP_INVALID(tab) \ 1462 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1463 1464 #define PWR_MAP(tab) \ 1465 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1466 1467 #define WORKLOAD_MAP(profile, workload) \ 1468 [profile] = {1, (workload)} 1469 1470 /** 1471 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1472 * 1473 * @dst: Pointer to destination struct 1474 * @first_dst_member: The member name in @dst where the overwrite begins 1475 * @last_dst_member: The member name in @dst where the overwrite ends after 1476 * @src: Pointer to the source struct 1477 * @first_src_member: The member name in @src where the copy begins 1478 * 1479 */ 1480 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1481 src, first_src_member) \ 1482 ({ \ 1483 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1484 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1485 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1486 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1487 __dst_offset; \ 1488 BUILD_BUG_ON(__src_size != __dst_size); \ 1489 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1490 (u8 *)(src) + __src_offset, \ 1491 __dst_size); \ 1492 }) 1493 1494 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1495 int smu_get_power_limit(void *handle, 1496 uint32_t *limit, 1497 enum pp_power_limit_level pp_limit_level, 1498 enum pp_power_type pp_power_type); 1499 1500 bool smu_mode1_reset_is_support(struct smu_context *smu); 1501 bool smu_mode2_reset_is_support(struct smu_context *smu); 1502 int smu_mode1_reset(struct smu_context *smu); 1503 1504 extern const struct amd_ip_funcs smu_ip_funcs; 1505 1506 bool is_support_sw_smu(struct amdgpu_device *adev); 1507 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1508 int smu_write_watermarks_table(struct smu_context *smu); 1509 1510 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1511 uint32_t *min, uint32_t *max); 1512 1513 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1514 uint32_t min, uint32_t max); 1515 1516 int smu_set_gfx_power_up_by_imu(struct smu_context *smu); 1517 1518 int smu_set_ac_dc(struct smu_context *smu); 1519 1520 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 1521 enum pp_xgmi_plpd_mode mode); 1522 1523 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); 1524 1525 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); 1526 1527 int smu_set_residency_gfxoff(struct smu_context *smu, bool value); 1528 1529 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1530 1531 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1532 1533 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1534 uint64_t event_arg); 1535 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1536 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1537 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1538 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1539 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1540 #endif 1541 #endif 1542