1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include <linux/acpi_amd_wbrf.h> 26 #include <linux/units.h> 27 28 #include "amdgpu.h" 29 #include "kgd_pp_interface.h" 30 #include "dm_pp_interface.h" 31 #include "dm_pp_smu.h" 32 #include "smu_types.h" 33 #include "linux/firmware.h" 34 35 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 36 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 37 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 38 #define SMU_FW_NAME_LEN 0x24 39 40 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 41 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 42 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 43 44 // Power Throttlers 45 #define SMU_THROTTLER_PPT0_BIT 0 46 #define SMU_THROTTLER_PPT1_BIT 1 47 #define SMU_THROTTLER_PPT2_BIT 2 48 #define SMU_THROTTLER_PPT3_BIT 3 49 #define SMU_THROTTLER_SPL_BIT 4 50 #define SMU_THROTTLER_FPPT_BIT 5 51 #define SMU_THROTTLER_SPPT_BIT 6 52 #define SMU_THROTTLER_SPPT_APU_BIT 7 53 54 // Current Throttlers 55 #define SMU_THROTTLER_TDC_GFX_BIT 16 56 #define SMU_THROTTLER_TDC_SOC_BIT 17 57 #define SMU_THROTTLER_TDC_MEM_BIT 18 58 #define SMU_THROTTLER_TDC_VDD_BIT 19 59 #define SMU_THROTTLER_TDC_CVIP_BIT 20 60 #define SMU_THROTTLER_EDC_CPU_BIT 21 61 #define SMU_THROTTLER_EDC_GFX_BIT 22 62 #define SMU_THROTTLER_APCC_BIT 23 63 64 // Temperature 65 #define SMU_THROTTLER_TEMP_GPU_BIT 32 66 #define SMU_THROTTLER_TEMP_CORE_BIT 33 67 #define SMU_THROTTLER_TEMP_MEM_BIT 34 68 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 69 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 70 #define SMU_THROTTLER_TEMP_SOC_BIT 37 71 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 72 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 73 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 74 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 75 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 76 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 77 #define SMU_THROTTLER_VRHOT0_BIT 44 78 #define SMU_THROTTLER_VRHOT1_BIT 45 79 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 80 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 81 82 // Other 83 #define SMU_THROTTLER_PPM_BIT 56 84 #define SMU_THROTTLER_FIT_BIT 57 85 86 struct smu_hw_power_state { 87 unsigned int magic; 88 }; 89 90 struct smu_power_state; 91 92 enum smu_state_ui_label { 93 SMU_STATE_UI_LABEL_NONE, 94 SMU_STATE_UI_LABEL_BATTERY, 95 SMU_STATE_UI_TABEL_MIDDLE_LOW, 96 SMU_STATE_UI_LABEL_BALLANCED, 97 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 98 SMU_STATE_UI_LABEL_PERFORMANCE, 99 SMU_STATE_UI_LABEL_BACO, 100 }; 101 102 enum smu_state_classification_flag { 103 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 104 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 105 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 106 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 107 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 108 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 109 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 111 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 112 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 113 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 114 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 115 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 116 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 117 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 118 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 119 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 120 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 121 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 122 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 123 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 124 }; 125 126 struct smu_state_classification_block { 127 enum smu_state_ui_label ui_label; 128 enum smu_state_classification_flag flags; 129 int bios_index; 130 bool temporary_state; 131 bool to_be_deleted; 132 }; 133 134 struct smu_state_pcie_block { 135 unsigned int lanes; 136 }; 137 138 enum smu_refreshrate_source { 139 SMU_REFRESHRATE_SOURCE_EDID, 140 SMU_REFRESHRATE_SOURCE_EXPLICIT 141 }; 142 143 struct smu_state_display_block { 144 bool disable_frame_modulation; 145 bool limit_refreshrate; 146 enum smu_refreshrate_source refreshrate_source; 147 int explicit_refreshrate; 148 int edid_refreshrate_index; 149 bool enable_vari_bright; 150 }; 151 152 struct smu_state_memory_block { 153 bool dll_off; 154 uint8_t m3arb; 155 uint8_t unused[3]; 156 }; 157 158 struct smu_state_software_algorithm_block { 159 bool disable_load_balancing; 160 bool enable_sleep_for_timestamps; 161 }; 162 163 struct smu_temperature_range { 164 int min; 165 int max; 166 int edge_emergency_max; 167 int hotspot_min; 168 int hotspot_crit_max; 169 int hotspot_emergency_max; 170 int mem_min; 171 int mem_crit_max; 172 int mem_emergency_max; 173 int software_shutdown_temp; 174 int software_shutdown_temp_offset; 175 }; 176 177 struct smu_state_validation_block { 178 bool single_display_only; 179 bool disallow_on_dc; 180 uint8_t supported_power_levels; 181 }; 182 183 struct smu_uvd_clocks { 184 uint32_t vclk; 185 uint32_t dclk; 186 }; 187 188 /** 189 * Structure to hold a SMU Power State. 190 */ 191 struct smu_power_state { 192 uint32_t id; 193 struct list_head ordered_list; 194 struct list_head all_states_list; 195 196 struct smu_state_classification_block classification; 197 struct smu_state_validation_block validation; 198 struct smu_state_pcie_block pcie; 199 struct smu_state_display_block display; 200 struct smu_state_memory_block memory; 201 struct smu_state_software_algorithm_block software; 202 struct smu_uvd_clocks uvd_clocks; 203 struct smu_hw_power_state hardware; 204 }; 205 206 enum smu_power_src_type { 207 SMU_POWER_SOURCE_AC, 208 SMU_POWER_SOURCE_DC, 209 SMU_POWER_SOURCE_COUNT, 210 }; 211 212 enum smu_ppt_limit_type { 213 SMU_DEFAULT_PPT_LIMIT = 0, 214 SMU_FAST_PPT_LIMIT, 215 }; 216 217 enum smu_ppt_limit_level { 218 SMU_PPT_LIMIT_MIN = -1, 219 SMU_PPT_LIMIT_CURRENT, 220 SMU_PPT_LIMIT_DEFAULT, 221 SMU_PPT_LIMIT_MAX, 222 }; 223 224 enum smu_memory_pool_size { 225 SMU_MEMORY_POOL_SIZE_ZERO = 0, 226 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 227 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 228 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 229 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 230 }; 231 232 struct smu_user_dpm_profile { 233 uint32_t fan_mode; 234 uint32_t power_limit; 235 uint32_t fan_speed_pwm; 236 uint32_t fan_speed_rpm; 237 uint32_t flags; 238 uint32_t user_od; 239 240 /* user clock state information */ 241 uint32_t clk_mask[SMU_CLK_COUNT]; 242 uint32_t clk_dependency; 243 }; 244 245 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 246 do { \ 247 tables[table_id].size = s; \ 248 tables[table_id].align = a; \ 249 tables[table_id].domain = d; \ 250 } while (0) 251 252 struct smu_table { 253 uint64_t size; 254 uint32_t align; 255 uint8_t domain; 256 uint64_t mc_address; 257 void *cpu_addr; 258 struct amdgpu_bo *bo; 259 uint32_t version; 260 }; 261 262 enum smu_perf_level_designation { 263 PERF_LEVEL_ACTIVITY, 264 PERF_LEVEL_POWER_CONTAINMENT, 265 }; 266 267 struct smu_performance_level { 268 uint32_t core_clock; 269 uint32_t memory_clock; 270 uint32_t vddc; 271 uint32_t vddci; 272 uint32_t non_local_mem_freq; 273 uint32_t non_local_mem_width; 274 }; 275 276 struct smu_clock_info { 277 uint32_t min_mem_clk; 278 uint32_t max_mem_clk; 279 uint32_t min_eng_clk; 280 uint32_t max_eng_clk; 281 uint32_t min_bus_bandwidth; 282 uint32_t max_bus_bandwidth; 283 }; 284 285 struct smu_bios_boot_up_values { 286 uint32_t revision; 287 uint32_t gfxclk; 288 uint32_t uclk; 289 uint32_t socclk; 290 uint32_t dcefclk; 291 uint32_t eclk; 292 uint32_t vclk; 293 uint32_t dclk; 294 uint16_t vddc; 295 uint16_t vddci; 296 uint16_t mvddc; 297 uint16_t vdd_gfx; 298 uint8_t cooling_id; 299 uint32_t pp_table_id; 300 uint32_t format_revision; 301 uint32_t content_revision; 302 uint32_t fclk; 303 uint32_t lclk; 304 uint32_t firmware_caps; 305 }; 306 307 enum smu_table_id { 308 SMU_TABLE_PPTABLE = 0, 309 SMU_TABLE_WATERMARKS, 310 SMU_TABLE_CUSTOM_DPM, 311 SMU_TABLE_DPMCLOCKS, 312 SMU_TABLE_AVFS, 313 SMU_TABLE_AVFS_PSM_DEBUG, 314 SMU_TABLE_AVFS_FUSE_OVERRIDE, 315 SMU_TABLE_PMSTATUSLOG, 316 SMU_TABLE_SMU_METRICS, 317 SMU_TABLE_DRIVER_SMU_CONFIG, 318 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 319 SMU_TABLE_OVERDRIVE, 320 SMU_TABLE_I2C_COMMANDS, 321 SMU_TABLE_PACE, 322 SMU_TABLE_ECCINFO, 323 SMU_TABLE_COMBO_PPTABLE, 324 SMU_TABLE_WIFIBAND, 325 SMU_TABLE_COUNT, 326 }; 327 328 struct smu_table_context { 329 void *power_play_table; 330 uint32_t power_play_table_size; 331 void *hardcode_pptable; 332 unsigned long metrics_time; 333 void *metrics_table; 334 void *clocks_table; 335 void *watermarks_table; 336 337 void *max_sustainable_clocks; 338 struct smu_bios_boot_up_values boot_values; 339 void *driver_pptable; 340 void *combo_pptable; 341 void *ecc_table; 342 void *driver_smu_config_table; 343 struct smu_table tables[SMU_TABLE_COUNT]; 344 /* 345 * The driver table is just a staging buffer for 346 * uploading/downloading content from the SMU. 347 * 348 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 349 * SMU_MSG_TransferTableDram2Smu instructs SMU 350 * which content driver is interested. 351 */ 352 struct smu_table driver_table; 353 struct smu_table memory_pool; 354 struct smu_table dummy_read_1_table; 355 uint8_t thermal_controller_type; 356 357 void *overdrive_table; 358 void *boot_overdrive_table; 359 void *user_overdrive_table; 360 361 uint32_t gpu_metrics_table_size; 362 void *gpu_metrics_table; 363 }; 364 365 struct smu_context; 366 struct smu_dpm_policy; 367 368 struct smu_dpm_policy_desc { 369 const char *name; 370 char *(*get_desc)(struct smu_dpm_policy *dpm_policy, int level); 371 }; 372 373 struct smu_dpm_policy { 374 struct smu_dpm_policy_desc *desc; 375 enum pp_pm_policy policy_type; 376 unsigned long level_mask; 377 int current_level; 378 int (*set_policy)(struct smu_context *ctxt, int level); 379 }; 380 381 struct smu_dpm_policy_ctxt { 382 struct smu_dpm_policy policies[PP_PM_POLICY_NUM]; 383 unsigned long policy_mask; 384 }; 385 386 struct smu_dpm_context { 387 uint32_t dpm_context_size; 388 void *dpm_context; 389 void *golden_dpm_context; 390 enum amd_dpm_forced_level dpm_level; 391 enum amd_dpm_forced_level saved_dpm_level; 392 enum amd_dpm_forced_level requested_dpm_level; 393 struct smu_power_state *dpm_request_power_state; 394 struct smu_power_state *dpm_current_power_state; 395 struct mclock_latency_table *mclk_latency_table; 396 struct smu_dpm_policy_ctxt *dpm_policies; 397 }; 398 399 struct smu_power_gate { 400 bool uvd_gated; 401 bool vce_gated; 402 atomic_t vcn_gated; 403 atomic_t jpeg_gated; 404 atomic_t vpe_gated; 405 atomic_t umsch_mm_gated; 406 }; 407 408 struct smu_power_context { 409 void *power_context; 410 uint32_t power_context_size; 411 struct smu_power_gate power_gate; 412 }; 413 414 #define SMU_FEATURE_MAX (64) 415 struct smu_feature { 416 uint32_t feature_num; 417 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 418 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 419 }; 420 421 struct smu_clocks { 422 uint32_t engine_clock; 423 uint32_t memory_clock; 424 uint32_t bus_bandwidth; 425 uint32_t engine_clock_in_sr; 426 uint32_t dcef_clock; 427 uint32_t dcef_clock_in_sr; 428 }; 429 430 #define MAX_REGULAR_DPM_NUM 16 431 struct mclk_latency_entries { 432 uint32_t frequency; 433 uint32_t latency; 434 }; 435 struct mclock_latency_table { 436 uint32_t count; 437 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 438 }; 439 440 enum smu_reset_mode { 441 SMU_RESET_MODE_0, 442 SMU_RESET_MODE_1, 443 SMU_RESET_MODE_2, 444 }; 445 446 enum smu_baco_state { 447 SMU_BACO_STATE_ENTER = 0, 448 SMU_BACO_STATE_EXIT, 449 SMU_BACO_STATE_NONE, 450 }; 451 452 struct smu_baco_context { 453 uint32_t state; 454 bool platform_support; 455 bool maco_support; 456 }; 457 458 struct smu_freq_info { 459 uint32_t min; 460 uint32_t max; 461 uint32_t freq_level; 462 }; 463 464 struct pstates_clk_freq { 465 uint32_t min; 466 uint32_t standard; 467 uint32_t peak; 468 struct smu_freq_info custom; 469 struct smu_freq_info curr; 470 }; 471 472 struct smu_umd_pstate_table { 473 struct pstates_clk_freq gfxclk_pstate; 474 struct pstates_clk_freq socclk_pstate; 475 struct pstates_clk_freq uclk_pstate; 476 struct pstates_clk_freq vclk_pstate; 477 struct pstates_clk_freq dclk_pstate; 478 struct pstates_clk_freq fclk_pstate; 479 }; 480 481 struct cmn2asic_msg_mapping { 482 int valid_mapping; 483 int map_to; 484 uint32_t flags; 485 }; 486 487 struct cmn2asic_mapping { 488 int valid_mapping; 489 int map_to; 490 }; 491 492 struct stb_context { 493 uint32_t stb_buf_size; 494 bool enabled; 495 spinlock_t lock; 496 }; 497 498 enum smu_fw_status { 499 SMU_FW_INIT = 0, 500 SMU_FW_RUNTIME, 501 SMU_FW_HANG, 502 }; 503 504 #define WORKLOAD_POLICY_MAX 7 505 506 /* 507 * Configure wbrf event handling pace as there can be only one 508 * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms. 509 */ 510 #define SMU_WBRF_EVENT_HANDLING_PACE 10 511 512 struct smu_context { 513 struct amdgpu_device *adev; 514 struct amdgpu_irq_src irq_source; 515 516 const struct pptable_funcs *ppt_funcs; 517 const struct cmn2asic_msg_mapping *message_map; 518 const struct cmn2asic_mapping *clock_map; 519 const struct cmn2asic_mapping *feature_map; 520 const struct cmn2asic_mapping *table_map; 521 const struct cmn2asic_mapping *pwr_src_map; 522 const struct cmn2asic_mapping *workload_map; 523 struct mutex message_lock; 524 uint64_t pool_size; 525 526 struct smu_table_context smu_table; 527 struct smu_dpm_context smu_dpm; 528 struct smu_power_context smu_power; 529 struct smu_feature smu_feature; 530 struct amd_pp_display_configuration *display_config; 531 struct smu_baco_context smu_baco; 532 struct smu_temperature_range thermal_range; 533 void *od_settings; 534 535 struct smu_umd_pstate_table pstate_table; 536 uint32_t pstate_sclk; 537 uint32_t pstate_mclk; 538 539 bool od_enabled; 540 uint32_t current_power_limit; 541 uint32_t default_power_limit; 542 uint32_t max_power_limit; 543 uint32_t min_power_limit; 544 545 /* soft pptable */ 546 uint32_t ppt_offset_bytes; 547 uint32_t ppt_size_bytes; 548 uint8_t *ppt_start_addr; 549 550 bool support_power_containment; 551 bool disable_watermark; 552 553 #define WATERMARKS_EXIST (1 << 0) 554 #define WATERMARKS_LOADED (1 << 1) 555 uint32_t watermarks_bitmap; 556 uint32_t hard_min_uclk_req_from_dal; 557 bool disable_uclk_switch; 558 559 uint32_t workload_mask; 560 uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 561 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 562 uint32_t power_profile_mode; 563 uint32_t default_power_profile_mode; 564 bool pm_enabled; 565 bool is_apu; 566 567 uint32_t smc_driver_if_version; 568 uint32_t smc_fw_if_version; 569 uint32_t smc_fw_version; 570 uint32_t smc_fw_caps; 571 uint8_t smc_fw_state; 572 573 bool uploading_custom_pp_table; 574 bool dc_controlled_by_gpio; 575 576 struct work_struct throttling_logging_work; 577 atomic64_t throttle_int_counter; 578 struct work_struct interrupt_work; 579 580 unsigned fan_max_rpm; 581 unsigned manual_fan_speed_pwm; 582 583 uint32_t gfx_default_hard_min_freq; 584 uint32_t gfx_default_soft_max_freq; 585 uint32_t gfx_actual_hard_min_freq; 586 uint32_t gfx_actual_soft_max_freq; 587 588 /* APU only */ 589 uint32_t cpu_default_soft_min_freq; 590 uint32_t cpu_default_soft_max_freq; 591 uint32_t cpu_actual_soft_min_freq; 592 uint32_t cpu_actual_soft_max_freq; 593 uint32_t cpu_core_id_select; 594 uint16_t cpu_core_num; 595 596 struct smu_user_dpm_profile user_dpm_profile; 597 598 struct stb_context stb_context; 599 600 struct firmware pptable_firmware; 601 602 u32 param_reg; 603 u32 msg_reg; 604 u32 resp_reg; 605 606 u32 debug_param_reg; 607 u32 debug_msg_reg; 608 u32 debug_resp_reg; 609 610 struct delayed_work swctf_delayed_work; 611 612 /* data structures for wbrf feature support */ 613 bool wbrf_supported; 614 struct notifier_block wbrf_notifier; 615 struct delayed_work wbrf_delayed_work; 616 }; 617 618 struct i2c_adapter; 619 620 /** 621 * struct pptable_funcs - Callbacks used to interact with the SMU. 622 */ 623 struct pptable_funcs { 624 /** 625 * @run_btc: Calibrate voltage/frequency curve to fit the system's 626 * power delivery and voltage margins. Required for adaptive 627 * voltage frequency scaling (AVFS). 628 */ 629 int (*run_btc)(struct smu_context *smu); 630 631 /** 632 * @get_allowed_feature_mask: Get allowed feature mask. 633 * &feature_mask: Array to store feature mask. 634 * &num: Elements in &feature_mask. 635 */ 636 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 637 638 /** 639 * @get_current_power_state: Get the current power state. 640 * 641 * Return: Current power state on success, negative errno on failure. 642 */ 643 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 644 645 /** 646 * @set_default_dpm_table: Retrieve the default overdrive settings from 647 * the SMU. 648 */ 649 int (*set_default_dpm_table)(struct smu_context *smu); 650 651 int (*set_power_state)(struct smu_context *smu); 652 653 /** 654 * @populate_umd_state_clk: Populate the UMD power state table with 655 * defaults. 656 */ 657 int (*populate_umd_state_clk)(struct smu_context *smu); 658 659 /** 660 * @print_clk_levels: Print DPM clock levels for a clock domain 661 * to buffer. Star current level. 662 * 663 * Used for sysfs interfaces. 664 * Return: Number of characters written to the buffer 665 */ 666 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 667 668 /** 669 * @emit_clk_levels: Print DPM clock levels for a clock domain 670 * to buffer using sysfs_emit_at. Star current level. 671 * 672 * Used for sysfs interfaces. 673 * &buf: sysfs buffer 674 * &offset: offset within buffer to start printing, which is updated by the 675 * function. 676 * 677 * Return: 0 on Success or Negative to indicate an error occurred. 678 */ 679 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 680 681 /** 682 * @force_clk_levels: Set a range of allowed DPM levels for a clock 683 * domain. 684 * &clk_type: Clock domain. 685 * &mask: Range of allowed DPM levels. 686 */ 687 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 688 689 /** 690 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 691 * &type: Type of edit. 692 * &input: Edit parameters. 693 * &size: Size of &input. 694 */ 695 int (*od_edit_dpm_table)(struct smu_context *smu, 696 enum PP_OD_DPM_TABLE_COMMAND type, 697 long *input, uint32_t size); 698 699 /** 700 * @restore_user_od_settings: Restore the user customized 701 * OD settings on S3/S4/Runpm resume. 702 */ 703 int (*restore_user_od_settings)(struct smu_context *smu); 704 705 /** 706 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 707 * domain. 708 */ 709 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 710 enum smu_clk_type clk_type, 711 struct 712 pp_clock_levels_with_latency 713 *clocks); 714 /** 715 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 716 * domain. 717 */ 718 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 719 enum amd_pp_clock_type type, 720 struct 721 pp_clock_levels_with_voltage 722 *clocks); 723 724 /** 725 * @get_power_profile_mode: Print all power profile modes to 726 * buffer. Star current mode. 727 */ 728 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 729 730 /** 731 * @set_power_profile_mode: Set a power profile mode. Also used to 732 * create/set custom power profile modes. 733 * &input: Power profile mode parameters. 734 * &size: Size of &input. 735 */ 736 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 737 738 /** 739 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 740 * management. 741 */ 742 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 743 744 /** 745 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 746 * management. 747 */ 748 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 749 750 /** 751 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU 752 */ 753 int (*set_gfx_power_up_by_imu)(struct smu_context *smu); 754 755 /** 756 * @read_sensor: Read data from a sensor. 757 * &sensor: Sensor to read data from. 758 * &data: Sensor reading. 759 * &size: Size of &data. 760 */ 761 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 762 void *data, uint32_t *size); 763 764 /** 765 * @get_apu_thermal_limit: get apu core limit from smu 766 * &limit: current limit temperature in millidegrees Celsius 767 */ 768 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit); 769 770 /** 771 * @set_apu_thermal_limit: update all controllers with new limit 772 * &limit: limit temperature to be setted, in millidegrees Celsius 773 */ 774 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit); 775 776 /** 777 * @pre_display_config_changed: Prepare GPU for a display configuration 778 * change. 779 * 780 * Disable display tracking and pin memory clock speed to maximum. Used 781 * in display component synchronization. 782 */ 783 int (*pre_display_config_changed)(struct smu_context *smu); 784 785 /** 786 * @display_config_changed: Notify the SMU of the current display 787 * configuration. 788 * 789 * Allows SMU to properly track blanking periods for memory clock 790 * adjustment. Used in display component synchronization. 791 */ 792 int (*display_config_changed)(struct smu_context *smu); 793 794 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 795 796 /** 797 * @notify_smc_display_config: Applies display requirements to the 798 * current power state. 799 * 800 * Optimize deep sleep DCEFclk and mclk for the current display 801 * configuration. Used in display component synchronization. 802 */ 803 int (*notify_smc_display_config)(struct smu_context *smu); 804 805 /** 806 * @is_dpm_running: Check if DPM is running. 807 * 808 * Return: True if DPM is running, false otherwise. 809 */ 810 bool (*is_dpm_running)(struct smu_context *smu); 811 812 /** 813 * @get_fan_speed_pwm: Get the current fan speed in PWM. 814 */ 815 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 816 817 /** 818 * @get_fan_speed_rpm: Get the current fan speed in rpm. 819 */ 820 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 821 822 /** 823 * @set_watermarks_table: Configure and upload the watermarks tables to 824 * the SMU. 825 */ 826 int (*set_watermarks_table)(struct smu_context *smu, 827 struct pp_smu_wm_range_sets *clock_ranges); 828 829 /** 830 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 831 */ 832 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 833 834 /** 835 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 836 * &clocks_in_khz: Array of DPM levels. 837 * &num_states: Elements in &clocks_in_khz. 838 */ 839 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 840 841 /** 842 * @set_default_od_settings: Set the overdrive tables to defaults. 843 */ 844 int (*set_default_od_settings)(struct smu_context *smu); 845 846 /** 847 * @set_performance_level: Set a performance level. 848 */ 849 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 850 851 /** 852 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 853 * clock switching. 854 * 855 * Disabling this feature forces memory clock speed to maximum. 856 * Enabling sets the minimum memory clock capable of driving the 857 * current display configuration. 858 */ 859 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 860 861 /** 862 * @dump_pptable: Print the power play table to the system log. 863 */ 864 void (*dump_pptable)(struct smu_context *smu); 865 866 /** 867 * @get_power_limit: Get the device's power limits. 868 */ 869 int (*get_power_limit)(struct smu_context *smu, 870 uint32_t *current_power_limit, 871 uint32_t *default_power_limit, 872 uint32_t *max_power_limit, 873 uint32_t *min_power_limit); 874 875 /** 876 * @get_ppt_limit: Get the device's ppt limits. 877 */ 878 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 879 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 880 881 /** 882 * @set_df_cstate: Set data fabric cstate. 883 */ 884 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 885 886 /** 887 * @update_pcie_parameters: Update and upload the system's PCIe 888 * capabilites to the SMU. 889 * &pcie_gen_cap: Maximum allowed PCIe generation. 890 * &pcie_width_cap: Maximum allowed PCIe width. 891 */ 892 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap); 893 894 /** 895 * @i2c_init: Initialize i2c. 896 * 897 * The i2c bus is used internally by the SMU voltage regulators and 898 * other devices. The i2c's EEPROM also stores bad page tables on boards 899 * with ECC. 900 */ 901 int (*i2c_init)(struct smu_context *smu); 902 903 /** 904 * @i2c_fini: Tear down i2c. 905 */ 906 void (*i2c_fini)(struct smu_context *smu); 907 908 /** 909 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 910 */ 911 void (*get_unique_id)(struct smu_context *smu); 912 913 /** 914 * @get_dpm_clock_table: Get a copy of the DPM clock table. 915 * 916 * Used by display component in bandwidth and watermark calculations. 917 */ 918 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 919 920 /** 921 * @init_microcode: Request the SMU's firmware from the kernel. 922 */ 923 int (*init_microcode)(struct smu_context *smu); 924 925 /** 926 * @load_microcode: Load firmware onto the SMU. 927 */ 928 int (*load_microcode)(struct smu_context *smu); 929 930 /** 931 * @fini_microcode: Release the SMU's firmware. 932 */ 933 void (*fini_microcode)(struct smu_context *smu); 934 935 /** 936 * @init_smc_tables: Initialize the SMU tables. 937 */ 938 int (*init_smc_tables)(struct smu_context *smu); 939 940 /** 941 * @fini_smc_tables: Release the SMU tables. 942 */ 943 int (*fini_smc_tables)(struct smu_context *smu); 944 945 /** 946 * @init_power: Initialize the power gate table context. 947 */ 948 int (*init_power)(struct smu_context *smu); 949 950 /** 951 * @fini_power: Release the power gate table context. 952 */ 953 int (*fini_power)(struct smu_context *smu); 954 955 /** 956 * @check_fw_status: Check the SMU's firmware status. 957 * 958 * Return: Zero if check passes, negative errno on failure. 959 */ 960 int (*check_fw_status)(struct smu_context *smu); 961 962 /** 963 * @set_mp1_state: put SMU into a correct state for comming 964 * resume from runpm or gpu reset. 965 */ 966 int (*set_mp1_state)(struct smu_context *smu, 967 enum pp_mp1_state mp1_state); 968 969 /** 970 * @setup_pptable: Initialize the power play table and populate it with 971 * default values. 972 */ 973 int (*setup_pptable)(struct smu_context *smu); 974 975 /** 976 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 977 */ 978 int (*get_vbios_bootup_values)(struct smu_context *smu); 979 980 /** 981 * @check_fw_version: Print driver and SMU interface versions to the 982 * system log. 983 * 984 * Interface mismatch is not a critical failure. 985 */ 986 int (*check_fw_version)(struct smu_context *smu); 987 988 /** 989 * @powergate_sdma: Power up/down system direct memory access. 990 */ 991 int (*powergate_sdma)(struct smu_context *smu, bool gate); 992 993 /** 994 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 995 * gating. 996 */ 997 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 998 999 /** 1000 * @write_pptable: Write the power play table to the SMU. 1001 */ 1002 int (*write_pptable)(struct smu_context *smu); 1003 1004 /** 1005 * @set_driver_table_location: Send the location of the driver table to 1006 * the SMU. 1007 */ 1008 int (*set_driver_table_location)(struct smu_context *smu); 1009 1010 /** 1011 * @set_tool_table_location: Send the location of the tool table to the 1012 * SMU. 1013 */ 1014 int (*set_tool_table_location)(struct smu_context *smu); 1015 1016 /** 1017 * @notify_memory_pool_location: Send the location of the memory pool to 1018 * the SMU. 1019 */ 1020 int (*notify_memory_pool_location)(struct smu_context *smu); 1021 1022 /** 1023 * @system_features_control: Enable/disable all SMU features. 1024 */ 1025 int (*system_features_control)(struct smu_context *smu, bool en); 1026 1027 /** 1028 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 1029 * &msg: Type of message. 1030 * ¶m: Message parameter. 1031 * &read_arg: SMU response (optional). 1032 */ 1033 int (*send_smc_msg_with_param)(struct smu_context *smu, 1034 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 1035 1036 /** 1037 * @send_smc_msg: Send a message to the SMU. 1038 * &msg: Type of message. 1039 * &read_arg: SMU response (optional). 1040 */ 1041 int (*send_smc_msg)(struct smu_context *smu, 1042 enum smu_message_type msg, 1043 uint32_t *read_arg); 1044 1045 /** 1046 * @init_display_count: Notify the SMU of the number of display 1047 * components in current display configuration. 1048 */ 1049 int (*init_display_count)(struct smu_context *smu, uint32_t count); 1050 1051 /** 1052 * @set_allowed_mask: Notify the SMU of the features currently allowed 1053 * by the driver. 1054 */ 1055 int (*set_allowed_mask)(struct smu_context *smu); 1056 1057 /** 1058 * @get_enabled_mask: Get a mask of features that are currently enabled 1059 * on the SMU. 1060 * &feature_mask: Enabled feature mask. 1061 */ 1062 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1063 1064 /** 1065 * @feature_is_enabled: Test if a feature is enabled. 1066 * 1067 * Return: One if enabled, zero if disabled. 1068 */ 1069 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1070 1071 /** 1072 * @disable_all_features_with_exception: Disable all features with 1073 * exception to those in &mask. 1074 */ 1075 int (*disable_all_features_with_exception)(struct smu_context *smu, 1076 enum smu_feature_mask mask); 1077 1078 /** 1079 * @notify_display_change: General interface call to let SMU know about DC change 1080 */ 1081 int (*notify_display_change)(struct smu_context *smu); 1082 1083 /** 1084 * @set_power_limit: Set power limit in watts. 1085 */ 1086 int (*set_power_limit)(struct smu_context *smu, 1087 enum smu_ppt_limit_type limit_type, 1088 uint32_t limit); 1089 1090 /** 1091 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1092 * table with values from the SMU. 1093 */ 1094 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1095 1096 /** 1097 * @enable_thermal_alert: Enable thermal alert interrupts. 1098 */ 1099 int (*enable_thermal_alert)(struct smu_context *smu); 1100 1101 /** 1102 * @disable_thermal_alert: Disable thermal alert interrupts. 1103 */ 1104 int (*disable_thermal_alert)(struct smu_context *smu); 1105 1106 /** 1107 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1108 * clock speed in MHz. 1109 */ 1110 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1111 1112 /** 1113 * @display_clock_voltage_request: Set a hard minimum frequency 1114 * for a clock domain. 1115 */ 1116 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1117 pp_display_clock_request 1118 *clock_req); 1119 1120 /** 1121 * @get_fan_control_mode: Get the current fan control mode. 1122 */ 1123 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1124 1125 /** 1126 * @set_fan_control_mode: Set the fan control mode. 1127 */ 1128 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1129 1130 /** 1131 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1132 */ 1133 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1134 1135 /** 1136 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1137 */ 1138 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1139 1140 /** 1141 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1142 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1143 */ 1144 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1145 1146 /** 1147 * @gfx_off_control: Enable/disable graphics engine poweroff. 1148 */ 1149 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1150 1151 1152 /** 1153 * @get_gfx_off_status: Get graphics engine poweroff status. 1154 * 1155 * Return: 1156 * 0 - GFXOFF(default). 1157 * 1 - Transition out of GFX State. 1158 * 2 - Not in GFXOFF. 1159 * 3 - Transition into GFXOFF. 1160 */ 1161 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1162 1163 /** 1164 * @gfx_off_entrycount: total GFXOFF entry count at the time of 1165 * query since system power-up 1166 */ 1167 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount); 1168 1169 /** 1170 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging 1171 */ 1172 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); 1173 1174 /** 1175 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval 1176 */ 1177 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency); 1178 1179 /** 1180 * @register_irq_handler: Register interupt request handlers. 1181 */ 1182 int (*register_irq_handler)(struct smu_context *smu); 1183 1184 /** 1185 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1186 */ 1187 int (*set_azalia_d3_pme)(struct smu_context *smu); 1188 1189 /** 1190 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1191 * clock speeds table. 1192 * 1193 * Provides a way for the display component (DC) to get the max 1194 * sustainable clocks from the SMU. 1195 */ 1196 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1197 1198 /** 1199 * @get_bamaco_support: Check if GPU supports BACO/MACO 1200 * BACO: Bus Active, Chip Off 1201 * MACO: Memory Active, Chip Off 1202 */ 1203 int (*get_bamaco_support)(struct smu_context *smu); 1204 1205 /** 1206 * @baco_get_state: Get the current BACO state. 1207 * 1208 * Return: Current BACO state. 1209 */ 1210 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1211 1212 /** 1213 * @baco_set_state: Enter/exit BACO. 1214 */ 1215 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1216 1217 /** 1218 * @baco_enter: Enter BACO. 1219 */ 1220 int (*baco_enter)(struct smu_context *smu); 1221 1222 /** 1223 * @baco_exit: Exit Baco. 1224 */ 1225 int (*baco_exit)(struct smu_context *smu); 1226 1227 /** 1228 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1229 */ 1230 bool (*mode1_reset_is_support)(struct smu_context *smu); 1231 /** 1232 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1233 */ 1234 bool (*mode2_reset_is_support)(struct smu_context *smu); 1235 1236 /** 1237 * @mode1_reset: Perform mode1 reset. 1238 * 1239 * Complete GPU reset. 1240 */ 1241 int (*mode1_reset)(struct smu_context *smu); 1242 1243 /** 1244 * @mode2_reset: Perform mode2 reset. 1245 * 1246 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1247 * IPs reset varies by asic. 1248 */ 1249 int (*mode2_reset)(struct smu_context *smu); 1250 /* for gfx feature enablement after mode2 reset */ 1251 int (*enable_gfx_features)(struct smu_context *smu); 1252 1253 /** 1254 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1255 * domain in MHz. 1256 */ 1257 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1258 1259 /** 1260 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1261 * domain in MHz. 1262 */ 1263 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 1264 1265 /** 1266 * @set_power_source: Notify the SMU of the current power source. 1267 */ 1268 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1269 1270 /** 1271 * @log_thermal_throttling_event: Print a thermal throttling warning to 1272 * the system's log. 1273 */ 1274 void (*log_thermal_throttling_event)(struct smu_context *smu); 1275 1276 /** 1277 * @get_pp_feature_mask: Print a human readable table of enabled 1278 * features to buffer. 1279 */ 1280 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1281 1282 /** 1283 * @set_pp_feature_mask: Request the SMU enable/disable features to 1284 * match those enabled in &new_mask. 1285 */ 1286 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1287 1288 /** 1289 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1290 * 1291 * Return: Size of &table 1292 */ 1293 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1294 1295 /** 1296 * @get_pm_metrics: Get one snapshot of power management metrics from 1297 * PMFW. 1298 * 1299 * Return: Size of the metrics sample 1300 */ 1301 ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics, 1302 size_t size); 1303 1304 /** 1305 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1306 */ 1307 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1308 1309 /** 1310 * @gfx_ulv_control: Enable/disable ultra low voltage. 1311 */ 1312 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1313 1314 /** 1315 * @deep_sleep_control: Enable/disable deep sleep. 1316 */ 1317 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1318 1319 /** 1320 * @get_fan_parameters: Get fan parameters. 1321 * 1322 * Get maximum fan speed from the power play table. 1323 */ 1324 int (*get_fan_parameters)(struct smu_context *smu); 1325 1326 /** 1327 * @post_init: Helper function for asic specific workarounds. 1328 */ 1329 int (*post_init)(struct smu_context *smu); 1330 1331 /** 1332 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1333 */ 1334 void (*interrupt_work)(struct smu_context *smu); 1335 1336 /** 1337 * @gpo_control: Enable/disable graphics power optimization if supported. 1338 */ 1339 int (*gpo_control)(struct smu_context *smu, bool enablement); 1340 1341 /** 1342 * @gfx_state_change_set: Send the current graphics state to the SMU. 1343 */ 1344 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1345 1346 /** 1347 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1348 * parameters to defaults. 1349 */ 1350 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1351 1352 /** 1353 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1354 */ 1355 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1356 1357 /** 1358 * @wait_for_event: Wait for events from SMU. 1359 */ 1360 int (*wait_for_event)(struct smu_context *smu, 1361 enum smu_event_type event, uint64_t event_arg); 1362 1363 /** 1364 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1365 * of SMUBUS table. 1366 */ 1367 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1368 1369 /** 1370 * @send_rma_reason: message rma reason event to SMU. 1371 */ 1372 int (*send_rma_reason)(struct smu_context *smu); 1373 1374 /** 1375 * @get_ecc_table: message SMU to get ECC INFO table. 1376 */ 1377 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1378 1379 1380 /** 1381 * @stb_collect_info: Collects Smart Trace Buffers data. 1382 */ 1383 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1384 1385 /** 1386 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1387 */ 1388 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1389 1390 /** 1391 * @set_config_table: Apply the input DriverSmuConfig table settings. 1392 */ 1393 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1394 1395 /** 1396 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1397 * of SMUBUS table. 1398 */ 1399 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1400 1401 /** 1402 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP 1403 */ 1404 int (*init_pptable_microcode)(struct smu_context *smu); 1405 1406 /** 1407 * @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power 1408 * management. 1409 */ 1410 int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable); 1411 1412 /** 1413 * @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power 1414 * management. 1415 */ 1416 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable); 1417 1418 /** 1419 * @set_mall_enable: Init MALL power gating control. 1420 */ 1421 int (*set_mall_enable)(struct smu_context *smu); 1422 1423 /** 1424 * @notify_rlc_state: Notify RLC power state to SMU. 1425 */ 1426 int (*notify_rlc_state)(struct smu_context *smu, bool en); 1427 1428 /** 1429 * @is_asic_wbrf_supported: check whether PMFW supports the wbrf feature 1430 */ 1431 bool (*is_asic_wbrf_supported)(struct smu_context *smu); 1432 1433 /** 1434 * @enable_uclk_shadow: Enable the uclk shadow feature on wbrf supported 1435 */ 1436 int (*enable_uclk_shadow)(struct smu_context *smu, bool enable); 1437 1438 /** 1439 * @set_wbrf_exclusion_ranges: notify SMU the wifi bands occupied 1440 */ 1441 int (*set_wbrf_exclusion_ranges)(struct smu_context *smu, 1442 struct freq_band_range *exclusion_ranges); 1443 }; 1444 1445 typedef enum { 1446 METRICS_CURR_GFXCLK, 1447 METRICS_CURR_SOCCLK, 1448 METRICS_CURR_UCLK, 1449 METRICS_CURR_VCLK, 1450 METRICS_CURR_VCLK1, 1451 METRICS_CURR_DCLK, 1452 METRICS_CURR_DCLK1, 1453 METRICS_CURR_FCLK, 1454 METRICS_CURR_DCEFCLK, 1455 METRICS_AVERAGE_CPUCLK, 1456 METRICS_AVERAGE_GFXCLK, 1457 METRICS_AVERAGE_SOCCLK, 1458 METRICS_AVERAGE_FCLK, 1459 METRICS_AVERAGE_UCLK, 1460 METRICS_AVERAGE_VCLK, 1461 METRICS_AVERAGE_DCLK, 1462 METRICS_AVERAGE_VCLK1, 1463 METRICS_AVERAGE_DCLK1, 1464 METRICS_AVERAGE_GFXACTIVITY, 1465 METRICS_AVERAGE_MEMACTIVITY, 1466 METRICS_AVERAGE_VCNACTIVITY, 1467 METRICS_AVERAGE_SOCKETPOWER, 1468 METRICS_TEMPERATURE_EDGE, 1469 METRICS_TEMPERATURE_HOTSPOT, 1470 METRICS_TEMPERATURE_MEM, 1471 METRICS_TEMPERATURE_VRGFX, 1472 METRICS_TEMPERATURE_VRSOC, 1473 METRICS_TEMPERATURE_VRMEM, 1474 METRICS_THROTTLER_STATUS, 1475 METRICS_CURR_FANSPEED, 1476 METRICS_VOLTAGE_VDDSOC, 1477 METRICS_VOLTAGE_VDDGFX, 1478 METRICS_SS_APU_SHARE, 1479 METRICS_SS_DGPU_SHARE, 1480 METRICS_UNIQUE_ID_UPPER32, 1481 METRICS_UNIQUE_ID_LOWER32, 1482 METRICS_PCIE_RATE, 1483 METRICS_PCIE_WIDTH, 1484 METRICS_CURR_FANPWM, 1485 METRICS_CURR_SOCKETPOWER, 1486 METRICS_AVERAGE_VPECLK, 1487 METRICS_AVERAGE_IPUCLK, 1488 METRICS_AVERAGE_MPIPUCLK, 1489 METRICS_THROTTLER_RESIDENCY_PROCHOT, 1490 METRICS_THROTTLER_RESIDENCY_SPL, 1491 METRICS_THROTTLER_RESIDENCY_FPPT, 1492 METRICS_THROTTLER_RESIDENCY_SPPT, 1493 METRICS_THROTTLER_RESIDENCY_THM_CORE, 1494 METRICS_THROTTLER_RESIDENCY_THM_GFX, 1495 METRICS_THROTTLER_RESIDENCY_THM_SOC, 1496 } MetricsMember_t; 1497 1498 enum smu_cmn2asic_mapping_type { 1499 CMN2ASIC_MAPPING_MSG, 1500 CMN2ASIC_MAPPING_CLK, 1501 CMN2ASIC_MAPPING_FEATURE, 1502 CMN2ASIC_MAPPING_TABLE, 1503 CMN2ASIC_MAPPING_PWR, 1504 CMN2ASIC_MAPPING_WORKLOAD, 1505 }; 1506 1507 enum smu_baco_seq { 1508 BACO_SEQ_BACO = 0, 1509 BACO_SEQ_MSR, 1510 BACO_SEQ_BAMACO, 1511 BACO_SEQ_ULPS, 1512 BACO_SEQ_COUNT, 1513 }; 1514 1515 #define MSG_MAP(msg, index, flags) \ 1516 [SMU_MSG_##msg] = {1, (index), (flags)} 1517 1518 #define CLK_MAP(clk, index) \ 1519 [SMU_##clk] = {1, (index)} 1520 1521 #define FEA_MAP(fea) \ 1522 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1523 1524 #define FEA_MAP_REVERSE(fea) \ 1525 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1526 1527 #define FEA_MAP_HALF_REVERSE(fea) \ 1528 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1529 1530 #define TAB_MAP(tab) \ 1531 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1532 1533 #define TAB_MAP_VALID(tab) \ 1534 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1535 1536 #define TAB_MAP_INVALID(tab) \ 1537 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1538 1539 #define PWR_MAP(tab) \ 1540 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1541 1542 #define WORKLOAD_MAP(profile, workload) \ 1543 [profile] = {1, (workload)} 1544 1545 /** 1546 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1547 * 1548 * @dst: Pointer to destination struct 1549 * @first_dst_member: The member name in @dst where the overwrite begins 1550 * @last_dst_member: The member name in @dst where the overwrite ends after 1551 * @src: Pointer to the source struct 1552 * @first_src_member: The member name in @src where the copy begins 1553 * 1554 */ 1555 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1556 src, first_src_member) \ 1557 ({ \ 1558 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1559 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1560 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1561 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1562 __dst_offset; \ 1563 BUILD_BUG_ON(__src_size != __dst_size); \ 1564 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1565 (u8 *)(src) + __src_offset, \ 1566 __dst_size); \ 1567 }) 1568 1569 typedef struct { 1570 uint16_t LowFreq; 1571 uint16_t HighFreq; 1572 } WifiOneBand_t; 1573 1574 typedef struct { 1575 uint32_t WifiBandEntryNum; 1576 WifiOneBand_t WifiBandEntry[11]; 1577 uint32_t MmHubPadding[8]; 1578 } WifiBandEntryTable_t; 1579 1580 #define STR_SOC_PSTATE_POLICY "soc_pstate" 1581 #define STR_XGMI_PLPD_POLICY "xgmi_plpd" 1582 1583 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 1584 enum pp_pm_policy p_type); 1585 1586 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1587 int smu_get_power_limit(void *handle, 1588 uint32_t *limit, 1589 enum pp_power_limit_level pp_limit_level, 1590 enum pp_power_type pp_power_type); 1591 1592 bool smu_mode1_reset_is_support(struct smu_context *smu); 1593 bool smu_mode2_reset_is_support(struct smu_context *smu); 1594 int smu_mode1_reset(struct smu_context *smu); 1595 1596 extern const struct amd_ip_funcs smu_ip_funcs; 1597 1598 bool is_support_sw_smu(struct amdgpu_device *adev); 1599 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1600 int smu_write_watermarks_table(struct smu_context *smu); 1601 1602 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1603 uint32_t *min, uint32_t *max); 1604 1605 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1606 uint32_t min, uint32_t max); 1607 1608 int smu_set_gfx_power_up_by_imu(struct smu_context *smu); 1609 1610 int smu_set_ac_dc(struct smu_context *smu); 1611 1612 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 1613 enum pp_xgmi_plpd_mode mode); 1614 1615 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); 1616 1617 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); 1618 1619 int smu_set_residency_gfxoff(struct smu_context *smu, bool value); 1620 1621 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1622 1623 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1624 1625 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1626 uint64_t event_arg); 1627 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1628 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1629 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1630 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1631 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1632 int smu_send_rma_reason(struct smu_context *smu); 1633 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 1634 int level); 1635 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 1636 enum pp_pm_policy p_type, char *sysbuf); 1637 1638 #endif 1639 #endif 1640