1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 static void smu_power_profile_mode_get(struct smu_context *smu, 76 enum PP_SMC_POWER_PROFILE profile_mode); 77 static void smu_power_profile_mode_put(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79 80 static int smu_sys_get_pp_feature_mask(void *handle, 81 char *buf) 82 { 83 struct smu_context *smu = handle; 84 85 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 86 return -EOPNOTSUPP; 87 88 return smu_get_pp_feature_mask(smu, buf); 89 } 90 91 static int smu_sys_set_pp_feature_mask(void *handle, 92 uint64_t new_mask) 93 { 94 struct smu_context *smu = handle; 95 96 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 97 return -EOPNOTSUPP; 98 99 return smu_set_pp_feature_mask(smu, new_mask); 100 } 101 102 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 103 { 104 if (!smu->ppt_funcs->set_gfx_off_residency) 105 return -EINVAL; 106 107 return smu_set_gfx_off_residency(smu, value); 108 } 109 110 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 111 { 112 if (!smu->ppt_funcs->get_gfx_off_residency) 113 return -EINVAL; 114 115 return smu_get_gfx_off_residency(smu, value); 116 } 117 118 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 119 { 120 if (!smu->ppt_funcs->get_gfx_off_entrycount) 121 return -EINVAL; 122 123 return smu_get_gfx_off_entrycount(smu, value); 124 } 125 126 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 127 { 128 if (!smu->ppt_funcs->get_gfx_off_status) 129 return -EINVAL; 130 131 *value = smu_get_gfx_off_status(smu); 132 133 return 0; 134 } 135 136 int smu_set_soft_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t min, 139 uint32_t max) 140 { 141 int ret = 0; 142 143 if (smu->ppt_funcs->set_soft_freq_limited_range) 144 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 145 clk_type, 146 min, 147 max, 148 false); 149 150 return ret; 151 } 152 153 int smu_get_dpm_freq_range(struct smu_context *smu, 154 enum smu_clk_type clk_type, 155 uint32_t *min, 156 uint32_t *max) 157 { 158 int ret = -ENOTSUPP; 159 160 if (!min && !max) 161 return -EINVAL; 162 163 if (smu->ppt_funcs->get_dpm_ultimate_freq) 164 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 165 clk_type, 166 min, 167 max); 168 169 return ret; 170 } 171 172 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 173 { 174 int ret = 0; 175 struct amdgpu_device *adev = smu->adev; 176 177 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 178 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 179 if (ret) 180 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 181 } 182 return ret; 183 } 184 185 static u32 smu_get_mclk(void *handle, bool low) 186 { 187 struct smu_context *smu = handle; 188 uint32_t clk_freq; 189 int ret = 0; 190 191 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 192 low ? &clk_freq : NULL, 193 !low ? &clk_freq : NULL); 194 if (ret) 195 return 0; 196 return clk_freq * 100; 197 } 198 199 static u32 smu_get_sclk(void *handle, bool low) 200 { 201 struct smu_context *smu = handle; 202 uint32_t clk_freq; 203 int ret = 0; 204 205 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 206 low ? &clk_freq : NULL, 207 !low ? &clk_freq : NULL); 208 if (ret) 209 return 0; 210 return clk_freq * 100; 211 } 212 213 static int smu_set_gfx_imu_enable(struct smu_context *smu) 214 { 215 struct amdgpu_device *adev = smu->adev; 216 217 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 218 return 0; 219 220 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 221 return 0; 222 223 return smu_set_gfx_power_up_by_imu(smu); 224 } 225 226 static bool is_vcn_enabled(struct amdgpu_device *adev) 227 { 228 int i; 229 230 for (i = 0; i < adev->num_ip_blocks; i++) { 231 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 232 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 233 !adev->ip_blocks[i].status.valid) 234 return false; 235 } 236 237 return true; 238 } 239 240 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 241 bool enable) 242 { 243 struct smu_power_context *smu_power = &smu->smu_power; 244 struct smu_power_gate *power_gate = &smu_power->power_gate; 245 int ret = 0; 246 247 /* 248 * don't poweron vcn/jpeg when they are skipped. 249 */ 250 if (!is_vcn_enabled(smu->adev)) 251 return 0; 252 253 if (!smu->ppt_funcs->dpm_set_vcn_enable) 254 return 0; 255 256 if (atomic_read(&power_gate->vcn_gated) ^ enable) 257 return 0; 258 259 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, 0xff); 260 if (!ret) 261 atomic_set(&power_gate->vcn_gated, !enable); 262 263 return ret; 264 } 265 266 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 267 bool enable) 268 { 269 struct smu_power_context *smu_power = &smu->smu_power; 270 struct smu_power_gate *power_gate = &smu_power->power_gate; 271 int ret = 0; 272 273 if (!is_vcn_enabled(smu->adev)) 274 return 0; 275 276 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 277 return 0; 278 279 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 280 return 0; 281 282 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 283 if (!ret) 284 atomic_set(&power_gate->jpeg_gated, !enable); 285 286 return ret; 287 } 288 289 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 290 bool enable) 291 { 292 struct smu_power_context *smu_power = &smu->smu_power; 293 struct smu_power_gate *power_gate = &smu_power->power_gate; 294 int ret = 0; 295 296 if (!smu->ppt_funcs->dpm_set_vpe_enable) 297 return 0; 298 299 if (atomic_read(&power_gate->vpe_gated) ^ enable) 300 return 0; 301 302 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 303 if (!ret) 304 atomic_set(&power_gate->vpe_gated, !enable); 305 306 return ret; 307 } 308 309 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 310 bool enable) 311 { 312 struct smu_power_context *smu_power = &smu->smu_power; 313 struct smu_power_gate *power_gate = &smu_power->power_gate; 314 int ret = 0; 315 316 if (!smu->adev->enable_umsch_mm) 317 return 0; 318 319 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 320 return 0; 321 322 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 323 return 0; 324 325 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 326 if (!ret) 327 atomic_set(&power_gate->umsch_mm_gated, !enable); 328 329 return ret; 330 } 331 332 static int smu_set_mall_enable(struct smu_context *smu) 333 { 334 int ret = 0; 335 336 if (!smu->ppt_funcs->set_mall_enable) 337 return 0; 338 339 ret = smu->ppt_funcs->set_mall_enable(smu); 340 341 return ret; 342 } 343 344 /** 345 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 346 * 347 * @handle: smu_context pointer 348 * @block_type: the IP block to power gate/ungate 349 * @gate: to power gate if true, ungate otherwise 350 * 351 * This API uses no smu->mutex lock protection due to: 352 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 353 * This is guarded to be race condition free by the caller. 354 * 2. Or get called on user setting request of power_dpm_force_performance_level. 355 * Under this case, the smu->mutex lock protection is already enforced on 356 * the parent API smu_force_performance_level of the call path. 357 */ 358 static int smu_dpm_set_power_gate(void *handle, 359 uint32_t block_type, 360 bool gate) 361 { 362 struct smu_context *smu = handle; 363 int ret = 0; 364 365 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 366 dev_WARN(smu->adev->dev, 367 "SMU uninitialized but power %s requested for %u!\n", 368 gate ? "gate" : "ungate", block_type); 369 return -EOPNOTSUPP; 370 } 371 372 switch (block_type) { 373 /* 374 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 375 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 376 */ 377 case AMD_IP_BLOCK_TYPE_UVD: 378 case AMD_IP_BLOCK_TYPE_VCN: 379 ret = smu_dpm_set_vcn_enable(smu, !gate); 380 if (ret) 381 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 382 gate ? "gate" : "ungate"); 383 break; 384 case AMD_IP_BLOCK_TYPE_GFX: 385 ret = smu_gfx_off_control(smu, gate); 386 if (ret) 387 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 388 gate ? "enable" : "disable"); 389 break; 390 case AMD_IP_BLOCK_TYPE_SDMA: 391 ret = smu_powergate_sdma(smu, gate); 392 if (ret) 393 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 394 gate ? "gate" : "ungate"); 395 break; 396 case AMD_IP_BLOCK_TYPE_JPEG: 397 ret = smu_dpm_set_jpeg_enable(smu, !gate); 398 if (ret) 399 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 400 gate ? "gate" : "ungate"); 401 break; 402 case AMD_IP_BLOCK_TYPE_VPE: 403 ret = smu_dpm_set_vpe_enable(smu, !gate); 404 if (ret) 405 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 406 gate ? "gate" : "ungate"); 407 break; 408 default: 409 dev_err(smu->adev->dev, "Unsupported block type!\n"); 410 return -EINVAL; 411 } 412 413 return ret; 414 } 415 416 /** 417 * smu_set_user_clk_dependencies - set user profile clock dependencies 418 * 419 * @smu: smu_context pointer 420 * @clk: enum smu_clk_type type 421 * 422 * Enable/Disable the clock dependency for the @clk type. 423 */ 424 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 425 { 426 if (smu->adev->in_suspend) 427 return; 428 429 if (clk == SMU_MCLK) { 430 smu->user_dpm_profile.clk_dependency = 0; 431 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 432 } else if (clk == SMU_FCLK) { 433 /* MCLK takes precedence over FCLK */ 434 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 435 return; 436 437 smu->user_dpm_profile.clk_dependency = 0; 438 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 439 } else if (clk == SMU_SOCCLK) { 440 /* MCLK takes precedence over SOCCLK */ 441 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 442 return; 443 444 smu->user_dpm_profile.clk_dependency = 0; 445 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 446 } else 447 /* Add clk dependencies here, if any */ 448 return; 449 } 450 451 /** 452 * smu_restore_dpm_user_profile - reinstate user dpm profile 453 * 454 * @smu: smu_context pointer 455 * 456 * Restore the saved user power configurations include power limit, 457 * clock frequencies, fan control mode and fan speed. 458 */ 459 static void smu_restore_dpm_user_profile(struct smu_context *smu) 460 { 461 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 462 int ret = 0; 463 464 if (!smu->adev->in_suspend) 465 return; 466 467 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 468 return; 469 470 /* Enable restore flag */ 471 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 472 473 /* set the user dpm power limit */ 474 if (smu->user_dpm_profile.power_limit) { 475 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 476 if (ret) 477 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 478 } 479 480 /* set the user dpm clock configurations */ 481 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 482 enum smu_clk_type clk_type; 483 484 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 485 /* 486 * Iterate over smu clk type and force the saved user clk 487 * configs, skip if clock dependency is enabled 488 */ 489 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 490 smu->user_dpm_profile.clk_mask[clk_type]) { 491 ret = smu_force_smuclk_levels(smu, clk_type, 492 smu->user_dpm_profile.clk_mask[clk_type]); 493 if (ret) 494 dev_err(smu->adev->dev, 495 "Failed to set clock type = %d\n", clk_type); 496 } 497 } 498 } 499 500 /* set the user dpm fan configurations */ 501 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 502 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 503 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 504 if (ret != -EOPNOTSUPP) { 505 smu->user_dpm_profile.fan_speed_pwm = 0; 506 smu->user_dpm_profile.fan_speed_rpm = 0; 507 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 508 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 509 } 510 511 if (smu->user_dpm_profile.fan_speed_pwm) { 512 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 513 if (ret != -EOPNOTSUPP) 514 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 515 } 516 517 if (smu->user_dpm_profile.fan_speed_rpm) { 518 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 519 if (ret != -EOPNOTSUPP) 520 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 521 } 522 } 523 524 /* Restore user customized OD settings */ 525 if (smu->user_dpm_profile.user_od) { 526 if (smu->ppt_funcs->restore_user_od_settings) { 527 ret = smu->ppt_funcs->restore_user_od_settings(smu); 528 if (ret) 529 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 530 } 531 } 532 533 /* Disable restore flag */ 534 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 535 } 536 537 static int smu_get_power_num_states(void *handle, 538 struct pp_states_info *state_info) 539 { 540 if (!state_info) 541 return -EINVAL; 542 543 /* not support power state */ 544 memset(state_info, 0, sizeof(struct pp_states_info)); 545 state_info->nums = 1; 546 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 547 548 return 0; 549 } 550 551 bool is_support_sw_smu(struct amdgpu_device *adev) 552 { 553 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 554 if (adev->asic_type == CHIP_VEGA20) 555 return false; 556 557 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 558 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 559 return true; 560 561 return false; 562 } 563 564 bool is_support_cclk_dpm(struct amdgpu_device *adev) 565 { 566 struct smu_context *smu = adev->powerplay.pp_handle; 567 568 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 569 return false; 570 571 return true; 572 } 573 574 575 static int smu_sys_get_pp_table(void *handle, 576 char **table) 577 { 578 struct smu_context *smu = handle; 579 struct smu_table_context *smu_table = &smu->smu_table; 580 581 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 582 return -EOPNOTSUPP; 583 584 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 585 return -EINVAL; 586 587 if (smu_table->hardcode_pptable) 588 *table = smu_table->hardcode_pptable; 589 else 590 *table = smu_table->power_play_table; 591 592 return smu_table->power_play_table_size; 593 } 594 595 static int smu_sys_set_pp_table(void *handle, 596 const char *buf, 597 size_t size) 598 { 599 struct smu_context *smu = handle; 600 struct smu_table_context *smu_table = &smu->smu_table; 601 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 602 int ret = 0; 603 604 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 605 return -EOPNOTSUPP; 606 607 if (header->usStructureSize != size) { 608 dev_err(smu->adev->dev, "pp table size not matched !\n"); 609 return -EIO; 610 } 611 612 if (!smu_table->hardcode_pptable) { 613 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 614 if (!smu_table->hardcode_pptable) 615 return -ENOMEM; 616 } 617 618 memcpy(smu_table->hardcode_pptable, buf, size); 619 smu_table->power_play_table = smu_table->hardcode_pptable; 620 smu_table->power_play_table_size = size; 621 622 /* 623 * Special hw_fini action(for Navi1x, the DPMs disablement will be 624 * skipped) may be needed for custom pptable uploading. 625 */ 626 smu->uploading_custom_pp_table = true; 627 628 ret = smu_reset(smu); 629 if (ret) 630 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 631 632 smu->uploading_custom_pp_table = false; 633 634 return ret; 635 } 636 637 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 638 { 639 struct smu_feature *feature = &smu->smu_feature; 640 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 641 int ret = 0; 642 643 /* 644 * With SCPM enabled, the allowed featuremasks setting(via 645 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 646 * That means there is no way to let PMFW knows the settings below. 647 * Thus, we just assume all the features are allowed under 648 * such scenario. 649 */ 650 if (smu->adev->scpm_enabled) { 651 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 652 return 0; 653 } 654 655 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 656 657 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 658 SMU_FEATURE_MAX/32); 659 if (ret) 660 return ret; 661 662 bitmap_or(feature->allowed, feature->allowed, 663 (unsigned long *)allowed_feature_mask, 664 feature->feature_num); 665 666 return ret; 667 } 668 669 static int smu_set_funcs(struct amdgpu_device *adev) 670 { 671 struct smu_context *smu = adev->powerplay.pp_handle; 672 673 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 674 smu->od_enabled = true; 675 676 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 677 case IP_VERSION(11, 0, 0): 678 case IP_VERSION(11, 0, 5): 679 case IP_VERSION(11, 0, 9): 680 navi10_set_ppt_funcs(smu); 681 break; 682 case IP_VERSION(11, 0, 7): 683 case IP_VERSION(11, 0, 11): 684 case IP_VERSION(11, 0, 12): 685 case IP_VERSION(11, 0, 13): 686 sienna_cichlid_set_ppt_funcs(smu); 687 break; 688 case IP_VERSION(12, 0, 0): 689 case IP_VERSION(12, 0, 1): 690 renoir_set_ppt_funcs(smu); 691 break; 692 case IP_VERSION(11, 5, 0): 693 vangogh_set_ppt_funcs(smu); 694 break; 695 case IP_VERSION(13, 0, 1): 696 case IP_VERSION(13, 0, 3): 697 case IP_VERSION(13, 0, 8): 698 yellow_carp_set_ppt_funcs(smu); 699 break; 700 case IP_VERSION(13, 0, 4): 701 case IP_VERSION(13, 0, 11): 702 smu_v13_0_4_set_ppt_funcs(smu); 703 break; 704 case IP_VERSION(13, 0, 5): 705 smu_v13_0_5_set_ppt_funcs(smu); 706 break; 707 case IP_VERSION(11, 0, 8): 708 cyan_skillfish_set_ppt_funcs(smu); 709 break; 710 case IP_VERSION(11, 0, 2): 711 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 712 arcturus_set_ppt_funcs(smu); 713 /* OD is not supported on Arcturus */ 714 smu->od_enabled = false; 715 break; 716 case IP_VERSION(13, 0, 2): 717 aldebaran_set_ppt_funcs(smu); 718 /* Enable pp_od_clk_voltage node */ 719 smu->od_enabled = true; 720 break; 721 case IP_VERSION(13, 0, 0): 722 case IP_VERSION(13, 0, 10): 723 smu_v13_0_0_set_ppt_funcs(smu); 724 break; 725 case IP_VERSION(13, 0, 6): 726 case IP_VERSION(13, 0, 14): 727 smu_v13_0_6_set_ppt_funcs(smu); 728 /* Enable pp_od_clk_voltage node */ 729 smu->od_enabled = true; 730 break; 731 case IP_VERSION(13, 0, 7): 732 smu_v13_0_7_set_ppt_funcs(smu); 733 break; 734 case IP_VERSION(14, 0, 0): 735 case IP_VERSION(14, 0, 1): 736 case IP_VERSION(14, 0, 4): 737 smu_v14_0_0_set_ppt_funcs(smu); 738 break; 739 case IP_VERSION(14, 0, 2): 740 case IP_VERSION(14, 0, 3): 741 smu_v14_0_2_set_ppt_funcs(smu); 742 break; 743 default: 744 return -EINVAL; 745 } 746 747 return 0; 748 } 749 750 static int smu_early_init(struct amdgpu_ip_block *ip_block) 751 { 752 struct amdgpu_device *adev = ip_block->adev; 753 struct smu_context *smu; 754 int r; 755 756 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 757 if (!smu) 758 return -ENOMEM; 759 760 smu->adev = adev; 761 smu->pm_enabled = !!amdgpu_dpm; 762 smu->is_apu = false; 763 smu->smu_baco.state = SMU_BACO_STATE_NONE; 764 smu->smu_baco.platform_support = false; 765 smu->smu_baco.maco_support = false; 766 smu->user_dpm_profile.fan_mode = -1; 767 768 mutex_init(&smu->message_lock); 769 770 adev->powerplay.pp_handle = smu; 771 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 772 773 r = smu_set_funcs(adev); 774 if (r) 775 return r; 776 return smu_init_microcode(smu); 777 } 778 779 static int smu_set_default_dpm_table(struct smu_context *smu) 780 { 781 struct amdgpu_device *adev = smu->adev; 782 struct smu_power_context *smu_power = &smu->smu_power; 783 struct smu_power_gate *power_gate = &smu_power->power_gate; 784 int vcn_gate, jpeg_gate; 785 int ret = 0; 786 787 if (!smu->ppt_funcs->set_default_dpm_table) 788 return 0; 789 790 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 791 vcn_gate = atomic_read(&power_gate->vcn_gated); 792 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 793 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 794 795 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 796 ret = smu_dpm_set_vcn_enable(smu, true); 797 if (ret) 798 return ret; 799 } 800 801 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 802 ret = smu_dpm_set_jpeg_enable(smu, true); 803 if (ret) 804 goto err_out; 805 } 806 807 ret = smu->ppt_funcs->set_default_dpm_table(smu); 808 if (ret) 809 dev_err(smu->adev->dev, 810 "Failed to setup default dpm clock tables!\n"); 811 812 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 813 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 814 err_out: 815 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 816 smu_dpm_set_vcn_enable(smu, !vcn_gate); 817 818 return ret; 819 } 820 821 static int smu_apply_default_config_table_settings(struct smu_context *smu) 822 { 823 struct amdgpu_device *adev = smu->adev; 824 int ret = 0; 825 826 ret = smu_get_default_config_table_settings(smu, 827 &adev->pm.config_table); 828 if (ret) 829 return ret; 830 831 return smu_set_config_table(smu, &adev->pm.config_table); 832 } 833 834 static int smu_late_init(struct amdgpu_ip_block *ip_block) 835 { 836 struct amdgpu_device *adev = ip_block->adev; 837 struct smu_context *smu = adev->powerplay.pp_handle; 838 int ret = 0; 839 840 smu_set_fine_grain_gfx_freq_parameters(smu); 841 842 if (!smu->pm_enabled) 843 return 0; 844 845 ret = smu_post_init(smu); 846 if (ret) { 847 dev_err(adev->dev, "Failed to post smu init!\n"); 848 return ret; 849 } 850 851 /* 852 * Explicitly notify PMFW the power mode the system in. Since 853 * the PMFW may boot the ASIC with a different mode. 854 * For those supporting ACDC switch via gpio, PMFW will 855 * handle the switch automatically. Driver involvement 856 * is unnecessary. 857 */ 858 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 859 smu_set_ac_dc(smu); 860 861 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 862 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 863 return 0; 864 865 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 866 ret = smu_set_default_od_settings(smu); 867 if (ret) { 868 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 869 return ret; 870 } 871 } 872 873 ret = smu_populate_umd_state_clk(smu); 874 if (ret) { 875 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 876 return ret; 877 } 878 879 ret = smu_get_asic_power_limits(smu, 880 &smu->current_power_limit, 881 &smu->default_power_limit, 882 &smu->max_power_limit, 883 &smu->min_power_limit); 884 if (ret) { 885 dev_err(adev->dev, "Failed to get asic power limits!\n"); 886 return ret; 887 } 888 889 if (!amdgpu_sriov_vf(adev)) 890 smu_get_unique_id(smu); 891 892 smu_get_fan_parameters(smu); 893 894 smu_handle_task(smu, 895 smu->smu_dpm.dpm_level, 896 AMD_PP_TASK_COMPLETE_INIT); 897 898 ret = smu_apply_default_config_table_settings(smu); 899 if (ret && (ret != -EOPNOTSUPP)) { 900 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 901 return ret; 902 } 903 904 smu_restore_dpm_user_profile(smu); 905 906 return 0; 907 } 908 909 static int smu_init_fb_allocations(struct smu_context *smu) 910 { 911 struct amdgpu_device *adev = smu->adev; 912 struct smu_table_context *smu_table = &smu->smu_table; 913 struct smu_table *tables = smu_table->tables; 914 struct smu_table *driver_table = &(smu_table->driver_table); 915 uint32_t max_table_size = 0; 916 int ret, i; 917 918 /* VRAM allocation for tool table */ 919 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 920 ret = amdgpu_bo_create_kernel(adev, 921 tables[SMU_TABLE_PMSTATUSLOG].size, 922 tables[SMU_TABLE_PMSTATUSLOG].align, 923 tables[SMU_TABLE_PMSTATUSLOG].domain, 924 &tables[SMU_TABLE_PMSTATUSLOG].bo, 925 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 926 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 927 if (ret) { 928 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 929 return ret; 930 } 931 } 932 933 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 934 /* VRAM allocation for driver table */ 935 for (i = 0; i < SMU_TABLE_COUNT; i++) { 936 if (tables[i].size == 0) 937 continue; 938 939 /* If one of the tables has VRAM domain restriction, keep it in 940 * VRAM 941 */ 942 if ((tables[i].domain & 943 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 944 AMDGPU_GEM_DOMAIN_VRAM) 945 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 946 947 if (i == SMU_TABLE_PMSTATUSLOG) 948 continue; 949 950 if (max_table_size < tables[i].size) 951 max_table_size = tables[i].size; 952 } 953 954 driver_table->size = max_table_size; 955 driver_table->align = PAGE_SIZE; 956 957 ret = amdgpu_bo_create_kernel(adev, 958 driver_table->size, 959 driver_table->align, 960 driver_table->domain, 961 &driver_table->bo, 962 &driver_table->mc_address, 963 &driver_table->cpu_addr); 964 if (ret) { 965 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 966 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 967 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 968 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 969 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 970 } 971 972 return ret; 973 } 974 975 static int smu_fini_fb_allocations(struct smu_context *smu) 976 { 977 struct smu_table_context *smu_table = &smu->smu_table; 978 struct smu_table *tables = smu_table->tables; 979 struct smu_table *driver_table = &(smu_table->driver_table); 980 981 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 982 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 983 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 984 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 985 986 amdgpu_bo_free_kernel(&driver_table->bo, 987 &driver_table->mc_address, 988 &driver_table->cpu_addr); 989 990 return 0; 991 } 992 993 /** 994 * smu_alloc_memory_pool - allocate memory pool in the system memory 995 * 996 * @smu: amdgpu_device pointer 997 * 998 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 999 * and DramLogSetDramAddr can notify it changed. 1000 * 1001 * Returns 0 on success, error on failure. 1002 */ 1003 static int smu_alloc_memory_pool(struct smu_context *smu) 1004 { 1005 struct amdgpu_device *adev = smu->adev; 1006 struct smu_table_context *smu_table = &smu->smu_table; 1007 struct smu_table *memory_pool = &smu_table->memory_pool; 1008 uint64_t pool_size = smu->pool_size; 1009 int ret = 0; 1010 1011 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1012 return ret; 1013 1014 memory_pool->size = pool_size; 1015 memory_pool->align = PAGE_SIZE; 1016 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 1017 1018 switch (pool_size) { 1019 case SMU_MEMORY_POOL_SIZE_256_MB: 1020 case SMU_MEMORY_POOL_SIZE_512_MB: 1021 case SMU_MEMORY_POOL_SIZE_1_GB: 1022 case SMU_MEMORY_POOL_SIZE_2_GB: 1023 ret = amdgpu_bo_create_kernel(adev, 1024 memory_pool->size, 1025 memory_pool->align, 1026 memory_pool->domain, 1027 &memory_pool->bo, 1028 &memory_pool->mc_address, 1029 &memory_pool->cpu_addr); 1030 if (ret) 1031 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1032 break; 1033 default: 1034 break; 1035 } 1036 1037 return ret; 1038 } 1039 1040 static int smu_free_memory_pool(struct smu_context *smu) 1041 { 1042 struct smu_table_context *smu_table = &smu->smu_table; 1043 struct smu_table *memory_pool = &smu_table->memory_pool; 1044 1045 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1046 return 0; 1047 1048 amdgpu_bo_free_kernel(&memory_pool->bo, 1049 &memory_pool->mc_address, 1050 &memory_pool->cpu_addr); 1051 1052 memset(memory_pool, 0, sizeof(struct smu_table)); 1053 1054 return 0; 1055 } 1056 1057 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1058 { 1059 struct smu_table_context *smu_table = &smu->smu_table; 1060 struct smu_table *dummy_read_1_table = 1061 &smu_table->dummy_read_1_table; 1062 struct amdgpu_device *adev = smu->adev; 1063 int ret = 0; 1064 1065 if (!dummy_read_1_table->size) 1066 return 0; 1067 1068 ret = amdgpu_bo_create_kernel(adev, 1069 dummy_read_1_table->size, 1070 dummy_read_1_table->align, 1071 dummy_read_1_table->domain, 1072 &dummy_read_1_table->bo, 1073 &dummy_read_1_table->mc_address, 1074 &dummy_read_1_table->cpu_addr); 1075 if (ret) 1076 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1077 1078 return ret; 1079 } 1080 1081 static void smu_free_dummy_read_table(struct smu_context *smu) 1082 { 1083 struct smu_table_context *smu_table = &smu->smu_table; 1084 struct smu_table *dummy_read_1_table = 1085 &smu_table->dummy_read_1_table; 1086 1087 1088 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1089 &dummy_read_1_table->mc_address, 1090 &dummy_read_1_table->cpu_addr); 1091 1092 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1093 } 1094 1095 static int smu_smc_table_sw_init(struct smu_context *smu) 1096 { 1097 int ret; 1098 1099 /** 1100 * Create smu_table structure, and init smc tables such as 1101 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1102 */ 1103 ret = smu_init_smc_tables(smu); 1104 if (ret) { 1105 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1106 return ret; 1107 } 1108 1109 /** 1110 * Create smu_power_context structure, and allocate smu_dpm_context and 1111 * context size to fill the smu_power_context data. 1112 */ 1113 ret = smu_init_power(smu); 1114 if (ret) { 1115 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1116 return ret; 1117 } 1118 1119 /* 1120 * allocate vram bos to store smc table contents. 1121 */ 1122 ret = smu_init_fb_allocations(smu); 1123 if (ret) 1124 return ret; 1125 1126 ret = smu_alloc_memory_pool(smu); 1127 if (ret) 1128 return ret; 1129 1130 ret = smu_alloc_dummy_read_table(smu); 1131 if (ret) 1132 return ret; 1133 1134 ret = smu_i2c_init(smu); 1135 if (ret) 1136 return ret; 1137 1138 return 0; 1139 } 1140 1141 static int smu_smc_table_sw_fini(struct smu_context *smu) 1142 { 1143 int ret; 1144 1145 smu_i2c_fini(smu); 1146 1147 smu_free_dummy_read_table(smu); 1148 1149 ret = smu_free_memory_pool(smu); 1150 if (ret) 1151 return ret; 1152 1153 ret = smu_fini_fb_allocations(smu); 1154 if (ret) 1155 return ret; 1156 1157 ret = smu_fini_power(smu); 1158 if (ret) { 1159 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1160 return ret; 1161 } 1162 1163 ret = smu_fini_smc_tables(smu); 1164 if (ret) { 1165 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1166 return ret; 1167 } 1168 1169 return 0; 1170 } 1171 1172 static void smu_throttling_logging_work_fn(struct work_struct *work) 1173 { 1174 struct smu_context *smu = container_of(work, struct smu_context, 1175 throttling_logging_work); 1176 1177 smu_log_thermal_throttling(smu); 1178 } 1179 1180 static void smu_interrupt_work_fn(struct work_struct *work) 1181 { 1182 struct smu_context *smu = container_of(work, struct smu_context, 1183 interrupt_work); 1184 1185 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1186 smu->ppt_funcs->interrupt_work(smu); 1187 } 1188 1189 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1190 { 1191 struct smu_context *smu = 1192 container_of(work, struct smu_context, swctf_delayed_work.work); 1193 struct smu_temperature_range *range = 1194 &smu->thermal_range; 1195 struct amdgpu_device *adev = smu->adev; 1196 uint32_t hotspot_tmp, size; 1197 1198 /* 1199 * If the hotspot temperature is confirmed as below SW CTF setting point 1200 * after the delay enforced, nothing will be done. 1201 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1202 */ 1203 if (range->software_shutdown_temp && 1204 smu->ppt_funcs->read_sensor && 1205 !smu->ppt_funcs->read_sensor(smu, 1206 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1207 &hotspot_tmp, 1208 &size) && 1209 hotspot_tmp / 1000 < range->software_shutdown_temp) 1210 return; 1211 1212 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1213 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1214 orderly_poweroff(true); 1215 } 1216 1217 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1218 { 1219 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1220 struct smu_dpm_policy_ctxt *policy_ctxt; 1221 struct smu_dpm_policy *policy; 1222 1223 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1224 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1225 if (policy) 1226 policy->current_level = XGMI_PLPD_DEFAULT; 1227 return; 1228 } 1229 1230 /* PMFW put PLPD into default policy after enabling the feature */ 1231 if (smu_feature_is_enabled(smu, 1232 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1233 if (policy) 1234 policy->current_level = XGMI_PLPD_DEFAULT; 1235 } else { 1236 policy_ctxt = dpm_ctxt->dpm_policies; 1237 if (policy_ctxt) 1238 policy_ctxt->policy_mask &= 1239 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1240 } 1241 } 1242 1243 static bool smu_is_workload_profile_available(struct smu_context *smu, 1244 u32 profile) 1245 { 1246 if (profile >= PP_SMC_POWER_PROFILE_COUNT) 1247 return false; 1248 return smu->workload_map && smu->workload_map[profile].valid_mapping; 1249 } 1250 1251 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1252 { 1253 struct amdgpu_device *adev = ip_block->adev; 1254 struct smu_context *smu = adev->powerplay.pp_handle; 1255 int ret; 1256 1257 smu->pool_size = adev->pm.smu_prv_buffer_size; 1258 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1259 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1260 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1261 1262 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1263 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1264 atomic64_set(&smu->throttle_int_counter, 0); 1265 smu->watermarks_bitmap = 0; 1266 1267 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1268 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1269 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1270 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1271 1272 if (smu->is_apu || 1273 !smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) 1274 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1275 else 1276 smu->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1277 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1278 1279 smu->display_config = &adev->pm.pm_display_cfg; 1280 1281 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1282 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1283 1284 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1285 smu_swctf_delayed_work_handler); 1286 1287 ret = smu_smc_table_sw_init(smu); 1288 if (ret) { 1289 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1290 return ret; 1291 } 1292 1293 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1294 ret = smu_get_vbios_bootup_values(smu); 1295 if (ret) { 1296 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1297 return ret; 1298 } 1299 1300 ret = smu_init_pptable_microcode(smu); 1301 if (ret) { 1302 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1303 return ret; 1304 } 1305 1306 ret = smu_register_irq_handler(smu); 1307 if (ret) { 1308 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1309 return ret; 1310 } 1311 1312 /* If there is no way to query fan control mode, fan control is not supported */ 1313 if (!smu->ppt_funcs->get_fan_control_mode) 1314 smu->adev->pm.no_fan = true; 1315 1316 return 0; 1317 } 1318 1319 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1320 { 1321 struct amdgpu_device *adev = ip_block->adev; 1322 struct smu_context *smu = adev->powerplay.pp_handle; 1323 int ret; 1324 1325 ret = smu_smc_table_sw_fini(smu); 1326 if (ret) { 1327 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1328 return ret; 1329 } 1330 1331 if (smu->custom_profile_params) { 1332 kfree(smu->custom_profile_params); 1333 smu->custom_profile_params = NULL; 1334 } 1335 1336 smu_fini_microcode(smu); 1337 1338 return 0; 1339 } 1340 1341 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1342 { 1343 struct amdgpu_device *adev = smu->adev; 1344 struct smu_temperature_range *range = 1345 &smu->thermal_range; 1346 int ret = 0; 1347 1348 if (!smu->ppt_funcs->get_thermal_temperature_range) 1349 return 0; 1350 1351 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1352 if (ret) 1353 return ret; 1354 1355 adev->pm.dpm.thermal.min_temp = range->min; 1356 adev->pm.dpm.thermal.max_temp = range->max; 1357 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1358 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1359 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1360 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1361 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1362 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1363 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1364 1365 return ret; 1366 } 1367 1368 /** 1369 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1370 * 1371 * @smu: smu_context pointer 1372 * 1373 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1374 * Returns 0 on success, error on failure. 1375 */ 1376 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1377 { 1378 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1379 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1380 struct amdgpu_device *adev = smu->adev; 1381 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1382 uint64_t start, end; 1383 int ret, i, j; 1384 1385 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1386 if (ret) { 1387 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1388 return ret; 1389 } 1390 1391 /* 1392 * The exclusion ranges array we got might be filled with holes and duplicate 1393 * entries. For example: 1394 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1395 * We need to do some sortups to eliminate those holes and duplicate entries. 1396 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1397 */ 1398 for (i = 0; i < num_of_wbrf_ranges; i++) { 1399 start = wifi_bands[i].start; 1400 end = wifi_bands[i].end; 1401 1402 /* get the last valid entry to fill the intermediate hole */ 1403 if (!start && !end) { 1404 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1405 if (wifi_bands[j].start && wifi_bands[j].end) 1406 break; 1407 1408 /* no valid entry left */ 1409 if (j <= i) 1410 break; 1411 1412 start = wifi_bands[i].start = wifi_bands[j].start; 1413 end = wifi_bands[i].end = wifi_bands[j].end; 1414 wifi_bands[j].start = 0; 1415 wifi_bands[j].end = 0; 1416 num_of_wbrf_ranges = j; 1417 } 1418 1419 /* eliminate duplicate entries */ 1420 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1421 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1422 wifi_bands[j].start = 0; 1423 wifi_bands[j].end = 0; 1424 } 1425 } 1426 } 1427 1428 /* Send the sorted wifi_bands to PMFW */ 1429 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1430 /* Try to set the wifi_bands again */ 1431 if (unlikely(ret == -EBUSY)) { 1432 mdelay(5); 1433 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1434 } 1435 1436 return ret; 1437 } 1438 1439 /** 1440 * smu_wbrf_event_handler - handle notify events 1441 * 1442 * @nb: notifier block 1443 * @action: event type 1444 * @_arg: event data 1445 * 1446 * Calls relevant amdgpu function in response to wbrf event 1447 * notification from kernel. 1448 */ 1449 static int smu_wbrf_event_handler(struct notifier_block *nb, 1450 unsigned long action, void *_arg) 1451 { 1452 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1453 1454 switch (action) { 1455 case WBRF_CHANGED: 1456 schedule_delayed_work(&smu->wbrf_delayed_work, 1457 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1458 break; 1459 default: 1460 return NOTIFY_DONE; 1461 } 1462 1463 return NOTIFY_OK; 1464 } 1465 1466 /** 1467 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1468 * 1469 * @work: struct work_struct pointer 1470 * 1471 * Flood is over and driver will consume the latest exclusion ranges. 1472 */ 1473 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1474 { 1475 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1476 1477 smu_wbrf_handle_exclusion_ranges(smu); 1478 } 1479 1480 /** 1481 * smu_wbrf_support_check - check wbrf support 1482 * 1483 * @smu: smu_context pointer 1484 * 1485 * Verifies the ACPI interface whether wbrf is supported. 1486 */ 1487 static void smu_wbrf_support_check(struct smu_context *smu) 1488 { 1489 struct amdgpu_device *adev = smu->adev; 1490 1491 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1492 acpi_amd_wbrf_supported_consumer(adev->dev); 1493 1494 if (smu->wbrf_supported) 1495 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1496 } 1497 1498 /** 1499 * smu_wbrf_init - init driver wbrf support 1500 * 1501 * @smu: smu_context pointer 1502 * 1503 * Verifies the AMD ACPI interfaces and registers with the wbrf 1504 * notifier chain if wbrf feature is supported. 1505 * Returns 0 on success, error on failure. 1506 */ 1507 static int smu_wbrf_init(struct smu_context *smu) 1508 { 1509 int ret; 1510 1511 if (!smu->wbrf_supported) 1512 return 0; 1513 1514 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1515 1516 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1517 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1518 if (ret) 1519 return ret; 1520 1521 /* 1522 * Some wifiband exclusion ranges may be already there 1523 * before our driver loaded. To make sure our driver 1524 * is awared of those exclusion ranges. 1525 */ 1526 schedule_delayed_work(&smu->wbrf_delayed_work, 1527 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1528 1529 return 0; 1530 } 1531 1532 /** 1533 * smu_wbrf_fini - tear down driver wbrf support 1534 * 1535 * @smu: smu_context pointer 1536 * 1537 * Unregisters with the wbrf notifier chain. 1538 */ 1539 static void smu_wbrf_fini(struct smu_context *smu) 1540 { 1541 if (!smu->wbrf_supported) 1542 return; 1543 1544 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1545 1546 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1547 } 1548 1549 static int smu_smc_hw_setup(struct smu_context *smu) 1550 { 1551 struct smu_feature *feature = &smu->smu_feature; 1552 struct amdgpu_device *adev = smu->adev; 1553 uint8_t pcie_gen = 0, pcie_width = 0; 1554 uint64_t features_supported; 1555 int ret = 0; 1556 1557 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1558 case IP_VERSION(11, 0, 7): 1559 case IP_VERSION(11, 0, 11): 1560 case IP_VERSION(11, 5, 0): 1561 case IP_VERSION(11, 0, 12): 1562 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1563 dev_info(adev->dev, "dpm has been enabled\n"); 1564 ret = smu_system_features_control(smu, true); 1565 if (ret) 1566 dev_err(adev->dev, "Failed system features control!\n"); 1567 return ret; 1568 } 1569 break; 1570 default: 1571 break; 1572 } 1573 1574 ret = smu_init_display_count(smu, 0); 1575 if (ret) { 1576 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1577 return ret; 1578 } 1579 1580 ret = smu_set_driver_table_location(smu); 1581 if (ret) { 1582 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1583 return ret; 1584 } 1585 1586 /* 1587 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1588 */ 1589 ret = smu_set_tool_table_location(smu); 1590 if (ret) { 1591 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1592 return ret; 1593 } 1594 1595 /* 1596 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1597 * pool location. 1598 */ 1599 ret = smu_notify_memory_pool_location(smu); 1600 if (ret) { 1601 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1602 return ret; 1603 } 1604 1605 /* 1606 * It is assumed the pptable used before runpm is same as 1607 * the one used afterwards. Thus, we can reuse the stored 1608 * copy and do not need to resetup the pptable again. 1609 */ 1610 if (!adev->in_runpm) { 1611 ret = smu_setup_pptable(smu); 1612 if (ret) { 1613 dev_err(adev->dev, "Failed to setup pptable!\n"); 1614 return ret; 1615 } 1616 } 1617 1618 /* smu_dump_pptable(smu); */ 1619 1620 /* 1621 * With SCPM enabled, PSP is responsible for the PPTable transferring 1622 * (to SMU). Driver involvement is not needed and permitted. 1623 */ 1624 if (!adev->scpm_enabled) { 1625 /* 1626 * Copy pptable bo in the vram to smc with SMU MSGs such as 1627 * SetDriverDramAddr and TransferTableDram2Smu. 1628 */ 1629 ret = smu_write_pptable(smu); 1630 if (ret) { 1631 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1632 return ret; 1633 } 1634 } 1635 1636 /* issue Run*Btc msg */ 1637 ret = smu_run_btc(smu); 1638 if (ret) 1639 return ret; 1640 1641 /* Enable UclkShadow on wbrf supported */ 1642 if (smu->wbrf_supported) { 1643 ret = smu_enable_uclk_shadow(smu, true); 1644 if (ret) { 1645 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1646 return ret; 1647 } 1648 } 1649 1650 /* 1651 * With SCPM enabled, these actions(and relevant messages) are 1652 * not needed and permitted. 1653 */ 1654 if (!adev->scpm_enabled) { 1655 ret = smu_feature_set_allowed_mask(smu); 1656 if (ret) { 1657 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1658 return ret; 1659 } 1660 } 1661 1662 ret = smu_system_features_control(smu, true); 1663 if (ret) { 1664 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1665 return ret; 1666 } 1667 1668 smu_init_xgmi_plpd_mode(smu); 1669 1670 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1671 if (ret) { 1672 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1673 return ret; 1674 } 1675 bitmap_copy(feature->supported, 1676 (unsigned long *)&features_supported, 1677 feature->feature_num); 1678 1679 if (!smu_is_dpm_running(smu)) 1680 dev_info(adev->dev, "dpm has been disabled\n"); 1681 1682 /* 1683 * Set initialized values (get from vbios) to dpm tables context such as 1684 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1685 * type of clks. 1686 */ 1687 ret = smu_set_default_dpm_table(smu); 1688 if (ret) { 1689 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1690 return ret; 1691 } 1692 1693 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1694 pcie_gen = 4; 1695 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1696 pcie_gen = 3; 1697 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1698 pcie_gen = 2; 1699 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1700 pcie_gen = 1; 1701 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1702 pcie_gen = 0; 1703 1704 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1705 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1706 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1707 */ 1708 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1709 pcie_width = 7; 1710 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1711 pcie_width = 6; 1712 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1713 pcie_width = 5; 1714 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1715 pcie_width = 4; 1716 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1717 pcie_width = 3; 1718 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1719 pcie_width = 2; 1720 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1721 pcie_width = 1; 1722 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1723 if (ret) { 1724 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1725 return ret; 1726 } 1727 1728 ret = smu_get_thermal_temperature_range(smu); 1729 if (ret) { 1730 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1731 return ret; 1732 } 1733 1734 ret = smu_enable_thermal_alert(smu); 1735 if (ret) { 1736 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1737 return ret; 1738 } 1739 1740 ret = smu_notify_display_change(smu); 1741 if (ret) { 1742 dev_err(adev->dev, "Failed to notify display change!\n"); 1743 return ret; 1744 } 1745 1746 /* 1747 * Set min deep sleep dce fclk with bootup value from vbios via 1748 * SetMinDeepSleepDcefclk MSG. 1749 */ 1750 ret = smu_set_min_dcef_deep_sleep(smu, 1751 smu->smu_table.boot_values.dcefclk / 100); 1752 if (ret) { 1753 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1754 return ret; 1755 } 1756 1757 /* Init wbrf support. Properly setup the notifier */ 1758 ret = smu_wbrf_init(smu); 1759 if (ret) 1760 dev_err(adev->dev, "Error during wbrf init call\n"); 1761 1762 return ret; 1763 } 1764 1765 static int smu_start_smc_engine(struct smu_context *smu) 1766 { 1767 struct amdgpu_device *adev = smu->adev; 1768 int ret = 0; 1769 1770 smu->smc_fw_state = SMU_FW_INIT; 1771 1772 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1773 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1774 if (smu->ppt_funcs->load_microcode) { 1775 ret = smu->ppt_funcs->load_microcode(smu); 1776 if (ret) 1777 return ret; 1778 } 1779 } 1780 } 1781 1782 if (smu->ppt_funcs->check_fw_status) { 1783 ret = smu->ppt_funcs->check_fw_status(smu); 1784 if (ret) { 1785 dev_err(adev->dev, "SMC is not ready\n"); 1786 return ret; 1787 } 1788 } 1789 1790 /* 1791 * Send msg GetDriverIfVersion to check if the return value is equal 1792 * with DRIVER_IF_VERSION of smc header. 1793 */ 1794 ret = smu_check_fw_version(smu); 1795 if (ret) 1796 return ret; 1797 1798 return ret; 1799 } 1800 1801 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1802 { 1803 int ret; 1804 struct amdgpu_device *adev = ip_block->adev; 1805 struct smu_context *smu = adev->powerplay.pp_handle; 1806 1807 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1808 smu->pm_enabled = false; 1809 return 0; 1810 } 1811 1812 ret = smu_start_smc_engine(smu); 1813 if (ret) { 1814 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1815 return ret; 1816 } 1817 1818 /* 1819 * Check whether wbrf is supported. This needs to be done 1820 * before SMU setup starts since part of SMU configuration 1821 * relies on this. 1822 */ 1823 smu_wbrf_support_check(smu); 1824 1825 if (smu->is_apu) { 1826 ret = smu_set_gfx_imu_enable(smu); 1827 if (ret) 1828 return ret; 1829 smu_dpm_set_vcn_enable(smu, true); 1830 smu_dpm_set_jpeg_enable(smu, true); 1831 smu_dpm_set_vpe_enable(smu, true); 1832 smu_dpm_set_umsch_mm_enable(smu, true); 1833 smu_set_mall_enable(smu); 1834 smu_set_gfx_cgpg(smu, true); 1835 } 1836 1837 if (!smu->pm_enabled) 1838 return 0; 1839 1840 ret = smu_get_driver_allowed_feature_mask(smu); 1841 if (ret) 1842 return ret; 1843 1844 ret = smu_smc_hw_setup(smu); 1845 if (ret) { 1846 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1847 return ret; 1848 } 1849 1850 /* 1851 * Move maximum sustainable clock retrieving here considering 1852 * 1. It is not needed on resume(from S3). 1853 * 2. DAL settings come between .hw_init and .late_init of SMU. 1854 * And DAL needs to know the maximum sustainable clocks. Thus 1855 * it cannot be put in .late_init(). 1856 */ 1857 ret = smu_init_max_sustainable_clocks(smu); 1858 if (ret) { 1859 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1860 return ret; 1861 } 1862 1863 adev->pm.dpm_enabled = true; 1864 1865 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1866 1867 return 0; 1868 } 1869 1870 static int smu_disable_dpms(struct smu_context *smu) 1871 { 1872 struct amdgpu_device *adev = smu->adev; 1873 int ret = 0; 1874 bool use_baco = !smu->is_apu && 1875 ((amdgpu_in_reset(adev) && 1876 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1877 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1878 1879 /* 1880 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1881 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1882 */ 1883 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1884 case IP_VERSION(13, 0, 0): 1885 case IP_VERSION(13, 0, 7): 1886 case IP_VERSION(13, 0, 10): 1887 case IP_VERSION(14, 0, 2): 1888 case IP_VERSION(14, 0, 3): 1889 return 0; 1890 default: 1891 break; 1892 } 1893 1894 /* 1895 * For custom pptable uploading, skip the DPM features 1896 * disable process on Navi1x ASICs. 1897 * - As the gfx related features are under control of 1898 * RLC on those ASICs. RLC reinitialization will be 1899 * needed to reenable them. That will cost much more 1900 * efforts. 1901 * 1902 * - SMU firmware can handle the DPM reenablement 1903 * properly. 1904 */ 1905 if (smu->uploading_custom_pp_table) { 1906 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1907 case IP_VERSION(11, 0, 0): 1908 case IP_VERSION(11, 0, 5): 1909 case IP_VERSION(11, 0, 9): 1910 case IP_VERSION(11, 0, 7): 1911 case IP_VERSION(11, 0, 11): 1912 case IP_VERSION(11, 5, 0): 1913 case IP_VERSION(11, 0, 12): 1914 case IP_VERSION(11, 0, 13): 1915 return 0; 1916 default: 1917 break; 1918 } 1919 } 1920 1921 /* 1922 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1923 * on BACO in. Driver involvement is unnecessary. 1924 */ 1925 if (use_baco) { 1926 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1927 case IP_VERSION(11, 0, 7): 1928 case IP_VERSION(11, 0, 0): 1929 case IP_VERSION(11, 0, 5): 1930 case IP_VERSION(11, 0, 9): 1931 case IP_VERSION(13, 0, 7): 1932 return 0; 1933 default: 1934 break; 1935 } 1936 } 1937 1938 /* 1939 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 1940 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1941 */ 1942 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 1943 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 1944 return 0; 1945 1946 /* 1947 * For gpu reset, runpm and hibernation through BACO, 1948 * BACO feature has to be kept enabled. 1949 */ 1950 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1951 ret = smu_disable_all_features_with_exception(smu, 1952 SMU_FEATURE_BACO_BIT); 1953 if (ret) 1954 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1955 } else { 1956 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1957 if (!adev->scpm_enabled) { 1958 ret = smu_system_features_control(smu, false); 1959 if (ret) 1960 dev_err(adev->dev, "Failed to disable smu features.\n"); 1961 } 1962 } 1963 1964 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1965 * otherwise SMU will hang while interacting with RLC if RLC is halted 1966 * this is a WA for Vangogh asic which fix the SMU hang issue. 1967 */ 1968 ret = smu_notify_rlc_state(smu, false); 1969 if (ret) { 1970 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1971 return ret; 1972 } 1973 1974 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1975 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1976 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1977 adev->gfx.rlc.funcs->stop(adev); 1978 1979 return ret; 1980 } 1981 1982 static int smu_smc_hw_cleanup(struct smu_context *smu) 1983 { 1984 struct amdgpu_device *adev = smu->adev; 1985 int ret = 0; 1986 1987 smu_wbrf_fini(smu); 1988 1989 cancel_work_sync(&smu->throttling_logging_work); 1990 cancel_work_sync(&smu->interrupt_work); 1991 1992 ret = smu_disable_thermal_alert(smu); 1993 if (ret) { 1994 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1995 return ret; 1996 } 1997 1998 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1999 2000 ret = smu_disable_dpms(smu); 2001 if (ret) { 2002 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2003 return ret; 2004 } 2005 2006 return 0; 2007 } 2008 2009 static int smu_reset_mp1_state(struct smu_context *smu) 2010 { 2011 struct amdgpu_device *adev = smu->adev; 2012 int ret = 0; 2013 2014 if ((!adev->in_runpm) && (!adev->in_suspend) && 2015 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2016 IP_VERSION(13, 0, 10) && 2017 !amdgpu_device_has_display_hardware(adev)) 2018 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2019 2020 return ret; 2021 } 2022 2023 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2024 { 2025 struct amdgpu_device *adev = ip_block->adev; 2026 struct smu_context *smu = adev->powerplay.pp_handle; 2027 int ret; 2028 2029 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2030 return 0; 2031 2032 smu_dpm_set_vcn_enable(smu, false); 2033 smu_dpm_set_jpeg_enable(smu, false); 2034 smu_dpm_set_vpe_enable(smu, false); 2035 smu_dpm_set_umsch_mm_enable(smu, false); 2036 2037 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2038 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2039 2040 if (!smu->pm_enabled) 2041 return 0; 2042 2043 adev->pm.dpm_enabled = false; 2044 2045 ret = smu_smc_hw_cleanup(smu); 2046 if (ret) 2047 return ret; 2048 2049 ret = smu_reset_mp1_state(smu); 2050 if (ret) 2051 return ret; 2052 2053 return 0; 2054 } 2055 2056 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2057 { 2058 struct amdgpu_device *adev = ip_block->adev; 2059 struct smu_context *smu = adev->powerplay.pp_handle; 2060 2061 kfree(smu); 2062 } 2063 2064 static int smu_reset(struct smu_context *smu) 2065 { 2066 struct amdgpu_device *adev = smu->adev; 2067 struct amdgpu_ip_block *ip_block; 2068 int ret; 2069 2070 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2071 if (!ip_block) 2072 return -EINVAL; 2073 2074 ret = smu_hw_fini(ip_block); 2075 if (ret) 2076 return ret; 2077 2078 ret = smu_hw_init(ip_block); 2079 if (ret) 2080 return ret; 2081 2082 ret = smu_late_init(ip_block); 2083 if (ret) 2084 return ret; 2085 2086 return 0; 2087 } 2088 2089 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2090 { 2091 struct amdgpu_device *adev = ip_block->adev; 2092 struct smu_context *smu = adev->powerplay.pp_handle; 2093 int ret; 2094 uint64_t count; 2095 2096 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2097 return 0; 2098 2099 if (!smu->pm_enabled) 2100 return 0; 2101 2102 adev->pm.dpm_enabled = false; 2103 2104 ret = smu_smc_hw_cleanup(smu); 2105 if (ret) 2106 return ret; 2107 2108 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2109 2110 smu_set_gfx_cgpg(smu, false); 2111 2112 /* 2113 * pwfw resets entrycount when device is suspended, so we save the 2114 * last value to be used when we resume to keep it consistent 2115 */ 2116 ret = smu_get_entrycount_gfxoff(smu, &count); 2117 if (!ret) 2118 adev->gfx.gfx_off_entrycount = count; 2119 2120 /* clear this on suspend so it will get reprogrammed on resume */ 2121 smu->workload_mask = 0; 2122 2123 return 0; 2124 } 2125 2126 static int smu_resume(struct amdgpu_ip_block *ip_block) 2127 { 2128 int ret; 2129 struct amdgpu_device *adev = ip_block->adev; 2130 struct smu_context *smu = adev->powerplay.pp_handle; 2131 2132 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2133 return 0; 2134 2135 if (!smu->pm_enabled) 2136 return 0; 2137 2138 dev_info(adev->dev, "SMU is resuming...\n"); 2139 2140 ret = smu_start_smc_engine(smu); 2141 if (ret) { 2142 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2143 return ret; 2144 } 2145 2146 ret = smu_smc_hw_setup(smu); 2147 if (ret) { 2148 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2149 return ret; 2150 } 2151 2152 ret = smu_set_gfx_imu_enable(smu); 2153 if (ret) 2154 return ret; 2155 2156 smu_set_gfx_cgpg(smu, true); 2157 2158 smu->disable_uclk_switch = 0; 2159 2160 adev->pm.dpm_enabled = true; 2161 2162 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2163 2164 return 0; 2165 } 2166 2167 static int smu_display_configuration_change(void *handle, 2168 const struct amd_pp_display_configuration *display_config) 2169 { 2170 struct smu_context *smu = handle; 2171 2172 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2173 return -EOPNOTSUPP; 2174 2175 if (!display_config) 2176 return -EINVAL; 2177 2178 smu_set_min_dcef_deep_sleep(smu, 2179 display_config->min_dcef_deep_sleep_set_clk / 100); 2180 2181 return 0; 2182 } 2183 2184 static int smu_set_clockgating_state(void *handle, 2185 enum amd_clockgating_state state) 2186 { 2187 return 0; 2188 } 2189 2190 static int smu_set_powergating_state(void *handle, 2191 enum amd_powergating_state state) 2192 { 2193 return 0; 2194 } 2195 2196 static int smu_enable_umd_pstate(void *handle, 2197 enum amd_dpm_forced_level *level) 2198 { 2199 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2200 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2201 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2202 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2203 2204 struct smu_context *smu = (struct smu_context*)(handle); 2205 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2206 2207 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2208 return -EINVAL; 2209 2210 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2211 /* enter umd pstate, save current level, disable gfx cg*/ 2212 if (*level & profile_mode_mask) { 2213 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2214 smu_gpo_control(smu, false); 2215 smu_gfx_ulv_control(smu, false); 2216 smu_deep_sleep_control(smu, false); 2217 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2218 } 2219 } else { 2220 /* exit umd pstate, restore level, enable gfx cg*/ 2221 if (!(*level & profile_mode_mask)) { 2222 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2223 *level = smu_dpm_ctx->saved_dpm_level; 2224 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2225 smu_deep_sleep_control(smu, true); 2226 smu_gfx_ulv_control(smu, true); 2227 smu_gpo_control(smu, true); 2228 } 2229 } 2230 2231 return 0; 2232 } 2233 2234 static int smu_bump_power_profile_mode(struct smu_context *smu, 2235 long *custom_params, 2236 u32 custom_params_max_idx) 2237 { 2238 u32 workload_mask = 0; 2239 int i, ret = 0; 2240 2241 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2242 if (smu->workload_refcount[i]) 2243 workload_mask |= 1 << i; 2244 } 2245 2246 if (smu->workload_mask == workload_mask) 2247 return 0; 2248 2249 if (smu->ppt_funcs->set_power_profile_mode) 2250 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2251 custom_params, 2252 custom_params_max_idx); 2253 2254 if (!ret) 2255 smu->workload_mask = workload_mask; 2256 2257 return ret; 2258 } 2259 2260 static void smu_power_profile_mode_get(struct smu_context *smu, 2261 enum PP_SMC_POWER_PROFILE profile_mode) 2262 { 2263 smu->workload_refcount[profile_mode]++; 2264 } 2265 2266 static void smu_power_profile_mode_put(struct smu_context *smu, 2267 enum PP_SMC_POWER_PROFILE profile_mode) 2268 { 2269 if (smu->workload_refcount[profile_mode]) 2270 smu->workload_refcount[profile_mode]--; 2271 } 2272 2273 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2274 enum amd_dpm_forced_level level, 2275 bool skip_display_settings) 2276 { 2277 int ret = 0; 2278 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2279 2280 if (!skip_display_settings) { 2281 ret = smu_display_config_changed(smu); 2282 if (ret) { 2283 dev_err(smu->adev->dev, "Failed to change display config!"); 2284 return ret; 2285 } 2286 } 2287 2288 ret = smu_apply_clocks_adjust_rules(smu); 2289 if (ret) { 2290 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2291 return ret; 2292 } 2293 2294 if (!skip_display_settings) { 2295 ret = smu_notify_smc_display_config(smu); 2296 if (ret) { 2297 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2298 return ret; 2299 } 2300 } 2301 2302 if (smu_dpm_ctx->dpm_level != level) { 2303 ret = smu_asic_set_performance_level(smu, level); 2304 if (ret) { 2305 dev_err(smu->adev->dev, "Failed to set performance level!"); 2306 return ret; 2307 } 2308 2309 /* update the saved copy */ 2310 smu_dpm_ctx->dpm_level = level; 2311 } 2312 2313 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2314 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2315 smu_bump_power_profile_mode(smu, NULL, 0); 2316 2317 return ret; 2318 } 2319 2320 static int smu_handle_task(struct smu_context *smu, 2321 enum amd_dpm_forced_level level, 2322 enum amd_pp_task task_id) 2323 { 2324 int ret = 0; 2325 2326 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2327 return -EOPNOTSUPP; 2328 2329 switch (task_id) { 2330 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2331 ret = smu_pre_display_config_changed(smu); 2332 if (ret) 2333 return ret; 2334 ret = smu_adjust_power_state_dynamic(smu, level, false); 2335 break; 2336 case AMD_PP_TASK_COMPLETE_INIT: 2337 ret = smu_adjust_power_state_dynamic(smu, level, true); 2338 break; 2339 case AMD_PP_TASK_READJUST_POWER_STATE: 2340 ret = smu_adjust_power_state_dynamic(smu, level, true); 2341 break; 2342 default: 2343 break; 2344 } 2345 2346 return ret; 2347 } 2348 2349 static int smu_handle_dpm_task(void *handle, 2350 enum amd_pp_task task_id, 2351 enum amd_pm_state_type *user_state) 2352 { 2353 struct smu_context *smu = handle; 2354 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2355 2356 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2357 2358 } 2359 2360 static int smu_switch_power_profile(void *handle, 2361 enum PP_SMC_POWER_PROFILE type, 2362 bool enable) 2363 { 2364 struct smu_context *smu = handle; 2365 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2366 int ret; 2367 2368 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2369 return -EOPNOTSUPP; 2370 2371 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2372 return -EINVAL; 2373 2374 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2375 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2376 if (enable) 2377 smu_power_profile_mode_get(smu, type); 2378 else 2379 smu_power_profile_mode_put(smu, type); 2380 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2381 if (ret) { 2382 if (enable) 2383 smu_power_profile_mode_put(smu, type); 2384 else 2385 smu_power_profile_mode_get(smu, type); 2386 return ret; 2387 } 2388 } 2389 2390 return 0; 2391 } 2392 2393 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2394 { 2395 struct smu_context *smu = handle; 2396 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2397 2398 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2399 return -EOPNOTSUPP; 2400 2401 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2402 return -EINVAL; 2403 2404 return smu_dpm_ctx->dpm_level; 2405 } 2406 2407 static int smu_force_performance_level(void *handle, 2408 enum amd_dpm_forced_level level) 2409 { 2410 struct smu_context *smu = handle; 2411 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2412 int ret = 0; 2413 2414 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2415 return -EOPNOTSUPP; 2416 2417 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2418 return -EINVAL; 2419 2420 ret = smu_enable_umd_pstate(smu, &level); 2421 if (ret) 2422 return ret; 2423 2424 ret = smu_handle_task(smu, level, 2425 AMD_PP_TASK_READJUST_POWER_STATE); 2426 2427 /* reset user dpm clock state */ 2428 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2429 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2430 smu->user_dpm_profile.clk_dependency = 0; 2431 } 2432 2433 return ret; 2434 } 2435 2436 static int smu_set_display_count(void *handle, uint32_t count) 2437 { 2438 struct smu_context *smu = handle; 2439 2440 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2441 return -EOPNOTSUPP; 2442 2443 return smu_init_display_count(smu, count); 2444 } 2445 2446 static int smu_force_smuclk_levels(struct smu_context *smu, 2447 enum smu_clk_type clk_type, 2448 uint32_t mask) 2449 { 2450 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2451 int ret = 0; 2452 2453 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2454 return -EOPNOTSUPP; 2455 2456 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2457 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2458 return -EINVAL; 2459 } 2460 2461 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2462 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2463 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2464 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2465 smu_set_user_clk_dependencies(smu, clk_type); 2466 } 2467 } 2468 2469 return ret; 2470 } 2471 2472 static int smu_force_ppclk_levels(void *handle, 2473 enum pp_clock_type type, 2474 uint32_t mask) 2475 { 2476 struct smu_context *smu = handle; 2477 enum smu_clk_type clk_type; 2478 2479 switch (type) { 2480 case PP_SCLK: 2481 clk_type = SMU_SCLK; break; 2482 case PP_MCLK: 2483 clk_type = SMU_MCLK; break; 2484 case PP_PCIE: 2485 clk_type = SMU_PCIE; break; 2486 case PP_SOCCLK: 2487 clk_type = SMU_SOCCLK; break; 2488 case PP_FCLK: 2489 clk_type = SMU_FCLK; break; 2490 case PP_DCEFCLK: 2491 clk_type = SMU_DCEFCLK; break; 2492 case PP_VCLK: 2493 clk_type = SMU_VCLK; break; 2494 case PP_VCLK1: 2495 clk_type = SMU_VCLK1; break; 2496 case PP_DCLK: 2497 clk_type = SMU_DCLK; break; 2498 case PP_DCLK1: 2499 clk_type = SMU_DCLK1; break; 2500 case OD_SCLK: 2501 clk_type = SMU_OD_SCLK; break; 2502 case OD_MCLK: 2503 clk_type = SMU_OD_MCLK; break; 2504 case OD_VDDC_CURVE: 2505 clk_type = SMU_OD_VDDC_CURVE; break; 2506 case OD_RANGE: 2507 clk_type = SMU_OD_RANGE; break; 2508 default: 2509 return -EINVAL; 2510 } 2511 2512 return smu_force_smuclk_levels(smu, clk_type, mask); 2513 } 2514 2515 /* 2516 * On system suspending or resetting, the dpm_enabled 2517 * flag will be cleared. So that those SMU services which 2518 * are not supported will be gated. 2519 * However, the mp1 state setting should still be granted 2520 * even if the dpm_enabled cleared. 2521 */ 2522 static int smu_set_mp1_state(void *handle, 2523 enum pp_mp1_state mp1_state) 2524 { 2525 struct smu_context *smu = handle; 2526 int ret = 0; 2527 2528 if (!smu->pm_enabled) 2529 return -EOPNOTSUPP; 2530 2531 if (smu->ppt_funcs && 2532 smu->ppt_funcs->set_mp1_state) 2533 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2534 2535 return ret; 2536 } 2537 2538 static int smu_set_df_cstate(void *handle, 2539 enum pp_df_cstate state) 2540 { 2541 struct smu_context *smu = handle; 2542 int ret = 0; 2543 2544 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2545 return -EOPNOTSUPP; 2546 2547 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2548 return 0; 2549 2550 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2551 if (ret) 2552 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2553 2554 return ret; 2555 } 2556 2557 int smu_write_watermarks_table(struct smu_context *smu) 2558 { 2559 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2560 return -EOPNOTSUPP; 2561 2562 return smu_set_watermarks_table(smu, NULL); 2563 } 2564 2565 static int smu_set_watermarks_for_clock_ranges(void *handle, 2566 struct pp_smu_wm_range_sets *clock_ranges) 2567 { 2568 struct smu_context *smu = handle; 2569 2570 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2571 return -EOPNOTSUPP; 2572 2573 if (smu->disable_watermark) 2574 return 0; 2575 2576 return smu_set_watermarks_table(smu, clock_ranges); 2577 } 2578 2579 int smu_set_ac_dc(struct smu_context *smu) 2580 { 2581 int ret = 0; 2582 2583 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2584 return -EOPNOTSUPP; 2585 2586 /* controlled by firmware */ 2587 if (smu->dc_controlled_by_gpio) 2588 return 0; 2589 2590 ret = smu_set_power_source(smu, 2591 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2592 SMU_POWER_SOURCE_DC); 2593 if (ret) 2594 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2595 smu->adev->pm.ac_power ? "AC" : "DC"); 2596 2597 return ret; 2598 } 2599 2600 const struct amd_ip_funcs smu_ip_funcs = { 2601 .name = "smu", 2602 .early_init = smu_early_init, 2603 .late_init = smu_late_init, 2604 .sw_init = smu_sw_init, 2605 .sw_fini = smu_sw_fini, 2606 .hw_init = smu_hw_init, 2607 .hw_fini = smu_hw_fini, 2608 .late_fini = smu_late_fini, 2609 .suspend = smu_suspend, 2610 .resume = smu_resume, 2611 .is_idle = NULL, 2612 .check_soft_reset = NULL, 2613 .wait_for_idle = NULL, 2614 .soft_reset = NULL, 2615 .set_clockgating_state = smu_set_clockgating_state, 2616 .set_powergating_state = smu_set_powergating_state, 2617 }; 2618 2619 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2620 .type = AMD_IP_BLOCK_TYPE_SMC, 2621 .major = 11, 2622 .minor = 0, 2623 .rev = 0, 2624 .funcs = &smu_ip_funcs, 2625 }; 2626 2627 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2628 .type = AMD_IP_BLOCK_TYPE_SMC, 2629 .major = 12, 2630 .minor = 0, 2631 .rev = 0, 2632 .funcs = &smu_ip_funcs, 2633 }; 2634 2635 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2636 .type = AMD_IP_BLOCK_TYPE_SMC, 2637 .major = 13, 2638 .minor = 0, 2639 .rev = 0, 2640 .funcs = &smu_ip_funcs, 2641 }; 2642 2643 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2644 .type = AMD_IP_BLOCK_TYPE_SMC, 2645 .major = 14, 2646 .minor = 0, 2647 .rev = 0, 2648 .funcs = &smu_ip_funcs, 2649 }; 2650 2651 static int smu_load_microcode(void *handle) 2652 { 2653 struct smu_context *smu = handle; 2654 struct amdgpu_device *adev = smu->adev; 2655 int ret = 0; 2656 2657 if (!smu->pm_enabled) 2658 return -EOPNOTSUPP; 2659 2660 /* This should be used for non PSP loading */ 2661 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2662 return 0; 2663 2664 if (smu->ppt_funcs->load_microcode) { 2665 ret = smu->ppt_funcs->load_microcode(smu); 2666 if (ret) { 2667 dev_err(adev->dev, "Load microcode failed\n"); 2668 return ret; 2669 } 2670 } 2671 2672 if (smu->ppt_funcs->check_fw_status) { 2673 ret = smu->ppt_funcs->check_fw_status(smu); 2674 if (ret) { 2675 dev_err(adev->dev, "SMC is not ready\n"); 2676 return ret; 2677 } 2678 } 2679 2680 return ret; 2681 } 2682 2683 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2684 { 2685 int ret = 0; 2686 2687 if (smu->ppt_funcs->set_gfx_cgpg) 2688 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2689 2690 return ret; 2691 } 2692 2693 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2694 { 2695 struct smu_context *smu = handle; 2696 int ret = 0; 2697 2698 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2699 return -EOPNOTSUPP; 2700 2701 if (!smu->ppt_funcs->set_fan_speed_rpm) 2702 return -EOPNOTSUPP; 2703 2704 if (speed == U32_MAX) 2705 return -EINVAL; 2706 2707 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2708 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2709 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2710 smu->user_dpm_profile.fan_speed_rpm = speed; 2711 2712 /* Override custom PWM setting as they cannot co-exist */ 2713 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2714 smu->user_dpm_profile.fan_speed_pwm = 0; 2715 } 2716 2717 return ret; 2718 } 2719 2720 /** 2721 * smu_get_power_limit - Request one of the SMU Power Limits 2722 * 2723 * @handle: pointer to smu context 2724 * @limit: requested limit is written back to this variable 2725 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2726 * @pp_power_type: &pp_power_type type of power 2727 * Return: 0 on success, <0 on error 2728 * 2729 */ 2730 int smu_get_power_limit(void *handle, 2731 uint32_t *limit, 2732 enum pp_power_limit_level pp_limit_level, 2733 enum pp_power_type pp_power_type) 2734 { 2735 struct smu_context *smu = handle; 2736 struct amdgpu_device *adev = smu->adev; 2737 enum smu_ppt_limit_level limit_level; 2738 uint32_t limit_type; 2739 int ret = 0; 2740 2741 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2742 return -EOPNOTSUPP; 2743 2744 switch (pp_power_type) { 2745 case PP_PWR_TYPE_SUSTAINED: 2746 limit_type = SMU_DEFAULT_PPT_LIMIT; 2747 break; 2748 case PP_PWR_TYPE_FAST: 2749 limit_type = SMU_FAST_PPT_LIMIT; 2750 break; 2751 default: 2752 return -EOPNOTSUPP; 2753 } 2754 2755 switch (pp_limit_level) { 2756 case PP_PWR_LIMIT_CURRENT: 2757 limit_level = SMU_PPT_LIMIT_CURRENT; 2758 break; 2759 case PP_PWR_LIMIT_DEFAULT: 2760 limit_level = SMU_PPT_LIMIT_DEFAULT; 2761 break; 2762 case PP_PWR_LIMIT_MAX: 2763 limit_level = SMU_PPT_LIMIT_MAX; 2764 break; 2765 case PP_PWR_LIMIT_MIN: 2766 limit_level = SMU_PPT_LIMIT_MIN; 2767 break; 2768 default: 2769 return -EOPNOTSUPP; 2770 } 2771 2772 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2773 if (smu->ppt_funcs->get_ppt_limit) 2774 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2775 } else { 2776 switch (limit_level) { 2777 case SMU_PPT_LIMIT_CURRENT: 2778 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2779 case IP_VERSION(13, 0, 2): 2780 case IP_VERSION(13, 0, 6): 2781 case IP_VERSION(13, 0, 14): 2782 case IP_VERSION(11, 0, 7): 2783 case IP_VERSION(11, 0, 11): 2784 case IP_VERSION(11, 0, 12): 2785 case IP_VERSION(11, 0, 13): 2786 ret = smu_get_asic_power_limits(smu, 2787 &smu->current_power_limit, 2788 NULL, NULL, NULL); 2789 break; 2790 default: 2791 break; 2792 } 2793 *limit = smu->current_power_limit; 2794 break; 2795 case SMU_PPT_LIMIT_DEFAULT: 2796 *limit = smu->default_power_limit; 2797 break; 2798 case SMU_PPT_LIMIT_MAX: 2799 *limit = smu->max_power_limit; 2800 break; 2801 case SMU_PPT_LIMIT_MIN: 2802 *limit = smu->min_power_limit; 2803 break; 2804 default: 2805 return -EINVAL; 2806 } 2807 } 2808 2809 return ret; 2810 } 2811 2812 static int smu_set_power_limit(void *handle, uint32_t limit) 2813 { 2814 struct smu_context *smu = handle; 2815 uint32_t limit_type = limit >> 24; 2816 int ret = 0; 2817 2818 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2819 return -EOPNOTSUPP; 2820 2821 limit &= (1<<24)-1; 2822 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2823 if (smu->ppt_funcs->set_power_limit) 2824 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2825 2826 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2827 dev_err(smu->adev->dev, 2828 "New power limit (%d) is out of range [%d,%d]\n", 2829 limit, smu->min_power_limit, smu->max_power_limit); 2830 return -EINVAL; 2831 } 2832 2833 if (!limit) 2834 limit = smu->current_power_limit; 2835 2836 if (smu->ppt_funcs->set_power_limit) { 2837 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2838 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2839 smu->user_dpm_profile.power_limit = limit; 2840 } 2841 2842 return ret; 2843 } 2844 2845 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2846 { 2847 int ret = 0; 2848 2849 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2850 return -EOPNOTSUPP; 2851 2852 if (smu->ppt_funcs->print_clk_levels) 2853 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2854 2855 return ret; 2856 } 2857 2858 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2859 { 2860 enum smu_clk_type clk_type; 2861 2862 switch (type) { 2863 case PP_SCLK: 2864 clk_type = SMU_SCLK; break; 2865 case PP_MCLK: 2866 clk_type = SMU_MCLK; break; 2867 case PP_PCIE: 2868 clk_type = SMU_PCIE; break; 2869 case PP_SOCCLK: 2870 clk_type = SMU_SOCCLK; break; 2871 case PP_FCLK: 2872 clk_type = SMU_FCLK; break; 2873 case PP_DCEFCLK: 2874 clk_type = SMU_DCEFCLK; break; 2875 case PP_VCLK: 2876 clk_type = SMU_VCLK; break; 2877 case PP_VCLK1: 2878 clk_type = SMU_VCLK1; break; 2879 case PP_DCLK: 2880 clk_type = SMU_DCLK; break; 2881 case PP_DCLK1: 2882 clk_type = SMU_DCLK1; break; 2883 case OD_SCLK: 2884 clk_type = SMU_OD_SCLK; break; 2885 case OD_MCLK: 2886 clk_type = SMU_OD_MCLK; break; 2887 case OD_VDDC_CURVE: 2888 clk_type = SMU_OD_VDDC_CURVE; break; 2889 case OD_RANGE: 2890 clk_type = SMU_OD_RANGE; break; 2891 case OD_VDDGFX_OFFSET: 2892 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2893 case OD_CCLK: 2894 clk_type = SMU_OD_CCLK; break; 2895 case OD_FAN_CURVE: 2896 clk_type = SMU_OD_FAN_CURVE; break; 2897 case OD_ACOUSTIC_LIMIT: 2898 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2899 case OD_ACOUSTIC_TARGET: 2900 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2901 case OD_FAN_TARGET_TEMPERATURE: 2902 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2903 case OD_FAN_MINIMUM_PWM: 2904 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2905 case OD_FAN_ZERO_RPM_ENABLE: 2906 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 2907 case OD_FAN_ZERO_RPM_STOP_TEMP: 2908 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 2909 default: 2910 clk_type = SMU_CLK_COUNT; break; 2911 } 2912 2913 return clk_type; 2914 } 2915 2916 static int smu_print_ppclk_levels(void *handle, 2917 enum pp_clock_type type, 2918 char *buf) 2919 { 2920 struct smu_context *smu = handle; 2921 enum smu_clk_type clk_type; 2922 2923 clk_type = smu_convert_to_smuclk(type); 2924 if (clk_type == SMU_CLK_COUNT) 2925 return -EINVAL; 2926 2927 return smu_print_smuclk_levels(smu, clk_type, buf); 2928 } 2929 2930 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2931 { 2932 struct smu_context *smu = handle; 2933 enum smu_clk_type clk_type; 2934 2935 clk_type = smu_convert_to_smuclk(type); 2936 if (clk_type == SMU_CLK_COUNT) 2937 return -EINVAL; 2938 2939 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2940 return -EOPNOTSUPP; 2941 2942 if (!smu->ppt_funcs->emit_clk_levels) 2943 return -ENOENT; 2944 2945 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2946 2947 } 2948 2949 static int smu_od_edit_dpm_table(void *handle, 2950 enum PP_OD_DPM_TABLE_COMMAND type, 2951 long *input, uint32_t size) 2952 { 2953 struct smu_context *smu = handle; 2954 int ret = 0; 2955 2956 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2957 return -EOPNOTSUPP; 2958 2959 if (smu->ppt_funcs->od_edit_dpm_table) { 2960 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2961 } 2962 2963 return ret; 2964 } 2965 2966 static int smu_read_sensor(void *handle, 2967 int sensor, 2968 void *data, 2969 int *size_arg) 2970 { 2971 struct smu_context *smu = handle; 2972 struct smu_umd_pstate_table *pstate_table = 2973 &smu->pstate_table; 2974 int ret = 0; 2975 uint32_t *size, size_val; 2976 2977 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2978 return -EOPNOTSUPP; 2979 2980 if (!data || !size_arg) 2981 return -EINVAL; 2982 2983 size_val = *size_arg; 2984 size = &size_val; 2985 2986 if (smu->ppt_funcs->read_sensor) 2987 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2988 goto unlock; 2989 2990 switch (sensor) { 2991 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2992 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2993 *size = 4; 2994 break; 2995 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2996 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2997 *size = 4; 2998 break; 2999 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3000 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3001 *size = 4; 3002 break; 3003 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3004 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3005 *size = 4; 3006 break; 3007 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3008 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 3009 *size = 8; 3010 break; 3011 case AMDGPU_PP_SENSOR_UVD_POWER: 3012 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3013 *size = 4; 3014 break; 3015 case AMDGPU_PP_SENSOR_VCE_POWER: 3016 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3017 *size = 4; 3018 break; 3019 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3020 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 3021 *size = 4; 3022 break; 3023 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3024 *(uint32_t *)data = 0; 3025 *size = 4; 3026 break; 3027 default: 3028 *size = 0; 3029 ret = -EOPNOTSUPP; 3030 break; 3031 } 3032 3033 unlock: 3034 // assign uint32_t to int 3035 *size_arg = size_val; 3036 3037 return ret; 3038 } 3039 3040 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3041 { 3042 int ret = -EOPNOTSUPP; 3043 struct smu_context *smu = handle; 3044 3045 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3046 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3047 3048 return ret; 3049 } 3050 3051 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3052 { 3053 int ret = -EOPNOTSUPP; 3054 struct smu_context *smu = handle; 3055 3056 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3057 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3058 3059 return ret; 3060 } 3061 3062 static int smu_get_power_profile_mode(void *handle, char *buf) 3063 { 3064 struct smu_context *smu = handle; 3065 3066 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3067 !smu->ppt_funcs->get_power_profile_mode) 3068 return -EOPNOTSUPP; 3069 if (!buf) 3070 return -EINVAL; 3071 3072 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3073 } 3074 3075 static int smu_set_power_profile_mode(void *handle, 3076 long *param, 3077 uint32_t param_size) 3078 { 3079 struct smu_context *smu = handle; 3080 bool custom = false; 3081 int ret = 0; 3082 3083 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3084 !smu->ppt_funcs->set_power_profile_mode) 3085 return -EOPNOTSUPP; 3086 3087 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3088 custom = true; 3089 /* clear frontend mask so custom changes propogate */ 3090 smu->workload_mask = 0; 3091 } 3092 3093 if ((param[param_size] != smu->power_profile_mode) || custom) { 3094 /* clear the old user preference */ 3095 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3096 /* set the new user preference */ 3097 smu_power_profile_mode_get(smu, param[param_size]); 3098 ret = smu_bump_power_profile_mode(smu, 3099 custom ? param : NULL, 3100 custom ? param_size : 0); 3101 if (ret) 3102 smu_power_profile_mode_put(smu, param[param_size]); 3103 else 3104 /* store the user's preference */ 3105 smu->power_profile_mode = param[param_size]; 3106 } 3107 3108 return ret; 3109 } 3110 3111 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3112 { 3113 struct smu_context *smu = handle; 3114 3115 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3116 return -EOPNOTSUPP; 3117 3118 if (!smu->ppt_funcs->get_fan_control_mode) 3119 return -EOPNOTSUPP; 3120 3121 if (!fan_mode) 3122 return -EINVAL; 3123 3124 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3125 3126 return 0; 3127 } 3128 3129 static int smu_set_fan_control_mode(void *handle, u32 value) 3130 { 3131 struct smu_context *smu = handle; 3132 int ret = 0; 3133 3134 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3135 return -EOPNOTSUPP; 3136 3137 if (!smu->ppt_funcs->set_fan_control_mode) 3138 return -EOPNOTSUPP; 3139 3140 if (value == U32_MAX) 3141 return -EINVAL; 3142 3143 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3144 if (ret) 3145 goto out; 3146 3147 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3148 smu->user_dpm_profile.fan_mode = value; 3149 3150 /* reset user dpm fan speed */ 3151 if (value != AMD_FAN_CTRL_MANUAL) { 3152 smu->user_dpm_profile.fan_speed_pwm = 0; 3153 smu->user_dpm_profile.fan_speed_rpm = 0; 3154 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3155 } 3156 } 3157 3158 out: 3159 return ret; 3160 } 3161 3162 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3163 { 3164 struct smu_context *smu = handle; 3165 int ret = 0; 3166 3167 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3168 return -EOPNOTSUPP; 3169 3170 if (!smu->ppt_funcs->get_fan_speed_pwm) 3171 return -EOPNOTSUPP; 3172 3173 if (!speed) 3174 return -EINVAL; 3175 3176 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3177 3178 return ret; 3179 } 3180 3181 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3182 { 3183 struct smu_context *smu = handle; 3184 int ret = 0; 3185 3186 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3187 return -EOPNOTSUPP; 3188 3189 if (!smu->ppt_funcs->set_fan_speed_pwm) 3190 return -EOPNOTSUPP; 3191 3192 if (speed == U32_MAX) 3193 return -EINVAL; 3194 3195 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3196 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3197 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3198 smu->user_dpm_profile.fan_speed_pwm = speed; 3199 3200 /* Override custom RPM setting as they cannot co-exist */ 3201 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3202 smu->user_dpm_profile.fan_speed_rpm = 0; 3203 } 3204 3205 return ret; 3206 } 3207 3208 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3209 { 3210 struct smu_context *smu = handle; 3211 int ret = 0; 3212 3213 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3214 return -EOPNOTSUPP; 3215 3216 if (!smu->ppt_funcs->get_fan_speed_rpm) 3217 return -EOPNOTSUPP; 3218 3219 if (!speed) 3220 return -EINVAL; 3221 3222 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3223 3224 return ret; 3225 } 3226 3227 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3228 { 3229 struct smu_context *smu = handle; 3230 3231 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3232 return -EOPNOTSUPP; 3233 3234 return smu_set_min_dcef_deep_sleep(smu, clk); 3235 } 3236 3237 static int smu_get_clock_by_type_with_latency(void *handle, 3238 enum amd_pp_clock_type type, 3239 struct pp_clock_levels_with_latency *clocks) 3240 { 3241 struct smu_context *smu = handle; 3242 enum smu_clk_type clk_type; 3243 int ret = 0; 3244 3245 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3246 return -EOPNOTSUPP; 3247 3248 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3249 switch (type) { 3250 case amd_pp_sys_clock: 3251 clk_type = SMU_GFXCLK; 3252 break; 3253 case amd_pp_mem_clock: 3254 clk_type = SMU_MCLK; 3255 break; 3256 case amd_pp_dcef_clock: 3257 clk_type = SMU_DCEFCLK; 3258 break; 3259 case amd_pp_disp_clock: 3260 clk_type = SMU_DISPCLK; 3261 break; 3262 default: 3263 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3264 return -EINVAL; 3265 } 3266 3267 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3268 } 3269 3270 return ret; 3271 } 3272 3273 static int smu_display_clock_voltage_request(void *handle, 3274 struct pp_display_clock_request *clock_req) 3275 { 3276 struct smu_context *smu = handle; 3277 int ret = 0; 3278 3279 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3280 return -EOPNOTSUPP; 3281 3282 if (smu->ppt_funcs->display_clock_voltage_request) 3283 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3284 3285 return ret; 3286 } 3287 3288 3289 static int smu_display_disable_memory_clock_switch(void *handle, 3290 bool disable_memory_clock_switch) 3291 { 3292 struct smu_context *smu = handle; 3293 int ret = -EINVAL; 3294 3295 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3296 return -EOPNOTSUPP; 3297 3298 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3299 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3300 3301 return ret; 3302 } 3303 3304 static int smu_set_xgmi_pstate(void *handle, 3305 uint32_t pstate) 3306 { 3307 struct smu_context *smu = handle; 3308 int ret = 0; 3309 3310 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3311 return -EOPNOTSUPP; 3312 3313 if (smu->ppt_funcs->set_xgmi_pstate) 3314 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3315 3316 if (ret) 3317 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3318 3319 return ret; 3320 } 3321 3322 static int smu_get_baco_capability(void *handle) 3323 { 3324 struct smu_context *smu = handle; 3325 3326 if (!smu->pm_enabled) 3327 return false; 3328 3329 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3330 return false; 3331 3332 return smu->ppt_funcs->get_bamaco_support(smu); 3333 } 3334 3335 static int smu_baco_set_state(void *handle, int state) 3336 { 3337 struct smu_context *smu = handle; 3338 int ret = 0; 3339 3340 if (!smu->pm_enabled) 3341 return -EOPNOTSUPP; 3342 3343 if (state == 0) { 3344 if (smu->ppt_funcs->baco_exit) 3345 ret = smu->ppt_funcs->baco_exit(smu); 3346 } else if (state == 1) { 3347 if (smu->ppt_funcs->baco_enter) 3348 ret = smu->ppt_funcs->baco_enter(smu); 3349 } else { 3350 return -EINVAL; 3351 } 3352 3353 if (ret) 3354 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3355 (state)?"enter":"exit"); 3356 3357 return ret; 3358 } 3359 3360 bool smu_mode1_reset_is_support(struct smu_context *smu) 3361 { 3362 bool ret = false; 3363 3364 if (!smu->pm_enabled) 3365 return false; 3366 3367 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3368 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3369 3370 return ret; 3371 } 3372 3373 bool smu_mode2_reset_is_support(struct smu_context *smu) 3374 { 3375 bool ret = false; 3376 3377 if (!smu->pm_enabled) 3378 return false; 3379 3380 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3381 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3382 3383 return ret; 3384 } 3385 3386 int smu_mode1_reset(struct smu_context *smu) 3387 { 3388 int ret = 0; 3389 3390 if (!smu->pm_enabled) 3391 return -EOPNOTSUPP; 3392 3393 if (smu->ppt_funcs->mode1_reset) 3394 ret = smu->ppt_funcs->mode1_reset(smu); 3395 3396 return ret; 3397 } 3398 3399 static int smu_mode2_reset(void *handle) 3400 { 3401 struct smu_context *smu = handle; 3402 int ret = 0; 3403 3404 if (!smu->pm_enabled) 3405 return -EOPNOTSUPP; 3406 3407 if (smu->ppt_funcs->mode2_reset) 3408 ret = smu->ppt_funcs->mode2_reset(smu); 3409 3410 if (ret) 3411 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3412 3413 return ret; 3414 } 3415 3416 static int smu_enable_gfx_features(void *handle) 3417 { 3418 struct smu_context *smu = handle; 3419 int ret = 0; 3420 3421 if (!smu->pm_enabled) 3422 return -EOPNOTSUPP; 3423 3424 if (smu->ppt_funcs->enable_gfx_features) 3425 ret = smu->ppt_funcs->enable_gfx_features(smu); 3426 3427 if (ret) 3428 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3429 3430 return ret; 3431 } 3432 3433 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3434 struct pp_smu_nv_clock_table *max_clocks) 3435 { 3436 struct smu_context *smu = handle; 3437 int ret = 0; 3438 3439 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3440 return -EOPNOTSUPP; 3441 3442 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3443 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3444 3445 return ret; 3446 } 3447 3448 static int smu_get_uclk_dpm_states(void *handle, 3449 unsigned int *clock_values_in_khz, 3450 unsigned int *num_states) 3451 { 3452 struct smu_context *smu = handle; 3453 int ret = 0; 3454 3455 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3456 return -EOPNOTSUPP; 3457 3458 if (smu->ppt_funcs->get_uclk_dpm_states) 3459 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3460 3461 return ret; 3462 } 3463 3464 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3465 { 3466 struct smu_context *smu = handle; 3467 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3468 3469 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3470 return -EOPNOTSUPP; 3471 3472 if (smu->ppt_funcs->get_current_power_state) 3473 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3474 3475 return pm_state; 3476 } 3477 3478 static int smu_get_dpm_clock_table(void *handle, 3479 struct dpm_clocks *clock_table) 3480 { 3481 struct smu_context *smu = handle; 3482 int ret = 0; 3483 3484 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3485 return -EOPNOTSUPP; 3486 3487 if (smu->ppt_funcs->get_dpm_clock_table) 3488 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3489 3490 return ret; 3491 } 3492 3493 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3494 { 3495 struct smu_context *smu = handle; 3496 3497 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3498 return -EOPNOTSUPP; 3499 3500 if (!smu->ppt_funcs->get_gpu_metrics) 3501 return -EOPNOTSUPP; 3502 3503 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3504 } 3505 3506 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3507 size_t size) 3508 { 3509 struct smu_context *smu = handle; 3510 3511 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3512 return -EOPNOTSUPP; 3513 3514 if (!smu->ppt_funcs->get_pm_metrics) 3515 return -EOPNOTSUPP; 3516 3517 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3518 } 3519 3520 static int smu_enable_mgpu_fan_boost(void *handle) 3521 { 3522 struct smu_context *smu = handle; 3523 int ret = 0; 3524 3525 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3526 return -EOPNOTSUPP; 3527 3528 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3529 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3530 3531 return ret; 3532 } 3533 3534 static int smu_gfx_state_change_set(void *handle, 3535 uint32_t state) 3536 { 3537 struct smu_context *smu = handle; 3538 int ret = 0; 3539 3540 if (smu->ppt_funcs->gfx_state_change_set) 3541 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3542 3543 return ret; 3544 } 3545 3546 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3547 { 3548 int ret = 0; 3549 3550 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3551 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3552 3553 return ret; 3554 } 3555 3556 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3557 { 3558 int ret = -EOPNOTSUPP; 3559 3560 if (smu->ppt_funcs && 3561 smu->ppt_funcs->get_ecc_info) 3562 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3563 3564 return ret; 3565 3566 } 3567 3568 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3569 { 3570 struct smu_context *smu = handle; 3571 struct smu_table_context *smu_table = &smu->smu_table; 3572 struct smu_table *memory_pool = &smu_table->memory_pool; 3573 3574 if (!addr || !size) 3575 return -EINVAL; 3576 3577 *addr = NULL; 3578 *size = 0; 3579 if (memory_pool->bo) { 3580 *addr = memory_pool->cpu_addr; 3581 *size = memory_pool->size; 3582 } 3583 3584 return 0; 3585 } 3586 3587 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3588 size_t *size) 3589 { 3590 size_t offset = *size; 3591 int level; 3592 3593 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3594 if (level == policy->current_level) 3595 offset += sysfs_emit_at(sysbuf, offset, 3596 "%d : %s*\n", level, 3597 policy->desc->get_desc(policy, level)); 3598 else 3599 offset += sysfs_emit_at(sysbuf, offset, 3600 "%d : %s\n", level, 3601 policy->desc->get_desc(policy, level)); 3602 } 3603 3604 *size = offset; 3605 } 3606 3607 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3608 enum pp_pm_policy p_type, char *sysbuf) 3609 { 3610 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3611 struct smu_dpm_policy_ctxt *policy_ctxt; 3612 struct smu_dpm_policy *dpm_policy; 3613 size_t offset = 0; 3614 3615 policy_ctxt = dpm_ctxt->dpm_policies; 3616 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3617 !policy_ctxt->policy_mask) 3618 return -EOPNOTSUPP; 3619 3620 if (p_type == PP_PM_POLICY_NONE) 3621 return -EINVAL; 3622 3623 dpm_policy = smu_get_pm_policy(smu, p_type); 3624 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3625 return -ENOENT; 3626 3627 if (!sysbuf) 3628 return -EINVAL; 3629 3630 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3631 3632 return offset; 3633 } 3634 3635 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3636 enum pp_pm_policy p_type) 3637 { 3638 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3639 struct smu_dpm_policy_ctxt *policy_ctxt; 3640 int i; 3641 3642 policy_ctxt = dpm_ctxt->dpm_policies; 3643 if (!policy_ctxt) 3644 return NULL; 3645 3646 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3647 if (policy_ctxt->policies[i].policy_type == p_type) 3648 return &policy_ctxt->policies[i]; 3649 } 3650 3651 return NULL; 3652 } 3653 3654 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3655 int level) 3656 { 3657 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3658 struct smu_dpm_policy *dpm_policy = NULL; 3659 struct smu_dpm_policy_ctxt *policy_ctxt; 3660 int ret = -EOPNOTSUPP; 3661 3662 policy_ctxt = dpm_ctxt->dpm_policies; 3663 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3664 !policy_ctxt->policy_mask) 3665 return ret; 3666 3667 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3668 return -EINVAL; 3669 3670 dpm_policy = smu_get_pm_policy(smu, p_type); 3671 3672 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3673 return ret; 3674 3675 if (dpm_policy->current_level == level) 3676 return 0; 3677 3678 ret = dpm_policy->set_policy(smu, level); 3679 3680 if (!ret) 3681 dpm_policy->current_level = level; 3682 3683 return ret; 3684 } 3685 3686 static const struct amd_pm_funcs swsmu_pm_funcs = { 3687 /* export for sysfs */ 3688 .set_fan_control_mode = smu_set_fan_control_mode, 3689 .get_fan_control_mode = smu_get_fan_control_mode, 3690 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3691 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3692 .force_clock_level = smu_force_ppclk_levels, 3693 .print_clock_levels = smu_print_ppclk_levels, 3694 .emit_clock_levels = smu_emit_ppclk_levels, 3695 .force_performance_level = smu_force_performance_level, 3696 .read_sensor = smu_read_sensor, 3697 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3698 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3699 .get_performance_level = smu_get_performance_level, 3700 .get_current_power_state = smu_get_current_power_state, 3701 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3702 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3703 .get_pp_num_states = smu_get_power_num_states, 3704 .get_pp_table = smu_sys_get_pp_table, 3705 .set_pp_table = smu_sys_set_pp_table, 3706 .switch_power_profile = smu_switch_power_profile, 3707 /* export to amdgpu */ 3708 .dispatch_tasks = smu_handle_dpm_task, 3709 .load_firmware = smu_load_microcode, 3710 .set_powergating_by_smu = smu_dpm_set_power_gate, 3711 .set_power_limit = smu_set_power_limit, 3712 .get_power_limit = smu_get_power_limit, 3713 .get_power_profile_mode = smu_get_power_profile_mode, 3714 .set_power_profile_mode = smu_set_power_profile_mode, 3715 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3716 .set_mp1_state = smu_set_mp1_state, 3717 .gfx_state_change_set = smu_gfx_state_change_set, 3718 /* export to DC */ 3719 .get_sclk = smu_get_sclk, 3720 .get_mclk = smu_get_mclk, 3721 .display_configuration_change = smu_display_configuration_change, 3722 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3723 .display_clock_voltage_request = smu_display_clock_voltage_request, 3724 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3725 .set_active_display_count = smu_set_display_count, 3726 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3727 .get_asic_baco_capability = smu_get_baco_capability, 3728 .set_asic_baco_state = smu_baco_set_state, 3729 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3730 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3731 .asic_reset_mode_2 = smu_mode2_reset, 3732 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3733 .set_df_cstate = smu_set_df_cstate, 3734 .set_xgmi_pstate = smu_set_xgmi_pstate, 3735 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3736 .get_pm_metrics = smu_sys_get_pm_metrics, 3737 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3738 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3739 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3740 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3741 .get_dpm_clock_table = smu_get_dpm_clock_table, 3742 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3743 }; 3744 3745 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3746 uint64_t event_arg) 3747 { 3748 int ret = -EINVAL; 3749 3750 if (smu->ppt_funcs->wait_for_event) 3751 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3752 3753 return ret; 3754 } 3755 3756 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3757 { 3758 3759 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3760 return -EOPNOTSUPP; 3761 3762 /* Confirm the buffer allocated is of correct size */ 3763 if (size != smu->stb_context.stb_buf_size) 3764 return -EINVAL; 3765 3766 /* 3767 * No need to lock smu mutex as we access STB directly through MMIO 3768 * and not going through SMU messaging route (for now at least). 3769 * For registers access rely on implementation internal locking. 3770 */ 3771 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3772 } 3773 3774 #if defined(CONFIG_DEBUG_FS) 3775 3776 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3777 { 3778 struct amdgpu_device *adev = filp->f_inode->i_private; 3779 struct smu_context *smu = adev->powerplay.pp_handle; 3780 unsigned char *buf; 3781 int r; 3782 3783 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3784 if (!buf) 3785 return -ENOMEM; 3786 3787 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3788 if (r) 3789 goto out; 3790 3791 filp->private_data = buf; 3792 3793 return 0; 3794 3795 out: 3796 kvfree(buf); 3797 return r; 3798 } 3799 3800 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3801 loff_t *pos) 3802 { 3803 struct amdgpu_device *adev = filp->f_inode->i_private; 3804 struct smu_context *smu = adev->powerplay.pp_handle; 3805 3806 3807 if (!filp->private_data) 3808 return -EINVAL; 3809 3810 return simple_read_from_buffer(buf, 3811 size, 3812 pos, filp->private_data, 3813 smu->stb_context.stb_buf_size); 3814 } 3815 3816 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3817 { 3818 kvfree(filp->private_data); 3819 filp->private_data = NULL; 3820 3821 return 0; 3822 } 3823 3824 /* 3825 * We have to define not only read method but also 3826 * open and release because .read takes up to PAGE_SIZE 3827 * data each time so and so is invoked multiple times. 3828 * We allocate the STB buffer in .open and release it 3829 * in .release 3830 */ 3831 static const struct file_operations smu_stb_debugfs_fops = { 3832 .owner = THIS_MODULE, 3833 .open = smu_stb_debugfs_open, 3834 .read = smu_stb_debugfs_read, 3835 .release = smu_stb_debugfs_release, 3836 .llseek = default_llseek, 3837 }; 3838 3839 #endif 3840 3841 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3842 { 3843 #if defined(CONFIG_DEBUG_FS) 3844 3845 struct smu_context *smu = adev->powerplay.pp_handle; 3846 3847 if (!smu || (!smu->stb_context.stb_buf_size)) 3848 return; 3849 3850 debugfs_create_file_size("amdgpu_smu_stb_dump", 3851 S_IRUSR, 3852 adev_to_drm(adev)->primary->debugfs_root, 3853 adev, 3854 &smu_stb_debugfs_fops, 3855 smu->stb_context.stb_buf_size); 3856 #endif 3857 } 3858 3859 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3860 { 3861 int ret = 0; 3862 3863 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3864 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3865 3866 return ret; 3867 } 3868 3869 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3870 { 3871 int ret = 0; 3872 3873 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3874 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3875 3876 return ret; 3877 } 3878 3879 int smu_send_rma_reason(struct smu_context *smu) 3880 { 3881 int ret = 0; 3882 3883 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3884 ret = smu->ppt_funcs->send_rma_reason(smu); 3885 3886 return ret; 3887 } 3888