1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "vega10_thermal.h"
25 #include "vega10_hwmgr.h"
26 #include "vega10_smumgr.h"
27 #include "vega10_ppsmc.h"
28 #include "vega10_inc.h"
29 #include "soc15_common.h"
30 #include "pp_debug.h"
31
vega10_get_current_rpm(struct pp_hwmgr * hwmgr,uint32_t * current_rpm)32 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
33 {
34 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm, current_rpm);
35 return 0;
36 }
37
vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr * hwmgr,struct phm_fan_speed_info * fan_speed_info)38 int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
39 struct phm_fan_speed_info *fan_speed_info)
40 {
41
42 if (hwmgr->thermal_controller.fanInfo.bNoFan)
43 return 0;
44
45 fan_speed_info->supports_percent_read = true;
46 fan_speed_info->supports_percent_write = true;
47 fan_speed_info->min_percent = 0;
48 fan_speed_info->max_percent = 100;
49
50 if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
51 hwmgr->thermal_controller.fanInfo.
52 ucTachometerPulsesPerRevolution) {
53 fan_speed_info->supports_rpm_read = true;
54 fan_speed_info->supports_rpm_write = true;
55 fan_speed_info->min_rpm =
56 hwmgr->thermal_controller.fanInfo.ulMinRPM;
57 fan_speed_info->max_rpm =
58 hwmgr->thermal_controller.fanInfo.ulMaxRPM;
59 } else {
60 fan_speed_info->min_rpm = 0;
61 fan_speed_info->max_rpm = 0;
62 }
63
64 return 0;
65 }
66
vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr * hwmgr,uint32_t * speed)67 int vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr,
68 uint32_t *speed)
69 {
70 struct amdgpu_device *adev = hwmgr->adev;
71 uint32_t duty100, duty;
72 uint64_t tmp64;
73
74 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
75 CG_FDO_CTRL1, FMAX_DUTY100);
76 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
77 CG_THERMAL_STATUS, FDO_PWM_DUTY);
78
79 if (!duty100)
80 return -EINVAL;
81
82 tmp64 = (uint64_t)duty * 255;
83 do_div(tmp64, duty100);
84 *speed = min_t(uint32_t, tmp64, 255);
85
86 return 0;
87 }
88
vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr * hwmgr,uint32_t * speed)89 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
90 {
91 struct amdgpu_device *adev = hwmgr->adev;
92 struct vega10_hwmgr *data = hwmgr->backend;
93 uint32_t tach_period;
94 uint32_t crystal_clock_freq;
95 int result = 0;
96
97 if (hwmgr->thermal_controller.fanInfo.bNoFan)
98 return -1;
99
100 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
101 result = vega10_get_current_rpm(hwmgr, speed);
102 } else {
103 tach_period =
104 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
105 CG_TACH_STATUS,
106 TACH_PERIOD);
107
108 if (tach_period == 0)
109 return -EINVAL;
110
111 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
112
113 *speed = 60 * crystal_clock_freq * 10000 / tach_period;
114 }
115
116 return result;
117 }
118
119 /**
120 * vega10_fan_ctrl_set_static_mode - Set Fan Speed Control to static mode,
121 * so that the user can decide what speed to use.
122 * @hwmgr: the address of the powerplay hardware manager.
123 * @mode: the fan control mode, 0 default, 1 by percent, 5, by RPM
124 * Exception: Should always succeed.
125 */
vega10_fan_ctrl_set_static_mode(struct pp_hwmgr * hwmgr,uint32_t mode)126 int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
127 {
128 struct amdgpu_device *adev = hwmgr->adev;
129
130 if (hwmgr->fan_ctrl_is_in_default_mode) {
131 hwmgr->fan_ctrl_default_mode =
132 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
133 CG_FDO_CTRL2, FDO_PWM_MODE);
134 hwmgr->tmin =
135 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
136 CG_FDO_CTRL2, TMIN);
137 hwmgr->fan_ctrl_is_in_default_mode = false;
138 }
139
140 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
141 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
142 CG_FDO_CTRL2, TMIN, 0));
143 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
144 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
145 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
146
147 return 0;
148 }
149
150 /**
151 * vega10_fan_ctrl_set_default_mode - Reset Fan Speed Control to default mode.
152 * @hwmgr: the address of the powerplay hardware manager.
153 * Exception: Should always succeed.
154 */
vega10_fan_ctrl_set_default_mode(struct pp_hwmgr * hwmgr)155 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
156 {
157 struct amdgpu_device *adev = hwmgr->adev;
158
159 if (!hwmgr->fan_ctrl_is_in_default_mode) {
160 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
161 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
162 CG_FDO_CTRL2, FDO_PWM_MODE,
163 hwmgr->fan_ctrl_default_mode));
164 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
165 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
166 CG_FDO_CTRL2, TMIN,
167 hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
168 hwmgr->fan_ctrl_is_in_default_mode = true;
169 }
170
171 return 0;
172 }
173
174 /**
175 * vega10_enable_fan_control_feature - Enables the SMC Fan Control Feature.
176 *
177 * @hwmgr: the address of the powerplay hardware manager.
178 * Return: 0 on success. -1 otherwise.
179 */
vega10_enable_fan_control_feature(struct pp_hwmgr * hwmgr)180 static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
181 {
182 struct vega10_hwmgr *data = hwmgr->backend;
183
184 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
185 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
186 hwmgr, true,
187 data->smu_features[GNLD_FAN_CONTROL].
188 smu_feature_bitmap),
189 "Attempt to Enable FAN CONTROL feature Failed!",
190 return -1);
191 data->smu_features[GNLD_FAN_CONTROL].enabled = true;
192 }
193
194 return 0;
195 }
196
vega10_disable_fan_control_feature(struct pp_hwmgr * hwmgr)197 static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
198 {
199 struct vega10_hwmgr *data = hwmgr->backend;
200
201 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
202 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
203 hwmgr, false,
204 data->smu_features[GNLD_FAN_CONTROL].
205 smu_feature_bitmap),
206 "Attempt to Enable FAN CONTROL feature Failed!",
207 return -1);
208 data->smu_features[GNLD_FAN_CONTROL].enabled = false;
209 }
210
211 return 0;
212 }
213
vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr * hwmgr)214 int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
215 {
216 if (hwmgr->thermal_controller.fanInfo.bNoFan)
217 return -1;
218
219 PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
220 "Attempt to Enable SMC FAN CONTROL Feature Failed!",
221 return -1);
222
223 return 0;
224 }
225
226
vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr * hwmgr)227 int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
228 {
229 struct vega10_hwmgr *data = hwmgr->backend;
230
231 if (hwmgr->thermal_controller.fanInfo.bNoFan)
232 return -1;
233
234 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
235 PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
236 "Attempt to Disable SMC FAN CONTROL Feature Failed!",
237 return -1);
238 }
239 return 0;
240 }
241
242 /**
243 * vega10_fan_ctrl_set_fan_speed_pwm - Set Fan Speed in PWM.
244 * @hwmgr: the address of the powerplay hardware manager.
245 * @speed: is the percentage value (0 - 255) to be set.
246 */
vega10_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr * hwmgr,uint32_t speed)247 int vega10_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr *hwmgr,
248 uint32_t speed)
249 {
250 struct amdgpu_device *adev = hwmgr->adev;
251 uint32_t duty100;
252 uint32_t duty;
253 uint64_t tmp64;
254
255 if (hwmgr->thermal_controller.fanInfo.bNoFan)
256 return 0;
257
258 speed = min_t(uint32_t, speed, 255);
259
260 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
261 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
262
263 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
264 CG_FDO_CTRL1, FMAX_DUTY100);
265
266 if (duty100 == 0)
267 return -EINVAL;
268
269 tmp64 = (uint64_t)speed * duty100;
270 do_div(tmp64, 255);
271 duty = (uint32_t)tmp64;
272
273 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
274 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
275 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
276
277 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
278 }
279
280 /**
281 * vega10_fan_ctrl_reset_fan_speed_to_default - Reset Fan Speed to default.
282 * @hwmgr: the address of the powerplay hardware manager.
283 * Exception: Always succeeds.
284 */
vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr * hwmgr)285 int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
286 {
287 if (hwmgr->thermal_controller.fanInfo.bNoFan)
288 return 0;
289
290 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
291 return vega10_fan_ctrl_start_smc_fan_control(hwmgr);
292 else
293 return vega10_fan_ctrl_set_default_mode(hwmgr);
294 }
295
296 /**
297 * vega10_fan_ctrl_set_fan_speed_rpm - Set Fan Speed in RPM.
298 * @hwmgr: the address of the powerplay hardware manager.
299 * @speed: is the percentage value (min - max) to be set.
300 * Exception: Fails is the speed not lie between min and max.
301 */
vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr * hwmgr,uint32_t speed)302 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
303 {
304 struct amdgpu_device *adev = hwmgr->adev;
305 uint32_t tach_period;
306 uint32_t crystal_clock_freq;
307 int result = 0;
308
309 if (hwmgr->thermal_controller.fanInfo.bNoFan ||
310 speed == 0 ||
311 (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
312 (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
313 return -1;
314
315 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
316 result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
317
318 if (!result) {
319 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
320 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
321 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
322 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
323 CG_TACH_CTRL, TARGET_PERIOD,
324 tach_period));
325 }
326 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
327 }
328
329 /**
330 * vega10_thermal_get_temperature - Reads the remote temperature from the SIslands thermal controller.
331 *
332 * @hwmgr: The address of the hardware manager.
333 */
vega10_thermal_get_temperature(struct pp_hwmgr * hwmgr)334 int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
335 {
336 struct amdgpu_device *adev = hwmgr->adev;
337 int temp;
338
339 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
340
341 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
342 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
343
344 temp = temp & 0x1ff;
345
346 temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
347
348 return temp;
349 }
350
351 /**
352 * vega10_thermal_set_temperature_range - Set the requested temperature range for high and low alert signals
353 *
354 * @hwmgr: The address of the hardware manager.
355 * @range: Temperature range to be programmed for
356 * high and low alert signals
357 * Exception: PP_Result_BadInput if the input data is not valid.
358 */
vega10_thermal_set_temperature_range(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * range)359 static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
360 struct PP_TemperatureRange *range)
361 {
362 struct phm_ppt_v2_information *pp_table_info =
363 (struct phm_ppt_v2_information *)(hwmgr->pptable);
364 struct phm_tdp_table *tdp_table = pp_table_info->tdp_table;
365 struct amdgpu_device *adev = hwmgr->adev;
366 int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP;
367 int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP;
368 uint32_t val;
369
370 /* compare them in unit celsius degree */
371 if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
372 low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
373
374 /*
375 * As a common sense, usSoftwareShutdownTemp should be bigger
376 * than ThotspotLimit. For any invalid usSoftwareShutdownTemp,
377 * we will just use the max possible setting VEGA10_THERMAL_MAXIMUM_ALERT_TEMP
378 * to avoid false alarms.
379 */
380 if ((tdp_table->usSoftwareShutdownTemp >
381 range->hotspot_crit_max / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)) {
382 if (high > tdp_table->usSoftwareShutdownTemp)
383 high = tdp_table->usSoftwareShutdownTemp;
384 }
385
386 if (low > high)
387 return -EINVAL;
388
389 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
390
391 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
392 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
393 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
394 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
395 val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
396 (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
397 (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
398
399 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
400
401 return 0;
402 }
403
404 /**
405 * vega10_thermal_initialize - Programs thermal controller one-time setting registers
406 *
407 * @hwmgr: The address of the hardware manager.
408 */
vega10_thermal_initialize(struct pp_hwmgr * hwmgr)409 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
410 {
411 struct amdgpu_device *adev = hwmgr->adev;
412
413 if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
414 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
415 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
416 CG_TACH_CTRL, EDGE_PER_REV,
417 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));
418 }
419
420 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
421 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
422 CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
423
424 return 0;
425 }
426
427 /**
428 * vega10_thermal_enable_alert - Enable thermal alerts on the RV770 thermal controller.
429 *
430 * @hwmgr: The address of the hardware manager.
431 */
vega10_thermal_enable_alert(struct pp_hwmgr * hwmgr)432 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
433 {
434 struct amdgpu_device *adev = hwmgr->adev;
435 struct vega10_hwmgr *data = hwmgr->backend;
436 uint32_t val = 0;
437
438 if (data->smu_features[GNLD_FW_CTF].supported) {
439 if (data->smu_features[GNLD_FW_CTF].enabled)
440 printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
441
442 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
443 true,
444 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
445 "Attempt to Enable FW CTF feature Failed!",
446 return -1);
447 data->smu_features[GNLD_FW_CTF].enabled = true;
448 }
449
450 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
451 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
452 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
453
454 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
455
456 return 0;
457 }
458
459 /**
460 * vega10_thermal_disable_alert - Disable thermal alerts on the RV770 thermal controller.
461 * @hwmgr: The address of the hardware manager.
462 */
vega10_thermal_disable_alert(struct pp_hwmgr * hwmgr)463 int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
464 {
465 struct amdgpu_device *adev = hwmgr->adev;
466 struct vega10_hwmgr *data = hwmgr->backend;
467
468 if (data->smu_features[GNLD_FW_CTF].supported) {
469 if (!data->smu_features[GNLD_FW_CTF].enabled)
470 printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
471
472
473 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
474 false,
475 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
476 "Attempt to disable FW CTF feature Failed!",
477 return -1);
478 data->smu_features[GNLD_FW_CTF].enabled = false;
479 }
480
481 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
482
483 return 0;
484 }
485
486 /**
487 * vega10_thermal_stop_thermal_controller - Uninitialize the thermal controller.
488 * Currently just disables alerts.
489 * @hwmgr: The address of the hardware manager.
490 */
vega10_thermal_stop_thermal_controller(struct pp_hwmgr * hwmgr)491 int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
492 {
493 int result = vega10_thermal_disable_alert(hwmgr);
494
495 if (!hwmgr->thermal_controller.fanInfo.bNoFan)
496 vega10_fan_ctrl_set_default_mode(hwmgr);
497
498 return result;
499 }
500
501 /**
502 * vega10_thermal_setup_fan_table - Set up the fan table to control the fan using the SMC.
503 * @hwmgr: the address of the powerplay hardware manager.
504 * Return: result from set temperature range routine
505 */
vega10_thermal_setup_fan_table(struct pp_hwmgr * hwmgr)506 static int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
507 {
508 int ret;
509 struct vega10_hwmgr *data = hwmgr->backend;
510 PPTable_t *table = &(data->smc_state_table.pp_table);
511
512 if (!data->smu_features[GNLD_FAN_CONTROL].supported)
513 return 0;
514
515 table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
516 advanceFanControlParameters.usMaxFanRPM;
517 table->FanThrottlingRpm = hwmgr->thermal_controller.
518 advanceFanControlParameters.usFanRPMMaxLimit;
519 table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
520 advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
521 table->FanTargetTemperature = hwmgr->thermal_controller.
522 advanceFanControlParameters.usTMax;
523
524 smum_send_msg_to_smc_with_parameter(hwmgr,
525 PPSMC_MSG_SetFanTemperatureTarget,
526 (uint32_t)table->FanTargetTemperature,
527 NULL);
528
529 table->FanPwmMin = hwmgr->thermal_controller.
530 advanceFanControlParameters.usPWMMin * 255 / 100;
531 table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
532 advanceFanControlParameters.ulTargetGfxClk);
533 table->FanGainEdge = hwmgr->thermal_controller.
534 advanceFanControlParameters.usFanGainEdge;
535 table->FanGainHotspot = hwmgr->thermal_controller.
536 advanceFanControlParameters.usFanGainHotspot;
537 table->FanGainLiquid = hwmgr->thermal_controller.
538 advanceFanControlParameters.usFanGainLiquid;
539 table->FanGainVrVddc = hwmgr->thermal_controller.
540 advanceFanControlParameters.usFanGainVrVddc;
541 table->FanGainVrMvdd = hwmgr->thermal_controller.
542 advanceFanControlParameters.usFanGainVrMvdd;
543 table->FanGainPlx = hwmgr->thermal_controller.
544 advanceFanControlParameters.usFanGainPlx;
545 table->FanGainHbm = hwmgr->thermal_controller.
546 advanceFanControlParameters.usFanGainHbm;
547 table->FanZeroRpmEnable = hwmgr->thermal_controller.
548 advanceFanControlParameters.ucEnableZeroRPM;
549 table->FanStopTemp = hwmgr->thermal_controller.
550 advanceFanControlParameters.usZeroRPMStopTemperature;
551 table->FanStartTemp = hwmgr->thermal_controller.
552 advanceFanControlParameters.usZeroRPMStartTemperature;
553
554 ret = smum_smc_table_manager(hwmgr,
555 (uint8_t *)(&(data->smc_state_table.pp_table)),
556 PPTABLE, false);
557 if (ret)
558 pr_info("Failed to update Fan Control Table in PPTable!");
559
560 return ret;
561 }
562
vega10_enable_mgpu_fan_boost(struct pp_hwmgr * hwmgr)563 int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
564 {
565 struct vega10_hwmgr *data = hwmgr->backend;
566 PPTable_t *table = &(data->smc_state_table.pp_table);
567 int ret;
568
569 if (!data->smu_features[GNLD_FAN_CONTROL].supported)
570 return 0;
571
572 if (!hwmgr->thermal_controller.advanceFanControlParameters.
573 usMGpuThrottlingRPMLimit)
574 return 0;
575
576 table->FanThrottlingRpm = hwmgr->thermal_controller.
577 advanceFanControlParameters.usMGpuThrottlingRPMLimit;
578
579 ret = smum_smc_table_manager(hwmgr,
580 (uint8_t *)(&(data->smc_state_table.pp_table)),
581 PPTABLE, false);
582 if (ret) {
583 pr_info("Failed to update fan control table in pptable!");
584 return ret;
585 }
586
587 ret = vega10_disable_fan_control_feature(hwmgr);
588 if (ret) {
589 pr_info("Attempt to disable SMC fan control feature failed!");
590 return ret;
591 }
592
593 ret = vega10_enable_fan_control_feature(hwmgr);
594 if (ret)
595 pr_info("Attempt to enable SMC fan control feature failed!");
596
597 return ret;
598 }
599
600 /**
601 * vega10_thermal_start_smc_fan_control - Start the fan control on the SMC.
602 * @hwmgr: the address of the powerplay hardware manager.
603 * Return: result from set temperature range routine
604 */
vega10_thermal_start_smc_fan_control(struct pp_hwmgr * hwmgr)605 static int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
606 {
607 /* If the fantable setup has failed we could have disabled
608 * PHM_PlatformCaps_MicrocodeFanControl even after
609 * this function was included in the table.
610 * Make sure that we still think controlling the fan is OK.
611 */
612 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
613 vega10_fan_ctrl_start_smc_fan_control(hwmgr);
614
615 return 0;
616 }
617
618
vega10_start_thermal_controller(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * range)619 int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
620 struct PP_TemperatureRange *range)
621 {
622 int ret = 0;
623
624 if (range == NULL)
625 return -EINVAL;
626
627 vega10_thermal_initialize(hwmgr);
628 ret = vega10_thermal_set_temperature_range(hwmgr, range);
629 if (ret)
630 return -EINVAL;
631
632 vega10_thermal_enable_alert(hwmgr);
633 /* We should restrict performance levels to low before we halt the SMC.
634 * On the other hand we are still in boot state when we do this
635 * so it would be pointless.
636 * If this assumption changes we have to revisit this table.
637 */
638 ret = vega10_thermal_setup_fan_table(hwmgr);
639 if (ret)
640 return -EINVAL;
641
642 vega10_thermal_start_smc_fan_control(hwmgr);
643
644 return 0;
645 };
646
647
648
649
vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr * hwmgr)650 int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
651 {
652 if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
653 vega10_fan_ctrl_set_default_mode(hwmgr);
654 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
655 }
656 return 0;
657 }
658