1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _DMUB_DCN42_H_ 26 #define _DMUB_DCN42_H_ 27 28 #include "dmub_dcn35.h" 29 #include "dmub_dcn401.h" 30 31 32 struct dmub_srv; 33 34 /* DCN42 register definitions. */ 35 36 #define DMUB_DCN42_REGS() \ 37 DMUB_DCN35_REGS() \ 38 DMUB_SR(DMCUB_INTERRUPT_STATUS) \ 39 DMUB_SR(DMCUB_REG_INBOX0_RDY) \ 40 DMUB_SR(DMCUB_REG_INBOX0_MSG0) \ 41 DMUB_SR(DMCUB_REG_INBOX0_MSG1) \ 42 DMUB_SR(DMCUB_REG_INBOX0_MSG2) \ 43 DMUB_SR(DMCUB_REG_INBOX0_MSG3) \ 44 DMUB_SR(DMCUB_REG_INBOX0_MSG4) \ 45 DMUB_SR(DMCUB_REG_INBOX0_MSG5) \ 46 DMUB_SR(DMCUB_REG_INBOX0_MSG6) \ 47 DMUB_SR(DMCUB_REG_INBOX0_MSG7) \ 48 DMUB_SR(DMCUB_REG_INBOX0_MSG8) \ 49 DMUB_SR(DMCUB_REG_INBOX0_MSG9) \ 50 DMUB_SR(DMCUB_REG_INBOX0_MSG10) \ 51 DMUB_SR(DMCUB_REG_INBOX0_MSG11) \ 52 DMUB_SR(DMCUB_REG_INBOX0_MSG12) \ 53 DMUB_SR(DMCUB_REG_INBOX0_MSG13) \ 54 DMUB_SR(DMCUB_REG_INBOX0_MSG14) \ 55 DMUB_SR(DMCUB_REG_INBOX0_RSP) \ 56 DMUB_SR(DMCUB_REG_OUTBOX0_RDY) \ 57 DMUB_SR(DMCUB_REG_OUTBOX0_MSG0) \ 58 DMUB_SR(DMCUB_REG_OUTBOX0_RSP) \ 59 DMUB_SR(HOST_INTERRUPT_CSR) 60 61 #define DMUB_DCN42_FIELDS() \ 62 DMUB_DCN35_FIELDS() \ 63 DMUB_SF(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT) \ 64 DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK) \ 65 DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT) \ 66 DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN) \ 67 DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK) \ 68 DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT) \ 69 DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN) 70 71 struct dmub_srv_dcn42_reg_offset { 72 #define DMUB_SR(reg) uint32_t reg; 73 DMUB_DCN42_REGS() 74 DMCUB_INTERNAL_REGS() 75 #undef DMUB_SR 76 }; 77 78 struct dmub_srv_dcn42_reg_shift { 79 #define DMUB_SF(reg, field) uint8_t reg##__##field; 80 DMUB_DCN42_FIELDS() 81 #undef DMUB_SF 82 }; 83 84 struct dmub_srv_dcn42_reg_mask { 85 #define DMUB_SF(reg, field) uint32_t reg##__##field; 86 DMUB_DCN42_FIELDS() 87 #undef DMUB_SF 88 }; 89 90 struct dmub_srv_dcn42_regs { 91 struct dmub_srv_dcn42_reg_offset offset; 92 struct dmub_srv_dcn42_reg_mask mask; 93 struct dmub_srv_dcn42_reg_shift shift; 94 }; 95 96 /* Function declarations */ 97 98 /* Initialization and configuration */ 99 void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx); 100 void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params); 101 void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip); 102 void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub); 103 104 /* Reset and control */ 105 void dmub_dcn42_reset(struct dmub_srv *dmub); 106 void dmub_dcn42_reset_release(struct dmub_srv *dmub); 107 108 /* Firmware loading */ 109 void dmub_dcn42_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1); 110 void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1); 111 void dmub_dcn42_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6); 112 113 /* Mailbox operations - Inbox1 */ 114 void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub, const struct dmub_region *inbox1); 115 uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub); 116 uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub); 117 void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset); 118 119 /* Mailbox operations - Outbox1 */ 120 void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub, const struct dmub_region *outbox1); 121 uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub); 122 void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); 123 124 /* Mailbox operations - Outbox0 */ 125 void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub, const struct dmub_region *outbox0); 126 uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub); 127 void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); 128 129 /* Mailbox operations - Inbox0 */ 130 void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 131 void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub); 132 uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub); 133 134 /* REG Inbox0/Outbox0 operations */ 135 void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); 136 uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub); 137 void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); 138 void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub); 139 void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub); 140 void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable); 141 142 void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub); 143 void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg); 144 void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp); 145 uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub); 146 void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable); 147 uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub); 148 149 /* GPINT operations */ 150 void dmub_dcn42_set_gpint(struct dmub_srv *dmub, union dmub_gpint_data_register reg); 151 bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub, union dmub_gpint_data_register reg); 152 uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub); 153 uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub); 154 155 /* Status and detection */ 156 bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub); 157 bool dmub_dcn42_is_supported(struct dmub_srv *dmub); 158 bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub); 159 bool dmub_dcn42_should_detect(struct dmub_srv *dmub); 160 161 162 /* Firmware boot status and options */ 163 union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub); 164 union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub); 165 166 /* Timing and diagnostics */ 167 uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub); 168 void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub); 169 bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub); 170 171 #endif /* _DMUB_DCN42_H_ */ 172