1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _DMUB_DCN42_H_ 26 #define _DMUB_DCN42_H_ 27 28 #include "dmub_dcn35.h" 29 #include "dmub_dcn401.h" 30 31 32 struct dmub_srv; 33 34 /* DCN42 register definitions. */ 35 36 #define DMUB_DCN42_REGS() \ 37 DMUB_SR(DMCUB_CNTL) \ 38 DMUB_SR(DMCUB_CNTL2) \ 39 DMUB_SR(DMCUB_SEC_CNTL) \ 40 DMUB_SR(DMCUB_INBOX0_SIZE) \ 41 DMUB_SR(DMCUB_INBOX0_RPTR) \ 42 DMUB_SR(DMCUB_INBOX0_WPTR) \ 43 DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \ 44 DMUB_SR(DMCUB_INBOX1_SIZE) \ 45 DMUB_SR(DMCUB_INBOX1_RPTR) \ 46 DMUB_SR(DMCUB_INBOX1_WPTR) \ 47 DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \ 48 DMUB_SR(DMCUB_OUTBOX0_SIZE) \ 49 DMUB_SR(DMCUB_OUTBOX0_RPTR) \ 50 DMUB_SR(DMCUB_OUTBOX0_WPTR) \ 51 DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \ 52 DMUB_SR(DMCUB_OUTBOX1_SIZE) \ 53 DMUB_SR(DMCUB_OUTBOX1_RPTR) \ 54 DMUB_SR(DMCUB_OUTBOX1_WPTR) \ 55 DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \ 56 DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \ 57 DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \ 58 DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \ 59 DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \ 60 DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \ 61 DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \ 62 DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \ 63 DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \ 64 DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \ 65 DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \ 66 DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \ 67 DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \ 68 DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \ 69 DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \ 70 DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \ 71 DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \ 72 DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \ 73 DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \ 74 DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \ 75 DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \ 76 DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \ 77 DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \ 78 DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \ 79 DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \ 80 DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \ 81 DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \ 82 DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \ 83 DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \ 84 DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \ 85 DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \ 86 DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \ 87 DMUB_SR(DMCUB_REGION4_OFFSET) \ 88 DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \ 89 DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \ 90 DMUB_SR(DMCUB_REGION5_OFFSET) \ 91 DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \ 92 DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \ 93 DMUB_SR(DMCUB_REGION6_OFFSET) \ 94 DMUB_SR(DMCUB_REGION6_OFFSET_HIGH) \ 95 DMUB_SR(DMCUB_REGION6_TOP_ADDRESS) \ 96 DMUB_SR(DMCUB_SCRATCH0) \ 97 DMUB_SR(DMCUB_SCRATCH1) \ 98 DMUB_SR(DMCUB_SCRATCH2) \ 99 DMUB_SR(DMCUB_SCRATCH3) \ 100 DMUB_SR(DMCUB_SCRATCH4) \ 101 DMUB_SR(DMCUB_SCRATCH5) \ 102 DMUB_SR(DMCUB_SCRATCH6) \ 103 DMUB_SR(DMCUB_SCRATCH7) \ 104 DMUB_SR(DMCUB_SCRATCH8) \ 105 DMUB_SR(DMCUB_SCRATCH9) \ 106 DMUB_SR(DMCUB_SCRATCH10) \ 107 DMUB_SR(DMCUB_SCRATCH11) \ 108 DMUB_SR(DMCUB_SCRATCH12) \ 109 DMUB_SR(DMCUB_SCRATCH13) \ 110 DMUB_SR(DMCUB_SCRATCH14) \ 111 DMUB_SR(DMCUB_SCRATCH15) \ 112 DMUB_SR(DMCUB_SCRATCH16) \ 113 DMUB_SR(DMCUB_SCRATCH17) \ 114 DMUB_SR(DMCUB_SCRATCH18) \ 115 DMUB_SR(DMCUB_SCRATCH19) \ 116 DMUB_SR(DMCUB_SCRATCH20) \ 117 DMUB_SR(DMCUB_SCRATCH21) \ 118 DMUB_SR(DMCUB_GPINT_DATAIN0) \ 119 DMUB_SR(DMCUB_GPINT_DATAIN1) \ 120 DMUB_SR(DMCUB_GPINT_DATAOUT) \ 121 DMUB_SR(MMHUBBUB_SOFT_RESET) \ 122 DMUB_SR(DCN_VM_FB_LOCATION_BASE) \ 123 DMUB_SR(DCN_VM_FB_OFFSET) \ 124 DMUB_SR(DMCUB_TIMER_CURRENT) \ 125 DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \ 126 DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \ 127 DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \ 128 DMUB_SR(DMCUB_REGION3_TMR_AXI_SPACE) \ 129 DMUB_SR(DMCUB_INTERRUPT_ENABLE) \ 130 DMUB_SR(DMCUB_INTERRUPT_ACK) \ 131 DMUB_SR(DMU_CLK_CNTL) \ 132 DMUB_SR(DMCUB_INTERRUPT_STATUS) \ 133 DMUB_SR(DMCUB_REG_INBOX0_RDY) \ 134 DMUB_SR(DMCUB_REG_INBOX0_MSG0) \ 135 DMUB_SR(DMCUB_REG_INBOX0_MSG1) \ 136 DMUB_SR(DMCUB_REG_INBOX0_MSG2) \ 137 DMUB_SR(DMCUB_REG_INBOX0_MSG3) \ 138 DMUB_SR(DMCUB_REG_INBOX0_MSG4) \ 139 DMUB_SR(DMCUB_REG_INBOX0_MSG5) \ 140 DMUB_SR(DMCUB_REG_INBOX0_MSG6) \ 141 DMUB_SR(DMCUB_REG_INBOX0_MSG7) \ 142 DMUB_SR(DMCUB_REG_INBOX0_MSG8) \ 143 DMUB_SR(DMCUB_REG_INBOX0_MSG9) \ 144 DMUB_SR(DMCUB_REG_INBOX0_MSG10) \ 145 DMUB_SR(DMCUB_REG_INBOX0_MSG11) \ 146 DMUB_SR(DMCUB_REG_INBOX0_MSG12) \ 147 DMUB_SR(DMCUB_REG_INBOX0_MSG13) \ 148 DMUB_SR(DMCUB_REG_INBOX0_MSG14) \ 149 DMUB_SR(DMCUB_REG_INBOX0_RSP) \ 150 DMUB_SR(DMCUB_REG_OUTBOX0_RDY) \ 151 DMUB_SR(DMCUB_REG_OUTBOX0_MSG0) \ 152 DMUB_SR(DMCUB_REG_OUTBOX0_RSP) \ 153 DMUB_SR(HOST_INTERRUPT_CSR) 154 155 #define DMUB_DCN42_FIELDS() \ 156 DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \ 157 DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \ 158 DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \ 159 DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \ 160 DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \ 161 DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \ 162 DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \ 163 DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \ 164 DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \ 165 DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \ 166 DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \ 167 DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \ 168 DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \ 169 DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \ 170 DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \ 171 DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \ 172 DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \ 173 DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \ 174 DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \ 175 DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \ 176 DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \ 177 DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \ 178 DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \ 179 DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \ 180 DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \ 181 DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \ 182 DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_TOP_ADDRESS) \ 183 DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_ENABLE) \ 184 DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \ 185 DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \ 186 DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \ 187 DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \ 188 DMUB_SF(DMCUB_REGION3_TMR_AXI_SPACE, DMCUB_REGION3_TMR_AXI_SPACE) \ 189 DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \ 190 DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK) \ 191 DMUB_SF(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS) \ 192 DMUB_SF(DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE) \ 193 DMUB_SF(DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE) \ 194 DMUB_SF(DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE) \ 195 DMUB_SF(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT) \ 196 DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK) \ 197 DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT) \ 198 DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN) \ 199 DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK) \ 200 DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT) \ 201 DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN) 202 203 struct dmub_srv_dcn42_reg_offset { 204 #define DMUB_SR(reg) uint32_t reg; 205 DMUB_DCN42_REGS() 206 DMCUB_INTERNAL_REGS() 207 #undef DMUB_SR 208 }; 209 210 struct dmub_srv_dcn42_reg_shift { 211 #define DMUB_SF(reg, field) uint8_t reg##__##field; 212 DMUB_DCN42_FIELDS() 213 #undef DMUB_SF 214 }; 215 216 struct dmub_srv_dcn42_reg_mask { 217 #define DMUB_SF(reg, field) uint32_t reg##__##field; 218 DMUB_DCN42_FIELDS() 219 #undef DMUB_SF 220 }; 221 222 struct dmub_srv_dcn42_regs { 223 struct dmub_srv_dcn42_reg_offset offset; 224 struct dmub_srv_dcn42_reg_mask mask; 225 struct dmub_srv_dcn42_reg_shift shift; 226 }; 227 228 /* Function declarations */ 229 230 /* Initialization and configuration */ 231 void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx); 232 void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params); 233 void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip); 234 void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub); 235 236 /* Reset and control */ 237 void dmub_dcn42_reset(struct dmub_srv *dmub); 238 void dmub_dcn42_reset_release(struct dmub_srv *dmub); 239 240 /* Firmware loading */ 241 void dmub_dcn42_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1); 242 void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1); 243 void dmub_dcn42_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6); 244 245 /* Mailbox operations - Inbox1 */ 246 void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub, const struct dmub_region *inbox1); 247 uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub); 248 uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub); 249 void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset); 250 251 /* Mailbox operations - Outbox1 */ 252 void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub, const struct dmub_region *outbox1); 253 uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub); 254 void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); 255 256 /* Mailbox operations - Outbox0 */ 257 void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub, const struct dmub_region *outbox0); 258 uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub); 259 void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); 260 261 /* Mailbox operations - Inbox0 */ 262 void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 263 void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub); 264 uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub); 265 266 /* REG Inbox0/Outbox0 operations */ 267 void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); 268 uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub); 269 void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); 270 void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub); 271 void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub); 272 void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable); 273 274 void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub); 275 void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg); 276 void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp); 277 uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub); 278 void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable); 279 uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub); 280 281 /* GPINT operations */ 282 void dmub_dcn42_set_gpint(struct dmub_srv *dmub, union dmub_gpint_data_register reg); 283 bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub, union dmub_gpint_data_register reg); 284 uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub); 285 uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub); 286 287 /* Status and detection */ 288 bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub); 289 bool dmub_dcn42_is_supported(struct dmub_srv *dmub); 290 bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub); 291 bool dmub_dcn42_should_detect(struct dmub_srv *dmub); 292 293 294 /* Firmware boot status and options */ 295 union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub); 296 union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub); 297 298 /* Timing and diagnostics */ 299 uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub); 300 void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub); 301 bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub); 302 303 #endif /* _DMUB_DCN42_H_ */ 304