1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2026 Advanced Micro Devices, Inc. 4 5 #include "../dmub_srv.h" 6 #include "dmub_reg.h" 7 #include "dmub_dcn35.h" 8 #include "dmub_dcn401.h" 9 #include "dmub_dcn42.h" 10 11 #include "dcn/dcn_4_2_0_offset.h" 12 #include "dcn/dcn_4_2_0_sh_mask.h" 13 14 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 15 #define CTX dmub 16 #define REGS dmub->regs_dcn42 17 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) 18 19 void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) 20 { 21 struct dmub_srv_dcn42_regs *regs = dmub->regs_dcn42; 22 #define REG_STRUCT regs 23 24 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); 25 DMUB_DCN42_REGS() 26 DMCUB_INTERNAL_REGS() 27 #undef DMUB_SR 28 29 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); 30 DMUB_DCN42_FIELDS() 31 #undef DMUB_SF 32 33 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); 34 DMUB_DCN42_FIELDS() 35 #undef DMUB_SF 36 #undef REG_STRUCT 37 } 38 39 void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) 40 { 41 union dmub_fw_boot_options boot_options = {0}; 42 43 if (!dmub->dpia_supported) { 44 dmub->dpia_supported = dmub_dcn42_get_fw_boot_option(dmub).bits.enable_dpia != 0; 45 } 46 47 boot_options.bits.z10_disable = params->disable_z10; 48 boot_options.bits.dpia_supported = params->dpia_supported; 49 boot_options.bits.enable_dpia = dmub->dpia_supported && !params->disable_dpia; 50 boot_options.bits.usb4_cm_version = params->usb4_cm_version; 51 boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported; 52 boot_options.bits.power_optimization = params->power_optimization; 53 boot_options.bits.disable_clk_ds = params->disallow_dispclk_dppclk_ds; 54 boot_options.bits.disable_clk_gate = params->disable_clock_gate; 55 boot_options.bits.ips_disable = params->disable_ips; 56 boot_options.bits.ips_sequential_ono = params->ips_sequential_ono; 57 boot_options.bits.disable_sldo_opt = params->disable_sldo_opt; 58 boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig; 59 boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; 60 boot_options.bits.skip_phy_access = params->disallow_phy_access; 61 boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation; 62 63 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 64 } 65 66 static void dmub_dcn42_get_fb_base_offset(struct dmub_srv *dmub, 67 uint64_t *fb_base, 68 uint64_t *fb_offset) 69 { 70 uint32_t tmp; 71 72 /* 73 if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) { 74 *fb_base = dmub->soc_fb_info.fb_base; 75 *fb_offset = dmub->soc_fb_info.fb_offset; 76 return; 77 } 78 */ 79 80 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); 81 *fb_base = (uint64_t)tmp << 24; 82 83 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); 84 *fb_offset = (uint64_t)tmp << 24; 85 } 86 87 static inline void dmub_dcn42_translate_addr(const union dmub_addr *addr_in, 88 uint64_t fb_base, 89 uint64_t fb_offset, 90 union dmub_addr *addr_out) 91 { 92 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; 93 } 94 95 void dmub_dcn42_reset(struct dmub_srv *dmub) 96 { 97 union dmub_gpint_data_register cmd; 98 const uint32_t timeout = 100000; 99 uint32_t in_reset, is_enabled, scratch, i, pwait_mode; 100 101 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); 102 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled); 103 104 if (in_reset == 0 && is_enabled != 0) { 105 cmd.bits.status = 1; 106 cmd.bits.command_code = DMUB_GPINT__STOP_FW; 107 cmd.bits.param = 0; 108 109 dmub->hw_funcs.set_gpint(dmub, cmd); 110 111 for (i = 0; i < timeout; ++i) { 112 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) 113 break; 114 115 udelay(1); 116 } 117 118 for (i = 0; i < timeout; ++i) { 119 scratch = REG_READ(DMCUB_SCRATCH7); 120 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) 121 break; 122 123 udelay(1); 124 } 125 126 for (i = 0; i < timeout; ++i) { 127 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); 128 if (pwait_mode & (1 << 0)) 129 break; 130 131 udelay(1); 132 } 133 /* Force reset in case we timed out, DMCUB is likely hung. */ 134 } 135 136 if (is_enabled) { 137 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); 138 udelay(1); 139 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 140 } 141 142 REG_WRITE(DMCUB_INBOX1_RPTR, 0); 143 REG_WRITE(DMCUB_INBOX1_WPTR, 0); 144 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); 145 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); 146 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); 147 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); 148 REG_WRITE(DMCUB_SCRATCH0, 0); 149 150 /* Clear the GPINT command manually so we don't send anything during boot. */ 151 cmd.all = 0; 152 dmub->hw_funcs.set_gpint(dmub, cmd); 153 } 154 155 void dmub_dcn42_reset_release(struct dmub_srv *dmub) 156 { 157 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); 158 159 REG_UPDATE_3(DMU_CLK_CNTL, 160 LONO_DISPCLK_GATE_DISABLE, 1, 161 LONO_SOCCLK_GATE_DISABLE, 1, 162 LONO_DMCUBCLK_GATE_DISABLE, 1); 163 164 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); 165 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); 166 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0); 167 } 168 169 void dmub_dcn42_backdoor_load(struct dmub_srv *dmub, 170 const struct dmub_window *cw0, 171 const struct dmub_window *cw1) 172 { 173 union dmub_addr offset; 174 uint64_t fb_base, fb_offset; 175 176 dmub_dcn42_get_fb_base_offset(dmub, &fb_base, &fb_offset); 177 178 dmub_dcn42_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 179 180 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 181 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 182 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 183 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 184 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 185 DMCUB_REGION3_CW0_ENABLE, 1); 186 187 dmub_dcn42_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); 188 189 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 190 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 191 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 192 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 193 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 194 DMCUB_REGION3_CW1_ENABLE, 1); 195 196 /* TODO: Do we need to set DMCUB_MEM_UNIT_ID? */ 197 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0); 198 } 199 200 void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub, 201 const struct dmub_window *cw0, 202 const struct dmub_window *cw1) 203 { 204 union dmub_addr offset; 205 206 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 207 offset = cw0->offset; 208 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 209 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 210 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 211 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 212 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 213 DMCUB_REGION3_CW0_ENABLE, 1); 214 offset = cw1->offset; 215 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 216 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 217 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 218 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 219 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 220 DMCUB_REGION3_CW1_ENABLE, 1); 221 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 222 0x20); 223 } 224 void dmub_dcn42_setup_windows(struct dmub_srv *dmub, 225 const struct dmub_window *cw2, 226 const struct dmub_window *cw3, 227 const struct dmub_window *cw4, 228 const struct dmub_window *cw5, 229 const struct dmub_window *cw6, 230 const struct dmub_window *region6) 231 { 232 (void)cw2; 233 union dmub_addr offset; 234 235 offset = cw3->offset; 236 237 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); 238 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); 239 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); 240 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, 241 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, 242 DMCUB_REGION3_CW3_ENABLE, 1); 243 244 offset = cw4->offset; 245 246 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); 247 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); 248 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); 249 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, 250 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, 251 DMCUB_REGION3_CW4_ENABLE, 1); 252 253 offset = cw5->offset; 254 255 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); 256 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); 257 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); 258 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, 259 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, 260 DMCUB_REGION3_CW5_ENABLE, 1); 261 262 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); 263 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); 264 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, 265 DMCUB_REGION5_TOP_ADDRESS, 266 cw5->region.top - cw5->region.base - 1, 267 DMCUB_REGION5_ENABLE, 1); 268 269 offset = cw6->offset; 270 271 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); 272 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); 273 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); 274 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, 275 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, 276 DMCUB_REGION3_CW6_ENABLE, 1); 277 278 offset = region6->offset; 279 280 REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part); 281 REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part); 282 REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0, 283 DMCUB_REGION6_TOP_ADDRESS, 284 region6->region.top - region6->region.base - 1, 285 DMCUB_REGION6_ENABLE, 1); 286 } 287 288 uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub) 289 { 290 return REG_READ(DMCUB_INBOX1_WPTR); 291 } 292 293 uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub) 294 { 295 return REG_READ(DMCUB_INBOX1_RPTR); 296 } 297 298 void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub, 299 const struct dmub_region *outbox1) 300 { 301 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base); 302 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base); 303 } 304 305 uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub) 306 { 307 /** 308 * outbox1 wptr register is accessed without locks (dal & dc) 309 * and to be called only by dmub_srv_stat_get_notification() 310 */ 311 return REG_READ(DMCUB_OUTBOX1_WPTR); 312 } 313 314 void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) 315 { 316 /** 317 * outbox1 rptr register is accessed without locks (dal & dc) 318 * and to be called only by dmub_srv_stat_get_notification() 319 */ 320 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); 321 } 322 323 bool dmub_dcn42_is_supported(struct dmub_srv *dmub) 324 { 325 // DCN without DMUB is not a supported configuration; safe to assume that it is always 326 // present. 327 return true; 328 } 329 330 union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub) 331 { 332 union dmub_fw_boot_options option; 333 334 option.all = REG_READ(DMCUB_SCRATCH14); 335 return option; 336 } 337 338 void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub, 339 const struct dmub_region *outbox0) 340 { 341 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base); 342 343 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base); 344 } 345 346 bool dmub_dcn42_should_detect(struct dmub_srv *dmub) 347 { 348 uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0); 349 bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0; 350 return should_detect; 351 } 352 353 void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data) 354 { 355 REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all); 356 } 357 358 uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub) 359 { 360 return REG_READ(DMCUB_SCRATCH17); 361 } 362 363 bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub) 364 { 365 union dmub_fw_boot_status status; 366 uint32_t is_enable; 367 368 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); 369 if (is_enable == 0) 370 return false; 371 372 status.all = REG_READ(DMCUB_SCRATCH0); 373 374 return (status.bits.dal_fw && status.bits.hw_power_init_done && status.bits.mailbox_rdy) || 375 (!status.bits.dal_fw && status.bits.mailbox_rdy); 376 } 377 378 void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) 379 { 380 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); 381 } 382 383 bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub) 384 { 385 union dmub_fw_boot_status status; 386 uint32_t is_hw_init; 387 388 status.all = REG_READ(DMCUB_SCRATCH0); 389 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); 390 391 return is_hw_init != 0 && status.bits.dal_fw; 392 } 393 394 union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub) 395 { 396 union dmub_fw_boot_status status; 397 398 status.all = REG_READ(DMCUB_SCRATCH0); 399 return status; 400 } 401 402 void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) 403 { 404 union dmub_fw_boot_options boot_options; 405 boot_options.all = REG_READ(DMCUB_SCRATCH14); 406 boot_options.bits.skip_phy_init_panel_sequence = skip; 407 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 408 } 409 410 void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub) 411 { 412 /* DMCUB_REGION3_TMR_AXI_SPACE values: 413 * 0b011 (0x3) - FB physical address 414 * 0b100 (0x4) - GPU virtual address 415 * 416 * Default value is 0x3 (FB Physical address for TMR). When programming 417 * DMUB to be in system memory, change to 0x4. The system memory allocated 418 * is accessible by both GPU and CPU, so we use GPU virtual address. 419 */ 420 REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4); 421 } 422 423 void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub) 424 { 425 REG_WRITE(DMCUB_SCRATCH17, 0); 426 } 427 428 void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, 429 union dmub_rb_cmd *cmd) 430 { 431 uint32_t *dwords = (uint32_t *)cmd; 432 int32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; 433 uint32_t msg_index; 434 static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); 435 436 /* read remaining data based on payload size */ 437 for (msg_index = 0; msg_index < 15; msg_index++) { 438 if (payload_size_bytes <= msg_index * 4) { 439 break; 440 } 441 442 switch (msg_index) { 443 case 0: 444 REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[msg_index + 1]); 445 break; 446 case 1: 447 REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[msg_index + 1]); 448 break; 449 case 2: 450 REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[msg_index + 1]); 451 break; 452 case 3: 453 REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[msg_index + 1]); 454 break; 455 case 4: 456 REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[msg_index + 1]); 457 break; 458 case 5: 459 REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[msg_index + 1]); 460 break; 461 case 6: 462 REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[msg_index + 1]); 463 break; 464 case 7: 465 REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[msg_index + 1]); 466 break; 467 case 8: 468 REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[msg_index + 1]); 469 break; 470 case 9: 471 REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[msg_index + 1]); 472 break; 473 case 10: 474 REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[msg_index + 1]); 475 break; 476 case 11: 477 REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[msg_index + 1]); 478 break; 479 case 12: 480 REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[msg_index + 1]); 481 break; 482 case 13: 483 REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[msg_index + 1]); 484 break; 485 case 14: 486 REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[msg_index + 1]); 487 break; 488 } 489 } 490 491 /* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY 492 * interrupt. 493 */ 494 REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[0]); 495 } 496 497 uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub) 498 { 499 uint32_t status; 500 501 REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &status); 502 return status; 503 } 504 505 void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, 506 union dmub_rb_cmd *cmd) 507 { 508 uint32_t *dwords = (uint32_t *)cmd; 509 510 static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); 511 512 dwords[0] = REG_READ(DMCUB_REG_INBOX0_RSP); 513 dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG0); 514 dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG1); 515 dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG2); 516 dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG3); 517 dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG4); 518 dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG5); 519 dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG6); 520 dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG7); 521 dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG8); 522 dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG9); 523 dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG10); 524 dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG11); 525 dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG12); 526 dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG13); 527 dwords[15] = REG_READ(DMCUB_REG_INBOX0_MSG14); 528 } 529 530 void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub) 531 { 532 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 1); 533 } 534 535 void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub) 536 { 537 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 0); 538 } 539 540 void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable) 541 { 542 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0); 543 } 544 545 void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub) 546 { 547 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 1); 548 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 0); 549 } 550 551 void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg) 552 { 553 *msg = REG_READ(DMCUB_REG_OUTBOX0_MSG0); 554 } 555 556 557 void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable) 558 { 559 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN, enable ? 1:0); 560 } 561 562 uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub) 563 { 564 uint32_t status; 565 566 REG_GET(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT, &status); 567 return status; 568 } 569 570 void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub, 571 const struct dmub_region *inbox1) 572 { 573 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); 574 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); 575 } 576 577 void dmub_dcn42_set_gpint(struct dmub_srv *dmub, 578 union dmub_gpint_data_register reg) 579 { 580 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); 581 } 582 583 bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub, 584 union dmub_gpint_data_register reg) 585 { 586 union dmub_gpint_data_register test; 587 588 reg.bits.status = 0; 589 test.all = REG_READ(DMCUB_GPINT_DATAIN1); 590 591 return test.all == reg.all; 592 } 593 594 uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub) 595 { 596 return REG_READ(DMCUB_SCRATCH7); 597 } 598 599 uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub) 600 { 601 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT); 602 603 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0); 604 605 REG_WRITE(DMCUB_GPINT_DATAOUT, 0); 606 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1); 607 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0); 608 609 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1); 610 611 return dataout; 612 } 613 614 uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub) 615 { 616 return REG_READ(DMCUB_OUTBOX0_WPTR); 617 } 618 619 void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) 620 { 621 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); 622 } 623 624 uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub) 625 { 626 return REG_READ(DMCUB_TIMER_CURRENT); 627 } 628 629 void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub) 630 { 631 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset, is_pwait; 632 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; 633 struct dmub_timeout_info timeout = {0}; 634 635 if (!dmub) 636 return; 637 638 /* timeout data filled externally, cache before resetting memory */ 639 timeout = dmub->debug.timeout_info; 640 memset(&dmub->debug, 0, sizeof(dmub->debug)); 641 dmub->debug.timeout_info = timeout; 642 643 dmub->debug.dmcub_version = dmub->fw_version; 644 645 dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0); 646 dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1); 647 dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2); 648 dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3); 649 dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4); 650 dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5); 651 dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6); 652 dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7); 653 dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8); 654 dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9); 655 dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10); 656 dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11); 657 dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12); 658 dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13); 659 dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14); 660 dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15); 661 dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16); 662 663 dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 664 dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 665 dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 666 667 dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 668 dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 669 dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 670 671 dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 672 dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 673 dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 674 675 dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 676 dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 677 dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 678 679 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 680 ASSERT(is_dmub_enabled <= 0xFF); 681 dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled; 682 683 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait); 684 ASSERT(is_pwait <= 0xFF); 685 dmub->debug.is_pwait = (uint8_t)is_pwait; 686 687 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 688 ASSERT(is_soft_reset <= 0xFF); 689 dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset; 690 691 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 692 ASSERT(is_sec_reset <= 0xFF); 693 dmub->debug.is_dmcub_secure_reset = (uint8_t)is_sec_reset; 694 695 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 696 ASSERT(is_traceport_enabled <= 0xFF); 697 dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled; 698 699 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); 700 ASSERT(is_cw0_enabled <= 0xFF); 701 dmub->debug.is_cw0_enabled = (uint8_t)is_cw0_enabled; 702 703 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 704 ASSERT(is_cw6_enabled <= 0xFF); 705 dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled; 706 707 dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 708 } 709 710 bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub) 711 { 712 uint64_t region3_cw5_offset; 713 uint32_t top_addr, top_addr_enable, offset_low; 714 uint32_t offset_high, base_addr, fw_version; 715 bool is_vbios_fw = false; 716 717 memset(&dmub->preos_info, 0, sizeof(dmub->preos_info)); 718 719 fw_version = REG_READ(DMCUB_SCRATCH1); 720 is_vbios_fw = ((fw_version >> 6) & 0x01) ? true : false; 721 if (!is_vbios_fw) 722 return false; 723 724 dmub->preos_info.boot_status = REG_READ(DMCUB_SCRATCH0); 725 dmub->preos_info.fw_version = REG_READ(DMCUB_SCRATCH1); 726 dmub->preos_info.boot_options = REG_READ(DMCUB_SCRATCH14); 727 REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS, 728 DMCUB_REGION3_CW5_ENABLE, &top_addr_enable); 729 if (top_addr_enable) { 730 dmub_dcn42_get_fb_base_offset(dmub, 731 &dmub->preos_info.fb_base, &dmub->preos_info.fb_offset); 732 offset_low = REG_READ(DMCUB_REGION3_CW5_OFFSET); 733 offset_high = REG_READ(DMCUB_REGION3_CW5_OFFSET_HIGH); 734 region3_cw5_offset = ((uint64_t)offset_high << 32) | offset_low; 735 dmub->preos_info.trace_buffer_phy_addr = region3_cw5_offset 736 - dmub->preos_info.fb_base + dmub->preos_info.fb_offset; 737 738 REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS, 739 DMCUB_REGION3_CW5_TOP_ADDRESS, &top_addr); 740 base_addr = REG_READ(DMCUB_REGION3_CW5_BASE_ADDRESS) & 0x1FFFFFFF; 741 dmub->preos_info.trace_buffer_size = 742 (top_addr > base_addr) ? (top_addr - base_addr + 1) : 0; 743 } 744 745 return true; 746 } 747 748 void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp) 749 { 750 REG_WRITE(DMCUB_REG_OUTBOX0_RSP, *rsp); 751 } 752 753 uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub) 754 { 755 uint32_t status; 756 757 REG_GET(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT, &status); 758 return status; 759 } 760