1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef _DCN60_RESOURCE_H_ 6 #define _DCN60_RESOURCE_H_ 7 8 #include "core_types.h" 9 #include "dcn42/dcn42_mpc.h" 10 11 #define TO_DCN60_RES_POOL(pool)\ 12 container_of(pool, struct dcn60_resource_pool, base) 13 14 struct dcn60_resource_pool { 15 struct resource_pool base; 16 }; 17 18 struct resource_pool *dcn60_create_resource_pool( 19 const struct dc_init_data *init_data, 20 struct dc *dc); 21 22 bool dcn60_program_mcache_pipe_config(struct dc_state *context, 23 const struct dc_mcache_params *mcache_params); 24 25 bool dcn50_program_mcache_pipe_config(struct dc_state *context, 26 const struct dc_mcache_params *mcache_params); 27 28 /* HWSS */ 29 30 #define HWSEQ_DCN60_REG_LIST() \ 31 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 32 SR(DIO_MEM_PWR_CTRL), \ 33 SR(ODM_MEM_PWR_CTRL3), \ 34 SR(MMHUBBUB_MEM_PWR_CNTL), \ 35 SR(DCCG_GATE_DISABLE_CNTL), \ 36 SR(DCCG_GATE_DISABLE_CNTL2), \ 37 SR(DCFCLK_CNTL),\ 38 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 39 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 40 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 41 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 42 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 43 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 44 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 45 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 46 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 47 SR(MICROSECOND_TIME_BASE_DIV), \ 48 SR(MILLISECOND_TIME_BASE_DIV), \ 49 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 50 SR(RBBMIF_TIMEOUT_DIS), \ 51 SR(RBBMIF_TIMEOUT_DIS_2), \ 52 SR(DCHUBBUB_CRC_CTRL), \ 53 SR(DPP_TOP0_DPP_CRC_CTRL), \ 54 SR(MPC_CRC_CTRL), \ 55 SR(AZALIA_AUDIO_DTO), \ 56 SR(HPO_TOP_HW_CONTROL),\ 57 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 58 SR(HDCP_INTERRUPT_DEST) 59 60 /* HUBBUB */ 61 #define HUBBUB_REG_LIST_DCN60_RI(id) \ 62 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A), \ 63 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B), \ 64 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL), \ 65 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), \ 66 SR(DCHUBBUB_ARB_SAT_LEVEL), \ 67 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND), \ 68 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 69 SR(DCHUBBUB_TEST_DEBUG_INDEX), \ 70 SR(DCHUBBUB_TEST_DEBUG_DATA), \ 71 SR(DCHUBBUB_SOFT_RESET), \ 72 SR(DCHUBBUB_CRC_CTRL), \ 73 SR(DCN_VM_FB_LOCATION_BASE), \ 74 SR(DCN_VM_FB_LOCATION_TOP), \ 75 SR(DCN_VM_FB_OFFSET), \ 76 SR(DCN_VM_AGP_BOT), \ 77 SR(DCN_VM_AGP_TOP), \ 78 SR(DCN_VM_AGP_BASE), \ 79 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A), \ 80 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A), \ 81 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B), \ 82 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B), \ 83 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A), \ 84 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A), \ 85 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B), \ 86 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B), \ 87 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A), \ 88 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A), \ 89 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B), \ 90 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B), \ 91 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A), \ 92 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A), \ 93 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B), \ 94 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B), \ 95 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A), \ 96 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B), \ 97 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A), \ 98 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B), \ 99 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A), \ 100 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B), \ 101 SR(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A), \ 102 SR(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B), \ 103 SR(DCHUBBUB_DET0_CTRL), \ 104 SR(DCHUBBUB_DET1_CTRL), \ 105 SR(DCHUBBUB_DET2_CTRL), \ 106 SR(DCHUBBUB_DET3_CTRL), \ 107 SR(DCHUBBUB_COMPBUF_CTRL), \ 108 SR(COMPBUF_RESERVED_SPACE), \ 109 SR(DCHUBBUB_DEBUG_CTRL_0), \ 110 SR(DCHUBBUB_ARB_BUFFER_FULLNESS_WATERMARK_A), \ 111 SR(DCHUBBUB_ARB_BUFFER_FULLNESS_WATERMARK_B), \ 112 SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A), \ 113 SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B), \ 114 SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A), \ 115 SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B), \ 116 SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A), \ 117 SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B), \ 118 SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A), \ 119 SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B), \ 120 SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB), \ 121 SR(DCN_VM_FAULT_CNTL), \ 122 SR(DCN_VM_FAULT_STATUS), \ 123 SR(SDPIF_REQUEST_RATE_LIMIT), \ 124 SR(DCHUBBUB_CLOCK_CNTL), \ 125 SR(DCHUBBUB_SDPIF_CFG0), \ 126 SR(DCHUBBUB_SDPIF_CFG1), \ 127 SR(DCHUBBUB_MEM_PWR_MODE_CTRL), \ 128 SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL1), \ 129 SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL2), \ 130 SR(DCHUBBUB_CTRL_STATUS), \ 131 SR(DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL), \ 132 SR(DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2), \ 133 SR(DC_PERFMON5_PERFCOUNTER_CNTL), \ 134 SR(DC_PERFMON5_PERFCOUNTER_CNTL2), \ 135 SR(DC_PERFMON5_PERFCOUNTER_STATE), \ 136 SR(DC_PERFMON5_PERFMON_CNTL), \ 137 SR(DC_PERFMON5_PERFMON_CNTL2), \ 138 SR(DC_PERFMON5_PERFMON_CVALUE_INT_MISC), \ 139 SR(DC_PERFMON5_PERFMON_CVALUE_LOW), \ 140 SR(DC_PERFMON5_PERFMON_HI), \ 141 SR(DC_PERFMON5_PERFMON_LOW), \ 142 SR(FMON_CTRL), \ 143 SR(DCHUBBUB_ARB_QOS_FORCE) 144 145 /* HUBP */ 146 #define HUBP_REG_LIST_DCN60_RI(id) \ 147 SRI_ARR(NOM_PARAMETERS_0, HUBPREQ, id), \ 148 SRI_ARR(NOM_PARAMETERS_1, HUBPREQ, id), \ 149 SRI_ARR(NOM_PARAMETERS_2, HUBPREQ, id), \ 150 SRI_ARR(NOM_PARAMETERS_3, HUBPREQ, id), \ 151 SRI_ARR(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id), \ 152 SRI_ARR(DCHUBP_CNTL, HUBP, id), \ 153 SRI_ARR(HUBPREQ_DEBUG_DB, HUBP, id), \ 154 SRI_ARR(HUBPREQ_DEBUG, HUBP, id), \ 155 SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id), \ 156 SRI_ARR(DCSURF_LEGACY_ADDR_CONFIG, HUBP, id), \ 157 SRI_ARR(DCSURF_TILING_CONFIG, HUBP, id), \ 158 SRI_ARR(DCSURF_SURFACE_PITCH, HUBPREQ, id), \ 159 SRI_ARR(DCSURF_SURFACE_PITCH_C, HUBPREQ, id), \ 160 SRI_ARR(DCSURF_SURFACE_CONFIG, HUBP, id), \ 161 SRI_ARR(DCSURF_FLIP_CONTROL, HUBPREQ, id), \ 162 SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \ 163 SRI_ARR(DCSURF_PRI_VIEWPORT_START, HUBP, id), \ 164 SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \ 165 SRI_ARR(DCSURF_SEC_VIEWPORT_START, HUBP, id), \ 166 SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \ 167 SRI_ARR(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \ 168 SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \ 169 SRI_ARR(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \ 170 SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \ 171 SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id), \ 172 SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \ 173 SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id), \ 174 SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \ 175 SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id), \ 176 SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \ 177 SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id), \ 178 SRI_ARR(DCSURF_SURFACE_INUSE, HUBPREQ, id), \ 179 SRI_ARR(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id), \ 180 SRI_ARR(DCSURF_SURFACE_INUSE_C, HUBPREQ, id), \ 181 SRI_ARR(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id), \ 182 SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id), \ 183 SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id), \ 184 SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id), \ 185 SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id), \ 186 SRI_ARR(DCSURF_SURFACE_CONTROL, HUBPREQ, id), \ 187 SRI_ARR(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id), \ 188 SRI_ARR(HUBPRET_CONTROL, HUBPRET, id), \ 189 SRI_ARR(HUBPRET_READ_LINE_STATUS, HUBPRET, id), \ 190 SRI_ARR(DCN_EXPANSION_MODE, HUBPREQ, id), \ 191 SRI_ARR(DCHUBP_REQ_SIZE_CONFIG, HUBP, id), \ 192 SRI_ARR(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id), \ 193 SRI_ARR(BLANK_OFFSET_0, HUBPREQ, id), \ 194 SRI_ARR(BLANK_OFFSET_1, HUBPREQ, id), \ 195 SRI_ARR(DST_DIMENSIONS, HUBPREQ, id), \ 196 SRI_ARR(DST_AFTER_SCALER, HUBPREQ, id), \ 197 SRI_ARR(VBLANK_PARAMETERS_0, HUBPREQ, id), \ 198 SRI_ARR(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id), \ 199 SRI_ARR(VBLANK_PARAMETERS_1, HUBPREQ, id), \ 200 SRI_ARR(VBLANK_PARAMETERS_3, HUBPREQ, id), \ 201 SRI_ARR(NOM_PARAMETERS_4, HUBPREQ, id), \ 202 SRI_ARR(NOM_PARAMETERS_5, HUBPREQ, id), \ 203 SRI_ARR(PER_LINE_DELIVERY_PRE, HUBPREQ, id), \ 204 SRI_ARR(PER_LINE_DELIVERY, HUBPREQ, id), \ 205 SRI_ARR(VBLANK_PARAMETERS_2, HUBPREQ, id), \ 206 SRI_ARR(VBLANK_PARAMETERS_4, HUBPREQ, id), \ 207 SRI_ARR(NOM_PARAMETERS_6, HUBPREQ, id), \ 208 SRI_ARR(NOM_PARAMETERS_7, HUBPREQ, id), \ 209 SRI_ARR(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id), \ 210 SRI_ARR(DCN_SURF0_TTU_CNTL0, HUBPREQ, id), \ 211 SRI_ARR(DCN_SURF0_TTU_CNTL1, HUBPREQ, id), \ 212 SRI_ARR(DCN_SURF1_TTU_CNTL0, HUBPREQ, id), \ 213 SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id), \ 214 SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id), \ 215 SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id), \ 216 SRI_ARR(HUBP_CLK_CNTL, HUBP, id), \ 217 SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id), \ 218 SRI_ARR(PREFETCH_SETTINGS_C, HUBPREQ, id), \ 219 SRI_ARR(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id), \ 220 SRI_ARR(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id), \ 221 SRI_ARR(CURSOR_SETTINGS, HUBPREQ, id), \ 222 SRI_ARR(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \ 223 SRI_ARR(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \ 224 SRI_ARR(CURSOR_SIZE, CURSOR0_, id), \ 225 SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \ 226 SRI_ARR(CURSOR_POSITION, CURSOR0_, id), \ 227 SRI_ARR(CURSOR_HOT_SPOT, CURSOR0_, id), \ 228 SRI_ARR(CURSOR_DST_OFFSET, CURSOR0_, id), \ 229 SRI_ARR(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \ 230 SRI_ARR(DMDATA_ADDRESS_LOW, CURSOR0_, id), \ 231 SRI_ARR(DMDATA_CNTL, CURSOR0_, id), \ 232 SRI_ARR(DMDATA_SW_CNTL, CURSOR0_, id), \ 233 SRI_ARR(DMDATA_QOS_CNTL, CURSOR0_, id), \ 234 SRI_ARR(DMDATA_SW_DATA, CURSOR0_, id), \ 235 SRI_ARR(DMDATA_STATUS, CURSOR0_, id), \ 236 SRI_ARR(FLIP_PARAMETERS_0, HUBPREQ, id), \ 237 SRI_ARR(FLIP_PARAMETERS_1, HUBPREQ, id), \ 238 SRI_ARR(FLIP_PARAMETERS_2, HUBPREQ, id), \ 239 SRI_ARR(DCN_CUR1_TTU_CNTL0, HUBPREQ, id), \ 240 SRI_ARR(DCN_CUR1_TTU_CNTL1, HUBPREQ, id), \ 241 SRI_ARR(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \ 242 SRI_ARR(VMID_SETTINGS_0, HUBPREQ, id), \ 243 SRI_ARR(FLIP_PARAMETERS_3, HUBPREQ, id), \ 244 SRI_ARR(FLIP_PARAMETERS_4, HUBPREQ, id), \ 245 SRI_ARR(FLIP_PARAMETERS_5, HUBPREQ, id), \ 246 SRI_ARR(FLIP_PARAMETERS_6, HUBPREQ, id), \ 247 SRI_ARR(VBLANK_PARAMETERS_5, HUBPREQ, id), \ 248 SRI_ARR(VBLANK_PARAMETERS_6, HUBPREQ, id), \ 249 SRI_ARR(DCN_DMDATA_VM_CNTL, HUBPREQ, id), \ 250 SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \ 251 SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \ 252 HUBP_3DLUT_FL_REG_LIST_DCN401(id), \ 253 SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id), \ 254 SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id), \ 255 SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id), \ 256 SRI_ARR(DST_Y_DELTA_DRQ_LIMIT, HUBPREQ, id), \ 257 SRI_ARR(DST_Y_ALT_CH_DRQ_LIMIT, HUBPREQ, id) 258 259 /* DPP */ 260 #define DPP_REG_LIST_DCN60_RI(id) \ 261 SRI_ARR(CM_DEALPHA, CM, id), \ 262 SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \ 263 SRI_ARR(CM_BIAS_CR_R, CM, id), \ 264 SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \ 265 SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \ 266 SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \ 267 SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \ 268 SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \ 269 SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \ 270 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id), \ 271 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id), \ 272 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id), \ 273 SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id), \ 274 SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id), \ 275 SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id), \ 276 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id), \ 277 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id), \ 278 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id), \ 279 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id), \ 280 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id), \ 281 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id), \ 282 SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id), \ 283 SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id), \ 284 SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id), \ 285 SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id), \ 286 SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id), \ 287 SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id), \ 288 SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id), \ 289 SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id), \ 290 SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id), \ 291 SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id), \ 292 SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id), \ 293 SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id), \ 294 SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id), \ 295 SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id), \ 296 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id), \ 297 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id), \ 298 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id), \ 299 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id), \ 300 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id), \ 301 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id), \ 302 SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id), \ 303 SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id), \ 304 SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id), \ 305 SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id), \ 306 SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id), \ 307 SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id), \ 308 SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id), \ 309 SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id), \ 310 SRI_ARR(CM_HIST_CNTL, CM, id), \ 311 SRI_ARR(CM_HIST_LOCK, CM, id), \ 312 SRI_ARR(CM_HIST_INDEX, CM, id), \ 313 SRI_ARR(CM_HIST_DATA, CM, id), \ 314 SRI_ARR(CM_HIST_STATUS, CM, id), \ 315 SRI_ARR(CM_HIST_SCALE_SRC1, CM, id), \ 316 SRI_ARR(CM_HIST_COEFA_SRC2, CM, id), \ 317 SRI_ARR(CM_HIST_COEFB_SRC2, CM, id), \ 318 SRI_ARR(CM_HIST_COEFC_SRC2, CM, id), \ 319 SRI_ARR(CM_HIST_SCALE_SRC3, CM, id), \ 320 SRI_ARR(CM_HIST_BIAS_SRC1, CM, id), \ 321 SRI_ARR(CM_HIST_BIAS_SRC2, CM, id), \ 322 SRI_ARR(CM_HIST_BIAS_SRC3, CM, id), \ 323 SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \ 324 SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \ 325 SRI_ARR(OTG_H_BLANK, DSCL, id), \ 326 SRI_ARR(OTG_V_BLANK, DSCL, id), \ 327 SRI_ARR(SCL_MODE, DSCL, id), \ 328 SRI_ARR(LB_DATA_FORMAT, DSCL, id), \ 329 SRI_ARR(LB_MEMORY_CTRL, DSCL, id), \ 330 SRI_ARR(DSCL_AUTOCAL, DSCL, id), \ 331 SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \ 332 SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \ 333 SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id), \ 334 SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), \ 335 SRI_ARR(MPC_SIZE, DSCL, id), \ 336 SRI_ARR(SCL_BLACK_COLOR, DSCL, id), \ 337 SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \ 338 SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \ 339 SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \ 340 SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \ 341 SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id), \ 342 SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id), \ 343 SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id), \ 344 SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id), \ 345 SRI_ARR(RECOUT_START, DSCL, id), \ 346 SRI_ARR(RECOUT_SIZE, DSCL, id), \ 347 SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), \ 348 SRI_ARR(PRE_REALPHA, CNVC_CFG, id), \ 349 SRI_ARR(PRE_GAM, CNVC_CFG, id), \ 350 SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id), \ 351 SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id), \ 352 SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id), \ 353 SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id), \ 354 SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id), \ 355 SRI_ARR(CM_POST_CSC_CONTROL, CM, id), \ 356 SRI_ARR(CM_POST_CSC_C11_C12, CM, id), \ 357 SRI_ARR(CM_POST_CSC_C33_C34, CM, id), \ 358 SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \ 359 SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \ 360 SRI_ARR(CM_MEM_PWR_CTRL, CM, id), \ 361 SRI_ARR(CM_CONTROL, CM, id), \ 362 SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id), \ 363 SRI_ARR(CM_TEST_DEBUG_DATA, CM, id), \ 364 SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \ 365 SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ 366 SRI_ARR(CURSOR0_CONTROL, CM_CUR, id), \ 367 SRI_ARR(CURSOR0_COLOR0, CM_CUR, id), \ 368 SRI_ARR(CURSOR0_COLOR1, CM_CUR, id), \ 369 SRI_ARR(CURSOR0_FP_SCALE_BIAS_G_Y, CM_CUR, id), \ 370 SRI_ARR(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CM_CUR, id), \ 371 SRI_ARR(CUR0_MATRIX_MODE, CM_CUR, id), \ 372 SRI_ARR(CUR0_MATRIX_C11_C12_A, CM_CUR, id), \ 373 SRI_ARR(CUR0_MATRIX_C13_C14_A, CM_CUR, id), \ 374 SRI_ARR(CUR0_MATRIX_C21_C22_A, CM_CUR, id), \ 375 SRI_ARR(CUR0_MATRIX_C23_C24_A, CM_CUR, id), \ 376 SRI_ARR(CUR0_MATRIX_C31_C32_A, CM_CUR, id), \ 377 SRI_ARR(CUR0_MATRIX_C33_C34_A, CM_CUR, id), \ 378 SRI_ARR(CUR0_MATRIX_C11_C12_B, CM_CUR, id), \ 379 SRI_ARR(CUR0_MATRIX_C13_C14_B, CM_CUR, id), \ 380 SRI_ARR(CUR0_MATRIX_C21_C22_B, CM_CUR, id), \ 381 SRI_ARR(CUR0_MATRIX_C23_C24_B, CM_CUR, id), \ 382 SRI_ARR(CUR0_MATRIX_C31_C32_B, CM_CUR, id), \ 383 SRI_ARR(CUR0_MATRIX_C33_C34_B, CM_CUR, id), \ 384 SRI_ARR(DPP_CONTROL, DPP_TOP, id), \ 385 SRI_ARR(CM_HDR_MULT_COEF, CM, id), \ 386 SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \ 387 SRI_ARR(ALPHA_2BIT_LUT01, CNVC_CFG, id), \ 388 SRI_ARR(ALPHA_2BIT_LUT23, CNVC_CFG, id), \ 389 SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id), \ 390 SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id), \ 391 SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id), \ 392 SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id), \ 393 SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id), \ 394 SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id), \ 395 SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id), \ 396 SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id), \ 397 SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id), \ 398 SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id), \ 399 SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id), \ 400 SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id), \ 401 SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id), \ 402 SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id), \ 403 SRI_ARR(DSCL_CONTROL, DSCL, id), \ 404 SRI_ARR(DSCL_SC_MODE, DSCL, id), \ 405 SRI_ARR(DSCL_EASF_H_MODE, DSCL, id), \ 406 SRI_ARR(DSCL_EASF_H_BF_CNTL, DSCL, id), \ 407 SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, DSCL, id), \ 408 SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, DSCL, id), \ 409 SRI_ARR(DSCL_EASF_H_BF_FINAL_MAX_MIN, DSCL, id), \ 410 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG0, DSCL, id), \ 411 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG1, DSCL, id), \ 412 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG2, DSCL, id), \ 413 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG3, DSCL, id), \ 414 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG4, DSCL, id), \ 415 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG5, DSCL, id), \ 416 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG6, DSCL, id), \ 417 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG7, DSCL, id), \ 418 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG0, DSCL, id), \ 419 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG1, DSCL, id), \ 420 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG2, DSCL, id), \ 421 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG3, DSCL, id), \ 422 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG4, DSCL, id), \ 423 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG5, DSCL, id), \ 424 SRI_ARR(DSCL_EASF_V_MODE, DSCL, id), \ 425 SRI_ARR(DSCL_EASF_V_BF_CNTL, DSCL, id), \ 426 SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL1, DSCL, id), \ 427 SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL2, DSCL, id), \ 428 SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL3, DSCL, id), \ 429 SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, DSCL, id), \ 430 SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, DSCL, id), \ 431 SRI_ARR(DSCL_EASF_V_BF_FINAL_MAX_MIN, DSCL, id), \ 432 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG0, DSCL, id), \ 433 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG1, DSCL, id), \ 434 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG2, DSCL, id), \ 435 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG3, DSCL, id), \ 436 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG4, DSCL, id), \ 437 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG5, DSCL, id), \ 438 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG6, DSCL, id), \ 439 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG7, DSCL, id), \ 440 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG0, DSCL, id), \ 441 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG1, DSCL, id), \ 442 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG2, DSCL, id), \ 443 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG3, DSCL, id), \ 444 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG4, DSCL, id), \ 445 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id), \ 446 SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id), \ 447 SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id), \ 448 SRI_ARR(ISHARP_MODE, DSCL, id), \ 449 SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id), \ 450 SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id), \ 451 SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id), \ 452 SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id), \ 453 SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id), \ 454 SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id), \ 455 SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id), \ 456 SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id), \ 457 SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id), \ 458 SRI_ARR(ISHARP_DELTA_DATA, DSCL, id), \ 459 SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id), \ 460 SRI_ARR(ISHARP_DELTA_LUT_MEM_PWR_CTRL, DSCL, id), \ 461 SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id) 462 463 /* Stream encoder */ 464 #define SE_REG_LIST_DCN60_RI(id) \ 465 SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \ 466 SRI_ARR(HDMI_GC, DIG, id), \ 467 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ 468 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \ 469 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \ 470 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \ 471 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \ 472 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \ 473 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \ 474 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \ 475 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \ 476 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \ 477 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \ 478 SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \ 479 SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \ 480 SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id), \ 481 SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \ 482 SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \ 483 SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \ 484 SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \ 485 SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \ 486 SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \ 487 SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \ 488 SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \ 489 SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \ 490 SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \ 491 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \ 492 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \ 493 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \ 494 SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \ 495 SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \ 496 SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \ 497 SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \ 498 SRI_ARR(DP_SEC_TIMESTAMP, DP, id), \ 499 SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \ 500 SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ 501 SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id), \ 502 SRI_ARR(DME_CONTROL, DME, id), \ 503 SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \ 504 SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ 505 SRI_ARR(DIG_FE_CNTL, DIG, id), \ 506 SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \ 507 SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \ 508 SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \ 509 SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \ 510 SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id), \ 511 SRI_ARR(DIG_FE_AUDIO_CNTL, DIG, id) 512 513 /* DCCG */ 514 #define DCCG_REG_LIST_DCN60_RI() \ 515 SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0), \ 516 DCCG_SRII(DTO_PARAM, DPPCLK, 1), DCCG_SRII(DTO_PARAM, DPPCLK, 2), \ 517 DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \ 518 SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL), \ 519 SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL), \ 520 SR(DPSTREAMCLK_CNTL), SR(HDMISTREAMCLK_CNTL), \ 521 SR(SYMCLK32_SE_CNTL), SR(SYMCLK32_LE_CNTL), \ 522 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \ 523 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \ 524 SR(OTG_PIXEL_RATE_DIV), SR(DTBCLK_P_CNTL), \ 525 SR(DCCG_AUDIO_DTO_SOURCE), \ 526 SR(DPPCLK_CTRL), \ 527 DCCG_SRII(MODULO, DP_DTO, 0), DCCG_SRII(MODULO, DP_DTO, 1), \ 528 DCCG_SRII(MODULO, DP_DTO, 2), DCCG_SRII(MODULO, DP_DTO, 3), \ 529 DCCG_SRII(PHASE, DP_DTO, 0), DCCG_SRII(PHASE, DP_DTO, 1), \ 530 DCCG_SRII(PHASE, DP_DTO, 2), DCCG_SRII(PHASE, DP_DTO, 3), \ 531 SR(OTG_ADD_DROP_PIXEL_CNTL), \ 532 SR(DSCCLK0_DTO_PARAM), \ 533 SR(DSCCLK1_DTO_PARAM), \ 534 SR(DSCCLK2_DTO_PARAM), \ 535 SR(DSCCLK3_DTO_PARAM), \ 536 SR(DSCCLK_DTO_CTRL), \ 537 SR(DCCG_GATE_DISABLE_CNTL), \ 538 SR(DCCG_GATE_DISABLE_CNTL2), \ 539 SR(DCCG_GATE_DISABLE_CNTL3), \ 540 SR(DCCG_GATE_DISABLE_CNTL4), \ 541 SR(DCCG_GATE_DISABLE_CNTL5), \ 542 SR(DCCG_GATE_DISABLE_CNTL6), \ 543 SR(SYMCLKA_CLOCK_ENABLE), \ 544 SR(SYMCLKB_CLOCK_ENABLE), \ 545 SR(SYMCLKC_CLOCK_ENABLE), \ 546 SR(SYMCLKD_CLOCK_ENABLE), \ 547 SR(DSCCLK_SRC_SEL) 548 549 /* HPO FRL stream encoder */ 550 #define DCN60_HPO_FRL_STREAM_ENC_REG_LIST_RI(id) \ 551 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id), \ 552 SR_ARR(HDMI_STREAM_ENC_AUDIO_CONTROL, id) 553 554 #define DCN60_AUX_REG_LIST_RI(id, ddc_id) \ 555 DCN2_AUX_REG_LIST_RI(id), \ 556 SRI_ARR_DDC(DC_GPIO_DDC, MASK, ddc_id) 557 558 /* HPD */ 559 #define HPD_REG_LIST_DCN60_RI(id) \ 560 HPD_REG_LIST_RI(id), \ 561 SR_ARR(HPD_CTRL, id) 562 563 /* DSC */ 564 #define DSC_REG_LIST_DCN60_RI(id) \ 565 SRI_ARR(DSC_TOP_CONTROL, DSC_TOP, id), \ 566 SRI_ARR(DSC_DEBUG_CONTROL, DSC_TOP, id), \ 567 SRI_ARR(DSCC_CONFIG0, DSCC, id), SRI_ARR(DSCC_CONFIG1, DSCC, id), \ 568 SRI_ARR(DSCC_STATUS, DSCC, id), \ 569 SRI_ARR(DSCC_INTERRUPT_CONTROL0, DSCC, id), \ 570 SRI_ARR(DSCC_INTERRUPT_CONTROL1, DSCC, id), \ 571 SRI_ARR(DSCC_INTERRUPT_STATUS0, DSCC, id), \ 572 SRI_ARR(DSCC_INTERRUPT_STATUS1, DSCC, id), \ 573 SRI_ARR(DSCC_PPS_CONFIG0, DSCC, id), \ 574 SRI_ARR(DSCC_PPS_CONFIG1, DSCC, id), \ 575 SRI_ARR(DSCC_PPS_CONFIG2, DSCC, id), \ 576 SRI_ARR(DSCC_PPS_CONFIG3, DSCC, id), \ 577 SRI_ARR(DSCC_PPS_CONFIG4, DSCC, id), \ 578 SRI_ARR(DSCC_PPS_CONFIG5, DSCC, id), \ 579 SRI_ARR(DSCC_PPS_CONFIG6, DSCC, id), \ 580 SRI_ARR(DSCC_PPS_CONFIG7, DSCC, id), \ 581 SRI_ARR(DSCC_PPS_CONFIG8, DSCC, id), \ 582 SRI_ARR(DSCC_PPS_CONFIG9, DSCC, id), \ 583 SRI_ARR(DSCC_PPS_CONFIG10, DSCC, id), \ 584 SRI_ARR(DSCC_PPS_CONFIG11, DSCC, id), \ 585 SRI_ARR(DSCC_PPS_CONFIG12, DSCC, id), \ 586 SRI_ARR(DSCC_PPS_CONFIG13, DSCC, id), \ 587 SRI_ARR(DSCC_PPS_CONFIG14, DSCC, id), \ 588 SRI_ARR(DSCC_PPS_CONFIG15, DSCC, id), \ 589 SRI_ARR(DSCC_PPS_CONFIG16, DSCC, id), \ 590 SRI_ARR(DSCC_PPS_CONFIG17, DSCC, id), \ 591 SRI_ARR(DSCC_PPS_CONFIG18, DSCC, id), \ 592 SRI_ARR(DSCC_PPS_CONFIG19, DSCC, id), \ 593 SRI_ARR(DSCC_PPS_CONFIG20, DSCC, id), \ 594 SRI_ARR(DSCC_PPS_CONFIG21, DSCC, id), \ 595 SRI_ARR(DSCC_PPS_CONFIG22, DSCC, id), \ 596 SRI_ARR(DSCC_MEM_POWER_CONTROL0, DSCC, id), \ 597 SRI_ARR(DSCC_MEM_POWER_CONTROL1, DSCC, id), \ 598 SRI_ARR(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id), \ 599 SRI_ARR(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id) 600 601 /* OPTC */ 602 #define OPTC_COMMON_REG_LIST_DCN60_RI(inst) \ 603 SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \ 604 SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \ 605 SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \ 606 SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \ 607 SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \ 608 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \ 609 SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \ 610 SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \ 611 SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \ 612 SRI_ARR(OTG_H_TOTAL, OTG, inst), \ 613 SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \ 614 SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \ 615 SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \ 616 SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \ 617 SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \ 618 SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \ 619 SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \ 620 SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \ 621 SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \ 622 SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \ 623 SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \ 624 SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \ 625 SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \ 626 SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \ 627 SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \ 628 SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \ 629 SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \ 630 SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \ 631 SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \ 632 SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \ 633 SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \ 634 SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \ 635 SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \ 636 SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \ 637 SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \ 638 SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \ 639 SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \ 640 SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \ 641 SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \ 642 SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \ 643 SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \ 644 SRI_ARR(OTG_CRC0_DATA_R, OTG, inst), \ 645 SRI_ARR(OTG_CRC0_DATA_G, OTG, inst), \ 646 SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \ 647 SRI_ARR(OTG_CRC1_DATA_R, OTG, inst), \ 648 SRI_ARR(OTG_CRC1_DATA_G, OTG, inst), \ 649 SRI_ARR(OTG_CRC1_DATA_B, OTG, inst), \ 650 SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \ 651 SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \ 652 SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \ 653 SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \ 654 SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst), \ 655 SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst), \ 656 SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst), \ 657 SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst), \ 658 SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \ 659 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \ 660 SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \ 661 SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \ 662 SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \ 663 SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \ 664 SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \ 665 SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \ 666 SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \ 667 SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \ 668 SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \ 669 SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \ 670 SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \ 671 SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ 672 SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \ 673 SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),\ 674 SRI_ARR(INTERRUPT_DEST, OTG, inst) 675 676 #endif /* _DCN60_RESOURCE_H_ */ 677