1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef _DCN42_RESOURCE_H_ 28 #define _DCN42_RESOURCE_H_ 29 30 #include "core_types.h" 31 32 #define TO_DCN42_RES_POOL(pool) \ 33 container_of(pool, struct dcn42_resource_pool, base) 34 35 /* DPP */ 36 #define DPP_REG_LIST_DCN42_COMMON_RI(id) \ 37 SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \ 38 SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \ 39 SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \ 40 SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \ 41 SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \ 42 SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \ 43 SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \ 44 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id), \ 45 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id), \ 46 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id), \ 47 SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id), \ 48 SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id), \ 49 SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id), \ 50 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id), \ 51 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id), \ 52 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id), \ 53 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id), \ 54 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id), \ 55 SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id), \ 56 SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id), \ 57 SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id), \ 58 SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id), \ 59 SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id), \ 60 SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id), \ 61 SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id), \ 62 SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id), \ 63 SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id), \ 64 SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id), \ 65 SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id), \ 66 SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id), \ 67 SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id), \ 68 SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id), \ 69 SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id), \ 70 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id), \ 71 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id), \ 72 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id), \ 73 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id), \ 74 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id), \ 75 SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id), \ 76 SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id), \ 77 SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id), \ 78 SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id), \ 79 SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id), \ 80 SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id), \ 81 SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id), \ 82 SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id), \ 83 SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id), \ 84 SRI_ARR(CM_HIST_CNTL, CM, id), \ 85 SRI_ARR(CM_HIST_LOCK, CM, id), \ 86 SRI_ARR(CM_HIST_INDEX, CM, id), \ 87 SRI_ARR(CM_HIST_DATA, CM, id), \ 88 SRI_ARR(CM_HIST_STATUS, CM, id), \ 89 SRI_ARR(CM_HIST_SCALE_SRC1, CM, id), \ 90 SRI_ARR(CM_HIST_COEFA_SRC2, CM, id), \ 91 SRI_ARR(CM_HIST_COEFB_SRC2, CM, id), \ 92 SRI_ARR(CM_HIST_COEFC_SRC2, CM, id), \ 93 SRI_ARR(CM_HIST_SCALE_SRC3, CM, id), \ 94 SRI_ARR(CM_HIST_BIAS_SRC1, CM, id), \ 95 SRI_ARR(CM_HIST_BIAS_SRC2, CM, id), \ 96 SRI_ARR(CM_HIST_BIAS_SRC3, CM, id), \ 97 SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \ 98 SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \ 99 SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id), \ 100 SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id), \ 101 SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \ 102 SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \ 103 SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \ 104 SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id), \ 105 SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id), \ 106 SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \ 107 SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \ 108 SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \ 109 SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \ 110 SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id), \ 111 SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id), \ 112 SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id), \ 113 SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id), \ 114 SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id), \ 115 SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id), \ 116 SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id), \ 117 SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id), \ 118 SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id), \ 119 SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id), \ 120 SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id), \ 121 SRI_ARR(CM_POST_CSC_CONTROL, CM, id), \ 122 SRI_ARR(CM_POST_CSC_C11_C12, CM, id), \ 123 SRI_ARR(CM_POST_CSC_C33_C34, CM, id), \ 124 SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \ 125 SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \ 126 SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id), \ 127 SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id), \ 128 SRI_ARR(CM_TEST_DEBUG_DATA, CM, id), \ 129 SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \ 130 SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ 131 SRI_ARR(CURSOR0_CONTROL, CM_CUR, id), \ 132 SRI_ARR(CURSOR0_COLOR0, CM_CUR, id), \ 133 SRI_ARR(CURSOR0_COLOR1, CM_CUR, id), \ 134 SRI_ARR(CURSOR0_FP_SCALE_BIAS_G_Y, CM_CUR, id), \ 135 SRI_ARR(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CM_CUR, id), \ 136 SRI_ARR(CUR0_MATRIX_MODE, CM_CUR, id), \ 137 SRI_ARR(CUR0_MATRIX_C11_C12_A, CM_CUR, id), \ 138 SRI_ARR(CUR0_MATRIX_C13_C14_A, CM_CUR, id), \ 139 SRI_ARR(CUR0_MATRIX_C21_C22_A, CM_CUR, id), \ 140 SRI_ARR(CUR0_MATRIX_C23_C24_A, CM_CUR, id), \ 141 SRI_ARR(CUR0_MATRIX_C31_C32_A, CM_CUR, id), \ 142 SRI_ARR(CUR0_MATRIX_C33_C34_A, CM_CUR, id), \ 143 SRI_ARR(CUR0_MATRIX_C11_C12_B, CM_CUR, id), \ 144 SRI_ARR(CUR0_MATRIX_C13_C14_B, CM_CUR, id), \ 145 SRI_ARR(CUR0_MATRIX_C21_C22_B, CM_CUR, id), \ 146 SRI_ARR(CUR0_MATRIX_C23_C24_B, CM_CUR, id), \ 147 SRI_ARR(CUR0_MATRIX_C31_C32_B, CM_CUR, id), \ 148 SRI_ARR(CUR0_MATRIX_C33_C34_B, CM_CUR, id), \ 149 SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id), \ 150 SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \ 151 SRI_ARR(ALPHA_2BIT_LUT01, CNVC_CFG, id), \ 152 SRI_ARR(ALPHA_2BIT_LUT23, CNVC_CFG, id), \ 153 SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id), \ 154 SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id), \ 155 SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id), \ 156 SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id), \ 157 SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id), \ 158 SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id), \ 159 SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id), \ 160 SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id), \ 161 SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id), \ 162 SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id), \ 163 SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id), \ 164 SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id), \ 165 SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id), \ 166 SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id), \ 167 SRI_ARR(DSCL_CONTROL, DSCL, id), \ 168 SRI_ARR(DSCL_SC_MODE, DSCL, id), \ 169 SRI_ARR(DSCL_EASF_H_MODE, DSCL, id), \ 170 SRI_ARR(DSCL_EASF_H_BF_CNTL, DSCL, id), \ 171 SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, DSCL, id), \ 172 SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, DSCL, id), \ 173 SRI_ARR(DSCL_EASF_H_BF_FINAL_MAX_MIN, DSCL, id), \ 174 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG0, DSCL, id), \ 175 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG1, DSCL, id), \ 176 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG2, DSCL, id), \ 177 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG3, DSCL, id), \ 178 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG4, DSCL, id), \ 179 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG5, DSCL, id), \ 180 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG6, DSCL, id), \ 181 SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG7, DSCL, id), \ 182 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG0, DSCL, id), \ 183 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG1, DSCL, id), \ 184 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG2, DSCL, id), \ 185 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG3, DSCL, id), \ 186 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG4, DSCL, id), \ 187 SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG5, DSCL, id), \ 188 SRI_ARR(DSCL_EASF_V_MODE, DSCL, id), \ 189 SRI_ARR(DSCL_EASF_V_BF_CNTL, DSCL, id), \ 190 SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL1, DSCL, id), \ 191 SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL2, DSCL, id), \ 192 SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL3, DSCL, id), \ 193 SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, DSCL, id), \ 194 SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, DSCL, id), \ 195 SRI_ARR(DSCL_EASF_V_BF_FINAL_MAX_MIN, DSCL, id), \ 196 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG0, DSCL, id), \ 197 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG1, DSCL, id), \ 198 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG2, DSCL, id), \ 199 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG3, DSCL, id), \ 200 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG4, DSCL, id), \ 201 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG5, DSCL, id), \ 202 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG6, DSCL, id), \ 203 SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG7, DSCL, id), \ 204 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG0, DSCL, id), \ 205 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG1, DSCL, id), \ 206 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG2, DSCL, id), \ 207 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG3, DSCL, id), \ 208 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG4, DSCL, id), \ 209 SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id), \ 210 SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id), \ 211 SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id), \ 212 SRI_ARR(ISHARP_MODE, DSCL, id), \ 213 SRI_ARR(ISHARP_DELTA_LUT_MEM_PWR_CTRL, DSCL, id), \ 214 SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id), \ 215 SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id), \ 216 SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id), \ 217 SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id), \ 218 SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id), \ 219 SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id), \ 220 SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id), \ 221 SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id), \ 222 SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id), \ 223 SRI_ARR(ISHARP_DELTA_DATA, DSCL, id), \ 224 SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id), \ 225 SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id), \ 226 SRI_ARR(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \ 227 SRI_ARR(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id) 228 229 /* Stream encoder */ 230 #define SE_DCN42_REG_LIST_RI(id) \ 231 SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \ 232 SRI_ARR(HDMI_GC, DIG, id), \ 233 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ 234 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \ 235 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \ 236 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \ 237 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \ 238 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \ 239 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \ 240 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \ 241 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \ 242 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \ 243 SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \ 244 SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \ 245 SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \ 246 SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id), \ 247 SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \ 248 SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \ 249 SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \ 250 SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \ 251 SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \ 252 SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \ 253 SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \ 254 SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \ 255 SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \ 256 SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \ 257 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \ 258 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \ 259 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \ 260 SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \ 261 SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \ 262 SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \ 263 SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \ 264 SRI_ARR(DP_SEC_TIMESTAMP, DP, id), \ 265 SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \ 266 SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ 267 SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id), \ 268 SRI_ARR(DME_CONTROL, DME, id), \ 269 SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \ 270 SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ 271 SRI_ARR(DIG_FE_CNTL, DIG, id), \ 272 SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \ 273 SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \ 274 SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \ 275 SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \ 276 SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id),\ 277 SRI_ARR(DIG_FE_AUDIO_CNTL, DIG, id) 278 279 /* HPO DP stream encoder */ 280 #define DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id) \ 281 SR_ARR(DP_STREAM_MAPPER_CONTROL0, id), \ 282 SR_ARR(DP_STREAM_MAPPER_CONTROL1, id), \ 283 SR_ARR(DP_STREAM_MAPPER_CONTROL2, id), \ 284 SR_ARR(DP_STREAM_MAPPER_CONTROL3, id), \ 285 SRI_ARR(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id), \ 286 SRI_ARR(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id), \ 287 SRI_ARR(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id), \ 288 SRI_ARR(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id), \ 289 SRI_ARR(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id), \ 290 SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id), \ 291 SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \ 292 SRI_ARR(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id), \ 293 SRI_ARR(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id), \ 294 SRI_ARR(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id), \ 295 SRI_ARR(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id), \ 296 SRI_ARR(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id), \ 297 SRI_ARR(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id), \ 298 SRI_ARR(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id), \ 299 SRI_ARR(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id), \ 300 SRI_ARR(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id), \ 301 SRI_ARR(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id), \ 302 SRI_ARR(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \ 303 SRI_ARR(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id), \ 304 SRI_ARR(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id), \ 305 SRI_ARR(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id), \ 306 SRI_ARR(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id), \ 307 SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id), \ 308 SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id), \ 309 SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id), \ 310 SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id), \ 311 SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id), \ 312 SRI_ARR(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id), \ 313 SRI_ARR(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id), \ 314 SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \ 315 SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id) 316 317 /*HPO DP link encoder regs */ 318 #define DCN42_HPO_DP_LINK_ENC_REG_LIST_RI(id) \ 319 SRI_ARR(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \ 320 SRI_ARR(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \ 321 SRI_ARR(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \ 322 SRI_ARR(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \ 323 SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \ 324 SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \ 325 SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \ 326 SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \ 327 SRI_ARR(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id), \ 328 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \ 329 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \ 330 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id), \ 331 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id), \ 332 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id), \ 333 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id), \ 334 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id), \ 335 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id), \ 336 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id), \ 337 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id), \ 338 SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id), \ 339 SRI_ARR(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \ 340 SRI_ARR(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \ 341 SRI_ARR(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \ 342 SRI_ARR(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \ 343 SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \ 344 SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \ 345 SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \ 346 SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \ 347 SRI_ARR(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id) 348 349 #define VPG_DCN42_REG_LIST_RI(id) \ 350 SRI(VPG_GENERIC_STATUS, VPG, id), \ 351 SRI(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \ 352 SRI(VPG_GENERIC_PACKET_DATA, VPG, id), \ 353 SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \ 354 SRI(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \ 355 SRI(VPG_MEM_PWR, VPG, id) 356 357 /* DCCG */ 358 #define DCCG_REG_LIST_DCN42_RI() \ 359 SR(DPPCLK_DTO_CTRL), \ 360 DCCG_SRII(DTO_PARAM, DPPCLK, 0), \ 361 DCCG_SRII(DTO_PARAM, DPPCLK, 1), \ 362 DCCG_SRII(DTO_PARAM, DPPCLK, 2), \ 363 DCCG_SRII(DTO_PARAM, DPPCLK, 3), \ 364 DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \ 365 SR(HDMISTREAMCLK0_DTO_PARAM),\ 366 SR(DCCG_GLOBAL_FGCG_REP_CNTL),\ 367 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 368 SR(PHYASYMCLK_CLOCK_CNTL), \ 369 SR(PHYBSYMCLK_CLOCK_CNTL), \ 370 SR(PHYCSYMCLK_CLOCK_CNTL), \ 371 SR(PHYDSYMCLK_CLOCK_CNTL), \ 372 SR(PHYESYMCLK_CLOCK_CNTL), \ 373 SR(DPSTREAMCLK_CNTL), \ 374 SR(HDMISTREAMCLK_CNTL), \ 375 SR(SYMCLK32_SE_CNTL), \ 376 SR(SYMCLK32_LE_CNTL), \ 377 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), \ 378 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \ 379 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), \ 380 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \ 381 SR(OTG_PIXEL_RATE_DIV), \ 382 SR(DTBCLK_P_CNTL), \ 383 SR(DCCG_AUDIO_DTO_SOURCE), \ 384 SR(DENTIST_DISPCLK_CNTL), \ 385 SR(DPPCLK_CTRL), \ 386 DCCG_SRII(MODULO, DP_DTO, 0), \ 387 DCCG_SRII(MODULO, DP_DTO, 1), \ 388 DCCG_SRII(MODULO, DP_DTO, 2), \ 389 DCCG_SRII(MODULO, DP_DTO, 3), \ 390 DCCG_SRII(PHASE, DP_DTO, 0), \ 391 DCCG_SRII(PHASE, DP_DTO, 1), \ 392 DCCG_SRII(PHASE, DP_DTO, 2), \ 393 DCCG_SRII(PHASE, DP_DTO, 3), \ 394 SR(OTG_ADD_DROP_PIXEL_CNTL), \ 395 SR(DSCCLK0_DTO_PARAM), \ 396 SR(DSCCLK1_DTO_PARAM), \ 397 SR(DSCCLK2_DTO_PARAM), \ 398 SR(DSCCLK3_DTO_PARAM), \ 399 SR(DSCCLK_DTO_CTRL), \ 400 SR(DCCG_GATE_DISABLE_CNTL), \ 401 SR(DCCG_GATE_DISABLE_CNTL2), \ 402 SR(DCCG_GATE_DISABLE_CNTL3), \ 403 SR(DCCG_GATE_DISABLE_CNTL4), \ 404 SR(DCCG_GATE_DISABLE_CNTL5), \ 405 SR(DCCG_GATE_DISABLE_CNTL6), \ 406 SR(SYMCLKA_CLOCK_ENABLE), \ 407 SR(SYMCLKB_CLOCK_ENABLE), \ 408 SR(SYMCLKC_CLOCK_ENABLE), \ 409 SR(SYMCLKD_CLOCK_ENABLE), \ 410 SR(SYMCLKE_CLOCK_ENABLE) 411 412 #define DCN42_AUD_COMMON_MASK_SH_LIST(mask_sh) \ 413 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh), \ 414 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 415 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ 416 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ 417 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\ 418 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\ 419 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\ 420 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\ 421 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\ 422 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\ 423 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\ 424 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\ 425 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh) 426 427 /* HPO FRL stream encoder */ 428 #define DCN42_HPO_FRL_STREAM_ENC_REG_LIST_RI(id) \ 429 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id), \ 430 SR_ARR(HDMI_STREAM_ENC_AUDIO_CONTROL, id),\ 431 SR_ARR(HDMI_TB_ENC_MEM_CTRL, id),\ 432 SR_ARR(HDMI_FRL_ENC_MEM_CTRL, id) 433 /* OPTC */ 434 #define OPTC_COMMON_REG_LIST_DCN42_RI(inst) \ 435 SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \ 436 SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \ 437 SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \ 438 SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \ 439 SRI_ARR(OTG_MASTER_UPDATE_MODE, OTG, inst), \ 440 SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst), \ 441 SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst), \ 442 SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \ 443 SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\ 444 SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \ 445 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \ 446 SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \ 447 SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \ 448 SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \ 449 SRI_ARR(OTG_H_TOTAL, OTG, inst), \ 450 SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \ 451 SRI_ARR(OTG_H_SYNC_A, OTG, inst),\ 452 SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \ 453 SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), \ 454 SRI_ARR(OTG_V_TOTAL, OTG, inst), \ 455 SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \ 456 SRI_ARR(OTG_V_SYNC_A, OTG, inst), \ 457 SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \ 458 SRI_ARR(OTG_CONTROL, OTG, inst), \ 459 SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \ 460 SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \ 461 SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \ 462 SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \ 463 SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \ 464 SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \ 465 SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \ 466 SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \ 467 SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \ 468 SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \ 469 SRI_ARR(OTG_STATUS, OTG, inst), \ 470 SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \ 471 SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \ 472 SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \ 473 SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \ 474 SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \ 475 SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \ 476 SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \ 477 SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \ 478 SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \ 479 SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \ 480 SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \ 481 SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \ 482 SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \ 483 SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \ 484 SRI_ARR(OPTC_RSMU_UNDERFLOW, ODM, inst), \ 485 SRI_ARR(OPTC_UNDERFLOW_THRESHOLD, ODM, inst), \ 486 SRI_ARR(CONTROL, VTG, inst), \ 487 SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \ 488 SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \ 489 SRI_ARR(OTG_CRC_CNTL, OTG, inst), \ 490 SRI_ARR(OTG_CRC0_DATA_R, OTG, inst), \ 491 SRI_ARR(OTG_CRC0_DATA_G, OTG, inst), \ 492 SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \ 493 SRI_ARR(OTG_CRC1_DATA_R, OTG, inst), \ 494 SRI_ARR(OTG_CRC1_DATA_G, OTG, inst), \ 495 SRI_ARR(OTG_CRC1_DATA_B, OTG, inst), \ 496 SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \ 497 SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \ 498 SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \ 499 SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \ 500 SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst), \ 501 SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst), \ 502 SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst), \ 503 SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst), \ 504 SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\ 505 SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\ 506 SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\ 507 SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\ 508 SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\ 509 SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\ 510 SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\ 511 SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\ 512 SR_ARR(GSL_SOURCE_SELECT, inst), \ 513 SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \ 514 SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \ 515 SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \ 516 SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \ 517 SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \ 518 SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \ 519 SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \ 520 SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \ 521 SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \ 522 SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \ 523 SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \ 524 SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \ 525 SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \ 526 SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ 527 SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \ 528 SRI_ARR(OTG_PWA_FRAME_SYNC_CONTROL, OTG, inst),\ 529 SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),\ 530 SRI_ARR(INTERRUPT_DEST, OTG, inst) 531 532 /* CLK SRC */ 533 #define CS_COMMON_REG_LIST_DCN42_RI(index, pllid) \ 534 SRI_ARR_ALPHABET(PIXCLK_RESYNC_CNTL, PHYPLL, index, pllid), \ 535 SRII_ARR_2(PHASE, DP_DTO, 0, index), \ 536 SRII_ARR_2(PHASE, DP_DTO, 1, index), \ 537 SRII_ARR_2(PHASE, DP_DTO, 2, index), \ 538 SRII_ARR_2(PHASE, DP_DTO, 3, index), \ 539 SRII_ARR_2(MODULO, DP_DTO, 0, index), \ 540 SRII_ARR_2(MODULO, DP_DTO, 1, index), \ 541 SRII_ARR_2(MODULO, DP_DTO, 2, index), \ 542 SRII_ARR_2(MODULO, DP_DTO, 3, index), \ 543 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index), \ 544 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index), \ 545 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index), \ 546 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index) 547 548 /* ABM */ 549 #define ABM_DCN42_REG_LIST_RI(id) \ 550 SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ 551 SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ 552 SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id), \ 553 SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ 554 SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ 555 SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ 556 SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ 557 SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id), \ 558 SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ 559 SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ 560 SRI_ARR(DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, ABM, id), \ 561 SRI_ARR(DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, ABM, id), \ 562 SRI_ARR(DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, ABM, id), \ 563 SRI_ARR(DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, ABM, id), \ 564 SRI_ARR(DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, ABM, id), \ 565 SRI_ARR(DC_ABM1_HG_RESULT_DATA, ABM, id), \ 566 SRI_ARR(DC_ABM1_HG_RESULT_INDEX, ABM, id), \ 567 SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_DATA, ABM, id), \ 568 SRI_ARR(DC_ABM1_ACE_PWL_CNTL, ABM, id) 569 570 /* HUBP */ 571 #define HUBP_REG_LIST_DCN42_RI(id) \ 572 HUBP_REG_LIST_DCN30_RI(id), SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \ 573 SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \ 574 SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \ 575 SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, id), \ 576 HUBP_3DLUT_FL_REG_LIST_DCN401(id) 577 struct dcn42_resource_pool { 578 struct resource_pool base; 579 }; 580 struct resource_pool *dcn42_create_resource_pool( 581 const struct dc_init_data *init_data, 582 struct dc *dc); 583 584 enum dc_status dcn42_validate_bandwidth(struct dc *dc, 585 struct dc_state *context, 586 enum dc_validate_mode validate_mode); 587 588 void dcn42_prepare_mcache_programming(struct dc *dc, struct dc_state *context); 589 int dcn42_get_power_profile(const struct dc_state *context); 590 591 #endif /* _DCN42_RESOURCE_H_ */ 592