1 /* SPDX-License-Identifier: MIT */ 2 3 /* Copyright 2026 Advanced Micro Devices, Inc.*/ 4 5 #ifndef __DCN42_PG_CNTL_H__ 6 #define __DCN42_PG_CNTL_H__ 7 8 #include "pg_cntl.h" 9 10 #define PG_CNTL_REG_LIST_DCN42()\ 11 SR(DOMAIN0_PG_CONFIG), \ 12 SR(DOMAIN1_PG_CONFIG), \ 13 SR(DOMAIN2_PG_CONFIG), \ 14 SR(DOMAIN3_PG_CONFIG), \ 15 SR(DOMAIN16_PG_CONFIG), \ 16 SR(DOMAIN17_PG_CONFIG), \ 17 SR(DOMAIN18_PG_CONFIG), \ 18 SR(DOMAIN19_PG_CONFIG), \ 19 SR(DOMAIN22_PG_CONFIG), \ 20 SR(DOMAIN23_PG_CONFIG), \ 21 SR(DOMAIN24_PG_CONFIG), \ 22 SR(DOMAIN25_PG_CONFIG), \ 23 SR(DOMAIN26_PG_CONFIG), \ 24 SR(DOMAIN0_PG_STATUS), \ 25 SR(DOMAIN1_PG_STATUS), \ 26 SR(DOMAIN2_PG_STATUS), \ 27 SR(DOMAIN3_PG_STATUS), \ 28 SR(DOMAIN16_PG_STATUS), \ 29 SR(DOMAIN17_PG_STATUS), \ 30 SR(DOMAIN18_PG_STATUS), \ 31 SR(DOMAIN19_PG_STATUS), \ 32 SR(DOMAIN22_PG_STATUS), \ 33 SR(DOMAIN23_PG_STATUS), \ 34 SR(DOMAIN24_PG_STATUS), \ 35 SR(DOMAIN25_PG_STATUS), \ 36 SR(DOMAIN26_PG_STATUS), \ 37 SR(DC_IP_REQUEST_CNTL) 38 39 #define PG_CNTL_SF(reg_name, field_name, post_fix)\ 40 .field_name = reg_name ## __ ## field_name ## post_fix 41 42 #define PG_CNTL_MASK_SH_LIST_DCN42(mask_sh) \ 43 PG_CNTL_SF(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 44 PG_CNTL_SF(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 45 PG_CNTL_SF(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 46 PG_CNTL_SF(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 47 PG_CNTL_SF(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 48 PG_CNTL_SF(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 49 PG_CNTL_SF(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 50 PG_CNTL_SF(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 51 PG_CNTL_SF(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 52 PG_CNTL_SF(DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 53 PG_CNTL_SF(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 54 PG_CNTL_SF(DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 55 PG_CNTL_SF(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 56 PG_CNTL_SF(DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 57 PG_CNTL_SF(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 58 PG_CNTL_SF(DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 59 PG_CNTL_SF(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 60 PG_CNTL_SF(DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 61 PG_CNTL_SF(DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 62 PG_CNTL_SF(DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 63 PG_CNTL_SF(DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 64 PG_CNTL_SF(DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 65 PG_CNTL_SF(DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 66 PG_CNTL_SF(DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 67 PG_CNTL_SF(DOMAIN26_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 68 PG_CNTL_SF(DOMAIN26_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 69 PG_CNTL_SF(DOMAIN0_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 70 PG_CNTL_SF(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 71 PG_CNTL_SF(DOMAIN1_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 72 PG_CNTL_SF(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 73 PG_CNTL_SF(DOMAIN2_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 74 PG_CNTL_SF(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 75 PG_CNTL_SF(DOMAIN3_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 76 PG_CNTL_SF(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 77 PG_CNTL_SF(DOMAIN16_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 78 PG_CNTL_SF(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 79 PG_CNTL_SF(DOMAIN17_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 80 PG_CNTL_SF(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 81 PG_CNTL_SF(DOMAIN18_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 82 PG_CNTL_SF(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 83 PG_CNTL_SF(DOMAIN19_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 84 PG_CNTL_SF(DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 85 PG_CNTL_SF(DOMAIN22_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 86 PG_CNTL_SF(DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 87 PG_CNTL_SF(DOMAIN23_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 88 PG_CNTL_SF(DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 89 PG_CNTL_SF(DOMAIN24_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 90 PG_CNTL_SF(DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 91 PG_CNTL_SF(DOMAIN25_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 92 PG_CNTL_SF(DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 93 PG_CNTL_SF(DOMAIN26_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 94 PG_CNTL_SF(DOMAIN26_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 95 PG_CNTL_SF(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 96 97 struct pg_cntl_shift { 98 uint8_t IP_REQUEST_EN; 99 uint8_t DOMAIN_POWER_FORCEON; 100 uint8_t DOMAIN_POWER_GATE; 101 uint8_t DOMAIN_DESIRED_PWR_STATE; 102 uint8_t DOMAIN_PGFSM_PWR_STATUS; 103 }; 104 struct pg_cntl_mask { 105 uint32_t IP_REQUEST_EN; 106 uint32_t DOMAIN_POWER_FORCEON; 107 uint32_t DOMAIN_POWER_GATE; 108 uint32_t DOMAIN_DESIRED_PWR_STATE; 109 uint32_t DOMAIN_PGFSM_PWR_STATUS; 110 }; 111 112 struct pg_cntl_registers { 113 uint32_t LONO_STATE; 114 uint32_t DC_IP_REQUEST_CNTL; 115 uint32_t DOMAIN0_PG_CONFIG; 116 uint32_t DOMAIN1_PG_CONFIG; 117 uint32_t DOMAIN2_PG_CONFIG; 118 uint32_t DOMAIN3_PG_CONFIG; 119 uint32_t DOMAIN16_PG_CONFIG; 120 uint32_t DOMAIN17_PG_CONFIG; 121 uint32_t DOMAIN18_PG_CONFIG; 122 uint32_t DOMAIN19_PG_CONFIG; 123 uint32_t DOMAIN22_PG_CONFIG; 124 uint32_t DOMAIN23_PG_CONFIG; 125 uint32_t DOMAIN24_PG_CONFIG; 126 uint32_t DOMAIN25_PG_CONFIG; 127 uint32_t DOMAIN26_PG_CONFIG; 128 uint32_t DOMAIN0_PG_STATUS; 129 uint32_t DOMAIN1_PG_STATUS; 130 uint32_t DOMAIN2_PG_STATUS; 131 uint32_t DOMAIN3_PG_STATUS; 132 uint32_t DOMAIN16_PG_STATUS; 133 uint32_t DOMAIN17_PG_STATUS; 134 uint32_t DOMAIN18_PG_STATUS; 135 uint32_t DOMAIN19_PG_STATUS; 136 uint32_t DOMAIN22_PG_STATUS; 137 uint32_t DOMAIN23_PG_STATUS; 138 uint32_t DOMAIN24_PG_STATUS; 139 uint32_t DOMAIN25_PG_STATUS; 140 uint32_t DOMAIN26_PG_STATUS; 141 }; 142 143 struct dcn_pg_cntl { 144 struct pg_cntl base; 145 const struct pg_cntl_registers *regs; 146 const struct pg_cntl_shift *pg_cntl_shift; 147 const struct pg_cntl_mask *pg_cntl_mask; 148 }; 149 150 void pg_cntl42_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on); 151 void pg_cntl42_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, 152 unsigned int hubp_dpp_inst, bool power_on); 153 void pg_cntl42_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on); 154 void pg_cntl42_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on); 155 void pg_cntl42_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on); 156 void pg_cntl42_mpcc_pg_control(struct pg_cntl *pg_cntl, 157 unsigned int mpcc_inst, bool power_on); 158 void pg_cntl42_opp_pg_control(struct pg_cntl *pg_cntl, 159 unsigned int opp_inst, bool power_on); 160 void pg_cntl42_optc_pg_control(struct pg_cntl *pg_cntl, 161 unsigned int optc_inst, bool power_on); 162 void pg_cntl42_mem_pg_control(struct pg_cntl *pg_cntl, bool power_on); 163 void pg_cntl42_dio_pg_control(struct pg_cntl *pg_cntl, bool power_on); 164 void dcn42_pg_cntl_destroy(struct pg_cntl **pg_cntl); 165 void pg_cntl42_init_pg_status(struct pg_cntl *pg_cntl); 166 167 struct pg_cntl *pg_cntl42_create( 168 struct dc_context *ctx, 169 const struct pg_cntl_registers *regs, 170 const struct pg_cntl_shift *pg_cntl_shift, 171 const struct pg_cntl_mask *pg_cntl_mask); 172 173 void dcn_pg_cntl_destroy(struct pg_cntl **pg_cntl); 174 175 #endif /* DCN42_PG_CNTL */ 176