1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2025 Advanced Micro Devices, Inc. 4 5 #include "dcn30/dcn30_optc.h" 6 #include "dcn31/dcn31_optc.h" 7 #include "dcn32/dcn32_optc.h" 8 #include "dcn401/dcn401_optc.h" 9 #include "dcn42/dcn42_optc.h" 10 #include "dcn60_optc.h" 11 #include "reg_helper.h" 12 #include "dc.h" 13 #include "dcn_calc_math.h" 14 #include "dc_dmub_srv.h" 15 16 #define REG(reg)\ 17 optc1->tg_regs->reg 18 19 #define CTX \ 20 optc1->base.ctx 21 22 #undef FN 23 #define FN(reg_name, field_name) \ 24 optc1->tg_shift->field_name, optc1->tg_mask->field_name 25 26 static const struct timing_generator_funcs dcn60_tg_funcs = { 27 .validate_timing = optc1_validate_timing, 28 .program_timing = optc1_program_timing, 29 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 30 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 31 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 32 .program_global_sync = optc401_program_global_sync, 33 .enable_crtc = optc401_enable_crtc, 34 .disable_crtc = optc401_disable_crtc, 35 .phantom_crtc_post_enable = optc401_phantom_crtc_post_enable, 36 .disable_phantom_crtc = optc401_disable_phantom_otg, 37 /* used by enable_timing_synchronization. Not need for FPGA */ 38 .is_counter_moving = optc1_is_counter_moving, 39 .get_position = optc1_get_position, 40 .get_frame_count = optc1_get_vblank_counter, 41 .get_scanoutpos = optc1_get_crtc_scanoutpos, 42 .get_otg_active_size = optc1_get_otg_active_size, 43 .set_early_control = optc1_set_early_control, 44 /* used by enable_timing_synchronization. Not need for FPGA */ 45 .wait_for_state = optc1_wait_for_state, 46 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 47 .triplebuffer_lock = optc3_triplebuffer_lock, 48 .triplebuffer_unlock = optc2_triplebuffer_unlock, 49 .enable_reset_trigger = optc1_enable_reset_trigger, 50 .enable_crtc_reset = optc1_enable_crtc_reset, 51 .disable_reset_trigger = optc1_disable_reset_trigger, 52 .lock = optc3_lock, 53 .unlock = optc1_unlock, 54 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, 55 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, 56 .enable_optc_clock = optc1_enable_optc_clock, 57 .set_drr = optc401_set_drr, 58 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, 59 .set_vtotal_min_max = optc401_set_vtotal_min_max, 60 .set_static_screen_control = optc1_set_static_screen_control, 61 .program_stereo = optc1_program_stereo, 62 .is_stereo_left_eye = optc1_is_stereo_left_eye, 63 .tg_init = optc3_tg_init, 64 .is_tg_enabled = optc1_is_tg_enabled, 65 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 66 .clear_optc_underflow = optc1_clear_optc_underflow, 67 .get_crc = optc42_get_crc, 68 .configure_crc = optc1_configure_crc, 69 .set_dsc_config = optc3_set_dsc_config, 70 .get_dsc_status = optc2_get_dsc_status, 71 .set_odm_bypass = optc401_set_odm_bypass, 72 .set_odm_combine = optc401_set_odm_combine, 73 .wait_odm_doublebuffer_pending_clear = optc32_wait_odm_doublebuffer_pending_clear, 74 .set_h_timing_div_manual_mode = optc401_set_h_timing_div_manual_mode, 75 .get_optc_source = optc2_get_optc_source, 76 .set_out_mux = optc401_set_out_mux, 77 .set_drr_trigger_window = optc3_set_drr_trigger_window, 78 .set_vtotal_change_limit = optc3_set_vtotal_change_limit, 79 .set_gsl = optc2_set_gsl, 80 .set_gsl_source_select = NULL, 81 .set_vtg_params = optc1_set_vtg_params, 82 .program_manual_trigger = optc2_program_manual_trigger, 83 .setup_manual_trigger = optc2_setup_manual_trigger, 84 .get_hw_timing = optc1_get_hw_timing, 85 .is_two_pixels_per_container = optc1_is_two_pixels_per_container, 86 .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, 87 .get_otg_double_buffer_pending = optc3_get_otg_update_pending, 88 .get_pipe_update_pending = optc3_get_pipe_update_pending, 89 .set_vupdate_keepout = optc401_set_vupdate_keepout, 90 .wait_update_lock_status = optc401_wait_update_lock_status, 91 .read_otg_state = optc31_read_otg_state, 92 .optc_read_reg_state = optc31_read_reg_state, 93 }; 94 95 void dcn60_timing_generator_init(struct optc *optc1) 96 { 97 optc1->base.funcs = &dcn60_tg_funcs; 98 99 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 100 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 101 102 optc1->min_h_blank = 32; 103 optc1->min_v_blank = 3; 104 optc1->min_v_blank_interlace = 5; 105 optc1->min_h_sync_width = 4; 106 optc1->min_v_sync_width = 1; 107 } 108