1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2026 Advanced Micro Devices, Inc. 4 5 #include "reg_helper.h" 6 #include "dc.h" 7 #include "dcn42_mpc.h" 8 #include "dcn10/dcn10_cm_common.h" 9 #include "basics/conversion.h" 10 #include "mpc.h" 11 12 #define REG(reg)\ 13 mpc42->mpc_regs->reg 14 15 #define CTX \ 16 mpc42->base.ctx 17 18 #undef FN 19 #define FN(reg_name, field_name) \ 20 mpc42->mpc_shift->field_name, mpc42->mpc_mask->field_name 21 22 23 void mpc42_init_mpcc(struct mpcc *mpcc, int mpcc_inst) 24 { 25 mpcc->mpcc_id = mpcc_inst; 26 mpcc->dpp_id = 0xf; 27 mpcc->mpcc_bot = NULL; 28 mpcc->blnd_cfg.overlap_only = false; 29 mpcc->blnd_cfg.global_alpha = 0xfff; 30 mpcc->blnd_cfg.global_gain = 0xfff; 31 mpcc->blnd_cfg.background_color_bpc = 4; 32 mpcc->blnd_cfg.bottom_gain_mode = 0; 33 mpcc->blnd_cfg.top_gain = 0x1f000; 34 mpcc->blnd_cfg.bottom_inside_gain = 0x1f000; 35 mpcc->blnd_cfg.bottom_outside_gain = 0x1f000; 36 mpcc->sm_cfg.enable = false; 37 mpcc->shared_bottom = false; 38 } 39 40 void mpc42_update_blending( 41 struct mpc *mpc, 42 struct mpcc_blnd_cfg *blnd_cfg, 43 int mpcc_id) 44 { 45 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 46 47 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); 48 49 REG_UPDATE_5(MPCC_CONTROL[mpcc_id], 50 MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, 51 MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha, 52 MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only, 53 MPCC_BG_BPC, blnd_cfg->background_color_bpc, 54 MPCC_BOT_GAIN_MODE, blnd_cfg->bottom_gain_mode); 55 REG_UPDATE_2(MPCC_CONTROL2[mpcc_id], 56 MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha, 57 MPCC_GLOBAL_GAIN, blnd_cfg->global_gain); 58 59 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); 60 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); 61 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); 62 63 mpcc->blnd_cfg = *blnd_cfg; 64 } 65 66 /* RMCM Shaper functions */ 67 void mpc42_power_on_rmcm_shaper_3dlut( 68 struct mpc *mpc, 69 uint32_t mpcc_id, 70 bool power_on) 71 { 72 uint32_t power_status_shaper = 2; 73 uint32_t power_status_3dlut = 2; 74 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 75 int max_retries = 10; 76 77 REG_SET(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], 0, 78 MPC_RMCM_3DLUT_MEM_PWR_DIS, power_on == true ? 0 : 1); 79 REG_SET(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], 0, 80 MPC_RMCM_SHAPER_MEM_PWR_DIS, power_on == true ? 0 : 1); 81 /* wait for memory to fully power up */ 82 if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { 83 REG_WAIT(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); 84 REG_WAIT(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); 85 } 86 87 /*read status is not mandatory, it is just for debugging*/ 88 REG_GET(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_SHAPER_MEM_PWR_STATE, &power_status_shaper); 89 REG_GET(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut); 90 91 if (power_status_shaper != 0 && power_on == true) 92 BREAK_TO_DEBUGGER(); 93 94 if (power_status_3dlut != 0 && power_on == true) 95 BREAK_TO_DEBUGGER(); 96 } 97 98 void mpc42_configure_rmcm_shaper_lut( 99 struct mpc *mpc, 100 bool is_ram_a, 101 uint32_t mpcc_id) 102 { 103 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 104 105 REG_UPDATE(MPC_RMCM_SHAPER_SCALE_G_B[mpcc_id], 106 MPC_RMCM_SHAPER_SCALE_B, 0x7000); 107 REG_UPDATE(MPC_RMCM_SHAPER_SCALE_G_B[mpcc_id], 108 MPC_RMCM_SHAPER_SCALE_G, 0x7000); 109 REG_UPDATE(MPC_RMCM_SHAPER_SCALE_R[mpcc_id], 110 MPC_RMCM_SHAPER_SCALE_R, 0x7000); 111 REG_UPDATE(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], 112 MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, 7); 113 REG_UPDATE(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], 114 MPC_RMCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); 115 REG_SET(MPC_RMCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPC_RMCM_SHAPER_LUT_INDEX, 0); 116 } 117 118 void mpc42_program_rmcm_shaper_luta_settings( 119 struct mpc *mpc, 120 const struct pwl_params *params, 121 uint32_t mpcc_id) 122 { 123 const struct gamma_curve *curve; 124 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 125 126 REG_SET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0, 127 MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 128 MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 129 REG_SET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0, 130 MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x, 131 MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 132 REG_SET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0, 133 MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x, 134 MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 135 136 REG_SET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0, 137 MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 138 MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 139 REG_SET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0, 140 MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x, 141 MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y); 142 REG_SET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0, 143 MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x, 144 MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y); 145 146 curve = params->arr_curve_points; 147 if (curve) { 148 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0, 149 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 150 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 151 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 152 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 153 154 curve += 2; 155 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0, 156 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 157 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 158 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 159 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 160 161 curve += 2; 162 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0, 163 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 164 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 165 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 166 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 167 168 curve += 2; 169 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0, 170 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 171 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 172 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 173 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 174 175 curve += 2; 176 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0, 177 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 178 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 179 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 180 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 181 182 curve += 2; 183 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0, 184 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 185 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 186 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 187 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 188 189 curve += 2; 190 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0, 191 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 192 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 193 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 194 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 195 196 curve += 2; 197 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0, 198 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 199 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 200 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 201 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 202 203 204 curve += 2; 205 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0, 206 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 207 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 208 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 209 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 210 211 curve += 2; 212 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0, 213 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 214 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 215 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 216 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 217 218 curve += 2; 219 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0, 220 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 221 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 222 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 223 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 224 225 curve += 2; 226 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0, 227 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 228 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 229 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 230 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 231 232 curve += 2; 233 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0, 234 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 235 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 236 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 237 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 238 239 curve += 2; 240 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0, 241 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 242 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 243 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 244 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 245 246 curve += 2; 247 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0, 248 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 249 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 250 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 251 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 252 253 curve += 2; 254 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0, 255 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 256 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 257 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 258 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 259 260 curve += 2; 261 REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0, 262 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 263 MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 264 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 265 MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 266 } 267 } 268 269 270 void mpc42_program_rmcm_shaper_lutb_settings( 271 struct mpc *mpc, 272 const struct pwl_params *params, 273 uint32_t mpcc_id) 274 { 275 const struct gamma_curve *curve; 276 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 277 278 REG_SET_2(MPC_RMCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0, 279 MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 280 MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); 281 REG_SET_2(MPC_RMCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0, 282 MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x, 283 MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); 284 REG_SET_2(MPC_RMCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0, 285 MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x, 286 MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); 287 288 REG_SET_2(MPC_RMCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0, 289 MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 290 MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 291 REG_SET_2(MPC_RMCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0, 292 MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x, 293 MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y); 294 REG_SET_2(MPC_RMCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0, 295 MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x, 296 MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y); 297 298 curve = params->arr_curve_points; 299 if (curve) { 300 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0, 301 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 302 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 303 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 304 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 305 306 curve += 2; 307 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0, 308 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 309 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 310 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 311 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 312 313 314 curve += 2; 315 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0, 316 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 317 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 318 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 319 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 320 321 curve += 2; 322 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0, 323 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 324 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 325 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 326 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 327 328 curve += 2; 329 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0, 330 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 331 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 332 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 333 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 334 335 curve += 2; 336 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0, 337 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 338 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 339 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 340 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 341 342 curve += 2; 343 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0, 344 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 345 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 346 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 347 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 348 349 curve += 2; 350 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0, 351 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 352 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 353 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 354 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 355 356 curve += 2; 357 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0, 358 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 359 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 360 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 361 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 362 363 curve += 2; 364 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0, 365 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 366 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 367 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 368 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 369 370 curve += 2; 371 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0, 372 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 373 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 374 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 375 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 376 377 curve += 2; 378 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0, 379 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 380 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 381 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 382 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 383 384 curve += 2; 385 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0, 386 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 387 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 388 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 389 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 390 391 curve += 2; 392 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0, 393 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 394 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 395 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 396 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 397 398 curve += 2; 399 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0, 400 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 401 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 402 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 403 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 404 405 curve += 2; 406 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0, 407 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 408 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 409 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 410 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 411 412 curve += 2; 413 REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0, 414 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, 415 MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 416 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, 417 MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 418 } 419 } 420 421 void mpc42_program_rmcm_shaper_lut( 422 struct mpc *mpc, 423 const struct pwl_result_data *rgb, 424 uint32_t num, 425 uint32_t mpcc_id) 426 { 427 uint32_t i, red, green, blue; 428 uint32_t red_delta, green_delta, blue_delta; 429 uint32_t red_value, green_value, blue_value; 430 431 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 432 433 for (i = 0; i < num; i++) { 434 435 red = rgb[i].red_reg; 436 green = rgb[i].green_reg; 437 blue = rgb[i].blue_reg; 438 439 red_delta = rgb[i].delta_red_reg; 440 green_delta = rgb[i].delta_green_reg; 441 blue_delta = rgb[i].delta_blue_reg; 442 443 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); 444 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); 445 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); 446 447 REG_SET(MPC_RMCM_SHAPER_LUT_DATA[mpcc_id], 0, MPC_RMCM_SHAPER_LUT_DATA, red_value); 448 REG_SET(MPC_RMCM_SHAPER_LUT_DATA[mpcc_id], 0, MPC_RMCM_SHAPER_LUT_DATA, green_value); 449 REG_SET(MPC_RMCM_SHAPER_LUT_DATA[mpcc_id], 0, MPC_RMCM_SHAPER_LUT_DATA, blue_value); 450 } 451 } 452 453 void mpc42_enable_3dlut_fl(struct mpc *mpc, bool enable, int mpcc_id) 454 { 455 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 456 457 //if enabled cho0se mpc 0, else: off (default value) 458 REG_UPDATE(MPC_RMCM_CNTL[mpcc_id], MPC_RMCM_CNTL, enable ? 0 : 0xF); //0xF is not connected 459 460 REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPC_RMCM_3DLUT_WRITE_EN_MASK, 0); 461 462 REG_UPDATE(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_3DLUT_MEM_PWR_DIS, enable ? 0 : 3); 463 } 464 465 void mpc42_update_3dlut_fast_load_select(struct mpc *mpc, int mpcc_id, int hubp_idx) 466 { 467 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 468 469 REG_SET(MPC_RMCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, 470 MPC_RMCM_3DLUT_FL_SEL, 471 hubp_idx); 472 } 473 474 void mpc42_populate_rmcm_lut(struct mpc *mpc, const union mcm_lut_params params, 475 bool lut_bank_a, int mpcc_id) 476 { 477 const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B; 478 const struct pwl_params *lut_shaper = params.pwl; 479 480 if (lut_shaper == NULL) 481 return; 482 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) 483 mpc42_power_on_rmcm_shaper_3dlut(mpc, mpcc_id, true); 484 485 mpc42_configure_rmcm_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id); 486 487 if (next_mode == LUT_RAM_A) 488 mpc42_program_rmcm_shaper_luta_settings(mpc, lut_shaper, mpcc_id); 489 else 490 mpc42_program_rmcm_shaper_lutb_settings(mpc, lut_shaper, mpcc_id); 491 492 mpc42_program_rmcm_shaper_lut( 493 mpc, lut_shaper->rgb_resulted, lut_shaper->hw_points_num, mpcc_id); 494 495 mpc42_power_on_rmcm_shaper_3dlut(mpc, mpcc_id, false); 496 } 497 498 void mpc42_program_rmcm_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, 499 bool lut_bank_a, bool enabled, int mpcc_id) 500 { 501 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 502 503 switch (id) { 504 case MCM_LUT_3DLUT: 505 REG_UPDATE(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_MODE, 506 (!enabled) ? 0 : 507 (lut_bank_a) ? 1 : 2); 508 509 REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], 510 MPC_RMCM_3DLUT_RAM_SEL, 511 (lut_bank_a) ? 0 : 1); 512 break; 513 case MCM_LUT_SHAPER: 514 REG_UPDATE(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], 515 MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, 7); 516 517 REG_UPDATE(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], 518 MPC_RMCM_SHAPER_LUT_WRITE_SEL, 519 lut_bank_a == true ? 0:1); 520 521 REG_SET(MPC_RMCM_SHAPER_LUT_INDEX[mpcc_id], 0, 522 MPC_RMCM_SHAPER_LUT_INDEX, 0); 523 break; 524 default: 525 break; 526 } 527 } 528 529 void mpc42_program_lut_mode(struct mpc *mpc, 530 bool enable, 531 bool lut_bank_a, 532 int mpcc_id) 533 { 534 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 535 536 if (enable) { 537 REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); 538 } else { 539 REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, 0); 540 } 541 } 542 543 static uint32_t mpc42_get_rmcm_3dlut_width( 544 const enum dc_cm_lut_size size) 545 { 546 uint32_t width = 0; 547 548 switch (size) { 549 case CM_LUT_SIZE_333333: 550 width = 2; 551 break; 552 case CM_LUT_SIZE_171717: 553 default: 554 width = 0; 555 break; 556 } 557 558 return width; 559 } 560 561 void mpc42_program_rmcm_3dlut_size(struct mpc *mpc, 562 const enum dc_cm_lut_size size, 563 int mpcc_id) 564 { 565 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 566 uint32_t width = mpc42_get_rmcm_3dlut_width(size); 567 568 REG_UPDATE(MPC_RMCM_3DLUT_MODE[mpcc_id], 569 MPC_RMCM_3DLUT_SIZE, width); 570 } 571 572 void mpc42_program_rmcm_3dlut_fast_load_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id) 573 { 574 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 575 576 REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_R[mpcc_id], 577 MPC_RMCM_3DLUT_OUT_OFFSET_R, bias, 578 MPC_RMCM_3DLUT_OUT_SCALE_R, scale); 579 580 REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_G[mpcc_id], 581 MPC_RMCM_3DLUT_OUT_OFFSET_G, bias, 582 MPC_RMCM_3DLUT_OUT_SCALE_G, scale); 583 584 REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_B[mpcc_id], 585 MPC_RMCM_3DLUT_OUT_OFFSET_B, bias, 586 MPC_RMCM_3DLUT_OUT_SCALE_B, scale); 587 } 588 589 void mpc42_program_rmcm_bit_depth(struct mpc *mpc, uint16_t bit_depth, int mpcc_id) 590 { 591 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 592 593 REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPC_RMCM_3DLUT_WRITE_EN_MASK, 0xF); 594 595 //program bit_depth 596 REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], 597 MPC_RMCM_3DLUT_30BIT_EN, 598 (bit_depth == 10) ? 1 : 0); 599 } 600 601 void mpc42_set_fl_config( 602 struct mpc *mpc, 603 struct mpc_fl_3dlut_config *cfg, 604 int mpcc_id) 605 { 606 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 607 608 uint32_t width = mpc42_get_rmcm_3dlut_width(cfg->size); 609 /* 610 From: Jie Zhou 611 612 To program any of the memories content. The following sequence is used. 613 Set the MPCC_OGAM/SHAPER/3DLUT/1DLUT_PWR_DIS to 1 (Only need to set the one 614 that is being programmed) Set DISPCLK_G_PIPE<i>_GATE_DISABLE to 1 for the 615 MPCC pipe that’s being used, so the memory’s clock is ungated. Program the 616 target memory. Set the MPCC_OGAM/SHAPER/3DLUT/1DLUT_PWR_DIS back to 0. 617 Set DISPCLK_G_PIPE<i>_GATE_DISABLE back to 0 618 */ 619 620 //disconnect fl from mpc 621 REG_SET(MPCC_MCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, 622 MPCC_MCM_3DLUT_FL_SEL, 0xF); 623 624 REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], 625 MPC_RMCM_3DLUT_WRITE_EN_MASK, 0xF); 626 627 //program bit_depth 628 REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], 629 MPC_RMCM_3DLUT_30BIT_EN, (cfg->bit_depth == 10) ? 1 : 0); 630 631 REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], 632 MPC_RMCM_3DLUT_RAM_SEL, (cfg->select_lut_bank_a) ? 0 : 1); 633 634 //bias and scale 635 REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_R[mpcc_id], 636 MPC_RMCM_3DLUT_OUT_OFFSET_R, cfg->bias, 637 MPC_RMCM_3DLUT_OUT_SCALE_R, cfg->scale); 638 639 REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_G[mpcc_id], 640 MPC_RMCM_3DLUT_OUT_OFFSET_G, cfg->bias, 641 MPC_RMCM_3DLUT_OUT_SCALE_G, cfg->scale); 642 643 REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_B[mpcc_id], 644 MPC_RMCM_3DLUT_OUT_OFFSET_B, cfg->bias, 645 MPC_RMCM_3DLUT_OUT_SCALE_B, cfg->scale); 646 647 //width 648 REG_UPDATE_2(MPC_RMCM_3DLUT_MODE[mpcc_id], 649 MPC_RMCM_3DLUT_SIZE, width, 650 MPC_RMCM_3DLUT_MODE, (!cfg->enabled) ? 0 : (cfg->select_lut_bank_a) ? 1 : 2); 651 652 //connect to hubp 653 REG_SET(MPC_RMCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, 654 MPC_RMCM_3DLUT_FL_SEL, cfg->hubp_index); 655 656 //ENABLE 657 //if enabled pick mpc 0, else: off (0xF) 658 //in future we'll select specific MPC 659 REG_UPDATE(MPC_RMCM_CNTL[mpcc_id], MPC_RMCM_CNTL, cfg->enabled ? 0 : 0xF); 660 } 661 662 void mpc42_read_mpcc_state( 663 struct mpc *mpc, 664 int mpcc_inst, 665 struct mpcc_state *s) 666 { 667 struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); 668 669 mpc1_read_mpcc_state(mpc, mpcc_inst, s); 670 671 if (mpcc_inst < 2) { 672 /* RMCM 3DLUT Status */ 673 REG_GET_4(MPC_RMCM_MEM_PWR_CTRL[mpcc_inst], MPC_RMCM_3DLUT_MEM_PWR_FORCE, &s->rmcm_regs.rmcm_3dlut_mem_pwr_force, 674 MPC_RMCM_3DLUT_MEM_PWR_DIS, &s->rmcm_regs.rmcm_3dlut_mem_pwr_dis, 675 MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE, &s->rmcm_regs.rmcm_3dlut_mem_pwr_mode, 676 MPC_RMCM_3DLUT_MEM_PWR_STATE, &s->rmcm_regs.rmcm_3dlut_mem_pwr_state); 677 678 REG_GET_3(MPC_RMCM_3DLUT_MODE[mpcc_inst], MPC_RMCM_3DLUT_SIZE, &s->rmcm_regs.rmcm_3dlut_size, 679 MPC_RMCM_3DLUT_MODE, &s->rmcm_regs.rmcm_3dlut_mode, 680 MPC_RMCM_3DLUT_MODE_CURRENT, &s->rmcm_regs.rmcm_3dlut_mode_cur); 681 682 REG_GET_4(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_inst], MPC_RMCM_3DLUT_READ_SEL, &s->rmcm_regs.rmcm_3dlut_read_sel, 683 MPC_RMCM_3DLUT_30BIT_EN, &s->rmcm_regs.rmcm_3dlut_30bit_en, 684 MPC_RMCM_3DLUT_WRITE_EN_MASK, &s->rmcm_regs.rmcm_3dlut_wr_en_mask, 685 MPC_RMCM_3DLUT_RAM_SEL, &s->rmcm_regs.rmcm_3dlut_ram_sel); 686 687 REG_GET(MPC_RMCM_3DLUT_OUT_NORM_FACTOR[mpcc_inst], MPC_RMCM_3DLUT_OUT_NORM_FACTOR, &s->rmcm_regs.rmcm_3dlut_out_norm_factor); 688 689 REG_GET(MPC_RMCM_3DLUT_FAST_LOAD_SELECT[mpcc_inst], MPC_RMCM_3DLUT_FL_SEL, &s->rmcm_regs.rmcm_3dlut_fl_sel); 690 691 REG_GET_2(MPC_RMCM_3DLUT_OUT_OFFSET_R[mpcc_inst], MPC_RMCM_3DLUT_OUT_OFFSET_R, &s->rmcm_regs.rmcm_3dlut_out_offset_r, 692 MPC_RMCM_3DLUT_OUT_SCALE_R, &s->rmcm_regs.rmcm_3dlut_out_scale_r); 693 694 REG_GET_3(MPC_RMCM_3DLUT_FAST_LOAD_STATUS[mpcc_inst], MPC_RMCM_3DLUT_FL_DONE, &s->rmcm_regs.rmcm_3dlut_fl_done, 695 MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW, &s->rmcm_regs.rmcm_3dlut_fl_soft_underflow, 696 MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW, &s->rmcm_regs.rmcm_3dlut_fl_hard_underflow); 697 698 /* RMCM Shaper Status */ 699 REG_GET_4(MPC_RMCM_MEM_PWR_CTRL[mpcc_inst], MPC_RMCM_SHAPER_MEM_PWR_FORCE, &s->rmcm_regs.rmcm_shaper_mem_pwr_force, 700 MPC_RMCM_SHAPER_MEM_PWR_DIS, &s->rmcm_regs.rmcm_shaper_mem_pwr_dis, 701 MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE, &s->rmcm_regs.rmcm_shaper_mem_pwr_mode, 702 MPC_RMCM_SHAPER_MEM_PWR_STATE, &s->rmcm_regs.rmcm_shaper_mem_pwr_state); 703 704 REG_GET_2(MPC_RMCM_SHAPER_CONTROL[mpcc_inst], MPC_RMCM_SHAPER_LUT_MODE, &s->rmcm_regs.rmcm_shaper_lut_mode, 705 MPC_RMCM_SHAPER_MODE_CURRENT, &s->rmcm_regs.rmcm_shaper_mode_cur); 706 707 REG_GET_2(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_inst], MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, &s->rmcm_regs.rmcm_shaper_lut_write_en_mask, 708 MPC_RMCM_SHAPER_LUT_WRITE_SEL, &s->rmcm_regs.rmcm_shaper_lut_write_sel); 709 710 REG_GET(MPC_RMCM_SHAPER_OFFSET_B[mpcc_inst], MPC_RMCM_SHAPER_OFFSET_B, &s->rmcm_regs.rmcm_shaper_offset_b); 711 712 REG_GET(MPC_RMCM_SHAPER_SCALE_G_B[mpcc_inst], MPC_RMCM_SHAPER_SCALE_B, &s->rmcm_regs.rmcm_shaper_scale_b); 713 714 REG_GET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_B[mpcc_inst], MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_start_b, 715 MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_start_seg_b); 716 717 REG_GET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_B[mpcc_inst], MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_end_b, 718 MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_end_base_b); 719 720 REG_GET(MPC_RMCM_CNTL[mpcc_inst], MPC_RMCM_CNTL, &s->rmcm_regs.rmcm_cntl); 721 } 722 } 723 724 static const struct mpc_funcs dcn42_mpc_funcs = { 725 .read_mpcc_state = mpc42_read_mpcc_state, 726 .insert_plane = mpc1_insert_plane, 727 .remove_mpcc = mpc1_remove_mpcc, 728 .mpc_init = mpc32_mpc_init, 729 .mpc_init_single_inst = mpc3_mpc_init_single_inst, 730 .update_blending = mpc42_update_blending, 731 .cursor_lock = mpc1_cursor_lock, 732 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, 733 .wait_for_idle = mpc2_assert_idle_mpcc, 734 .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect, 735 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw, 736 .set_denorm = mpc3_set_denorm, 737 .set_denorm_clamp = mpc3_set_denorm_clamp, 738 .set_output_csc = mpc3_set_output_csc, 739 .set_ocsc_default = mpc3_set_ocsc_default, 740 .set_output_gamma = mpc3_set_output_gamma, 741 .set_dwb_mux = mpc3_set_dwb_mux, 742 .disable_dwb_mux = mpc3_disable_dwb_mux, 743 .is_dwb_idle = mpc3_is_dwb_idle, 744 .set_gamut_remap = mpc401_set_gamut_remap, 745 .program_shaper = mpc32_program_shaper, 746 .program_3dlut = mpc32_program_3dlut, 747 .program_1dlut = mpc32_program_post1dlut, 748 .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, 749 .get_mpc_out_mux = mpc1_get_mpc_out_mux, 750 .mpc_read_reg_state = mpc3_read_reg_state, 751 .set_bg_color = mpc1_set_bg_color, 752 .set_movable_cm_location = mpc401_set_movable_cm_location, 753 .update_3dlut_fast_load_select = mpc401_update_3dlut_fast_load_select, 754 .get_3dlut_fast_load_status = mpc401_get_3dlut_fast_load_status, 755 .populate_lut = mpc401_populate_lut, 756 .program_lut_read_write_control = mpc401_program_lut_read_write_control, 757 .program_lut_mode = mpc401_program_lut_mode, 758 .get_lut_mode = mpc401_get_lut_mode, 759 .rmcm = { 760 .enable_3dlut_fl = mpc42_enable_3dlut_fl, 761 .update_3dlut_fast_load_select = mpc42_update_3dlut_fast_load_select, 762 .program_lut_read_write_control = mpc42_program_rmcm_lut_read_write_control, 763 .program_lut_mode = mpc42_program_lut_mode, 764 .program_3dlut_size = mpc42_program_rmcm_3dlut_size, 765 .program_bias_scale = mpc42_program_rmcm_3dlut_fast_load_bias_scale, 766 .program_bit_depth = mpc42_program_rmcm_bit_depth, 767 .power_on_shaper_3dlut = mpc42_power_on_rmcm_shaper_3dlut, 768 .populate_lut = mpc42_populate_rmcm_lut, 769 .fl_3dlut_configure = mpc42_set_fl_config, 770 }, 771 }; 772 773 void dcn42_mpc_construct(struct dcn42_mpc *mpc42, 774 struct dc_context *ctx, 775 const struct dcn42_mpc_registers *mpc_regs, 776 const struct dcn42_mpc_shift *mpc_shift, 777 const struct dcn42_mpc_mask *mpc_mask, 778 int num_mpcc, 779 int num_rmu) 780 { 781 int i; 782 783 mpc42->base.ctx = ctx; 784 785 mpc42->base.funcs = &dcn42_mpc_funcs; 786 787 mpc42->mpc_regs = mpc_regs; 788 mpc42->mpc_shift = mpc_shift; 789 mpc42->mpc_mask = mpc_mask; 790 791 mpc42->mpcc_in_use_mask = 0; 792 mpc42->num_mpcc = num_mpcc; 793 mpc42->num_rmu = num_rmu; 794 795 for (i = 0; i < MAX_MPCC; i++) 796 mpc42_init_mpcc(&mpc42->base.mpcc_array[i], i); 797 } 798