xref: /linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.c (revision 0fc8f6200d2313278fbf4539bbab74677c685531)
1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2026 Advanced Micro Devices, Inc.
4 
5 #include "dcn35/dcn35_mmhubbub.h"
6 #include "dcn42_mmhubbub.h"
7 #include "reg_helper.h"
8 
9 #define REG(reg)                                                             \
10 	((const struct dcn35_mmhubbub_registers *)(mcif_wb30->mcif_wb_regs)) \
11 		->reg
12 
13 #define CTX mcif_wb30->base.ctx
14 
15 #undef FN
16 #define FN(reg_name, field_name)                                                \
17 	((const struct dcn35_mmhubbub_shift *)(mcif_wb30->mcif_wb_shift))       \
18 		->field_name,                                                   \
19 		((const struct dcn35_mmhubbub_mask *)(mcif_wb30->mcif_wb_mask)) \
20 			->field_name
21 
22 void dcn42_mmhubbub_set_fgcg(struct dcn30_mmhubbub *mcif_wb30, bool enabled)
23 {
24 	REG_UPDATE(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, !enabled);
25 }
26