1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2026 Advanced Micro Devices, Inc.
4
5 #include "dm_services.h"
6 #include "include/logger_interface.h"
7 #include "../dce110/irq_service_dce110.h"
8
9 #include "dcn/dcn_6_0_0_offset.h"
10 #include "dcn/dcn_6_0_0_sh_mask.h"
11
12 #include "irq_service_dcn60.h"
13
14 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
15
16 #define DCN_BASE__INST0_SEG2 0x000034C0
17
to_dal_irq_source_dcn60(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)18 static enum dc_irq_source to_dal_irq_source_dcn60(
19 struct irq_service *irq_service,
20 uint32_t src_id,
21 uint32_t ext_id)
22 {
23 (void)irq_service;
24 (void)src_id;
25 (void)ext_id;
26 switch (src_id) {
27 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
28 return DC_IRQ_SOURCE_VBLANK1;
29 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
30 return DC_IRQ_SOURCE_VBLANK2;
31 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
32 return DC_IRQ_SOURCE_VBLANK3;
33 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
34 return DC_IRQ_SOURCE_VBLANK4;
35 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
36 return DC_IRQ_SOURCE_VBLANK5;
37 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
38 return DC_IRQ_SOURCE_VBLANK6;
39 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
40 return DC_IRQ_SOURCE_DC1_VLINE0;
41 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
42 return DC_IRQ_SOURCE_DC2_VLINE0;
43 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
44 return DC_IRQ_SOURCE_DC3_VLINE0;
45 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
46 return DC_IRQ_SOURCE_DC4_VLINE0;
47 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
48 return DC_IRQ_SOURCE_DC5_VLINE0;
49 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
50 return DC_IRQ_SOURCE_DC6_VLINE0;
51 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
52 return DC_IRQ_SOURCE_PFLIP1;
53 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
54 return DC_IRQ_SOURCE_PFLIP2;
55 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
56 return DC_IRQ_SOURCE_PFLIP3;
57 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
58 return DC_IRQ_SOURCE_PFLIP4;
59 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
60 return DC_IRQ_SOURCE_PFLIP5;
61 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
62 return DC_IRQ_SOURCE_PFLIP6;
63 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
64 return DC_IRQ_SOURCE_VUPDATE1;
65 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
66 return DC_IRQ_SOURCE_VUPDATE2;
67 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
68 return DC_IRQ_SOURCE_VUPDATE3;
69 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
70 return DC_IRQ_SOURCE_VUPDATE4;
71 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
72 return DC_IRQ_SOURCE_VUPDATE5;
73 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
74 return DC_IRQ_SOURCE_VUPDATE6;
75 case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
76 return DC_IRQ_SOURCE_DMCUB_OUTBOX;
77
78 case DCN_1_0__SRCID__DC_HPD1_INT:
79 /* generic src_id for all HPD and HPDRX interrupts */
80 switch (ext_id) {
81 case DCN_1_0__CTXID__DC_HPD1_INT:
82 return DC_IRQ_SOURCE_HPD1;
83 case DCN_1_0__CTXID__DC_HPD2_INT:
84 return DC_IRQ_SOURCE_HPD2;
85 case DCN_1_0__CTXID__DC_HPD3_INT:
86 return DC_IRQ_SOURCE_HPD3;
87 case DCN_1_0__CTXID__DC_HPD4_INT:
88 return DC_IRQ_SOURCE_HPD4;
89 case DCN_1_0__CTXID__DC_HPD5_INT:
90 return DC_IRQ_SOURCE_HPD5;
91 case DCN_1_0__CTXID__DC_HPD6_INT:
92 return DC_IRQ_SOURCE_HPD6;
93 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
94 return DC_IRQ_SOURCE_HPD1RX;
95 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
96 return DC_IRQ_SOURCE_HPD2RX;
97 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
98 return DC_IRQ_SOURCE_HPD3RX;
99 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
100 return DC_IRQ_SOURCE_HPD4RX;
101 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
102 return DC_IRQ_SOURCE_HPD5RX;
103 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
104 return DC_IRQ_SOURCE_HPD6RX;
105 default:
106 return DC_IRQ_SOURCE_INVALID;
107 }
108 break;
109
110 default:
111 return DC_IRQ_SOURCE_INVALID;
112 }
113 }
114
115 static struct irq_source_info_funcs hpd_irq_info_funcs = {
116 .set = NULL,
117 .ack = hpd0_ack
118 };
119
120 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
121 .set = NULL,
122 .ack = NULL
123 };
124
125 static struct irq_source_info_funcs pflip_irq_info_funcs = {
126 .set = NULL,
127 .ack = NULL
128 };
129
130 static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
131 .set = NULL,
132 .ack = NULL
133 };
134
135 static struct irq_source_info_funcs vblank_irq_info_funcs = {
136 .set = NULL,
137 .ack = NULL
138 };
139
140 static struct irq_source_info_funcs outbox_irq_info_funcs = {
141 .set = NULL,
142 .ack = NULL
143 };
144
145 static struct irq_source_info_funcs vline0_irq_info_funcs = {
146 .set = NULL,
147 .ack = NULL
148 };
149
150 static struct irq_source_info_funcs vline1_irq_info_funcs = {
151 .set = NULL,
152 .ack = NULL
153 };
154
155 static struct irq_source_info_funcs vline2_irq_info_funcs = {
156 .set = NULL,
157 .ack = NULL
158 };
159
160 #undef BASE_INNER
161 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
162
163 /* compile time expand base address. */
164 #define BASE(seg) \
165 BASE_INNER(seg)
166
167 #define SRI(reg_name, block, id)\
168 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
169 reg ## block ## id ## _ ## reg_name
170
171 #define SRI_DMUB(reg_name)\
172 BASE(reg ## reg_name ## _BASE_IDX) + \
173 reg ## reg_name
174
175 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
176 .enable_reg = SRI(reg1, block, reg_num),\
177 .enable_mask = \
178 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
179 .enable_value = {\
180 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
181 (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
182 },\
183 .ack_reg = SRI(reg2, block, reg_num),\
184 .ack_mask = \
185 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
186 .ack_value = \
187 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
188
189 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
190 .enable_reg = SRI_DMUB(reg1),\
191 .enable_mask = \
192 reg1 ## __ ## mask1 ## _MASK,\
193 .enable_value = {\
194 reg1 ## __ ## mask1 ## _MASK,\
195 (uint32_t)~reg1 ## __ ## mask1 ## _MASK \
196 },\
197 .ack_reg = SRI_DMUB(reg2),\
198 .ack_mask = \
199 reg2 ## __ ## mask2 ## _MASK,\
200 .ack_value = \
201 reg2 ## __ ## mask2 ## _MASK \
202
203 #define hpd_int_entry(reg_num)\
204 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
205 IRQ_REG_ENTRY(HPD, reg_num,\
206 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
207 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
208 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
209 .funcs = &hpd_irq_info_funcs\
210 }
211
212 #define hpd_rx_int_entry(reg_num)\
213 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
214 IRQ_REG_ENTRY(HPD, reg_num,\
215 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
216 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
217 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
218 .funcs = &hpd_rx_irq_info_funcs\
219 }
220 #define pflip_int_entry(reg_num)\
221 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
222 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
223 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
224 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
225 .funcs = &pflip_irq_info_funcs\
226 }
227
228 #define vblank_int_entry(reg_num)\
229 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
230 IRQ_REG_ENTRY(OTG, reg_num,\
231 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
232 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
233 .funcs = &vblank_irq_info_funcs\
234 }
235 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
236 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
237 */
238 #define vupdate_no_lock_int_entry(reg_num)\
239 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
240 IRQ_REG_ENTRY(OTG, reg_num,\
241 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
242 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
243 .funcs = &vupdate_no_lock_irq_info_funcs\
244 }
245
246 #define vline0_int_entry(reg_num)\
247 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
248 IRQ_REG_ENTRY(OTG, reg_num,\
249 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
250 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
251 .funcs = &vline0_irq_info_funcs\
252 }
253 #define vline1_int_entry(reg_num)\
254 [DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\
255 IRQ_REG_ENTRY(OTG, reg_num,\
256 OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE,\
257 OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_CLEAR),\
258 .funcs = &vline1_irq_info_funcs\
259 }
260 #define vline2_int_entry(reg_num)\
261 [DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\
262 IRQ_REG_ENTRY(OTG, reg_num,\
263 OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE,\
264 OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_CLEAR),\
265 .funcs = &vline2_irq_info_funcs\
266 }
267 #define dmub_outbox_int_entry()\
268 [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
269 IRQ_REG_ENTRY_DMUB(\
270 DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
271 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
272 .funcs = &outbox_irq_info_funcs\
273 }
274
275 #define dummy_irq_entry() \
276 {\
277 .funcs = &dummy_irq_info_funcs\
278 }
279
280 #define i2c_int_entry(reg_num) \
281 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
282
283 #define dp_sink_int_entry(reg_num) \
284 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
285
286 #define gpio_pad_int_entry(reg_num) \
287 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
288
289 #define dc_underflow_int_entry(reg_num) \
290 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
291
292 static struct irq_source_info_funcs dummy_irq_info_funcs = {
293 .set = dal_irq_service_dummy_set,
294 .ack = dal_irq_service_dummy_ack
295 };
296
297 static const struct irq_source_info
298 irq_source_info_dcn60[DAL_IRQ_SOURCES_NUMBER] = {
299 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
300 hpd_int_entry(0),
301 hpd_int_entry(1),
302 hpd_int_entry(2),
303 hpd_int_entry(3),
304 hpd_rx_int_entry(0),
305 hpd_rx_int_entry(1),
306 hpd_rx_int_entry(2),
307 hpd_rx_int_entry(3),
308 i2c_int_entry(1),
309 i2c_int_entry(2),
310 i2c_int_entry(3),
311 i2c_int_entry(4),
312 i2c_int_entry(5),
313 i2c_int_entry(6),
314 dp_sink_int_entry(1),
315 dp_sink_int_entry(2),
316 dp_sink_int_entry(3),
317 dp_sink_int_entry(4),
318 dp_sink_int_entry(5),
319 dp_sink_int_entry(6),
320 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
321 pflip_int_entry(0),
322 pflip_int_entry(1),
323 pflip_int_entry(2),
324 pflip_int_entry(3),
325 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
326 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
327 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
328 gpio_pad_int_entry(0),
329 gpio_pad_int_entry(1),
330 gpio_pad_int_entry(2),
331 gpio_pad_int_entry(3),
332 gpio_pad_int_entry(4),
333 gpio_pad_int_entry(5),
334 gpio_pad_int_entry(6),
335 gpio_pad_int_entry(7),
336 gpio_pad_int_entry(8),
337 gpio_pad_int_entry(9),
338 gpio_pad_int_entry(10),
339 gpio_pad_int_entry(11),
340 gpio_pad_int_entry(12),
341 gpio_pad_int_entry(13),
342 gpio_pad_int_entry(14),
343 gpio_pad_int_entry(15),
344 gpio_pad_int_entry(16),
345 gpio_pad_int_entry(17),
346 gpio_pad_int_entry(18),
347 gpio_pad_int_entry(19),
348 gpio_pad_int_entry(20),
349 gpio_pad_int_entry(21),
350 gpio_pad_int_entry(22),
351 gpio_pad_int_entry(23),
352 gpio_pad_int_entry(24),
353 gpio_pad_int_entry(25),
354 gpio_pad_int_entry(26),
355 gpio_pad_int_entry(27),
356 gpio_pad_int_entry(28),
357 gpio_pad_int_entry(29),
358 gpio_pad_int_entry(30),
359 dc_underflow_int_entry(1),
360 dc_underflow_int_entry(2),
361 dc_underflow_int_entry(3),
362 dc_underflow_int_entry(4),
363 dc_underflow_int_entry(5),
364 dc_underflow_int_entry(6),
365 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
366 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
367 vblank_int_entry(0),
368 vblank_int_entry(1),
369 vblank_int_entry(2),
370 vblank_int_entry(3),
371 [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
372 [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
373 dmub_outbox_int_entry(),
374 vupdate_no_lock_int_entry(0),
375 vupdate_no_lock_int_entry(1),
376 vupdate_no_lock_int_entry(2),
377 vupdate_no_lock_int_entry(3),
378 vline0_int_entry(0),
379 vline0_int_entry(1),
380 vline0_int_entry(2),
381 vline0_int_entry(3),
382 vline1_int_entry(0),
383 vline1_int_entry(1),
384 vline1_int_entry(2),
385 vline1_int_entry(3),
386 vline2_int_entry(0),
387 vline2_int_entry(1),
388 vline2_int_entry(2),
389 vline2_int_entry(3),
390 };
391
392 static const struct irq_service_funcs irq_service_funcs_dcn60 = {
393 .to_dal_irq_source = to_dal_irq_source_dcn60
394 };
395
dcn60_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)396 static void dcn60_irq_construct(
397 struct irq_service *irq_service,
398 struct irq_service_init_data *init_data)
399 {
400 dal_irq_service_construct(irq_service, init_data);
401
402 irq_service->info = irq_source_info_dcn60;
403 irq_service->funcs = &irq_service_funcs_dcn60;
404 }
405
dal_irq_service_dcn60_create(struct irq_service_init_data * init_data)406 struct irq_service *dal_irq_service_dcn60_create(
407 struct irq_service_init_data *init_data)
408 {
409 struct irq_service *irq_service = kzalloc_obj(*irq_service);
410
411 if (!irq_service)
412 return NULL;
413
414 dcn60_irq_construct(irq_service, init_data);
415 return irq_service;
416 }
417