1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2026 Advanced Micro Devices, Inc.
4
5 #include "dm_services.h"
6 #include "include/logger_interface.h"
7 #include "../dce110/irq_service_dce110.h"
8
9 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
10 #include "dcn/dcn_4_2_0_offset.h"
11 #include "dcn/dcn_4_2_0_sh_mask.h"
12
13 #include "irq_service_dcn42.h"
14
15 #define DCN_BASE__INST0_SEG2 0x000034C0
16
to_dal_irq_source_dcn42(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)17 static enum dc_irq_source to_dal_irq_source_dcn42(
18 struct irq_service *irq_service,
19 uint32_t src_id,
20 uint32_t ext_id)
21 {
22 (void)irq_service;
23 (void)src_id;
24 (void)ext_id;
25 switch (src_id) {
26 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
27 return DC_IRQ_SOURCE_VBLANK1;
28 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
29 return DC_IRQ_SOURCE_VBLANK2;
30 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
31 return DC_IRQ_SOURCE_VBLANK3;
32 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
33 return DC_IRQ_SOURCE_VBLANK4;
34 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
35 return DC_IRQ_SOURCE_VBLANK5;
36 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
37 return DC_IRQ_SOURCE_VBLANK6;
38 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
39 return DC_IRQ_SOURCE_DC1_VLINE0;
40 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
41 return DC_IRQ_SOURCE_DC2_VLINE0;
42 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
43 return DC_IRQ_SOURCE_DC3_VLINE0;
44 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
45 return DC_IRQ_SOURCE_DC4_VLINE0;
46 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
47 return DC_IRQ_SOURCE_DC5_VLINE0;
48 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
49 return DC_IRQ_SOURCE_DC6_VLINE0;
50 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
51 return DC_IRQ_SOURCE_PFLIP1;
52 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
53 return DC_IRQ_SOURCE_PFLIP2;
54 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
55 return DC_IRQ_SOURCE_PFLIP3;
56 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
57 return DC_IRQ_SOURCE_PFLIP4;
58 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
59 return DC_IRQ_SOURCE_PFLIP5;
60 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
61 return DC_IRQ_SOURCE_PFLIP6;
62 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
63 return DC_IRQ_SOURCE_VUPDATE1;
64 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
65 return DC_IRQ_SOURCE_VUPDATE2;
66 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
67 return DC_IRQ_SOURCE_VUPDATE3;
68 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
69 return DC_IRQ_SOURCE_VUPDATE4;
70 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
71 return DC_IRQ_SOURCE_VUPDATE5;
72 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
73 return DC_IRQ_SOURCE_VUPDATE6;
74 case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
75 return DC_IRQ_SOURCE_DMCUB_OUTBOX;
76 case DCN_1_0__SRCID__DC_HPD1_INT:
77 /* generic src_id for all HPD and HPDRX interrupts */
78 switch (ext_id) {
79 case DCN_1_0__CTXID__DC_HPD1_INT:
80 return DC_IRQ_SOURCE_HPD1;
81 case DCN_1_0__CTXID__DC_HPD2_INT:
82 return DC_IRQ_SOURCE_HPD2;
83 case DCN_1_0__CTXID__DC_HPD3_INT:
84 return DC_IRQ_SOURCE_HPD3;
85 case DCN_1_0__CTXID__DC_HPD4_INT:
86 return DC_IRQ_SOURCE_HPD4;
87 case DCN_1_0__CTXID__DC_HPD5_INT:
88 return DC_IRQ_SOURCE_HPD5;
89 case DCN_1_0__CTXID__DC_HPD6_INT:
90 return DC_IRQ_SOURCE_HPD6;
91 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
92 return DC_IRQ_SOURCE_HPD1RX;
93 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
94 return DC_IRQ_SOURCE_HPD2RX;
95 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
96 return DC_IRQ_SOURCE_HPD3RX;
97 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
98 return DC_IRQ_SOURCE_HPD4RX;
99 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
100 return DC_IRQ_SOURCE_HPD5RX;
101 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
102 return DC_IRQ_SOURCE_HPD6RX;
103 default:
104 return DC_IRQ_SOURCE_INVALID;
105 }
106 break;
107 default:
108 return DC_IRQ_SOURCE_INVALID;
109 }
110
111 }
112
113 static struct irq_source_info_funcs hpd_irq_info_funcs = {
114 .set = NULL,
115 .ack = hpd0_ack
116 };
117
118 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
119 .set = NULL,
120 .ack = NULL
121 };
122
123 static struct irq_source_info_funcs pflip_irq_info_funcs = {
124 .set = NULL,
125 .ack = NULL
126 };
127
128 static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
129 .set = NULL,
130 .ack = NULL
131 };
132
133 static struct irq_source_info_funcs vblank_irq_info_funcs = {
134 .set = NULL,
135 .ack = NULL
136 };
137
138 static struct irq_source_info_funcs outbox_irq_info_funcs = {
139 .set = NULL,
140 .ack = NULL
141 };
142
143 static struct irq_source_info_funcs vline0_irq_info_funcs = {
144 .set = NULL,
145 .ack = NULL
146 };
147
148 static struct irq_source_info_funcs vline1_irq_info_funcs = {
149 .set = NULL,
150 .ack = NULL
151 };
152
153 static struct irq_source_info_funcs vline2_irq_info_funcs = {
154 .set = NULL,
155 .ack = NULL
156 };
157
158 #undef BASE_INNER
159 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
160
161 /* compile time expand base address. */
162 #define BASE(seg) \
163 BASE_INNER(seg)
164
165 #define SRI(reg_name, block, id)\
166 (BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
167 reg ## block ## id ## _ ## reg_name)
168
169 #define SRI_DMUB(reg_name)\
170 (BASE(reg ## reg_name ## _BASE_IDX) + \
171 reg ## reg_name)
172
173 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
174 .enable_reg = SRI(reg1, block, reg_num),\
175 .enable_mask = \
176 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
177 .enable_value = {\
178 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
179 (uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
180 },\
181 .ack_reg = SRI(reg2, block, reg_num),\
182 .ack_mask = \
183 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
184 .ack_value = \
185 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
186
187 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
188 .enable_reg = SRI_DMUB(reg1),\
189 .enable_mask = \
190 reg1 ## __ ## mask1 ## _MASK,\
191 .enable_value = {\
192 reg1 ## __ ## mask1 ## _MASK,\
193 (uint32_t)~reg1 ## __ ## mask1 ## _MASK \
194 },\
195 .ack_reg = SRI_DMUB(reg2),\
196 .ack_mask = \
197 reg2 ## __ ## mask2 ## _MASK,\
198 .ack_value = \
199 reg2 ## __ ## mask2 ## _MASK \
200
201 #define hpd_int_entry(reg_num)\
202 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
203 IRQ_REG_ENTRY(HPD, reg_num,\
204 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
205 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
206 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
207 .funcs = &hpd_irq_info_funcs\
208 }
209
210 #define hpd_rx_int_entry(reg_num)\
211 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
212 IRQ_REG_ENTRY(HPD, reg_num,\
213 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
214 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
215 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
216 .funcs = &hpd_rx_irq_info_funcs\
217 }
218 #define pflip_int_entry(reg_num)\
219 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
220 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
221 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
222 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
223 .funcs = &pflip_irq_info_funcs\
224 }
225
226 #define vblank_int_entry(reg_num)\
227 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
228 IRQ_REG_ENTRY(OTG, reg_num,\
229 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
230 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
231 .funcs = &vblank_irq_info_funcs\
232 }
233
234 #define vupdate_no_lock_int_entry(reg_num)\
235 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
236 IRQ_REG_ENTRY(OTG, reg_num,\
237 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
238 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
239 .funcs = &vupdate_no_lock_irq_info_funcs\
240 }
241
242 #define vline0_int_entry(reg_num)\
243 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
244 IRQ_REG_ENTRY(OTG, reg_num,\
245 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
246 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
247 .funcs = &vline0_irq_info_funcs\
248 }
249 #define vline1_int_entry(reg_num)\
250 [DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\
251 IRQ_REG_ENTRY(OTG, reg_num,\
252 OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE,\
253 OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_CLEAR),\
254 .funcs = &vline1_irq_info_funcs\
255 }
256 #define vline2_int_entry(reg_num)\
257 [DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\
258 IRQ_REG_ENTRY(OTG, reg_num,\
259 OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE,\
260 OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_CLEAR),\
261 .funcs = &vline2_irq_info_funcs\
262 }
263 #define dmub_outbox_int_entry()\
264 [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
265 IRQ_REG_ENTRY_DMUB(\
266 DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
267 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
268 .funcs = &outbox_irq_info_funcs\
269 }
270
271 #define dummy_irq_entry() \
272 {\
273 .funcs = &dummy_irq_info_funcs\
274 }
275
276 #define i2c_int_entry(reg_num) \
277 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
278
279 #define dp_sink_int_entry(reg_num) \
280 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
281
282 #define gpio_pad_int_entry(reg_num) \
283 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
284
285 #define dc_underflow_int_entry(reg_num) \
286 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
287
288 static struct irq_source_info_funcs dummy_irq_info_funcs = {
289 .set = dal_irq_service_dummy_set,
290 .ack = dal_irq_service_dummy_ack
291 };
292
293 static const struct irq_source_info irq_source_info_dcn42[DAL_IRQ_SOURCES_NUMBER] = {
294 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
295 /* HPD (1-4) */
296 hpd_int_entry(0),
297 hpd_int_entry(1),
298 hpd_int_entry(2),
299 hpd_int_entry(3),
300 /* HPD RX (1-4) */
301 hpd_rx_int_entry(0),
302 hpd_rx_int_entry(1),
303 hpd_rx_int_entry(2),
304 hpd_rx_int_entry(3),
305 /* I2C (1-6) */
306 i2c_int_entry(1),
307 i2c_int_entry(2),
308 i2c_int_entry(3),
309 i2c_int_entry(4),
310 i2c_int_entry(5),
311 i2c_int_entry(6),
312 /* DP sink (1-6) keep table shape */
313 dp_sink_int_entry(1),
314 dp_sink_int_entry(2),
315 dp_sink_int_entry(3),
316 dp_sink_int_entry(4),
317 dp_sink_int_entry(5),
318 dp_sink_int_entry(6),
319 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
320 /* PFLIP (1-4) */
321 pflip_int_entry(0),
322 pflip_int_entry(1),
323 pflip_int_entry(2),
324 pflip_int_entry(3),
325 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
326 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
327 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
328 /* GPIO pads */
329 gpio_pad_int_entry(0),
330 gpio_pad_int_entry(1),
331 gpio_pad_int_entry(2),
332 gpio_pad_int_entry(3),
333 gpio_pad_int_entry(4),
334 gpio_pad_int_entry(5),
335 gpio_pad_int_entry(6),
336 gpio_pad_int_entry(7),
337 gpio_pad_int_entry(8),
338 gpio_pad_int_entry(9),
339 gpio_pad_int_entry(10),
340 gpio_pad_int_entry(11),
341 gpio_pad_int_entry(12),
342 gpio_pad_int_entry(13),
343 gpio_pad_int_entry(14),
344 gpio_pad_int_entry(15),
345 gpio_pad_int_entry(16),
346 gpio_pad_int_entry(17),
347 gpio_pad_int_entry(18),
348 gpio_pad_int_entry(19),
349 gpio_pad_int_entry(20),
350 gpio_pad_int_entry(21),
351 gpio_pad_int_entry(22),
352 gpio_pad_int_entry(23),
353 gpio_pad_int_entry(24),
354 gpio_pad_int_entry(25),
355 gpio_pad_int_entry(26),
356 gpio_pad_int_entry(27),
357 gpio_pad_int_entry(28),
358 gpio_pad_int_entry(29),
359 gpio_pad_int_entry(30),
360 /* Underflow (1-4 active, keep 5-6 dummy) */
361 dc_underflow_int_entry(1),
362 dc_underflow_int_entry(2),
363 dc_underflow_int_entry(3),
364 dc_underflow_int_entry(4),
365 dc_underflow_int_entry(5),
366 dc_underflow_int_entry(6),
367 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
368 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
369 vblank_int_entry(0),
370 vblank_int_entry(1),
371 vblank_int_entry(2),
372 vblank_int_entry(3),
373 [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
374 [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
375 dmub_outbox_int_entry(),
376 vupdate_no_lock_int_entry(0),
377 vupdate_no_lock_int_entry(1),
378 vupdate_no_lock_int_entry(2),
379 vupdate_no_lock_int_entry(3),
380 vline0_int_entry(0),
381 vline0_int_entry(1),
382 vline0_int_entry(2),
383 vline0_int_entry(3),
384 vline1_int_entry(0),
385 vline1_int_entry(1),
386 vline1_int_entry(2),
387 vline1_int_entry(3),
388 vline2_int_entry(0),
389 vline2_int_entry(1),
390 vline2_int_entry(2),
391 vline2_int_entry(3),
392 };
393
394 static const struct irq_service_funcs irq_service_funcs_dcn42 = {
395 .to_dal_irq_source = to_dal_irq_source_dcn42
396 };
397
dcn42_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)398 static void dcn42_irq_construct(struct irq_service *irq_service,
399 struct irq_service_init_data *init_data)
400 {
401 dal_irq_service_construct(irq_service, init_data);
402 irq_service->info = irq_source_info_dcn42;
403 irq_service->funcs = &irq_service_funcs_dcn42;
404 }
405
dal_irq_service_dcn42_create(struct irq_service_init_data * init_data)406 struct irq_service *dal_irq_service_dcn42_create(struct irq_service_init_data *init_data)
407 {
408 struct irq_service *irq_service = kzalloc_obj(*irq_service);
409
410 if (!irq_service)
411 return NULL;
412
413 dcn42_irq_construct(irq_service, init_data);
414 return irq_service;
415 }
416