1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #include "dce110/dce110_hwseq.h" 6 #include "dcn10/dcn10_hwseq.h" 7 #include "dcn20/dcn20_hwseq.h" 8 #include "dcn21/dcn21_hwseq.h" 9 #include "dcn30/dcn30_hwseq.h" 10 #include "dcn31/dcn31_hwseq.h" 11 #include "dcn32/dcn32_hwseq.h" 12 #include "dcn35/dcn35_hwseq.h" 13 #include "dcn401/dcn401_hwseq.h" 14 #include "dcn42/dcn42_hwseq.h" 15 #include "dcn50/dcn50_hwseq.h" 16 #include "dcn60_init.h" 17 #include "dcn60_hwseq.h" 18 19 static const struct hw_sequencer_funcs dcn60_funcs = { 20 .program_gamut_remap = dcn401_program_gamut_remap, 21 .init_hw = dcn60_init_hw, 22 .apply_ctx_to_hw = dcn60_apply_ctx_to_hw, 23 .apply_ctx_for_surface = NULL, 24 .program_front_end_for_ctx = dcn50_program_front_end_for_ctx, 25 .wait_for_pending_cleared = dcn10_wait_for_pending_cleared, 26 .post_unlock_program_front_end = dcn50_post_unlock_program_front_end, 27 .update_plane_addr = dcn20_update_plane_addr, 28 .update_dchub = dcn10_update_dchub, 29 .update_pending_status = dcn10_update_pending_status, 30 .program_output_csc = dcn20_program_output_csc, 31 .trigger_3dlut_dma_load = dcn401_trigger_3dlut_dma_load, 32 .enable_accelerated_mode = dce110_enable_accelerated_mode, 33 .enable_timing_synchronization = dcn10_enable_timing_synchronization, 34 .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, 35 .update_info_frame = dcn31_update_info_frame, 36 .send_immediate_sdp_message = dcn10_send_immediate_sdp_message, 37 .enable_stream = dcn401_enable_stream, 38 .disable_stream = dce110_disable_stream, 39 .unblank_stream = dcn401_unblank_stream, 40 .blank_stream = dce110_blank_stream, 41 .enable_audio_stream = dce110_enable_audio_stream, 42 .disable_audio_stream = dce110_disable_audio_stream, 43 .disable_plane = dcn20_disable_plane, 44 .disable_plane_sequence = dcn401_disable_plane_sequence, 45 .pipe_control_lock = dcn20_pipe_control_lock, 46 .interdependent_update_lock = dcn401_interdependent_update_lock, 47 .cursor_lock = dcn10_cursor_lock, 48 .prepare_bandwidth = dcn401_prepare_bandwidth, 49 .prepare_bandwidth_sequence = dcn401_prepare_bandwidth_sequence, 50 .optimize_bandwidth = dcn401_optimize_bandwidth, 51 .optimize_bandwidth_sequence = dcn401_optimize_bandwidth_sequence, 52 .update_bandwidth = dcn20_update_bandwidth, 53 .set_drr = dcn10_set_drr, 54 .get_position = dcn10_get_position, 55 .set_static_screen_control = dcn35_set_static_screen_control, 56 .setup_stereo = dcn42_setup_stereo, 57 .set_avmute = dcn30_set_avmute, 58 .log_hw_state = dcn10_log_hw_state, 59 .get_hw_state = dcn10_get_hw_state, 60 .clear_status_bits = dcn10_clear_status_bits, 61 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, 62 .wait_for_mpcc_disconnect_sequence = dcn401_wait_for_mpcc_disconnect_sequence, 63 .edp_backlight_control = dce110_edp_backlight_control, 64 .edp_power_control = dce110_edp_power_control, 65 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 66 .edp_wait_for_T12 = dce110_edp_wait_for_T12, 67 .set_cursor_position = dcn401_set_cursor_position, 68 .set_cursor_attribute = dcn60_set_cursor_attribute, 69 .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, 70 .abort_cursor_offload_update = dcn35_abort_cursor_offload_update, 71 .begin_cursor_offload_update = dcn35_begin_cursor_offload_update, 72 .commit_cursor_offload_update = dcn35_commit_cursor_offload_update, 73 .update_cursor_offload_pipe = dcn60_update_cursor_offload_pipe, 74 .notify_cursor_offload_drr_update = dcn35_notify_cursor_offload_drr_update, 75 .program_cursor_offload_now = dcn35_program_cursor_offload_now, 76 .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, 77 .set_clock = dcn10_set_clock, 78 .get_clock = dcn10_get_clock, 79 .program_triplebuffer = dcn20_program_triple_buffer, 80 .enable_writeback = dcn30_enable_writeback, 81 .disable_writeback = dcn30_disable_writeback, 82 .update_writeback = dcn30_update_writeback, 83 .dmdata_status_done = dcn20_dmdata_status_done, 84 .program_dmdata_engine = dcn30_program_dmdata_engine, 85 .set_dmdata_attributes = dcn20_set_dmdata_attributes, 86 .init_sys_ctx = dcn31_init_sys_ctx, 87 .init_vm_ctx = dcn20_init_vm_ctx, 88 .set_flip_control_gsl = dcn20_set_flip_control_gsl, 89 .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, 90 .calc_vupdate_position = dcn10_calc_vupdate_position, 91 .setup_hdmi_frl_link = dcn30_setup_hdmi_frl_link, 92 .apply_idle_power_optimizations = dcn60_apply_idle_power_optimizations, 93 .does_plane_fit_in_mall = NULL, 94 .set_backlight_level = dcn21_set_backlight_level, 95 .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, 96 .hardware_release = dcn401_hardware_release, 97 .set_pipe = dcn21_set_pipe, 98 .enable_lvds_link_output = dce110_enable_lvds_link_output, 99 .enable_tmds_link_output = dce110_enable_tmds_link_output, 100 .enable_dp_link_output = dce110_enable_dp_link_output, 101 .disable_link_output = dcn401_disable_link_output, 102 .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, 103 .get_dcc_en_bits = dcn10_get_dcc_en_bits, 104 .enable_phantom_streams = NULL, 105 .disable_phantom_streams = NULL, 106 .update_visual_confirm_color = dcn10_update_visual_confirm_color, 107 .update_phantom_vp_position = NULL, 108 .update_dsc_pg = NULL, 109 .apply_update_flags_for_phantom = NULL, 110 .wait_for_dcc_meta_propagation = dcn401_wait_for_dcc_meta_propagation, 111 .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, 112 .dmub_hw_control_lock = dcn401_dmub_hw_control_lock, 113 .fams2_update_config = dcn401_fams2_update_config, 114 .dmub_hw_control_lock_fast = dcn401_dmub_hw_control_lock_fast, 115 .program_outstanding_updates = dcn401_program_outstanding_updates, 116 .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, 117 .detect_pipe_changes = dcn401_detect_pipe_changes, 118 .enable_plane = dcn20_enable_plane, 119 .enable_plane_sequence = dcn401_enable_plane_sequence, 120 .update_dchubp_dpp = dcn50_update_dchubp_dpp, 121 .update_dchubp_dpp_sequence = dcn50_update_dchubp_dpp_sequence, 122 .post_unlock_reset_opp = dcn20_post_unlock_reset_opp, 123 .post_unlock_reset_opp_sequence = dcn401_post_unlock_reset_opp_sequence, 124 .get_underflow_debug_data = dcn30_get_underflow_debug_data, 125 .program_perfmon = dcn60_program_perfmon, 126 }; 127 128 static const struct hwseq_private_funcs dcn60_private_funcs = { 129 .init_pipes = dcn10_init_pipes, 130 .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, 131 .plane_atomic_disconnect_sequence = dcn401_plane_atomic_disconnect_sequence, 132 .update_mpcc = dcn42_update_mpcc, 133 .update_mpcc_sequence = dcn50_update_mpcc_sequence, 134 .set_input_transfer_func = dcn32_set_input_transfer_func, 135 .set_output_transfer_func = dcn401_set_output_transfer_func, 136 .power_down = dce110_power_down, 137 .enable_display_power_gating = dcn10_dummy_display_power_gating, 138 .blank_pixel_data = dcn20_blank_pixel_data, 139 .blank_pixel_data_sequence = dcn401_blank_pixel_data_sequence, 140 .reset_hw_ctx_wrap = dcn401_reset_hw_ctx_wrap, 141 .enable_stream_timing = dcn401_enable_stream_timing, 142 .edp_backlight_control = dce110_edp_backlight_control, 143 .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, 144 .setup_vupdate_interrupt_sequence = dcn401_setup_vupdate_interrupt_sequence, 145 .did_underflow_occur = dcn10_did_underflow_occur, 146 .init_blank = dcn32_init_blank, 147 .disable_vga = NULL, 148 .bios_golden_init = dcn10_bios_golden_init, 149 .plane_atomic_disable = dcn20_plane_atomic_disable, 150 .plane_atomic_power_down = dcn401_plane_atomic_power_down, 151 .plane_atomic_power_down_sequence = dcn401_plane_atomic_power_down_sequence, 152 .enable_power_gating_plane = NULL, 153 .hubp_pg_control = NULL, 154 .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, 155 .program_all_writeback_pipes_in_tree_sequence = dcn401_program_all_writeback_pipes_in_tree_sequence, 156 .update_odm = dcn401_update_odm, 157 .update_odm_sequence = dcn401_update_odm_sequence, 158 .dsc_pg_control = NULL, 159 .dsc_pg_status = NULL, 160 .set_hdr_multiplier = dcn10_set_hdr_multiplier, 161 .set_hdr_multiplier_sequence = dcn401_set_hdr_multiplier_sequence, 162 .wait_for_blank_complete = dcn20_wait_for_blank_complete, 163 .set_mcm_luts = dcn42_set_mcm_luts, 164 .program_mall_pipe_config = NULL, 165 .update_mall_sel = NULL, 166 .calculate_dccg_k1_k2_values = NULL, 167 .apply_single_controller_ctx_to_hw = dcn60_apply_single_controller_ctx_to_hw, 168 .reset_back_end_for_pipe = dcn401_reset_back_end_for_pipe, 169 .program_cm_hist = dcn42_program_cm_hist, 170 .program_pipe = dcn401_program_pipe, 171 .program_pipe_sequence = dcn401_program_pipe_sequence, 172 .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, 173 .set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe, 174 }; 175 176 void dcn60_hw_sequencer_init_functions(struct dc *dc) 177 { 178 dc->hwss = dcn60_funcs; 179 dc->hwseq->funcs = dcn60_private_funcs; 180 181 } 182